JP2001258268A - Half-bridge inverter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of main switching elements Q1, Q2 turning on at the same time, resulting from erroneous operation caused by sudden noise inputted in an input signal IN into a pulse generating circuit 24. SOLUTION: This circuit is formed so as to permit a pulse filter circuit 26 to block the passing of a setting output signal OUT (set) if a reset output signal OUT (reset) of the pulse generating circuit 24 is not outputted, which is caused by the small pulse duration of an output signal HO of a dead time control circuit 22 on high side. It is thus possible to prevent the main switching elements Q1, Q2 from turning on at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a half-bridge type inverter circuit, and more particularly to a half-bridge type inverter circuit to which a load driven by a high voltage is connected.

[0002]

2. Description of the Related Art FIG. 1 shows a configuration of a half-bridge type inverter circuit for lighting. Q1 and Q2 are power MOSFETs
A main switching element composed of T, D1,
D2 is a commutation diode of a resonance current composed of a parasitic diode between the drain and source of the power MOSFET. L of the ballast circuit is a resonance reactor, C1 is a DC component cutting capacitor, C2 is a filament preheating capacitor, and the fluorescent lamp has a circuit configuration connected in parallel with the filament preheating capacitor C2.

FIG. 2 shows operation waveforms when the lamp is turned on. VGS1 and VGS2 are the main switching elements Q
1, the gate-source voltage of Q2. During operation, the main switching elements Q1 and Q2 alternately turn on and off alternately, and in order to prevent the main switching elements Q1 and Q2 from turning on at the same time, a dead time period during which both the main switching elements Q1 and Q2 are off is set. Have.

[0004] High-side main switching element Q1
Turns on when VGS1 goes high, and the drain current indicated by ID1 flows. As a result, a square wave voltage is applied to the ballast circuit composed of L, C1, C2 and the fluorescent lamp, and a sine wave ballast current I1 flows. The ballast current I1 during lamp operation is a combined current of the filament current I2 and the lamp current I3.

The low-side main switching element Q2
Turns on when VGS2 goes high, and drain current ID2
Flows. As a result, the energy stored in the ballast circuit is released, and the ballast current I1, the filament current I2, and the lamp current I3 decrease in the negative direction.

A normal half-bridge type inverter circuit is operated at a frequency in a delay region higher than the resonance frequency of the ballast circuit. Therefore, the ballast current I1 can be changed by the switching frequency of the main switching elements Q1 and Q2, so that the brightness can be adjusted.

As shown in FIG. 1, an input signal from the control circuit 1 is converted into a predetermined drive signal (for example, VGS) by a drive circuit 2.
1, VGS2), and the main switching element Q
1, Q2 is being driven.

FIG. 3 shows a specific circuit block of the drive circuit 2. That is, a signal input circuit 21, dead time control circuits 22 and 23 for performing dead time control on the high side and the low side,
Pulse generating circuit 24, level shift circuit 25, pulse filter circuit 26, flip-flop circuit 27 serving as a storage circuit, and an output for supplying a drive signal for driving high-side and low-side main switching elements Q1 and Q2. It is composed of circuits 28 and 29.

The drive circuit 2 shapes an output signal from the control circuit 1 by a signal input circuit 21 and then inputs the output signal to dead time control circuits 22 and 23 for performing high-side and low-side dead time control. As shown in (1), a high-side output signal HO delayed from the input signal (output signal of the control circuit 1) and a low-side output signal LO falling before the high-side output signal HO rises are formed. The main switching element Q is used for the high side output signal HO and the low side output signal LO.
There is a dead time in which both 1 and Q2 become low level so that they do not turn on at the same time.

In the drive circuit 2 on the high side, since the main switching element Q1 is driven at a voltage of about 600 volts, it is necessary to shift the high side output signal HO to a high voltage of about 600 volts to generate the drive signal VGS1. . The output signal PGIN of the dead time control circuit 22 is input to the pulse generation circuit 24, and the set output signal OUT (Set) and the reset output signal OUT (Res)
et). These signals are input to the next high voltage level shift circuit 25, and the high voltage set output signal OUT (Set) and the reset output signal OUT (Res)
et). These signals are passed by a pulse filter circuit 26 to pass a signal having a certain pulse width or more to set and reset the flip-flop circuit 27, output a high-side output signal HO from an output circuit 28, and output a high-side main signal. The switching element Q1 is driven.

FIG. 7 shows a pulse generation circuit 24. In order to output a set output signal OUT (Set) and a reset output signal OUT (Reset) from the input signal PGIN from the dead time control circuit 22 on the high side, the input signal PGIN is output to the inverter circuit 2 on the set side.
The signal S1 inverted at 41 and the input signal PGIN are delayed by a two-stage delay circuit 242 and shaped by an inverter circuit 243 connected at two stages to form a signal S2. Both signals S
1 and S2 are input to a NOR gate circuit 244, a set output signal OUT (Set) is obtained, and further shaped through an inverter circuit 245 connected in two stages. Similarly, the reset side outputs the reset output signal OUT from the signals R1 and R2.
(Reset) is generated.

[0012]

In such a half-bridge type inverter circuit, the main switching element Q1,
In order to prevent Q2 from turning on at the same time, a dead time period during which both drive signals (for example, VGS1 and VGS2) are off is provided.

However, when sudden noise is input to the input signal PGIN to the pulse generation circuit 24 of the drive circuit 2, a malfunction occurs, and there is a problem that the main switching elements Q1 and Q2 are simultaneously turned on.

As shown in FIG. 8, when the pulse width of input signal PGIN to pulse generating circuit 24 is as narrow as 15 ns or less, since signal S2 and signal R2 are not transmitted by delay circuit 242, set output signal OUT (Set) is output. Has the same waveform as the input signal PGIN. On the other hand, the reset output signal OUT (Reset) disappears and is maintained at the low level. For this purpose, the set output signal OUT (Set)
Since only the reset output signal OUT (Reset) disappears, the high-side output signal HO is maintained at a high level. That is, the main switching elements Q1 and Q2 are simultaneously turned on.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the problem that the main switching elements Q1 and Q2 are in the simultaneous ON mode. In a half-bridge type inverter circuit, the drive circuit 2 is inputted from the control circuit 1 to the drive circuit 2. A high-side and low-side dead time control circuit 22 for generating a dead time period from input signals
23 and a set output signal OUT from the output signal PGIN of the dead time control circuit 22 on the high side.
(Set) and the reset output signal OUT (Rese
t), the set output signal OUT (Set) and the reset output signal OUT (R
reset), a level shift circuit 25 for boosting the set output signal OUT (Set), a pulse filter circuit 26 for allowing the set output signal OUT (Set) and the reset output signal OUT (Reset) to pass those having a certain pulse width or more, and the pulse filter circuit 26 From the set output signal OUT (Se
t) and a storage circuit 27 that is set and reset by the reset output signal OUT (Reset), an output circuit 28 that outputs a high-side output signal HO based on the output from the storage circuit 27, and the low-side dead time control circuit 23. An output circuit 29 outputs a low-side output signal LO as an output. The pulse width of the output signal PGIN of the high-side dead time control circuit 22 is narrow, and the reset output signal O of the pulse generation circuit 24 is small.
When the UT (Reset) is not output, the set output signal OUT (Set) is output by the pulse filter circuit 26.
, So that the main switching elements Q1 and Q2 are prevented from being simultaneously turned on.

[0016]

FIG. 1 shows an embodiment of the present invention.
This will be described with reference to FIG.

FIG. 1 shows a configuration of a half-bridge type inverter circuit for lighting. Q1 and Q2 are power MOSFETs
, And D1 and D
Reference numeral 2 denotes a commutation diode of a resonance current formed by a parasitic diode between the drain and the source of the power MOSFET. L of the ballast circuit is a resonance reactor, C1 is a DC component cutting capacitor, C2 is a filament preheating capacitor, and the fluorescent lamp has a circuit configuration connected in parallel with the filament preheating capacitor C2.

FIG. 2 shows operation waveforms, and FIG. 3 shows a circuit block of a drive circuit. The basic operation principle and circuit configuration are the same as those described in the section of the prior art, and thus description thereof will be omitted.

FIG. 4 shows an input signal (an output signal of the control circuit 1).
7 shows the waveforms of the high-side output signal HO delayed from the low-side output signal LO and the low-side output signal LO falling before the high-side output signal HO rises. The high-side output signal HO and the low-side output signal LO have a main switching element Q1,
There is a dead time in which both become low level so that Q2 does not turn on at the same time.

FIG. 7 shows the pulse generation circuit 24. In order to output the set output signal OUT (Set) and the reset output signal OUT (Reset) from the input signal PGIN from the high-side dead time control circuit 22, the input signal IN is output to the inverter circuit 241 on the set side.
, And the input signal IN is delayed by the two-stage delay circuit 242, and the two-stage connected inverter circuit 2
Shaping is performed at 43 to form a signal S2. Both signals S1, S2
Are input to a NOR gate circuit 244, a set output signal OUT (Set) is obtained, and further shaped through an inverter circuit 245 connected in two stages. Similarly, the reset side outputs the reset output signal OUT (Res) from the signals R1 and R2.
et).

As shown in FIG. 8, when the pulse width of the input signal PGIN to the pulse generation circuit 24 is as narrow as 12 ns or less, the signal S2 and the signal R2 are not transmitted by the delay circuit 242, so that the set output signal OUT (Set) Has the same waveform as the input signal PGIN. On the other hand, the reset output signal OUT (Reset) disappears and is maintained at the low level.

FIG. 9 shows a pulse input width of the output signal PGIN of the dead time control circuit 22 which is an input to the pulse generation circuit 24, and a set output signal OUT (Set) and a reset output signal OUT (output) from the pulse generation circuit 24. (Reset) is shown.

High side output signal HO of drive circuit 2
Is a set output signal OUT (Se) of the pulse generation circuit 24.
t), the reset output signal OUT (R
set) to be low level.
When the pulse width of the input signal is reduced to about 12 ns or less by the operation of the delay circuit 242 of the pulse generation circuit 24, the reset output signal OUT (Reset) changes to the set output signal OUT (Se).
The region disappears before t), and the high-side output signal HO is maintained at a high level by the remaining set output signal OUT (Set) as shown in FIG.

FIG. 5 is a specific circuit diagram of the level shift circuit 25 and the pulse filter circuit 26 to which the set output signal OUT (Set) is applied. The level shift circuit 2 to which the reset output signal OUT (Reset) is applied
5 and the pulse filter circuit 26 have similar circuits.

The feature of the present invention is that the pulse filter circuit 2
At 6. The pulse filter circuit 26 performs waveform shaping 2
It comprises inverter circuits 261 and 262 connected in stages, a delay circuit 263, and inverter circuits 264 and 265 connected in two stages for waveform shaping. Delay circuit 263
Is the output terminal of the CMOS inverter circuit and the P-channel MO
It comprises a resistor R connected between the drain terminals of the S transistor and a capacitor C connected between the output terminal and the common potential VS. By selecting a time constant formed by the resistor R and the capacitor C, a pulse width that can pass through the pulse filter circuit 26 can be determined. Note that the common potential VS is an intermediate potential between the main switching element Q1 and the main switching element Q2, VB is a high-voltage power supply potential, and COM indicates a ground potential.

FIG. 6 shows the relationship between the filter width that causes simultaneous ON and the resistance R (in FIG. 6, represented by a PSD (pulse signal delay) resistance). Reset output signal OUT (Rese
In the region where t) is surely left, an operation range of 18 nS or more in filter width and an optimum design value of 22 nS to 24 nS were selected. Therefore, in order to make the filter width 18 nS or more, the resistance R needs to be 6.5 KΩ or more. About 9 KΩ is preferable in consideration of manufacturing variations. The capacitance is 2.3 pF.

The resistance R of the delay circuit 263 for outputting the set output signal OUT (Set) of the pulse filter circuit 26 is set to Rs.
Resistance R of delay circuit (not shown) on UT (Reset) side
Is set to Rr, by setting Rs> Rr, the set output signal OUT (Set) can be surely eliminated first when the input signal PGIN from the pulse generation circuit 24 is narrow, which is effective in preventing simultaneous ON. It is. Actually, Rs is 9K
Rr was set to 4.7 KΩ when Ω was set.

As is clear from FIG. 9, if the pulse output width from the pulse generating circuit 24 is 18 ns or more, the reset output signal OUT (Reset) does not always disappear, so that the main switching element Q1,
Q2 can be prevented from turning on at the same time.

[0029]

According to the present invention, the pulse filter circuit 2
6 by selecting the time constant of the delay circuit 263, the reset output signal OUT (R
set) until the area where the output signal (set) remains reliably.
(Set) is not transmitted, and it is possible to prevent the main switching elements Q1 and Q2 from being simultaneously turned on. This makes it possible to provide a half-bridge type inverter circuit in which a malfunction due to sudden noise is completely avoided.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the present invention and a conventional half-bridge type inverter circuit.

FIG. 2 is a diagram illustrating operation waveforms of the present invention and a conventional half-bridge type inverter circuit.

FIG. 3 is a diagram illustrating a drive circuit of the present invention and a conventional half-bridge type inverter circuit.

FIG. 4 is a diagram illustrating operation waveforms of the dead time control circuit of the present invention and a conventional half-bridge type inverter circuit.

FIG. 5 is a diagram illustrating a pulse filter circuit of the half-bridge type inverter circuit of the present invention.

FIG. 6 is a diagram illustrating characteristics of the pulse filter circuit of the half-bridge type inverter circuit according to the present invention.

FIG. 7 is a diagram illustrating a pulse generation circuit of the present invention and a conventional half-bridge type inverter circuit.

FIG. 8 is a diagram illustrating operation waveforms of the pulse generation circuit of the present invention and a conventional half-bridge inverter circuit.

FIG. 9 is a diagram illustrating characteristics of a pulse generation circuit of the half-bridge type inverter circuit of the present invention.

[Explanation of symbols]

 Q1, Q2 Main switching elements D1, D2 Commutation diode of resonance current L Reactor C1 DC component cut capacitor C2 Filament preheating capacitor

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) EZ14 EZ50 FX12 FX17 FX33 FX37 FX40 GX01 GX02 GX06

Claims (4)

[Claims] 1. A half-bridge type switching circuit comprising a high-side main switching element and a low-side main switching element, and a drive circuit for outputting an output signal provided with a dead time period for driving the switching circuit. A half-bridge type inverter circuit comprising: a high-side and a low-side dead time control circuit that forms a dead time period from an input signal input from a control circuit to the drive circuit; and the high-side dead time control. A pulse generating circuit for generating a set output signal and a reset output signal from an output of the circuit, a level shift circuit for boosting the set output signal and the reset output signal, and a certain pulse width or more of the set output signal and the reset output signal Through things A pulse filter circuit, an output circuit for outputting a high-side output signal based on the set output signal and the reset output signal from the pulse filter circuit, and an output circuit for outputting a low-side output signal at the output of the low-side dead time control circuit. The pulse width of the output of the dead time control circuit on the high side is narrow, and the set output signal is not passed by the pulse filter circuit when the reset output signal of the pulse generation circuit is not output. A half-bridge type inverter circuit characterized by preventing simultaneous ON of both main switching elements. 2. The time constant of a delay circuit in the pulse filter circuit is set so that the pulse output circuit can pass the set output signal having an input pulse width equal to or larger than an input pulse width at which the reset output signal disappears. Item 2. A half-bridge type inverter circuit according to item 1. 3. The pulse filter according to claim 1, wherein a time constant of the delay circuit in the pulse filter circuit is set to be smaller than a pulse width through which the set output signal can pass. Half-bridge type inverter circuit. 4. The delay circuit comprises a resistor connected between an output terminal of a CMOS inverter circuit and a drain terminal of a P-channel MOS transistor, and a capacitor connected between the output terminal and a common potential. Claim 2
Or a half-bridge type inverter circuit according to claim 3.