JP2013038309A - Semiconductor module and semiconductor device including the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor module structure which can inhibit warp of a heat dissipation substrate to avoid poor connection and deterioration in heat dissipation properties.SOLUTION: Heat dissipation substrates 12-15 are connected to lead frames 9-11 and semiconductor chips 7a, 7b, 8a, 8b are directly connected with the lead frames 9-11 but not connected via conductor parts 12a-15a of the heat dissipation substrates 12-15. By this, the conductor parts 12a-15a can be a solid structure without division of the conductor parts 12a-15a. Accordingly, warp of the heat dissipation substrate 12-15 occurring when a high temperature is lowered to a room temperature such as after resin encapsulation performed at a high temperature can be inhibited. As a result, connection between the semiconductor chips 7a, 7b and the lead frames 9-11, and connection between the lead frames 9-11 and the heat dissipation substrates 12-15 can be successfully performed.

Description

  The present invention relates to a semiconductor module in which a semiconductor chip on which a semiconductor power element that performs heat dissipation through a heat dissipation substrate is formed and a heat dissipation substrate are sealed with a resin, and a semiconductor device including the same.

  Conventionally, in Patent Document 1, a semiconductor device in which a heat sink provided with fins constituting a cooling mechanism is attached to a semiconductor module in which a semiconductor chip on which a semiconductor power element is formed and a heat radiating substrate are sealed with a resin is integrated. Proposed.

  FIG. 15 is a cross-sectional view of this semiconductor device. As shown in FIG. 15, the copper foil J3a of the heat dissipation board J3 on which the copper foil J3a having the desired pattern and the insulating board J3b and the copper foil J3c are joined to the semiconductor chips J1 and J2 on which the semiconductor power elements are formed. And the heat sink J4 provided with the fin J4a is being fixed to the copper foil J3c side among the thermal radiation board | substrates J3. The semiconductor chips J1 and J2 are a semiconductor chip J1 in which an insulated gate field effect transistor (hereinafter referred to as IGBT) is formed as a semiconductor power element, and a semiconductor chip J2 in which a free wheel diode (hereinafter referred to as FWD) is formed. ing. The signal line electrode including the gate electrode of the semiconductor chip J1 is connected to the lead frame J5 through the copper foil J3a, and the emitter electrode of the semiconductor chip J1 and the anode electrode of the semiconductor chip J2 are connected to the lead frame J6 through the copper foil J3a. ing. The collector electrode of the semiconductor chip J1 and the cathode electrode of the semiconductor chip J2 are the copper foil of the heat dissipation board J9 in which the copper foil J9a, the insulating board J9b, and the copper foil J9c are formed through the spacers J7 and J8 made of conductors. It is connected to J9a and connected to the lead frame J10 through this copper foil J9a.

JP 2009-117428 A

  However, in the semiconductor device described in Patent Document 1, the heat dissipation substrate J3 is warped, and it is difficult to join the copper foil J3a and the first and second semiconductor chips J1 and J2, or the copper foil J3c and the heat sink. There arises a problem that joining with J4 becomes difficult.

  FIG. 16 is an enlarged view of the heat dissipation board J3 and an enlarged cross-sectional view showing the heat dissipation board J3 being warped. As shown in FIGS. 15 and 16 (a), the copper foil J3a of the heat dissipation board J3 is patterned, a portion connected to the signal line electrode including the gate electrode of the first semiconductor chip J1, and the first semiconductor It is divided and insulated from the part connected to the emitter electrode of the chip J1 and the anode electrode of the second semiconductor chip J2. For this reason, the patterns of the copper foils J3a and J3c are not symmetrical on the front and back surfaces of the heat dissipation board J3, and warpage occurs in the heat dissipation board J3 when the temperature is lowered from a high temperature during manufacturing to room temperature. According to the experimental results, a large warp of 200 to 400 μm has been confirmed. For this reason, as shown in FIG. 16B, for example, even if the copper foil J3a and the bump J11 disposed on the signal line electrode of the first semiconductor chip J1 cannot be connected or can be connected to each other. , Bonding becomes weak.

  Further, even if the copper foil J3a and the signal line electrode of the first semiconductor chip J1 or the emitter electrode of the semiconductor chip J1 and the anode electrode of the semiconductor chip J2 can be joined, the copper foil J3c and the heat sink J4 cannot be joined. The problem that heat resistance deteriorates arises.

  An object of this invention is to provide the semiconductor module of the structure which can suppress the curvature of a thermal radiation board | substrate, and a semiconductor device provided with the same in view of the said point.

  In order to achieve the above object, according to the first aspect of the present invention, the first lead frame (9) and the second lead frame (10) are arranged on both surfaces of the semiconductor chip (7a), and the first lead frame (9 The first heat dissipation substrate (12) is bonded to the second lead frame (10) and the second heat dissipation substrate (13) is bonded to the second lead frame (10), and these are resin-sealed with a resin portion (16). The first and second heat radiating substrates (12, 13) are both a first conductor portion (12a, 13a) constituting a surface to be joined to the first and second lead frames (9, 10), and a resin. A second conductor portion (12c, 13c) constituting a surface exposed from the portion (16), and an insulating substrate (12b) sandwiched between the first and second conductor portions (12a, 13a, 12c, 13c) 13b), the first conductor portion 12a, 13a) and a second conductor portion (12c, 13c) is characterized in that it is symmetrical with with being a solid structure which is not divided.

  In this way, the semiconductor chip (7a) is directly connected to the first and second lead frames (9, 10), and the first conductor portions (12a, 13a) of the first and second heat dissipation substrates (12, 13). ) Is not connected through the structure. For this reason, the 1st conductor part (12a, 13a) can be made into the solid structure which is not divided | segmented, and it can be made symmetrical with the 2nd conductor part (12c, 13c). Accordingly, it is possible to suppress the warpage of the first and second heat dissipation substrates (12, 13) when the temperature is lowered from high temperature to room temperature after resin sealing at high temperature. Therefore, the connection between the semiconductor chip (7a) and the first and second lead frames (9, 10), and the first and second lead frames (9, 10) and the first and second heat dissipation substrates (12, 13) can be connected well.

  According to the second aspect of the present invention, one of the two sides sandwiching the semiconductor chip (7a) has a component configuration in which the first lead frame (9) and the first heat dissipation substrate (12) are arranged, and the other is the first. Since the two lead frame (10) and the second heat radiating substrate (13) are arranged in a component configuration, the component configurations on both sides of the semiconductor chip (7a) are symmetrical. .

  In this way, the components arranged on both sides of the semiconductor chip (7a) are symmetrical. For this reason, it becomes possible to reduce the curvature based on asymmetry. In particular, since the first conductor portions (12a, 13a) of the first and second heat radiating boards (12, 13) can have a solid structure, both the first and second heat radiating boards (12, 13) have the same structure. Therefore, the structures on both sides of the semiconductor chip (7a) can be made more symmetrical. Therefore, it is possible to further reduce warping based on asymmetry.

  In the third aspect of the present invention, the first lead frame (9) and the second lead frame (10) are arranged on both surfaces of the first semiconductor chip (7a) and the second semiconductor chip (7b) is second on both surfaces. A lead frame (10) and a third lead frame (11) are arranged. Further, the first lead frame (9) has a first heat dissipation substrate (12), and the second lead frame (10) has second and third heat dissipation substrates ( 13, 14), a semiconductor module in which a fourth heat dissipation substrate (15) is joined to a third lead frame (11), and these are resin-sealed with a resin portion (16), wherein the first to fourth heat dissipation substrates (12 to 15) are surfaces exposed from the first conductor portions (12a to 15a) and the resin portion (16) that form surfaces joined to the first to third lead frames (9 to 11). 2nd conductor part (12c-15c) which constitutes And an insulating substrate (12b-15b) sandwiched between the first and second conductor portions (12a-15a, 12c-15c), and the first conductor portion (12a-15a) and the second conductor portion. (12c to 15c) are characterized by being a solid structure that is not divided and having a symmetrical shape.

  Thus, even in a semiconductor module having a structure in which the first and second semiconductor chips (7a, 7b) are provided, the first and second semiconductor chips (7a, 7b) are connected to the first to third lead frames (9). To 11) are not directly connected to each other via the first conductor portions (12a to 15a) of the first to fourth heat dissipation substrates (12 to 15). For this reason, the 1st conductor part (12a-15a) can be made into the solid structure which is not divided | segmented, and it can be made symmetrical with the 2nd conductor part (12c-15c). Therefore, it is possible to suppress the occurrence of warping in the first to fourth heat dissipation substrates (12 to 15) when the temperature is lowered from high temperature to room temperature after resin sealing at high temperature. Therefore, the connection between the first and second semiconductor chips (7a, 7b) and the first to third lead frames (9 to 11), the first to third lead frames (9 to 11) and the first to first lead frames (9 to 11). Connection with the fourth heat dissipation substrate (12 to 15) can be performed satisfactorily.

  In the invention according to claim 4, one of both sides sandwiching the first semiconductor chip (7 a) has a component configuration in which the first lead frame (9) and the first heat dissipation substrate (12) are arranged, and the other Is a component configuration in which the second lead frame (10) and the second heat dissipation substrate (13) are arranged, so that the component configurations on both sides of the first semiconductor chip (7a) are symmetrical, One of the two sides sandwiching the second semiconductor chip (7b) has a component configuration in which the second lead frame (10) and the third heat dissipation substrate (14) are arranged, and the other is the third lead frame (11). Since the fourth heat dissipating substrate (15) is arranged as a component structure, the component structures on both sides of the second semiconductor chip (7b) are symmetrical.

  In this way, the component configurations arranged on both sides of the first and second semiconductor chips (7a, 7b) are symmetrical. For this reason, it becomes possible to reduce the curvature based on asymmetry. In particular, since the first conductor portions (12a to 15a) of the first to fourth heat radiating substrates (12 to 15) can have a solid structure, the first to fourth heat radiating substrates (12 to 15) can have the same structure. Therefore, the structures on both sides of the first and second semiconductor chips (7a, 7b) can be made more symmetrical. Therefore, it is possible to further reduce warping based on asymmetry.

  In the invention according to claim 5, between the place where the first semiconductor chip (7a) is arranged and the place where the second semiconductor chip (7b) is arranged in the second lead frame (10), An opening (10d) is provided.

  As described above, the portion that is not symmetrical with respect to the first and second semiconductor chips (7a, 7b), that is, the place where the first semiconductor chip (7a) is arranged in the second lead frame (10) and the first. 2 An opening (10d) is provided between the semiconductor chip (7b) and the place where the semiconductor chip (7b) is disposed. Thereby, the part of the second lead frame (10) can be reduced and the asymmetric part can be reduced as much as possible. Therefore, the symmetry on both sides of the first and second semiconductor chips (7a, 7b) is further increased, and the warp based on the asymmetry can be further reduced.

  The invention according to claim 6 is characterized in that a snubber circuit (40) is provided between the first lead frame (9) and the third lead frame (11).

  Thus, by providing the snubber circuit (40) between the first lead frame (9) and the third lead frame (11), it is possible to further reduce the inductance, thereby reducing the switching loss and suppressing the surge voltage. It is effective.

  The invention according to claim 7 is characterized in that the first terminal (P) and the third terminal (N) are a positive electrode terminal and a negative electrode terminal, and the positive electrode terminal and the negative electrode terminal are arranged adjacent to each other. .

  As described above, in the structure in which the positive electrode terminal and the negative electrode terminal are arranged adjacent to each other, the distance between the positive electrode terminal and the negative electrode terminal is reduced. For this reason, the area in the power supply closed loop is reduced, and the inductance L can be made relatively small. This is because magnetic flux cancellation works by passing currents in different directions at close positions, resulting in a small inductance.

  The invention according to claim 8 is characterized in that a concave portion (16a) or a convex portion (16b) is formed in the resin portion (16) between each of the first to third terminals (P). .

  Thus, by providing the concave portion (16a) and the convex portion (16b) in the resin portion (16), it is possible to increase the creeping distance and to reduce the distance between the positive electrode and the negative electrode terminal, thereby contributing to the reduction of inductance. To do. This means that the interval between the first to third terminals (P, O, N) is narrowed, and as a result, the semiconductor module can be reduced in size.

  In the invention according to claim 9, the resin constituting the resin part (16) is the first and second conductor parts (12a to 15a, 12c to 15c) provided in the first to fourth heat dissipation boards (12 to 15). It is a material having a smaller linear expansion coefficient than

  If it does in this way, expansion and contraction of the 1st and 2nd conductor parts (12a-15a, 12c-15c) can be suppressed by the resin part (16), and more of the 1st-4th heat dissipation board (12-15) can be suppressed. Warpage can be suppressed.

  According to a tenth aspect of the present invention, in the semiconductor module according to any one of the first to ninth aspects, a surface on which the first and fourth heat dissipation substrates (12, 15) are exposed, a second, a second, 3 The heat dissipation board (13, 14) is provided with heat sinks (51, 61) in which the refrigerant is circulated on both sides of the surface where the heat dissipation board (13, 14) is exposed.

  As described above, by disposing the heat sinks (51, 61) on both surfaces of the semiconductor module, a semiconductor device having a cooling mechanism can be obtained.

  In the invention according to claim 11, the heat sink (61) exposes the surface from which the first and fourth heat radiating substrates (12, 15) are exposed and the second and third heat radiating substrates (13, 14). It is directly mounted on the surface, and is characterized in that cooling is performed by a direct cooling method in which the refrigerant is brought into direct contact with the exposed surfaces of the first to fourth heat dissipation substrates (12 to 15).

  As described above, the first to fourth heat dissipation substrates (12 to 15) in which the insulating substrates (12b to 15b) are sandwiched between the first conductor portions (12a to 15a) and the second conductor portions (12c to 15c). Are joined to each lead frame (9 to 11). For this reason, between the 1st conductor part (12a-15a) and the 2nd conductor part (12c-15c) can be electrically isolate | separated by the insulated substrate (12b-15b). Therefore, it becomes possible to attach the heat sink (61) directly to the exposed surfaces of the first to fourth heat dissipation substrates (12 to 15), and cooling by the direct cooling method in which the refrigerant directly touches the exposed surfaces.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a circuit diagram of an inverter to which a semiconductor module according to a first embodiment of the present invention is applied. It is the figure which showed the semiconductor module with which an inverter is equipped, (a) is a top surface layout view, (b) is AA 'sectional drawing of (a), (c) is BB' sectional drawing of (a). It is. It is an exploded view of each part which comprises a semiconductor module. 6 is a cross-sectional view showing a manufacturing process of the semiconductor module 4. FIG. (A) is an enlarged view of a connecting portion between the conventional semiconductor chip J1 and the heat dissipation board J3, and (b) is the vicinity of the semiconductor chip 7a, the lead frame 10 and the heat dissipation board 13 of the semiconductor module 4 according to the first embodiment. FIG. 6 is a schematic diagram showing a range in which heat from semiconductor chips 7 and 8 is diffused. FIG. It is the front layout figure of the semiconductor module 4 which showed the mode at the time of changing arrangement | positioning of the positive electrode terminal P, the negative electrode terminal N, and the output terminal O. FIG. It is a front layout figure of semiconductor module 4 concerning a 2nd embodiment of the present invention. It is a front layout figure of semiconductor module 4 concerning the modification of a 2nd embodiment. It is sectional drawing of the semiconductor module 4 concerning 3rd Embodiment of this invention. It is a front layout figure of the semiconductor module 4 concerning 4th Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 5th Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 6th Embodiment of this invention. It is the graph which compared the cooling capability of the semiconductor device of the indirect cooling system of 5th Embodiment, and the semiconductor device of the direct cooling system of 6th Embodiment. It is sectional drawing of the semiconductor device provided with the conventional semiconductor module. It is the expanded sectional view which showed the enlarged view of the thermal radiation board | substrate J3, and the mode that the thermal radiation board | substrate J3 curved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. In the present embodiment, an inverter provided with a semiconductor module according to an embodiment of the present invention will be described as an example.

  1 is a circuit diagram of an inverter, FIG. 2 is a diagram showing a semiconductor module provided in the inverter, (a) is a top layout view, (b) is a cross-sectional view taken along line AA ′ of (a), c) is a BB ′ cross-sectional view of (a). FIG. 3 is an exploded view of each part constituting the semiconductor module.

  As shown in FIG. 1, the inverter 1 is for AC driving a three-phase motor 3 that is a load based on a DC power source 2, and has a configuration in which upper and lower arms connected in series are connected in parallel for three phases. An intermediate potential between the upper arm and the lower arm is applied to the U-phase, V-phase, and W-phase of the three-phase motor 3 while being sequentially switched. One phase of the upper arm and the lower arm of the inverter 1 is a single semiconductor module 4, and the inverter 1 is configured by including three semiconductor modules 4 shown in FIGS. 2 and 3. For example, the inverter 1 is configured by unitizing and integrating three semiconductor modules 4. The capacitor 1a connected in parallel with the inverter 1 is a smoothing capacitor and is inserted for inductance reduction.

  Moreover, as shown in FIG. 1, each upper arm and each lower arm are comprised by IGBT5 and FWD6 which are semiconductor power elements, respectively. In this embodiment, the semiconductor chip 7 on which the IGBT 5 is formed and the semiconductor chip 8 on which the FWD 6 is formed (both see FIGS. 2 and 3) are separate chips, and the emitter-collector of the IGBT 5 and the anode-cathode of the FWD 6 are Electrically connected. Further, the positive terminal P, the negative terminal N, the output terminal O, and the signal line terminals S1 and S2 of the upper arm of each semiconductor module 4 are projected so as to be exposed to the outside as shown in FIG. Then, the positive and negative terminals of the DC power source 2 and the three-phase motor 3 are connected to the positive terminal P, the negative terminal N and the output terminal O, respectively, so that the circuit configuration shown in FIG. In such a configuration, the inverter 1 is driven by controlling the gate voltage of the IGBT 5 by controlling the input voltage to the signal line terminals S1 and S2.

  Next, the detailed structure of the semiconductor module 4 provided in the inverter 1 configured as described above will be described.

  As shown in FIGS. 2 and 3, the semiconductor module 4 includes semiconductor chips 7 and 8, lead frames 9, 10, and 11, heat dissipation substrates 12 to 15 and the like, which are shown in FIGS. ), The structure is integrated by being resin-sealed by the resin portion 16.

  The semiconductor chips 7 and 8 are configured using Si, SiC, GaN or the like as a base material substrate. The semiconductor chip 7 includes a semiconductor chip 7a on which the upper arm side IGBT 5 is formed and a semiconductor chip 7b on which the lower arm side IGBT 5 is formed. The semiconductor chip 8 includes a semiconductor chip 8a in which the FWD 6 on the upper arm side is formed and a semiconductor chip 8b in which the FWD 6 on the lower arm side is formed. Both of the semiconductor chips 7a and 7b are configured such that the IGBT 5 is a vertical element that allows current to flow in the vertical direction of the substrate, and the semiconductor chips 8a and 8b are both configured as vertical elements that allow the current to flow in the vertical direction of the substrate. It is composed. For example, the semiconductor chips 7a and 7b have a structure in which a signal line electrode 71 including a gate electrode and an emitter electrode 72 are disposed on the front surface side, and a collector electrode 73 is disposed on the entire rear surface side. The semiconductor chips 8a and 8b have a structure in which an anode electrode 81 is formed on the front surface side and a cathode electrode 82 is formed on the entire back surface side.

  In the case of this embodiment, the left side of the paper in FIGS. 2A and 2B is the upper arm, and the right side of the paper is the lower arm. For this reason, the semiconductor chip 7a is arranged with the signal line electrode 71 and the emitter electrode 72 including the gate electrode directed upward on the paper surface and the collector electrode 73 directed downward on the paper surface. The semiconductor chip 7b is turned upside down with respect to the semiconductor chip 7a. The signal line electrode 71 and the emitter electrode 72 including the gate electrode are directed below the paper surface, and the collector electrode 73 is directed above the paper surface. Similarly, the semiconductor chip 8a is arranged with the anode electrode directed upward on the paper surface and the cathode electrode directed downward on the paper surface. The semiconductor chip 8b is arranged with the cathode electrode directed upward on the paper surface and the anode electrode directed downward on the paper surface. As shown in FIG. 2A, the upper-arm semiconductor chips 7a and 8a are arranged in the vertical direction on the paper surface, and the lower-arm semiconductor chips 7b and 8b are arranged in the vertical direction on the paper surface.

  The lead frames 9 to 11 include a lead frame 9 including a positive terminal P, a lead frame 10 including a signal line terminal S1 connected to the output terminal O and the semiconductor chip 7a of the upper arm, a negative terminal N and an upper arm. There is a lead frame 11 including a signal line terminal S2 connected to the semiconductor chip 7a.

  The lead frame 9 is composed of a plate-shaped conductor, is composed of a metal plate having Cu, Al, Fe or the like as a main component and has an area connected to the heat dissipation substrate 12, and is formed by, for example, pressing a metal plate Is done. The upper arm semiconductor chips 7a and 8a are mounted on the lead frame 9, and the surface of the semiconductor chip 7a on the side of the collector electrode 73 and the surface of the semiconductor chip 8a on the side of the cathode electrode 82 are covered through the bonding materials 20 and 21. It is joined. Further, the lead frame 9 is provided with a positive terminal P, which extends from the square plate-like portion 9 a to one side in the arrangement direction of the semiconductor chips 7 a and 8 a and is drawn out of the resin portion 16.

  The lead frame 10 is also made of a plate-like conductor, and is made of a metal plate having an area connected to the heat dissipation boards 13 and 14, for example, mainly composed of Cu, Al, Fe, etc., for example, pressing the metal plate Is formed. All of the upper arm semiconductor chips 7a and 8a and the lower arm semiconductor chips 7b and 8b are connected to the lead frame 10. Specifically, the signal line electrode 71 and the emitter electrode 72 including the gate electrode of the semiconductor chip 7a of the upper arm are connected to the lead frame 10, and the anode electrode 81 of the semiconductor chip 8a is connected to the lead frame 10. The collector electrode 73 of the semiconductor chip 7b is connected and the cathode electrode 82 of the semiconductor chip 8b is connected. As shown in FIG. 2C, for the upper arm, the semiconductor chip 7a has a signal line electrode 71 including a gate electrode connected to the lead frame 10 via the bonding material 22 and an emitter electrode 72 via the bonding material 23. In the semiconductor chip 8 a, the anode electrode 81 is connected to the lead frame 10 through the bonding material 24. Further, as shown in FIG. 3, for the lower arm, the semiconductor chip 7b has the collector electrode 73 connected to the lead frame 10 through the bonding material 25, and the semiconductor chip 8b has the cathode electrode 82 connected through the bonding material 26. Are connected to the lead frame 10.

  The lead frame 10 is provided with an output terminal O and a signal line terminal S 1, and is drawn out of the resin portion 16.

  The output terminal O is connected to the portion of the lead frame 10 to which the emitter electrode 72 of the semiconductor chip 7a and the anode electrode 81 of the semiconductor chip 8a are connected, and the collector electrode 73 of the semiconductor chip 7b and the cathode electrode 82 of the semiconductor chip 8b. It is extended from the square plate-shaped part 10a of the large area used as a part to become. Specifically, it extends from the corner where the semiconductor chip 8b is arranged among the four corners of the square plate-like portion 10a and is drawn out in the same direction as the positive terminal P. Further, the output terminal O is bent in the middle and has the same height as the positive terminal P of the lead frame 9.

  The signal line terminal S1 is disposed at a corner located diagonally to the corner where the output terminal O is disposed, among the four corners of the square plate-like portion 10a. A plurality of signal line terminals S1 are provided, and the final product has a structure that can be separated from the square plate-like portion 10a. That is, each signal line terminal S1 has the arrangement direction of the semiconductor chips 7a and 8a as the longitudinal direction, and the end on the square plate-like portion 10a side is separated from the square plate-like portion 10a. It is connected to the frame part 10b extended from the square plate-like part 10a. The signal line terminal S1 is separated from the square plate-shaped portion 10a by finally cutting and cutting the frame portion 10b. Note that the end of the signal line terminal S1 opposite to the square plate-like portion 10a is also connected by the frame portion 10c, but this frame portion 10c is finally cut and separated. For this reason, the signal line terminals S1 are finally separated from each other.

  Further, the end of the signal line terminal S1 on the square plate-like portion 10a side is made thinner than the plate thickness of the square plate-like portion 10a. Specifically, as shown in FIG. 2C, the surface on the semiconductor chip 7a side of the end on the square plate-like portion 10a side of the signal line terminal S1 is flush with the square plate-like portion 10a. However, the surface on the opposite side is positioned lower than the square plate-like portion 10b. For this reason, as indicated by an arrow in the figure, a space is provided between the signal line terminal S1 and the heat dissipation board 13.

  Further, a through hole 17 penetrating the front and back is formed at the end of the signal line terminal S1 on the side of the square plate portion 10a, that is, the end of the side connected to the signal line electrode 71 including the gate electrode of the semiconductor chip 7a. The bonding material 22 enters the through hole 17. For this reason, the joining material 22 enters the through-hole 17 and can be reliably joined, and the through-hole 17 functions as an anchor so that the joining material 22 is difficult to come out of the through-hole 17. Thereby, it becomes possible to join the joining material 22 and the signal line terminal S1 more firmly. Further, the signal line terminal S1 is bent at an intermediate position in the longitudinal direction, and the end opposite to the square plate-like portion 10a is set to the same height as the lead frame 9.

  A through hole 19 is also formed on the side farther from the semiconductor chip 7a than the through hole 17 in the signal line terminal S1. The resin can be flowed when the resin sealing is performed by the resin portion 16 by the through-hole 19, so that the resin filling property (wraparound) can be further improved.

  The lead frame 11 is also composed of a plate-like conductor, which is composed of a metal plate having, for example, Cu, Al, Fe, etc. as a main component and an area connected to the heat dissipation substrate 15, for example, by pressing the metal plate. It is formed. The lead frame 11 is connected to lower-arm semiconductor chips 7b and 8b. Specifically, in the semiconductor chip 7 b, the signal line electrode 71 including the gate electrode is connected to the lead frame 11 through a bonding material (not shown), and the emitter electrode 72 is connected to the lead frame 11 through the bonding material 27. In the semiconductor chip 8 b, the anode electrode 81 is connected to the lead frame 11 through the bonding material 28.

  The lead frame 11 is provided with a negative electrode terminal N and a signal line terminal S 2, and is drawn out of the resin portion 16.

  The negative electrode terminal N extends from a wide-area square plate-like portion 11a in the lead frame 11, which is a portion to which the emitter electrode 72 of the semiconductor chip 7b and the anode electrode 81 of the semiconductor chip 8b are connected. Specifically, the negative electrode terminal N extends in one of the arrangement directions of the semiconductor chips 7b and 8b at a position between the positive electrode terminal P provided on the lead frame 9 and the output terminal O provided on the lead frame 10. And is pulled out of the resin portion 16.

  The signal line terminal S2 is arranged on the opposite side to the side where the negative electrode terminal N is arranged in the square plate-like portion 11a. A plurality of signal line terminals S2 are also provided, and the final product has a structure that can be separated from the square plate-like portion 11a. That is, each signal line terminal S2 has the longitudinal direction of the arrangement direction of the semiconductor chips 7b and 8b, and the end on the square plate-like portion 11a side is separated from the square plate-like portion 11a. It is connected to a frame portion 11b extended from the square plate portion 11a. The signal line terminal S2 is separated from the square plate-shaped portion 11a by finally cutting and cutting the frame portion 11b. Note that the end of the signal line terminal S2 opposite to the square plate-like portion 11a is also connected by the frame portion 11c, but this frame portion 11c is finally cut and separated. For this reason, the signal line terminals S2 are finally separated from each other.

  Further, a through hole 18 penetrating the front and back of the signal line terminal S2 is formed at the tip of the signal line terminal S2 on the square plate-like portion 11a side, that is, the portion connected to the signal line electrode 71 including the gate electrode of the semiconductor chip 7b. Is formed. The through hole 18 plays the same role as the through hole 17 in the signal line terminal S1. A bonding material (not shown) that connects between the signal line terminal S <b> 2 and the signal line electrode 71 enters the through hole 18.

  Although not shown in the cross section, the thickness of the signal line terminal S2 on the side connected to the signal line electrode 71 including the gate electrode, that is, the side of the square plate-like portion 11a, is the same as that of the signal line terminal S1. It is made thinner than the shape portion 11a. Further, a through hole 19 is also formed on the side farther from the semiconductor chip 7a than the through hole 18 in the signal line terminal S2, so that the resin filling property (wraparound) at the time of resin sealing is improved.

  The heat dissipating substrates 12 to 15 are formed in a square plate shape, and are joined to the surface of the lead frames 9 to 11 opposite to the surface on which the semiconductor chips 7 and 8 are disposed, thereby the semiconductor chips 7a and 7b and the like. The heat generated is dissipated. Each heat dissipation board 12-15 is set as the structure which has conductor parts 12a-15a, insulation board | substrates 12b-15b, and conductor parts 12c-15c. The conductor portions 12a to 15a and the conductor portions 12c to 15c included in the heat dissipation substrates 12 to 15 are both configured by a solid structure that is not divided with respect to the insulating substrates 12b to 15b. It is formed symmetrically on both sides. That is, when two intersecting sides of the rectangular plate-like heat dissipation boards 12 to 15 are regarded as the X axis and the Y axis, the conductor parts 12a to 15a and the conductor parts 12c to 15c are basically the same in both the X axis direction and the Y axis direction. In particular, the shape is symmetrical and the thickness is also equal. The conductor portions 12a to 15a and the conductor portions 12c to 15c are basically preferably completely symmetrical, but the conductor portions 12a to 15a and the conductor portions 12c to 15c are formed of the heat dissipation substrates 12 to 15. It is only necessary that the arrangement locations coincide so that the areas of at least 80%, preferably 95% or more overlap when viewed from the normal direction.

The conductor portions 12a to 15a are portions arranged on the lead frames 9 to 11 side with respect to the insulating substrates 12b to 15b, and are respectively connected to the lead frames 9 to 11 via the bonding materials 29, 30, 31, and 32, respectively. It is connected. The insulating substrates 12b to 15b are disposed between the conductor portions 12a to 15a and the conductor portions 12c to 15c, and insulate them. The conductor portions 12c to 15c are disposed on the opposite side to the lead frames 9 to 11 with respect to the insulating substrates 12b to 15b, and the surface opposite to the insulating substrates 12b to 15b is exposed from the resin portion 16. ing. The conductor parts 12a to 15a and the conductor parts 12c to 15c are made of a material mainly composed of Cu, Al, Fe or the like, and are made of, for example, a Cu thick film having a thickness of 0.3 to 0.8 mm. The insulating substrates 12b to 15b are made of, for example, SiN, AlN, Al ₂ O _{3 having a} thickness of 0.1 to 0.5 mm.

  The resin part 16 is comprised with the material whose linear expansion coefficient is lower than the constituent material of the conductor parts 12a-15a, 12c-15c with which the thermal radiation board | substrates 12-15 are equipped. If it does in this way, expansion / contraction of the conductor parts 12a-15a and 12c-15c can be suppressed by the resin part 16, and it becomes possible to suppress the curvature of the thermal radiation boards 12-15 more.

  The semiconductor module 4 according to the present embodiment is configured by the above structure. Then, the manufacturing method of the semiconductor module 4 comprised in this way is demonstrated. FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor module 4 according to the present embodiment, and shows a manufacturing process in a cross section corresponding to FIG.

[Step shown in FIG. 4 (a)]
Lead frames 9 to 11 formed by punching a metal plate or the like are prepared (however, only the lead frames 9 and 10 are shown in the drawing. In the following drawings, the cross section corresponding to FIG. 2C) Although only described, the description of each step is also performed for portions other than the cross section of FIG. Then, the bonding materials 20, 21, 27, and 28 are installed at the locations where the semiconductor chips 7 a, 7 b, 8 a, and 8 b are to be mounted on the surfaces of the lead frames 9 and 11. In addition, solders 23 to 26 are installed at locations corresponding to the semiconductor chips 7a, 7b, 8a, and 8b on the surface of the lead frame 10, and a bonding material 22 is installed on the signal line terminal S1, and also illustrated on the signal line terminal S2. Do not install bonding material. Further, heat radiation boards 12 to 15 (only the heat radiation boards 12 and 13 are shown in the figure) are prepared, and the portions corresponding to the connection points with the lead frames 9 to 11 among the heat radiation boards 12 to 15. Also, the bonding materials 29 to 32 are installed.

  For example, the bonding materials 20, 21, 23 to 26, and 29 to 32 are formed by applying a solid material such as a solder foil, a sintered Ag paste, or the like by printing or dispensing. The bonding material 22 of the signal line terminal S1 and the bonding material of the signal line terminal S2 are installed by first fixing them by reflow processing after mounting solder balls or the like in the corresponding places. By the reflow process at this time, the bonding materials 20, 21, 23 to 26, and 29 to 32 may be temporarily attached.

  Further, the bonding material 22 of the signal line terminal S1 and the bonding material of the signal line terminal S2 are higher than the bonding materials 20, 21, 23 to 28 and have a low melting point (preferably a low melting point of about 10 ° C.). It is configured. For example, the bonding material 22 of the signal line terminal S1 and the bonding material of the signal line terminal S2 are made of SnAgCu (melting point 218 ° C.), and the bonding materials 20, 21, 23 to 28 are made of SnCuNi (melting point 228 ° C.). It is composed. In addition, although there is no restriction | limiting in particular about height and melting | fusing point about the bonding materials 29-32, these are also comprised by SnCuNi type | system | group (melting | fusing point 228 degreeC).

[Step shown in FIG. 4B]
The heat dissipation substrates 12 to 15 and the lead frames 9 to 11 are bonded to each other through the bonding materials 29 to 32. Then, after arranging the lead frame 9 to which the heat dissipation substrate 12 is bonded and the lead frame 11 to which the heat dissipation substrate 15 is bonded, the semiconductor chips 7a, 7b, 8a, and 8b are mounted on the bonding materials 20, 21, 27, and 28. To do. Thereafter, the lead frame 10 on which the heat dissipation boards 13 and 14 are joined is turned over, that is, mounted so that the lead frame 10 side faces the lead frames 9 and 11.

[Step shown in FIG. 4 (c)]
Perform reflow processing. As shown in FIG. 4B, when the lead frame 10 to which the heat dissipation boards 13 and 14 are bonded is mounted, the bonding material 22 of the signal line terminal S1 and the bonding material of the signal line terminal S2 are bonded to the bonding materials 20, 21, Since the height is higher than 23 to 28, the lead frame 10 is inclined to cause backlash.

  However, when each of the bonding materials 20 to 32 is melted by the reflow process, the inclination of the lead frame 10 is corrected and becomes horizontal, so that rattling can be eliminated. In particular, as described above, if the bonding material 22 is made of a material having a melting point lower than that of the bonding materials 20, 21, 23 to 28, the bonding material 22 that is the inclination factor of the lead frame 10 is first melted and loaded. Therefore, the height of the bonding material 22 can be matched with the height of the bonding materials 20, 21, 23 to 28. In the case of this embodiment, since the through holes 17 and 18 are formed in the signal line terminals S1 and S2, the excess of the bonding material 22 escapes into the through holes 17 and 18, and the height of the bonding material 22 is further increased. The height of the bonding material 20, 21, 23 to 28 can be matched. Then, by raising the temperature of the reflow treatment after the heights of the bonding materials 20 to 28 are further increased, all the bonding materials 20 to 32 are melted, and the respective portions are bonded by the bonding materials 20 to 32.

[Step shown in FIG. 4 (d)]
After performing primer treatment with polyimide, polyamide, or the like as necessary, each part joined by the joining materials 20 to 32 is placed in a molding die (not shown), and resin injection is performed. Stop. Thus, the semiconductor module 4 having the structure shown in FIG. 2 is configured. Thereafter, unnecessary portions such as the frame portions 10b, 10c, 11b, and 11c are cut. At this time, since the cut portions of the frame portions 10b and 11b are exposed from the resin portion 16, it is preferable to cover them with an insulating resin that can be cured at a low temperature. In this way, the semiconductor module 4 according to the present embodiment is completed.

  According to the semiconductor module 4 and the method for manufacturing the semiconductor module 4 as described above, the following effects can be obtained.

  (1) In this embodiment, the heat dissipation boards 12 to 15 are connected to the lead frames 9 to 11, but the semiconductor chips 7a, 7b, 8a, and 8b are directly connected to the lead frames 9 to 11. The structure is not connected via the conductor portions 12a to 15a of the heat dissipation boards 12 to 15. For this reason, the following effect can be acquired. This effect will be described with reference to FIG.

  FIG. 5A is an enlarged view of a connection portion between the conventional semiconductor chip J1 and the heat dissipation substrate J3, and FIG. 5B is a semiconductor chip 7a, the lead frame 10 and the heat dissipation substrate of the semiconductor module 4 according to the present embodiment. FIG.

  As shown in FIG. 5A, conventionally, the signal line electrode of the semiconductor chip J1 is connected to the lead frame J5 via the copper foil J3a of the heat dissipation board J3, and the emitter electrode is also connected to the copper foil J3a of the heat dissipation board J3. And connected to the lead frame J6. For this reason, the copper foil J3a must be divided, and the copper foil J3a and the copper foil J3c arranged on the front and back of the insulating substrate J3b do not have a symmetrical pattern. Thereby, a curvature will generate | occur | produce in the thermal radiation board | substrate J3.

  On the other hand, as shown in FIG. 5B, in this embodiment, the semiconductor chip 7a is not connected to the lead frame 10 through the conductor portions 12a and 13a of the heat dissipation substrates 12 and 13. For this reason, the conductor parts 12a and 13a can be made into the solid structure which is not divided | segmented. Therefore, it is possible to suppress the occurrence of warpage in the heat dissipation substrates 12 and 13 when the temperature is lowered from high temperature to room temperature after resin sealing at a high temperature. Therefore, the connection between the semiconductor chip 7a and the lead frames 9, 10 and the connection between the lead frames 9, 10 and the heat dissipation substrates 12, 13 can be performed satisfactorily. In addition, in FIG.5 (b), although the heat dissipation board | substrates 12 and 13 are mentioned as an example, the same thing can be said also about the heat dissipation board | substrates 14 and 15. FIG.

  (2) Further, in the conventional semiconductor module, the component configurations on both sides of the semiconductor chips J1 and J2 are not symmetrical. That is, as shown in FIG. 15, the signal line electrode including the gate electrode of the semiconductor chip J1, the emitter electrode side, and the anode electrode side of the semiconductor chip J2 are directly connected to the heat radiating substrate J3. The structure is connected to the heat dissipation board J9 via J7 and J8. For this reason, warping based on asymmetry occurs due to the fact that the component configurations on both sides of the semiconductor chips J1 and J2 are not symmetrical.

  On the other hand, in the semiconductor module 4 of this embodiment, the component structure arrange | positioned on both sides on both sides of the semiconductor chips 7 and 8 becomes a symmetrical structure. For this reason, it becomes possible to reduce the curvature based on asymmetry. In particular, in the case of the present embodiment, since the conductor portion 13a of the heat dissipation board 13 can be a solid structure, both the heat dissipation boards 12 and 13 can have the same structure. Can be made more symmetrical. Therefore, it is possible to further reduce warping based on asymmetry.

  In the case of the semiconductor module 4 of the present embodiment, the heat dissipation substrates 13 and 14 connected to the lead frame 10 can be configured with a single substrate without being divided. Further, the heat radiating substrates 12 and 15 can also be configured as a single substrate without being divided if the conductor portions 12a and 15a are insulated and separated to have different potentials. However, since the heat dissipation substrates 12 to 15 are separate substrates, the structures on both sides of the semiconductor chips 7 and 8 can be made symmetrical. For this reason, it becomes possible to reduce the curvature based on the above asymmetry.

  Moreover, when comprising the thermal radiation boards 12-15 by a separate board | substrate, it is preferable to divide each thermal radiation board | substrate 12-15 into the minimum size. That is, the warpage increases as the size of each of the heat dissipation boards 12-15 increases, so that the warpage can be reduced by making the heat dissipation boards 12-15 as small as possible. In addition, since the space for the resin to enter increases compared to the case of using a single substrate, the resin flowability (wraparound property) can be improved, and the resin filling property can be improved. Become. However, since the heat dissipation substrates 12 to 15 radiate heat from the semiconductor chips 7 and 8, the heat dissipation substrates 12 to 15 have dimensions that do not cause thermal interference in consideration of the range in which heat from the semiconductor chips 7 and 8 is diffused. Is preferred. FIG. 6 is a schematic diagram showing a range in which heat from the semiconductor chips 7 and 8 is diffused. As shown in this figure, heat is diffused at an angle of 45 ° from the semiconductor chips 7 and 8. In consideration of this, it is preferable to determine the dimensions of the heat dissipation substrates 12 to 15 so that the ranges in which heat diffuses do not overlap.

  (3) Furthermore, in the semiconductor module 4 of this embodiment, the positive electrode terminal P, the negative electrode terminal N, and the output terminal O are arranged so as to be arranged in that order, and the positive electrode terminal P and the negative electrode terminal N are arranged adjacent to each other. To be. As shown in FIG. 1, a smoothing capacitor 1a is inserted in parallel with the inverter 1 to reduce the inductance. However, in order to further reduce the inductance, the positive terminal P and the negative electrode are connected. It is preferable that the terminal N be arranged close to the terminal N.

  FIG. 7 is a front layout view of the semiconductor module 4 showing a state where the arrangement of the positive terminal P, the negative terminal N, and the output terminal O is changed. As shown in FIG. 7B, when the positive terminal P, the output terminal O, and the negative terminal N are arranged in that order, the distance between the positive terminal P and the output terminal O is increased. For this reason, the area in the power supply closed loop shown in the figure becomes large, and the inductance L becomes relatively large. On the other hand, as shown in FIG. 7A, in the structure in which the positive electrode terminal P and the negative electrode terminal N are arranged next to each other as in the present embodiment, the distance between the positive electrode terminal P and the negative electrode terminal N is short. For this reason, the area in the power supply closed loop shown in the figure is reduced, and the inductance L can be made relatively small. This is because magnetic flux cancellation works by passing currents in different directions at close positions, resulting in a small inductance.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the structure of the lead frame 10 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only different parts will be described.

  FIG. 8 is a front layout view of the semiconductor module 4 according to the present embodiment. As shown in this figure, in the present embodiment, between the region where the semiconductor chips 7a, 8a of the upper arm are arranged and the region where the semiconductor chips 7b, 8b of the lower arm are arranged in the lead frame 10. The structure is provided with a plurality of openings 10d.

  As described above, the semiconductor module 4 preferably has a symmetrical structure on both sides of the semiconductor chips 7 and 8. However, as can be seen from the cross-sectional view of FIG. 2B, only the region of the lead frame 10 where the semiconductor chips 7a, 8a of the upper arm are arranged and the semiconductor chips 7b, 8b of the lower arm are arranged. An asymmetric part is formed between the regions.

  For this reason, in this embodiment, by providing a plurality of openings 10d in this part, the part of the lead frame 10 is reduced, and the asymmetric part is reduced as much as possible. Thereby, the symmetry of both sides across the semiconductor chips 7 and 8 is further increased, and it is possible to further reduce the warp due to the asymmetry.

(Modification of the second embodiment)
In the second embodiment, the number of openings 10d is arbitrary and may be any number. In other words, FIG. 8 shows a case where seven openings 10d are formed, but for example, three openings 10d may be provided as shown in FIG. Of course, there may be one, or a plurality other than three or seven. However, the wiring connecting the upper arm and the lower arm between the region of the lead frame 10 where the semiconductor chips 7a, 8a of the upper arm are disposed and the region of the semiconductor chips 7b, 8b of the lower arm is disposed. A large current flows through this wiring. For this reason, if the number of openings 10d is increased or the size of the openings 10d is increased, the cross-sectional area of the wiring connecting the upper arm and the lower arm is decreased and the wiring resistance is increased. It is preferable to design the number of openings 10d in consideration of resistance.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, the structure of the resin portion 16 is changed with respect to the first embodiment, and the others are the same as those in the first embodiment, and therefore only different portions will be described.

  FIG. 10 is a cross-sectional view of the semiconductor module 4 according to the present embodiment. As shown in this figure, in this embodiment, a snubber circuit 40 is provided between the lead frame 9 and the lead frame 11. The snubber circuit 40 is a circuit configured by a resistor R, a capacitor C, a diode Di, and the like, and plays a role of reducing an inductance L configured between the lead frame 9 and the lead frame 11.

  In the semiconductor module 4, a current flows through a current path in the order of the lead frame 9 → the semiconductor chips 7 a and 8 a → the lead frame 10 → the semiconductor chips 7 b and 8 b → the lead frame 11. At this time, a large potential difference is generated between the lead frame 9 and the lead frame 11. Then, the value obtained by multiplying the inductance L by the current time change di / dt becomes the surge voltage ΔV, and if this surge voltage ΔV is large, insulation assurance and switching loss increase become problems, so the inductance L is made as small as possible. Is preferred.

  Therefore, by providing the snubber circuit 40 between the lead frame 9 and the lead frame 11 as in this embodiment, if the inductance L between them is reduced, the inductance can be further reduced, and the switching loss. It is effective for reduction and suppression of surge voltage.

  Such a snubber circuit 40 may be arranged in any form between the lead frame 9 and the lead frame 11, but in this embodiment, the end faces of the lead frame 9 and the lead frame 11 that face each other. The snubber circuit 40 is disposed so as to be sandwiched between them. In this way, the space between the lead frame 9 and the lead frame 11 can be effectively utilized, and a space for arranging the snubber circuit 40 can be eliminated.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In the present embodiment, the structure of the resin portion 16 is changed with respect to the first embodiment, and the others are the same as those in the first embodiment, and therefore only different portions will be described.

  FIG. 11 is a partially enlarged view of the semiconductor module 4 according to the present embodiment. As shown in this figure, in this embodiment, a concave portion 16a is provided between the positive electrode terminal P and the negative electrode terminal N in the resin portion 16, or a convex portion 16b is provided between the negative electrode terminal N and the output terminal O. I am doing so.

  In the semiconductor module 4 as in the first and second embodiments, the exposed conductor portions 12c to 15c of the heat dissipation substrates 12 to 15 are internally insulated by the insulating substrates 12b to 15b, and there are portions where a potential difference occurs. Inside the resin part 16. For this reason, even if it electrically connects between the conductor part 12c and the conductor part 15c, or between the conductor part 13c and the conductor part 14c, there is no problem and you may narrow between these.

  However, with respect to the positive terminal P, the negative terminal N, and the output terminal O exposed from the resin portion 16, potential differences occurred between the positive terminal P and the negative terminal N and between the negative terminal N and the output terminal O. It becomes a state. For this reason, it is necessary to earn a creepage distance between them. On the other hand, if the concave portions 16a and the convex portions 16b are provided between them as in the present embodiment, it is possible to increase the creepage distance and reduce the distance between the positive electrode and the negative electrode terminal. Contributes to inductance reduction. This means that the intervals between the positive terminal P and the negative terminal N and between the negative terminal N and the output terminal O are narrowed. As a result, the semiconductor module 4 can be downsized. In addition, the area inside the power supply closed loop is reduced, the inductance L can be made relatively small, and the current can be canceled by passing the currents in different directions at close positions, and the inductance L can be further reduced. It becomes possible.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. In the present embodiment, a semiconductor device to which the semiconductor module 4 described in the first to fourth embodiments is applied will be described. Here, a semiconductor device to which the semiconductor module 4 shown in the third embodiment is applied will be described as an example, but of course, as a semiconductor device to which the semiconductor module 4 shown in the first, second, and fourth embodiments is applied. Also good.

  FIG. 12 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, heat sinks 51 are provided on both surfaces of the semiconductor module 4 via grease 50. The fins 50 are provided inside the heat sink 51, and a coolant such as cooling water is recirculated through a cooling device (not shown). With such a configuration, cooling by an indirect cooling method in which heat generated by the semiconductor module 4 via the grease 50 is indirectly cooled can be performed. As described above, by disposing the heat sinks 51 on both surfaces of the semiconductor module 4, a semiconductor device having a cooling mechanism can be obtained.

(Sixth embodiment)
A sixth embodiment of the present invention will be described. In this embodiment, the structure of the cooling mechanism is changed with respect to the fifth embodiment, and the other parts are the same as those in the fifth embodiment, and therefore only different parts will be described.

  FIG. 13 is a cross-sectional view of the semiconductor device according to the present embodiment. As shown in this figure, a case 61 having a side wall surrounding one side as a bottom surface and surrounding the periphery of the semiconductor module 4 with an opening on the opposite side of the bottom surface and fins 60 protruding from the bottom is disposed on both sides of the semiconductor module 4. Yes. In the case 61, a coolant such as cooling water is recirculated through a cooling device (not shown). The case 61 is arranged such that the fins 60 are pierced into the heat radiation boards 12 to 15, and the seal ring 62 is arranged between the side wall of the case 61 and the resin part 16, so that refrigerant leakage can be prevented. is there.

  With such a configuration, it is possible to perform cooling by a direct cooling method in which the semiconductor module 4 is directly cooled by the refrigerant.

  The heat sink 61 can be attached to the exposed surfaces of the heat dissipation boards 12 to 15 to enhance the cooling function. However, when the exposed surfaces are in conduction with the lead frames 9 to 11, the exposed surfaces are insulated. A cooling device or the like is attached with a film or the like. That is, only the indirect cooling method as described in the fifth embodiment can be adopted. However, in the semiconductor module 4 described in the first to fourth embodiments, the heat dissipating substrates 12 to 15 in which the insulating substrates 12b to 15b are sandwiched between the conductor portions 12a to 15a and the conductor portions 12c to 15c are connected to the lead frames 9. ~ 11. For this reason, between the conductor parts 12a-15a and the conductor parts 12c-15c can be electrically isolate | separated by the insulated substrates 12b-15b. Therefore, it becomes possible to attach the heat sink 61 directly to the exposed surfaces of the heat dissipation substrates 12 to 15, and cooling by a direct cooling method in which the refrigerant is directly brought into contact with the exposed surfaces.

  FIG. 14 is a graph comparing the cooling capacities of the indirect cooling semiconductor device of the fifth embodiment and the direct cooling semiconductor device of the present embodiment. As shown in this figure, according to the direct cooling method, it is possible to reduce the thermal resistance by about 15% as compared with the indirect cooling method. For this reason, it becomes possible to improve a cooling capability by being able to employ | adopt a direct cooling system like this embodiment.

  Here, the semiconductor device to which the semiconductor module 4 shown in the third embodiment is applied has been described as an example, but of course, as a semiconductor device to which the semiconductor module 4 shown in the first, second, and fourth embodiments is applied. Also good.

(Other embodiments)
In the above embodiments, the semiconductor module 4 having a 2in1 structure has been described as an example. However, a 1 in 1 structure may be used, and the present invention can also be applied to a 6 in 1 structure in which six semiconductor power elements of three upper arms and lower arms are sealed in one resin portion.

In addition, since each said embodiment is 2in1 structure, it can be grasped | ascertained that this invention is applied to each of an upper arm and a lower arm. That is, in the present invention, when the first terminal is the positive terminal P and the first lead frame is the lead frame 9, the second terminal is the output terminal O and the second lead frame is the lead frame 10, but the first terminal is the output. When the first lead frame is the lead frame 10 at the terminal O, the second terminal is the negative terminal N and the second lead frame is the lead frame 11.

In each of the above embodiments, the semiconductor chip 7a on which the IGBT is formed and the semiconductor chip 8a on which the FWD is formed are separated from each other, and the semiconductor chip 7 on which the IGBT is formed.
b and the semiconductor chip 8b on which the FWD was formed were formed as separate chips. However, each of these may be a single chip.

  In the above embodiment, a vertical structure IGBT is taken as an example of the semiconductor power element, but a vertical structure power MOSFET may be used. That is, the present invention is applied to the semiconductor module 4 using the semiconductor chip 7a, 7b having a structure in which the signal line electrode is formed on the front surface side, the front surface electrode is formed, and the back surface electrode is formed on the back surface side. Can be applied.

  In addition, the design and the like of various parts provided in the semiconductor module 4 described in the above embodiments can be appropriately changed. For example, the portions of the lead frames 9 to 11 that are joined to the semiconductor chips 7 and 8 are the rectangular plate-like portions 9a to 11a, but they are not necessarily square.

1 Inverter 2 DC power supply 3 Three-phase motor 4 Semiconductor module 5 IGBT
6 FWD
7 (7a, 7b) Semiconductor chip 8 (8a, 8b) Semiconductor chip 9, 10, 11 Lead frame 9a, 10a, 11a Square plate-like part 10b, 10c, 11b, 11c Frame part 12-15 Heat radiation board 12a-15a, 12c to 15c Conductor portion 12b to 15b Insulating substrate 16 Resin portion 17, 18, 19 Through hole 20 to 32 Bonding material 71 Signal line electrode 72 Emitter electrode (surface electrode)
73 Collector electrode (back electrode)
81 Anode electrode 82 Cathode electrode

Claims (11)

A semiconductor power element having a front surface and a back surface and having a vertical structure is formed, a signal line electrode (71) is formed on the front surface side, a front surface electrode (72) is formed, and a back surface electrode (73) is formed on the back surface side. A semiconductor chip (7a) formed with
A first lead frame (9) connected to the back electrode (73) of the semiconductor chip (7a) and provided with a first terminal (P);
A plate-like portion connected to the signal line electrode (71) and the surface electrode (72) connected to the signal line electrode (71) of the semiconductor chip (7a) and extended with the second terminal (O). A second lead frame (10) provided with (10a);
A first heat dissipation substrate (12) joined to a surface of the first lead frame (9) opposite to a surface on which the semiconductor chip (7a) is disposed;
A second heat dissipating substrate (13) joined to a surface of the second lead frame (10) opposite to the surface on which the semiconductor chip (7a) is disposed;
The first and second lead frames (9, 10) of the first and second heat dissipation substrates (12, 13) are joined while exposing the first terminal (P) and the second terminal (O). The semiconductor chip (7a), the first and second lead frames (9, 10), and the first and second heat dissipation substrates (12, 13) are sealed so that the surface opposite to the surface to be exposed is exposed. A resin part (16) to be
The first and second heat radiating substrates (12, 13) are both first conductor portions (12a, 13a) constituting surfaces to be joined to the first and second lead frames (9, 10); The second conductor portions (12c, 13c) constituting the surface exposed from the resin portion (16), and the insulating substrate (12a, 13a, 12c, 13c) sandwiched between the first and second conductor portions (12a, 13a, 12c, 13c) 12b, 13b), and the first conductor portions (12a, 13a) and the second conductor portions (12c, 13c) have a solid structure that is not divided and are symmetrical. A semiconductor module characterized by the following.   One of the two sides sandwiching the semiconductor chip (7a) is a component configuration in which the first lead frame (9) and the first heat dissipation substrate (12) are arranged, and the other is the second lead frame (10). 2 and the second heat dissipation substrate (13) are arranged so that the component configurations on both sides of the semiconductor chip (7a) are symmetrical. The semiconductor module described in 1. A semiconductor power element having a front surface and a back surface and having a vertical structure is formed, a signal line electrode (71) is formed on the front surface side, a front surface electrode (72) is formed, and a back surface electrode (73) is formed on the back surface side. First and second semiconductor chips (7a, 7b) formed with
A first lead frame (9) connected to the back electrode (73) of the first semiconductor chip (7a) and provided with a first terminal (P);
The signal line terminal (S1) connected to the signal line electrode (71) of the first semiconductor chip (7a), the surface electrode (72) of the first semiconductor chip (7a), and the second semiconductor chip ( A second lead frame (10) provided with a plate-like portion (10a) connected to the back electrode (73) of 7b) and extended with a second terminal (O);
A signal line terminal (S2) connected to the signal line electrode (71) of the second semiconductor chip (7b) and a third electrode connected to the surface electrode (72) of the second semiconductor chip (7b). A third lead frame (11) provided with a plate-like portion (11a) with terminals (N) extended;
A first heat dissipation substrate (12) joined to a surface of the first lead frame (9) opposite to a surface on which the first semiconductor chip (7a) is disposed;
Second and third heat dissipating substrates (13, 14) joined to the surface of the second lead frame (10) opposite to the surface on which the first and second semiconductor chips (7a, 7b) are disposed; ,
A fourth heat dissipation substrate (15) joined to a surface of the third lead frame (11) opposite to the surface on which the second semiconductor chip (7b) is disposed;
The first to third lead frames (9 to 11) of the first to fourth heat dissipation substrates (12 to 15) are joined while exposing the first to third terminals (P, O, N). The first and second semiconductor chips (7a, 7b), the first to third lead frames (9, 10), and the first to fourth heat dissipation substrates (12) so as to expose the surface opposite to the surface. To 15) and a resin part (16) for sealing,
The first to fourth heat radiating substrates (12 to 15) are both first conductor portions (12a to 15a) constituting surfaces to be joined to the first to third lead frames (9 to 11), and A second conductor portion (12c to 15c) that constitutes a surface exposed from the resin portion (16), and an insulating substrate sandwiched between these first and second conductor portions (12a to 15a, 12c to 15c) 12b to 15b), and the first conductor portions (12a to 15a) and the second conductor portions (12c to 15c) have a solid structure that is not divided and have a symmetrical shape. A semiconductor module characterized by the following. One of the two sides sandwiching the first semiconductor chip (7a) has a component configuration in which the first lead frame (9) and the first heat dissipation substrate (12) are arranged, and the other is the second lead frame. (10) and the second heat dissipating substrate (13) are arranged in a component configuration, so that the component configurations on both sides of the first semiconductor chip (7a) are symmetrical,
One of the two sides sandwiching the second semiconductor chip (7b) has a component configuration in which the second lead frame (10) and the third heat dissipation substrate (14) are arranged, and the other is the third lead frame. (11) and the fourth heat dissipation substrate (15) are arranged as a component configuration, and the component configurations on both sides of the second semiconductor chip (7b) are symmetrical. The semiconductor module according to claim 3.   In the second lead frame (10), an opening (10d) is provided between a place where the first semiconductor chip (7a) is arranged and a place where the second semiconductor chip (7b) is arranged. The semiconductor module according to claim 3, wherein the semiconductor module is provided.   A snubber circuit (40) is provided between the first lead frame (9) and the third lead frame (11), according to any one of claims 3 to 5. Semiconductor module.   The first terminal (P) and the third terminal (N) are a positive electrode terminal and a negative electrode terminal, respectively, and the positive electrode terminal and the negative electrode terminal are arranged adjacent to each other. The semiconductor module as described in any one.   The concave portion (16a) or the convex portion (16b) is formed in the resin portion (16) between each of the first to third terminals (P). The semiconductor module as described in any one.   The resin constituting the resin part (16) has a linear expansion coefficient higher than that of the first and second conductor parts (12a to 15a, 12c to 15c) provided in the first to fourth heat dissipation boards (12 to 15). The semiconductor module according to claim 3, wherein the semiconductor module is a small material. A semiconductor module according to any one of claims 1 to 9,
Inside the semiconductor module, on both sides of the surface where the first and fourth heat dissipation substrates (12, 15) are exposed and the surface where the second and third heat dissipation substrates (13, 14) are exposed. A semiconductor device comprising a heat sink (51, 61) through which a refrigerant is circulated.   The heat sink (61) is directly attached to the surface from which the first and fourth heat dissipation substrates (12, 15) are exposed and the surface from which the second and third heat dissipation substrates (13, 14) are exposed, 11. The semiconductor device according to claim 10, wherein the cooling is performed by a direct cooling method in which the refrigerant is brought into direct contact with the exposed surfaces of the first to fourth heat dissipation substrates (12 to 15).

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