JP2013037622A - Printed circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed circuit board in which even when the number of chips incorporated in each memory 7 and 8 is two or one, the same printed circuit board PCB is available, and the number of the arrangement places of resistance elements R2 to R6 for path switching composing paths L1 to L4 between an address decoder and the memories and a path L0 between a processor and the address decoder is small, and the SI analysis steps of the paths L1 to L4 between the address decoder and the memories is not increased.SOLUTION: A path L0 between a processor and an address decoder comprises: a first instruction signal path A23-A through which an instruction signal can be supplied from a first MPU output terminal A23 to a first address decoder input terminal A, and on which a resistance element R4 for path switching can be mounted; a second instruction signal path A24-B through which the instruction signal can be supplied from a terminal A24 to an input terminal B; and a fixed instruction signal path R6-A through which an earth signal Se can be supplied to an input terminal A, and on which a resistance element R6 for path switching can be mounted.

Description

  The present invention makes it possible to control a plurality of memories containing chips by a processor (hereinafter also referred to as MPU) via an address decoder, and by changing the arrangement of the path switching resistance elements, the memory capacity or chip (bank ) Even if the number is changed, in the case where mounting is possible using the same printed circuit board, there are few path switching resistive elements, the path is simple, the number of paths does not increase, and the SI analysis man-hours for the path do not increase. The present invention relates to a printed circuit board, and particularly used for a vehicle instrument.

  Conventionally, as Patent Literature 1, a memory bus connection method between a central processing unit and a main storage device is known, and in particular, a memory bus connection method capable of arbitrarily changing the connection of the memory bus is known. This includes a main memory (MEM) composed of a plurality of memory elements, a central processing unit (CPU) that outputs a signal to the main memory, and a signal output from the central processing unit as a memory in the main memory 4 A memory access control unit (MAC) that converts and outputs a signal according to the input conditions of the element is configured, and the central processing unit and the memory access control unit, and the memory access control unit and the main storage device are respectively connected by buses. It is connected.

  As a result of the frequent expansion of memory capacity, the increase in the number of data signals and the change of control signals in recent years, memory access control is required in order to make the memory bus connection compatible with the latest memory devices in the market. It has been pointed out that it is necessary to change the connection between the memory unit and the memory element. In addition, since the memory access control unit and the memory element are physically and fixedly connected, when the connection between the memory access control unit and the memory element is changed, the board on which the component is mounted is redesigned. It presents the challenge of lacking economics and responsiveness.

  For this purpose, the memory bus connection method of Patent Document 1 is based on a main memory means composed of a plurality of memory elements, a central processing means for outputting a signal to the main memory means, and a signal output from the central processing means. Memory access control means for converting the signal into a signal in accordance with the input condition of the memory element and outputting the signal, and the central processing means and the memory access control means, and the memory access control means and the main storage means are respectively connected by a bus. Thus, in a memory bus connection system in which data is written or read in the main memory means according to a signal output from the central processing means, a memory element and a memory access are provided between the main memory means and the memory access control means. Memory bus connection conversion means comprising physical switches for controlling connection with the control means is provided. In this physical switch, connection data between the input terminal and the output terminal is written in advance, and in accordance with this connection, the input signal is transferred to the output terminal and output, and the programmable logic array for memory bus connection conversion It is.

Japanese Patent Laid-Open No. 10-283256

  Also, in conventional digital systems for high-speed transmission, if the waveform of a high-speed digital signal that has passed through a signal line is distorted (tilt at the rising edge of the waveform), the digital LSI that receives the signal may not operate normally. It was important to evaluate signal integrity (Signal Integrity; that is, waveform quality, hereinafter referred to as SI).

  SI evaluation / confirmation is generally performed by simulation using EDA tools (software, hardware, and tools required to automate and support electrical design work such as electronic devices and semiconductors). . In this case, in order to reduce the number of man-hours for simulation, it is desirable that the number of signal lines to be evaluated is reduced.

  Furthermore, conventionally, there are a two-chip enable method in which two chips (banks) are built in the memory, and a one-chip enable method in which one chip (bank) is built in the memory, and each has 32 Mbytes, 16 Mbytes, etc. In the case where there are different capacities, when switching between these chips, it is necessary to respond by switching the path on the input side and output side of the address decoder. It is preferable to reduce the number of path switching resistive elements used at this time from the viewpoint of cost. However, with respect to such a problem, Patent Document 1 described above cannot present any specific solution structure.

  Here, the printed circuit board mounting circuit devised by the inventor in the development process will be described, and the problems will be described in more detail. In FIG. 4, an address decoder 17 is mounted between the processor 15 on the printed circuit board and the memories 7 and 8. The memories 7 and 8 include a two-chip memory in which two memory elements are incorporated and a one-chip memory in which one memory is incorporated.

  In addition, the memories 7 and 8 having the same capacity of 32 Mbytes include those constituted by a one-chip built-in type and those constituted by a two-chip built-in type. The manufacturers of the memories 7 and 8 include Company A and Company B. Among these, even if the printed circuit board mounting circuit that connects the 32-Mbyte memories 7 and 8 to the processor 15 is completed by using the product of Company A, the product of Company B that is an alternative to the product of Company A is used. In such a case, it is necessary to be able to continue using the same printed circuit board.

  Furthermore, in the case of changing to the above alternative product, it is necessary to construct a mounting space for the path switching resistance element (0Ω chip resistance) that can be mounted on the printed circuit board and a path to the path switching resistance element in advance. is there. And when it changes to an alternative, it is desirable to be able to cope with the same printed circuit board only by changing the position where the path switching resistive element is mounted.

  Further, from the viewpoint of cost, it is desirable that the number of the path switching resistance elements is small. Also, an increase in the variation of paths from the address decoder 17 to the memories 7 and 8 is not preferable because it requires man-hours for SI analysis. Therefore, it is desirable that the number of paths from the address decoder 17 to the memories 7 and 8 is small even if the substitute is used. The inventor devised the printed circuit board mounting circuit in the development process shown in FIG. 4 while having this problem. In the following, the printed circuit board in this unknown process will be described.

(When using a 2-chip enable system of Company A and supporting a total capacity of 64 Mbytes)
In FIG. 4A, each of the memories 7 and 8 composed of two chips has two 16-Mbyte chips 1, 2, 3, and 4 mounted therein. Twenty-three signal lines (address buses) 10 and 11 are directly connected from the processor 15 to the memories 7 and 8 to the address bus connection terminals A0 to A22.

  In the memories 7 and 8, terminals BE0 # and BE1 # are bank enable terminals, and one of the chips 3, 4, 5, and 6 is selected by a signal input to these terminals. When the instruction signals at the output terminals A23 and A24 of the processor 15 are “00”, the output terminal Y0 of the address decoder 17 is valid. When the instruction signal is “01”, the output terminal Y1 of the address decoder 17 is When the instruction signal is “10”, the output terminal Y2 of the address decoder 17 is enabled. When the instruction signal is “11”, the output terminal Y3 of the address decoder 17 is enabled. Here, in each case of the instruction signals “00”, “01”, “10”, and “11”, the least significant bit is input to the first address decoder input terminal A, and the next bit is the second address decoder input terminal. B is input.

  In the case of FIG. 4A, among the lands for mounting the path switching resistance element, the resistance is actually mounted on the lands R1 and R3, and the path switching resistance element is mounted on the lands R2 and R4. Is not implemented. Further, as the path, a path illustrated in a chain shape in which dots are superimposed on a solid line is used, and a path illustrated only by a solid line is not used as a circuit.

  In the following description, the lands and the path switching resistive elements mounted on the lands are given the same reference numerals (R4 and the like), and the lands on which the path switching resistive elements are mounted are illustrated by solid lines, A land where the path switching resistive element is not mounted is illustrated by a broken line.

(When A company's 1-chip enable method supports a total capacity of 32 Mbytes)
In FIG. 4B, each of the memories 7 and 8 has one 16 Mbyte chip mounted therein. When the instruction signal “0” from the output terminal A23 of the processor 15 is input to the input terminal A, the output terminal Y0 of the address decoder 17 becomes valid and the instruction signal “1” is input to the input terminal A. In this case, the output terminal Y1 of the address decoder 17 becomes valid.

  As a result, one of the terminals CE # of each of the memories 7 and 8 becomes valid. When a signal is input to the terminal CE #, the single chip 1 or chip 3 in the corresponding memory 7 or 8 becomes valid. In the case of FIG. 4B, the path switching resistance elements are actually mounted on the lands R1, R4, and R6, and the path switching resistance elements are not mounted on the lands R2, R3, and R5.

(In case of B company supporting 1M chip enable system with a total capacity of 64M bytes)
In FIG. 4C, each of the memories 5 and 6 has one 32 Mbyte chip mounted therein. Since the capacity of one chip is twice that of FIG. 4A, it is necessary to increase the number of addresses by one. Thus, when the number of addresses increases by one, the capacity can be doubled. However, in this case, with a double capacity, 23 address signals A0 to A22 are not sufficient to specify an address, and another address signal terminal A23 is added.

  Whether the valid output terminals Y0 and Y1 of the address decoder 17 are switched depending on whether the output terminal A24 of the processor 15 is "0" or "1". When the terminals Y0 and Y1 are switched, the upper 32 Mbyte chip is used. It is possible to select whether to use the lower 32 Mbyte chip. In the case of FIG. 4C, the path switching resistance elements are mounted on the lands R2, R4, and R6, and the path switching resistance elements are not mounted on the lands R1, R4, and R5.

(When B company supports a total capacity of 32 Mbytes with the 1 chip enable method)
Each of the memories 7 and 8 shown in FIG. 4D has a 16 Mbyte chip mounted therein. The terminals Y0 and Y1 of the address decoder 17 are switched depending on whether the output terminal A23 of the processor 15 is “0” or “1”. When the terminals Y0 and Y1 are switched, an effective memory signal (selection signal) indicating whether to use the upper 16 Mbyte chip 1 or the lower 16 Mbyte chip 3 is input to the terminal CE #. The output terminal A24 of the processor 15 is not used.

  In the case of FIG. 4C, among the lands for mounting resistors, the path switching resistance elements are actually mounted on the lands R1, R4, and R6, and the path switching resistance elements are mounted on the lands R2, R3, and R5. Not implemented.

  As described above, the printed mounting board in this development stage is at least in the case of the 16 Mbyte 2 chip enable method of FIG. 4A using a product of A company and the product of FIG. 4B using the product of A company. In the case of the 16 Mbyte 1 chip enable method, in the case of the 32 Mbyte 1 chip enable method in FIG. 4C using the product of B company, in the case of the 16 Mbyte 1 chip enable method in FIG. 4D using the product of B company, Each circuit can be mounted using a common printed circuit board. In the printed circuit board mounting circuit in the development process, there are a total of six lands (R1, R2, R3, R4) on both the input side and the output side of the address decoder 17 on which the path switching resistance element can be mounted. , R5, R6).

  Next, in FIG. 4, SI analysis lines that require SI analysis from the address decoder 17 to the memories 7 and 8 are represented by the number of paths shown in a chain, and from (a) to (d) in FIG. 4. (Between Y0-BE0 # or Y0-CE #), (between Y1-BE1 #) (between Y1-R6-CE #) (between Y2-R5-BE0 #) (between Y3-BE1 #) Five.

  In each case of the instruction signals “00”, “01”, “10”, and “11”, the least significant bit is input to the input terminal A of the address decoder, and the next bit is input to the input terminal B of the address decoder. As shown in FIG. 4, the printed circuit board mounting circuit devised in the development process is used from the least significant bit input terminal (input terminal A) on the input side of the address decoder 17, and the instruction signal is “0” “1”. If there is only one of these, an instruction signal is input only to the least significant bit input terminal (input terminal A), the non-least significant bit input terminal (input terminal B) is a fixed input terminal, and the path switching resistance element is the land. Mounted on R4, the non-least significant bit input terminal (input terminal B) is grounded and fixed to signal “0”.

  As a result, in the printed circuit board in the development process described above, a total of six lands on which the path switching resistor element can be mounted is necessary, and the SI analysis lines that require SI analysis from the address decoder 17 to the memories 7 and 8 are as follows. There were a total of five. The inventor further felt the necessity of a printed circuit board mounting circuit that reduces the number of lands on which the path switching resistance element can be mounted, and in this case does not increase the number of SI analysis lines that require SI analysis.

  The present invention has been made paying attention to such problems existing in the prior art, and the object thereof is to have a first memory and a second memory, from the processor to the first memory and the first memory. An address signal is supplied to the two memories, an effective memory signal is generated by an address decoder to which an instruction signal output from the processor is input, and a first memory and a second memory used by the processor are selected by the effective memory signal. In a printed circuit board on which an electric circuit can be mounted, each memory has two or one chip, and there is a difference in the number of address signal lines due to the difference in memory capacity. However, using the same printed circuit board, it is possible to configure an electric circuit according to each case, and to configure an address decoder memory path and a processor address decoder path. Distribution 設箇 plants path switching resistive element (the number of lands) less, SI analysis steps between the address decoder memory path does not increase, there is provided a printed circuit board.

  Descriptions of patent documents listed as prior art can be introduced or incorporated by reference as explanations of technical elements described in this specification.

  In order to achieve the above object, the present invention employs the following technical means. That is, in the first aspect of the invention, the first memory is mounted and the first memory mounting area having at least two memory terminals, and the second memory is mounted and the second memory is mounted and has at least two memory terminals. A processor mounting area in which a processor for supplying an address signal for specifying an address to the area, the first memory and the second memory and outputting an instruction signal is mounted; an instruction signal from the processor is input; An address decoder mounting area on which an address decoder that outputs a valid memory signal that enables one of them is mounted. The address decoder includes a first address decoder input terminal connected to the processor and a second address decoder. An address decoder input terminal is provided, and the first address decoder is connected to the memory terminal in the first memory mounting area. The output terminal and the second address decoder output terminal are connected, the third address decoder output terminal and the fourth address decoder output terminal are connected to the memory terminal of the second memory mounting area, and “0” is connected to the first address decoder input terminal. When a value indicating signal is input and a “0” value indicating signal is input to the second address decoder input terminal, a valid memory signal is output from the first address decoder output terminal, and “1” is input to the first address decoder input terminal. When the "1" value instruction signal is input and the "0" value instruction signal is input to the second address decoder input terminal, a valid memory signal is output from the second address decoder output terminal, and the first address decoder input terminal When a “0” value instruction signal is input to the second address decoder input terminal, a “1” value instruction signal is input to the third address decoder. When a valid memory signal is output from the output terminal, an instruction signal of “1” value is input to the first address decoder input terminal, and an instruction signal of “1” value is input to the second address decoder input terminal, In a printed circuit board that outputs a valid memory signal from the 4-address decoder output terminal, in the first mounting state in which a fixed signal of “0” value is input to the first address decoder input terminal instead of the instruction signal, the first address decoder input terminal In the second mounting state in which the first path switching resistance element that grounds the first address decoder can be mounted and the first address decoder input terminal is not grounded, the first path switching resistance element is removed and the processor is connected to the first address decoder input terminal. The second path switching resistance element for inputting the instruction signal from can be mounted, and either the first mounting state or the second mounting state is selected. It is characterized by being selected.

  According to the present invention, in order to wire both the first and second memories from the address decoder, among the first to fourth address decoder output terminals, the path from the first and second address decoder output terminals, It is easier to wire both the first and second memories by avoiding paths from adjacent output terminals such as paths from the third and fourth address decoder output terminals and splitting the paths. That is, when the first and third address decoder output terminals, the second and fourth address decoder output terminals, etc. are connected in a split state to the first and second memories, the number of transfer paths between the first and second memories is smaller. Therefore, the number of paths tends to be small, and the number of mounted resistance elements for path switching for creating a transition path tends to be small. In the present invention, when a signal of “0 or 1” is input to the second address decoder input terminal and a fixed ground signal “0” is supplied to the first address decoder input terminal, the first and third addresses An effective memory signal is supplied from the decoder output terminal to the memory terminal, and the path can be split. Therefore, in order to input the fixed signal “0” to the first address decoder input terminal, it is possible to mount a first path switching resistance element that grounds the first address decoder input terminal, and ground the first address decoder input terminal. If the second path switching resistance element for inputting the instruction signal from the processor to the first address decoder input terminal can be mounted, the path can be split from the address decoder to the first and second memories. The number of paths between the first and second memories can be reduced, the number of paths can be reduced, and the number of mounted path switching resistance elements for creating a transition path can be easily reduced. As a result, the number of path switching resistance elements is relatively small, and the number of SI analysis steps for evaluating the waveform quality (SI) of a high-speed digital signal that has passed through the signal path can be reduced by reducing the signal path between the address decoder memories. Reduced printed circuit boards can be provided.

  According to the second aspect of the present invention, in the first mounting state in which the first path switching resistive element is mounted, the path for inputting the instruction signal from the processor to the first address decoder input terminal is disconnected, and the first from the processor. And an address signal supply path for inputting an address signal to one memory terminal of each of the second memory areas.

  According to the present invention, even if the address signal increases due to the increase in the memory capacity of the first and second memories, the path from the processor to the first address decoder input terminal is disconnected, and the first and second memories from the processor are disconnected. Since the address signal supply path for supplying the address signal can be configured, the address signal does not run short even if the memory capacity increases.

  According to a third aspect of the present invention, a pair of paths for inputting an instruction signal from the processor to the second address decoder input terminal is further provided, and the third and fourth path switching resistive elements can be mounted to switch the paths. It is characterized by that.

  According to the present invention, the circuit further includes a pair of paths for inputting an instruction signal from the processor to the second address decoder input terminal, and the third and fourth path switching resistive elements can be mounted to switch the paths. An instruction signal can be input from the processor to the second address decoder input terminal regardless of whether the ground signal “0” fixed to the one address decoder input terminal is supplied or the first address decoder input terminal is not grounded. it can.

  In the invention according to claim 4, the first memory is mounted and the first memory mounting area having at least two memory terminals, and the second memory is mounted and the second memory mounting area having at least two memory terminals is provided. A processor mounting area in which a processor for supplying an address signal for specifying an address to the first memory and the second memory and outputting an instruction signal is mounted; and an instruction signal from the processor is input to either of the memory terminals And a first address decoder input terminal connected to the processor and a second address decoder input. And a first address decoder output terminal and a memory terminal in the first memory mounting area. The second address decoder output terminal is connected, the third address decoder output terminal and the fourth address decoder output terminal are connected to the memory terminal of the second memory mounting area, and the value of “0” is indicated to the first address decoder input terminal When a signal is input and an instruction signal of “0” value is input to the second address decoder input terminal, a valid memory signal is output from the first address decoder output terminal, and a “1” value is output to the first address decoder input terminal. When an instruction signal of “0” is input to the second address decoder input terminal, a valid memory signal is output from the second address decoder output terminal, and “0” is input to the first address decoder input terminal. When the “1” value instruction signal is input and the “1” value instruction signal is input to the second address decoder input terminal, the third address decoder output terminal The fourth address decoder outputs a valid memory signal, and when a "1" value instruction signal is input to the first address decoder input terminal and a "1" value instruction signal is input to the second address decoder input terminal. In a printed circuit board that outputs a valid memory signal from an output terminal, in a first mounting state in which a common instruction signal is input from a processor to a first address decoder input terminal and a second address decoder input terminal, the first and second addresses The common path switching resistive element connected to the decoder input terminal can be mounted. In the second mounting state in which individual instruction signals are input to the first and second address decoder input terminals, the common path switching resistive element is And one of the first and second address decoder input terminals is selected.

  According to the present invention, in order to wire both the first and second memories from the address decoder, among the first to fourth address decoder output terminals, the path from the first and second address decoder output terminals, By avoiding wiring from adjacent output terminals such as the path from the third and fourth address decoder output terminals and splitting the path, the number of paths between the first and second memories is reduced. There is a tendency that the number of mounted resistance elements for path switching for forming a crossing path is small. On the other hand, the address decoder can supply an effective memory signal from the first to fourth address decoder output terminals to the memory terminal according to four states of “00”, “01”, “10”, and “11”. . Since a common path switching resistance element for inputting a common instruction signal from the processor to the first address decoder input terminal and the second address decoder input terminal can be mounted, the common instruction signal “00” is provided. , “11”, a valid signal, that is, a valid memory signal is supplied from the first and fourth address decoder output terminals to the memory terminal in accordance with the two states, and the path can be split. Therefore, the number of path paths between the first and second memories is relatively small, the number of paths is small, and the number of path switching resistance elements for forming the path is relatively small. Accordingly, it is possible to provide a printed circuit board in which the number of SI analysis steps for evaluating the waveform quality (SI) of a high-speed digital signal that has passed through the signal path is reduced by reducing the signal path of the address decoder memory path.

  In the fifth aspect of the present invention, in the first mounting state in which the common path switching resistive element is mounted, the path for inputting the instruction signal from the processor to the first address decoder input terminal is disconnected, and the first, An address signal supply path for inputting an address signal to one memory terminal of each of the second memory areas is further provided.

  According to the present invention, even if the address signal increases due to the increase in the memory capacity of the first and second memories, the path from the processor to the first address decoder input terminal is disconnected, and the first and second memories from the processor are disconnected. Since the address signal supply path for supplying the address signal can be configured, the address signal does not run short even if the memory capacity increases.

It is an electrical connection diagram using the printed circuit board which shows 1st Embodiment of this invention. It is an electrical connection diagram using the printed circuit board which shows 2nd Embodiment of this invention. It is an electrical connection diagram using the printed circuit board which shows 3rd Embodiment of this invention. It is an electrical connection diagram using a non-known printed circuit board showing a form in the development process of the present invention.

  A plurality of modes for carrying out the present invention will be described below with reference to the drawings. In each embodiment, parts corresponding to the matters described in the preceding embodiment may be denoted by the same reference numerals, and redundant description may be omitted. When only a part of the configuration is described in each mode, the other modes described above can be applied to the other parts of the configuration. Not only combinations of parts that clearly indicate that the combination is possible in each embodiment, but also the embodiments are partially combined even if they are not clearly specified unless there is a problem with the combination. It is also possible.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIG. FIG. 1 is an electrical connection diagram using a printed circuit board PCB showing a first embodiment of the present invention.

(When using a 2-chip enable system of Company A and supporting a total capacity of 64 Mbytes)
In FIG. 1, reference numeral 15 denotes a processor (MPU) which reads a program stored in a memory, then receives data from an input device or a storage device according to the instructions of the program, calculates and processes the data according to the program. The data is sent to a storage device such as a memory or an output device such as a display. On the printed circuit board PCB, a processor mounting area 15R that is an area for mounting the processor 15 is formed.

  When the processor wants to access a specific memory, the access partner is specified by the address bus. At that time, an address decoder 17 is provided as a circuit that reads from the address bus which device is to be accessed and instructs the device to be accessed. The address decoder 17 generates an effective memory signal to be accessed from the value of the address bus. On the printed circuit board PCB, an address decoder mounting area 17R which is an area for mounting the address decoder 17 is formed.

  In FIG. 1A, first and second flash memories (hereinafter also simply referred to as first, second memory or simply memory) 7 and 8 comprising two chips (banks) are programs for controlling a vehicle instrument panel, The image data is stored, and two 16-Mbyte chips 1, 2, 3, and 4 are mounted therein. Further, on the printed circuit board PCB, first and second memory mounting regions 7R and 8R that are regions for mounting the first and second memories 7 and 8 are formed.

  With 16 Mbyte chips 1 and 2 or chips 3 and 4, addresses A0 to A22 are required. Therefore, 23 signal lines (address buses) 10 and 11 are directly connected from the processor 15 to the memories 7 and 8 from the address input terminals A0 to A22, and the address signal AS is supplied.

  In the memories 7 and 8, BE0 # and BE1 # are bank enable terminals, and a signal for selecting (activating) any one of the chips 1, 2, 3, and 4 is input. Whether the processor 15 uses data 2, 3, 4 is switched. The terminal NC is a non-connect terminal and is not connected to the internal circuit. These terminals can be either connected or not connected. The memories 7 and 8 have a memory capacity of 16 Mbytes × 4 = 64 Mbytes in total of two chips.

  When two instruction signals S1 from the first and second MPU output terminals A23 and A24 of the processor 15 are used, four states “00”, “01”, “10”, and “11” can be defined. In other words, four states can be instructed from the processor 15 to the address decoder 17 by a combination of the signals at the output terminals A23 and A24.

  When the instruction signal S1 of the first and second MPU output terminals A23 and A24 of the processor 15 is “00”, an effective memory signal S2 that enables the first address decoder output terminal Y0 of the address decoder 17 is output, and the instruction signal When S1 is “01”, a valid memory signal S2 that enables the second address decoder output terminal Y1 of the address decoder 17 is output. When the instruction signal S1 is “10”, the third address of the address decoder 17 is output. A valid memory signal S2 that enables the decoder output terminal Y2 is output. When the instruction signal S1 is “11”, a valid memory signal S2 that enables the fourth address decoder output terminal Y3 of the address decoder 17 is output. .

  Thereby, any one of the total four terminals BE0 # and BE1 # of each chip becomes effective. The two terminals of the output terminals A23 and A24 of the processor 15 can control a memory having a total capacity of 64 Mbytes by a two-chip enable method. Each time one terminal similar to the terminals A23 and A24 is added, it is possible to increase the memory with a capacity of 32 Mbytes.

  Although the example of the total capacity 64 Mbytes of company A has been described, it is necessary to be able to cope with the example of the total capacity 32 Mbytes of company A using the same printed circuit board PCB. In this case, the position at which the path switching resistive element including the line switching 0Ω resistor is mounted varies between 64 Mbytes and 32 Mbytes.

  For this purpose, the printed circuit board PCB has a land for resistance mounting (mounting area of the resistance element for path switching) so that either a total of 64 Mbytes or a total of 32 Mbytes of switching 0Ω resistance (hereinafter also simply referred to as resistance) may be mounted. (It is also simply referred to as a path switching resistor element) on the surface of the printed circuit board PCB.

  Further, as is well known, the printed circuit board PCB is provided with a path made of thin copper or the like (which constitutes a pattern wiring as a whole) on an insulating resin. In the case of FIG. 1A in which the total capacity 64 Mbyte memory of Company A is mounted using the same printed circuit board PCB on which this path is printed, the total capacity 32 Mbyte memory of Company A is mounted in FIG. ) Must be available.

  In the case of FIG. 1A, of the resistance mounting lands, resistors are actually mounted on the lands R2 and R4, and no resistors are mounted on the lands R3 and R6. Further, as the path, a path illustrated in a chain shape in which dots are superimposed on a solid line is used as a circuit, and a path illustrated only by a solid line is not used as a circuit.

(When A company supports a total capacity of 16 Mbytes with the 1 chip enable method)
In FIG. 1B, each of the memories 7 and 8 made up of one chip has one 16-Mbyte chip 1 and 3 mounted therein. In the memories 7 and 8, A22 to A0 have address input terminals, and the memories 7 and 8 have a total capacity of 32 Mbytes. Addresses A0 to A22 exist, and address buses 10 and 11 are connected from the processor to each memory.

  When an instruction signal from the output terminal A23 of the processor 15 is used, two states “0, 1” can be defined. In other words, two states can be instructed from the processor 15 to the address decoder 17 by the signal of the output terminal A23. When the instruction signal is “0”, the output terminal Y0 of the address decoder 17 is valid, and when the instruction signal is “1”, the output terminal Y2 of the address decoder 17 is valid. Thereby, an effective memory signal is input to one of the chip enable terminals CE # of the memories 7 and 8. When a valid memory signal is input to the terminal CE #, the single chip 1 or chip 3 in the corresponding memory 7 or 8 becomes valid.

  A memory having a total capacity of 32 Mbytes can be controlled by the output terminal A23 of the processor 15. Each time the number of terminals similar to the terminal A23 is increased, it is possible to increase the memory having a capacity of 16 Mbytes. In the case of FIG. 1B, among the lands for mounting resistors, resistors are actually mounted on the lands for lands R3 and R6, and no resistors are mounted on the lands for lands R2 and R4.

  As shown in FIGS. 1A and 1B, the printed circuit board according to the first embodiment has a total capacity of 32 Mbytes even if it is a 2-chip enable system with a total capacity of 64 Mbytes of the same manufacturer A. The same printed circuit board PCB can be used even in the one-chip enable system. In the present invention, the state in which the element is mounted is referred to as a printed circuit board, and the state before the element is mounted is referred to as a printed circuit board PCB.

  Here, Company A is adopted as the current development product, but it is necessary to make it possible to use the same printed circuit board PCB for Company B products, assuming that procurement of Company A products becomes difficult. There is. In this case, the position where the 0Ω resistor for line switching is mounted varies between Company A and Company B. Therefore, the printed circuit board PCB has a land for resistance mounting on the surface of the printed circuit board so that the line switching 0Ω resistor for Company A may be mounted or the line switching 0Ω resistor for Company B may be mounted. I have to keep it.

(In case of B company supporting 1M chip enable system with a total capacity of 64M bytes)
In FIG. 1 (c), each of the memories 5 and 6 consisting of one chip has one 32-Mbyte chip mounted therein. The total capacity is 64 Mbytes, which is the same as the company A illustrated in FIG.

  However, since the capacity of one chip is 32 Mbytes and the capacity is doubled, it is necessary to increase the number of addresses by one. As described above, when the number of addresses increases by one, the capacity can be doubled. That is, 23 addresses A0 to A22 are not sufficient, and another address signal supply path 10a, 11a is added.

  The valid output terminals Y0 and Y2 of the address decoder 17 are switched depending on whether the output terminal A24 of the processor 15 is “0” or “1”. When the terminals Y0 and Y2 are switched, it is possible to select whether to use the upper 32 Mbyte chip or the lower 32 Mbyte chip. In the case of FIG. 1C, the resistors are actually mounted on the lands for the lands R2 and R6 out of the lands for mounting the resistors, and the resistors are not mounted on the lands for the resistors R3 and R4.

(When B company supports a total capacity of 32 Mbytes with the 1 chip enable method)
Each of the memories 7 and 8 made up of one chip shown in FIG. 1D has one 16 Mbyte chip mounted therein. The total capacity is 32 Mbytes, which is the same as Company A illustrated in FIG.

  The terminals Y0 and Y2 of the address decoder 17 are switched depending on whether the output terminal A23 of the processor 15 is “0” or “1”. When the terminals Y0 and Y2 are switched, an effective memory signal indicating whether to use the upper 16 Mbyte chip 1 or the lower 16 Mbyte chip 3 is input to the terminal CE #. The output terminal A24 of the processor 15 is not used. In the case of FIG. 1C, among the lands for mounting resistors, resistors are actually mounted on the lands R3 and R6, and no resistors are mounted on the lands R2 and R4.

  As described above, the printed circuit board according to the first embodiment uses at least the product of company A, and uses the product of company A in the case of the 16 Mbyte 2 chip enable method of FIG. In the case of the 16 Mbyte 1 chip enable method of FIG. 1D, the product of company B is used, and in the case of the 32 Mbyte 1 chip enable method of FIG. 1C, the product of company B is used and in both cases of the 16 Mbyte 1 chip enable method of FIG. A common printed circuit board PCB can be used.

  In each of the above cases, the number of lands on which the path switching resistive element can be mounted is only four on the input side of the address decoder 17 (R2, R3, R4, R6). This is clearly an improvement compared to the need for six (R1, R2, R3, R4, R5, R6) in the electrical circuit (FIG. 4) using the printed circuit board PCB in the development process. .

  Also, as described above, in a digital system during high-speed transmission, if the waveform of a high-speed digital signal that has passed through a signal line is distorted, the digital LSI that received the signal may not operate normally, and SI is evaluated. SI analysis needs to be performed. The smaller the number of SI analysis lines, which are the paths to be subjected to SI analysis, can reduce the man-hours required for SI analysis.

  In FIG. 1, the SI analysis line from the address decoder 17 to the memories 7 and 8 is represented by the number of paths shown in a chain, and in (a) to (d) of FIG. 1, (Y0-BE0 # Or between terminals Y0 and CE #), (between Y1 and BE1 #) (between Y2 and BE0 # or between Y2 and CE #) (between Y3 and BE1 #). This is clearly improved as compared with the need for five SI analysis lines in the development circuit board mounted circuit.

  As described above, in the first embodiment, the printed circuit board mounting circuit has the following configuration. A first memory 7 having first memory chips 1, 2, and 5 and having first memory terminals BE 0 # and CE # and second memory terminals BE 1 # and NC, and second memory chips 3, 4, and 6 are provided. A second memory 8 having built-in third memory terminals BE0 #, CE # and fourth memory terminals BE1 #, NC, and a first memory 7 and a second memory 8 from a processor (hereinafter also referred to as MPU); The address memory 17 is supplied with an address signal, and an effective memory signal is generated by an address decoder 17 to which an instruction signal output from the processor is input, and the first memory chips 1, 2, 5, and 2 A printed circuit board mounting circuit for selecting any one of the memory chips 3, 4, and 6.

  In the processor, address bus connection terminals A0-A22 for outputting address signals, and two first MPU output terminals A23 and second MPU output terminals A24 are arranged in order from the address bus connection terminals A0-A22. The address decoder 17 has a first address decoder input terminal A and a second address decoder input terminal B arranged on the side connected to the processor, and the first to fourth address decoders on the side connected to the memories 7 and 8. Output terminals Y0, Y1, Y3, and Y4 are arranged.

  A plurality of address decoder inter-memory paths capable of supplying effective memory signals to the memories 7 and 8 from the first to fourth address decoder output terminals Y0, Y1, Y2, and Y3 are provided. The address decoder memory path has a first address decoder memory path L1 that can connect the first address decoder output terminal and the first memory terminal.

  A second address decoder memory path L2 is connectable between the second address decoder output terminal and the second memory terminal. A third address decoder inter-memory path L3 is connectable between the third address decoder output terminal and the third memory terminal. A fourth address decoder inter-memory path L4 is connectable between the fourth address decoder output terminal and the fourth memory terminal.

  An interprocessor address decoder path L0 capable of supplying an instruction signal from the two MPU output terminals A23 and A24 to the address decoder input terminals A and B is provided. In addition, address signal supply paths 10a and 11a capable of supplying an address signal from the first MPU output terminal A23 to the memories 7 and 8 are provided.

  Further, the first MPU output terminal A23 has a first instruction signal path A23-A that can supply an instruction signal to the first address decoder input terminal A and that can mount the path switching resistor element R4. An instruction signal can be supplied from the second MPU output terminal A24 to the second address decoder input terminal B, and a second instruction signal path A24-B in which the path switching resistor element R2 can be mounted is provided. An instruction signal can be supplied from the first MPU output terminal A23 to the first address decoder input terminal B, and a third instruction signal path A23-B in which the path switching resistor element R3 can be mounted is provided. Furthermore, a fixed instruction signal path R6-A is provided which can supply a fixed signal to the first address decoder input terminal A and can be mounted with a path switching resistance element R6.

  According to this configuration, the first memory chip 1, 2, 5 is incorporated, the first memory 7 having the first and second memory terminals BE 0 #, BE 1 #, CE #, NC, and the second memory chip 3. 4 and 6 and a second memory 8 having third and fourth memory terminals BE0 #, BE1 #, CE #, NC, and an address signal from the processor to the first memory 7 and the second memory 8. And an effective memory signal is generated by an address decoder 17 to which an instruction signal output from the processor is input, and the first memory chips 1, 2, 5 and second memory used by the processor are generated by the effective memory signal. In the printed circuit board mounting circuit for selecting any one of the chips 3, 4, 6, each of the memories 7, 8 may include two or one chip, 8 Even if there is difference in the number of address signal lines by the difference of using the same printed circuit board PCB, it can be constructed printed circuit board mounting circuit corresponding to each case.

  Further, the path switching resistance elements constituting the path between the address decoder memories and the path between processor address decoders L0 may be four places (R4, R2, R3, R3), there are few arrangement places, and between the address decoder memories. It is possible to provide a printed circuit board mounting circuit in which the SI analysis man-hour of the path decreases due to a decrease in the number of paths L0 between processor address decoders.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described in detail with reference to FIG. FIG. 2 is an electrical connection diagram using a printed circuit board PCB showing a second embodiment of the present invention.

(When using a 2-chip enable system of Company A and supporting a total capacity of 64 Mbytes)
In FIG. 2A, flash memories (hereinafter simply referred to as “memory”) 7 and 8 comprising two chips each have two 16 Mbyte chips 1, 2, 3, and 4 mounted therein. With 16 Mbyte chips 1 and 2 or chips 3 and 4, addresses A0 to A22 are required. Therefore, 23 signal lines (address buses) 10 and 11 are directly connected from the processor 15 to the memories 7 and 8 from the address input terminals A0 to A22.

  In the memories 7 and 8, BE0 # and BE1 # are bank enable terminals to which signals for selecting (activating) one of the chips 1, 2, 3, and 4 are input. These terminals BE0 # and BE1 # are used to switch which chip 1, 2, 3, 4 data the processor 15 uses.

  When two instruction signals from the output terminals A23 and A24 of the processor 15 are used, four states can be defined. When the instruction signal “00” is output from the output terminals A23 and A24 of the processor 15, the output terminal Y0 of the address decoder 17 is valid. When the instruction signal is “01”, the output terminal Y1 of the address decoder 17 is valid. When the signal is “10”, the output terminal Y2 of the address decoder 17 is valid, and when the signal is “11”, the output terminal Y3 of the address decoder 17 is valid.

  In the case of FIG. 2A, of the resistance mounting lands, resistors are actually mounted on the lands R4 and R8, and no resistors are mounted on the lands R5 and R10. Further, as the path, a path illustrated in a chain shape in which dots are superimposed on a solid line is used as a circuit, and a path illustrated only by a solid line is not used as a circuit.

(When A company supports a total capacity of 16 Mbytes with the 1 chip enable method)
In FIG. 2B, each of the memories 7 and 8 each consisting of one chip has one 16 Mbyte chip mounted therein. In this flash memory, A0 to A22 are address input terminals, and the memories 7 and 8 have a total capacity of 32 Mbytes. When the instruction signal is “0” from the output terminal A23 of the processor 15, the output terminal Y0 of the address decoder 17 is valid, and when the instruction signal is “1”, the output terminal Y1 of the address decoder 17 is valid.

  As a result, one of the terminals CE # of each of the memories 7 and 8 becomes valid. When a signal is input to the terminal CE #, the single chip 1 or 3 in the corresponding memory becomes valid. A memory having a total capacity of 32 Mbytes can be controlled by the output terminal A23 of the processor 15. Each time the number of terminals similar to the terminal A23 is increased, it is possible to increase the memory having a capacity of 16 Mbytes.

  In the case of FIG. 2B, of the lands for mounting resistors, the resistors are actually mounted on the lands for lands R4 and R9, and no resistors are mounted on the lands R6 and R7. As shown in FIGS. 2A and 2B, the printed circuit board according to the second embodiment has a total capacity of 32 Mbytes even if it is a 2-chip enable system with a total capacity of 64 Mbytes of the same manufacturer A. Even in the chip enable system, the same printed circuit board PCB can be used.

(In case of B company supporting 1M chip enable system with a total capacity of 64M bytes)
In FIG. 2C, each of the memories 5 and 6 made up of one chip has one 32 Mbyte chip mounted therein. The total capacity is 64 Mbytes, which is the same as Company A illustrated in FIG. However, since the capacity of one chip is 32 Mbytes and the capacity is doubled, it is necessary to increase the number of addresses by one. That is, 23 addresses A0 to A22 are not sufficient, and another address signal supply path 10a, 11a is added.

  The valid output terminals Y0 and Y2 of the address decoder 17 are switched depending on whether the output terminal A24 of the processor 15 is “0” or “1”. When the terminals Y0 and Y2 are switched, it is possible to select whether to use the upper 32 Mbyte chip or the lower 32 Mbyte chip. In the case of FIG. 2C, among the lands for mounting resistors, resistors are actually mounted on the lands for lands R6 and R7, and no resistors are mounted on the lands for lands R4 and R9.

(When B company supports a total capacity of 32 Mbytes with the 1 chip enable method)
Each of the memories 7 and 8 made up of one chip shown in FIG. 2D has one 16 Mbyte chip mounted therein. The total capacity is 32 Mbytes, which is the same as Company A illustrated in FIG.

  The terminals Y0 and Y1 of the address decoder 17 are switched depending on whether the output terminal A23 of the processor 15 is “0” or “1”. When the terminals Y0 and Y1 are switched, an effective memory signal indicating whether to use the upper 16 Mbyte chip 1 or the lower 16 Mbyte chip 3 is input to the terminal CE #. The output terminal A24 of the processor 15 is not used. In the case of FIG. 2C, of the lands for mounting resistors, resistors are actually mounted on the lands R4 and R9, and no resistors are mounted on the lands R6 and R7.

  As described above, the printed circuit board of the second embodiment uses at least the product of company A, and uses the product of company A in the case of the 16 Mbyte 2 chip enable method of FIG. In the case of the 16 Mbyte 1 chip enable method of FIG. 2D, the product of company B is used, and in the case of the 32 Mbyte 1 chip enable method of FIG. 2C, the product of company B is used and in both cases of the 16 Mbyte 1 chip enable method of FIG. A common printed circuit board PCB can be used.

  In each of the above cases, the line switching 0Ω resistor may be four (R4, R6, R7, R9) on both the input side and the output side of the address decoder 17. This is clearly an improvement compared to the need for six printed circuit boards in the development process.

  In FIG. 2, the SI analysis line from the address decoder 17 to the memories 7 and 8 is represented by the number of paths shown in a chain, and in (a) to (d) of FIG. 2, (Y0-BE0 # Or between terminals Y0-CE #), (between Y1-BE1 #) (between Y1-R9-CE #) (between Y2-BE0 # or Y2-CE #) (between Y3-BE1 #) It is.

  As described above, in the second embodiment, the printed circuit board mounting circuit has the following configuration. A first memory 7 having first memory chips 1, 2, and 5 and having first memory terminals BE 0 # and CE # and second memory terminals BE 1 # and NC, and second memory chips 3, 4, and 6 are provided. A second memory 8 having a built-in third memory terminal BE0 #, CE # and a fourth memory terminal BE1 #, NC, and supplying an address signal from the processor to the first memory 7 and the second memory 8, An effective memory signal is generated by an address decoder 17 to which an instruction signal output from the processor is input, and the first memory chips 1, 2, 5 and second memory chips 3, 4 used by the processor based on the effective memory signal. , 6 has a printed circuit board mounting circuit for selecting one of the chips.

  In the processor, address bus connection terminals A0 to A22 for outputting address signals, and two first MPU output terminals A23 and second MPU output terminals A24 are arranged in order from the address bus connection terminals A0 to A22. The address decoder 17 has a first address decoder input terminal A and a second address decoder input terminal B arranged on the side connected to the processor, and the first to fourth address decoders on the side connected to the memories 7 and 8. Output terminals Y0, Y1, Y2, and Y3 are arranged.

  A plurality of address decoder inter-memory paths capable of supplying an effective memory signal are provided from the first to fourth address decoder output terminals Y0, Y1, Y2, and Y3 to the first to fourth memory terminals of the memories 7 and 8, respectively. The address decoder inter-memory path has a first address decoder inter-memory path L1 that can connect the first address decoder output terminal Y0 and the first memory terminals BE0 # and CE #. The second address decoder output terminal Y1 and the second memory terminal BE1 # have a second address decoder memory path L2 that can connect the NC.

  The second address decoder output terminal Y1 and the third memory terminal CE # can be connected, and a switching address decoder inter-memory path L23 in which the path switching resistive element R9 can be mounted is provided. A third address decoder inter-memory path L3 is connectable between the third address decoder output terminal Y2 and the third memory terminals BE0 # and CE #, and the path switching resistive element R7 can be mounted. Furthermore, a fourth address decoder inter-memory path L4 that can connect the fourth address decoder output terminal Y3 and the fourth memory terminal BE1 # is provided.

  An interprocessor address decoder path L0 capable of supplying an instruction signal from the two MPU output terminals A23 and A24 to the address decoder input terminals A and B is provided. In addition, address signal supply paths 10a and 11a capable of supplying an address signal from the first MPU output terminal A23 to the memories 7 and 8 are provided.

  Further, the first MPU output terminal A23 has a first instruction signal path A23-A that can supply an instruction signal from the first MPU output terminal A23 to the first address decoder input terminal A and on which the path switching resistor element R4 can be mounted. A second instruction signal path A24-B is provided that can supply an instruction signal from the second MPU output terminal A24 to the second address decoder input terminal B. Furthermore, the ground signal Se, which is a signal fixed to the first address decoder input terminal A, can be supplied, and a fixed instruction signal path R6-A on which the path switching resistor element R6 can be mounted is provided.

  According to this configuration, the first memory chip 1, 2, 5 is incorporated, the first memory 7 having the first and second memory terminals BE 0 #, CE #, BE 1 #, NC, and the second memory chip 3. 4 and 6 and a second memory 8 having third and fourth memory terminals BE0 #, BE1 #, CE #, NC, and an address signal from the processor to the first memory 7 and the second memory 8. And an effective memory signal is generated by an address decoder 17 to which an instruction signal output from the processor is input, and the first memory chips 1, 2, 5 and second memory used by the processor are generated by the effective memory signal. In the printed circuit board mounting circuit for selecting any one of the chips 3, 4, and 6, each of the memories 7 and 8 has two or one chip, and the memory capacity Phase of By even if there is a difference in the number of address signal lines, using the same printed circuit board PCB, it can be constructed printed circuit mounting substrate in accordance with each case.

  Further, the path switching resistance elements R4, R6, R7, and R9 constituting the path between the address decoder memory and the path between the processor address decoders may be provided at four locations, the number of locations of the path switching resistance elements is small, and the address It is possible to provide a printed circuit board mounting circuit in which the SI analysis man-hours for the decoder memory paths L1, L2, L3, L4, and L23 do not increase.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described in detail with reference to FIG. FIG. 3 is an electrical connection diagram using a printed circuit board PCB showing a third embodiment of the present invention.

(When using a 2-chip enable system of Company A and supporting a total capacity of 64 Mbytes)
In FIG. 3A, the memories 7 and 8 having two chips each have two 16-Mbyte chips 1, 2, 3, and 4 mounted therein. With 16 Mbyte chips 1 and 2 or chips 3 and 4, addresses A0 to A22 are required. Therefore, 23 signal lines (address buses) 10 and 11 are directly connected from the processor 15 to the memories 7 and 8 from the address input terminals A0 to A22.

  In the memories 7 and 8, BE0 # and BE1 # are bank enable terminals, and a signal for selecting (activating) any one of the chips 1, 2, 3, and 4 is input. Whether the processor 15 uses data 2, 3, 4 is switched.

  When two instruction signals from the output terminals A23 and A24 of the processor 15 are used, four states can be defined. When the instruction signal “00” is output from the output terminals A23 and A24 of the processor 15, the output terminal Y0 of the address decoder 17 is valid. When the instruction signal is “01”, the output terminal Y1 of the address decoder 17 is valid. When the signal is “10”, the output terminal Y2 of the address decoder 17 is valid, and when the signal is “11”, the output terminal Y3 of the address decoder 17 is valid.

  In the case of FIG. 3A, of the resistance mounting lands, resistors are actually mounted on the lands R4, R5, and R7, and no resistors are mounted on the lands R6 and R8. Further, as the path, a path illustrated in a chain shape in which dots are superimposed on a solid line is used as a circuit, and a path illustrated only by a solid line is not used as a circuit.

(When A company supports a total capacity of 16 Mbytes with the 1 chip enable method)
In FIG. 3B, each of the memories 7 and 8 made of one chip has one 16 Mbyte chip mounted therein. In this flash memory, A22 to A0 have address input terminals, and the memories 7 and 8 have a total capacity of 32 Mbytes.

  When the instruction signal “0” from the output terminal A23 of the processor 15 is input to the terminal B, the output terminal Y0 of the address decoder 17 becomes valid, and when the instruction signal is “1”, the output terminal Y3 of the address decoder 17 Becomes effective. As a result, one of the terminals CE # of each of the memories 7 and 8 becomes valid. When a signal is input to the terminal CE #, the single chip 1 or 3 in the corresponding memory becomes valid.

  A memory having a total capacity of 32 Mbytes can be controlled by the output terminal A23 of the processor 15. Each time the number of terminals similar to the terminal A23 is increased, it is possible to increase the memory having a capacity of 16 Mbytes.

In the case of FIG. 3B, among the lands for mounting resistors, the resistors are actually mounted on the lands R4, R6, and R8, and no resistors are mounted on the lands for the lands R5 and R7.
As shown in FIGS. 3A and 3B, the printed circuit board according to the third embodiment is one chip with a total capacity of 32 Mbytes even if the two-chip enable system with a total capacity of 64 Mbytes of the same manufacturer A company. Even in the enable method, the same printed circuit board PCB can be used.

(In case of B company supporting 1M chip enable system with a total capacity of 64M bytes)
In FIG. 3C, each of the memories 5 and 6 made up of one chip has one 32 Mbyte chip mounted therein. The total capacity is 64 Mbytes, which is the same as Company A illustrated in FIG. However, since the capacity of one chip is 32 Mbytes and the capacity is doubled, it is necessary to increase the number of addresses by one. That is, 23 addresses A0 to A22 are not sufficient, and it is necessary to add another address signal supply path 10a, 11a.

  The valid output terminals Y0 and Y3 of the address decoder 17 are switched depending on whether the output terminal A24 of the processor 15 is “0” or “1”. When the terminals Y0 and Y3 are switched, it is possible to select whether to use the upper 32 Mbyte chip or the lower 32 Mbyte chip. In the case of FIG. 3C, of the lands for mounting resistors, resistors are actually mounted on the lands R5, R6, and R8, and no resistors are mounted on the lands R4 and R7.

(When B company supports a total capacity of 32 Mbytes with the 1 chip enable method)
Each of the memories 7 and 8 including one chip illustrated in FIG. 3D has a 16 Mbyte chip mounted therein. The total capacity is 32 Mbytes, which is the same as Company A illustrated in FIG. The terminals Y0 and Y3 of the address decoder 17 are switched depending on whether the output terminal A23 of the processor 15 is “0” or “1”. When the terminals Y0 and Y3 are switched, an effective memory signal indicating whether to use the upper 16 Mbyte chip 1 or the lower 16 Mbyte chip 3 is input to the terminal CE #. The output terminal A24 of the processor 15 is not used.

  In the case of FIG. 3D, among the lands for mounting resistors, resistors are actually mounted on the lands R4, R6, and R8, and no resistors are mounted on the lands R5 and R7.

  As described above, the printed circuit board according to the third embodiment uses at least the product of company A, and uses the product of company A in the case of the 16 Mbyte 2 chip enable method of FIG. In the case of the 16 Mbyte 1 chip enable method of FIG. 3D, the product of B company is used, and in the case of the 32 Mbyte 1 chip enable method of FIG. 3C, the product of B company is used and in the case of the 16 Mbyte 1 chip enable method of FIG. A common printed circuit board PCB can be used.

  In each of the above cases, the line switching 0Ω resistor may be five (R4, R5, R6, R7, R8) on both the input side and the output side of the address decoder 17. This is clearly an improvement compared to the need for six printed circuit boards in the development process. In FIG. 3, the SI analysis lines from the address decoder 17 to the memories 7 and 8 are represented by the number of paths shown in a chain, and in (a) to (d) of FIG. 3, (Y0-BE0 # Or between terminals Y0-CE #), (between Y1-BE1 #) (between Y2-R7-BE0 #) (Y3-BE1) (between Y3-R8-CE #).

  As described above, in the third embodiment, the printed circuit board mounting circuit has the following configuration. The first memory chip 1, 2, 5 is incorporated, the first memory 7 having first and second memory terminals BE 0 #, BE 1 #, CE #, NC, and the second memory chip 3, 4, 6 are incorporated. And a second memory 8 having third and fourth memory terminals BE0 #, BE1 #, CE #, NC, and an address signal is supplied from the processor to the first memory 7 and the second memory 8, and from the processor A valid memory signal is generated by an address decoder 17 to which an instruction signal to be output is input, and the first memory chips 1, 2, 5 and second memory chips 3, 4, 6 used by the processor based on the valid memory signal. In the printed circuit board mounting circuit that selects any one of the chips, the processor sequentially starts from the address bus connection terminals A0 to A22 that output address signals, and the address bus connection terminals A0 to A22. Two first 1MPU output terminal A23 and the 2MPU output terminal A24 are arranged.

  The address decoder 17 has a first address decoder input terminal A and a second address decoder input terminal B arranged on the side connected to the processor, and the first to fourth address decoders on the side connected to the memories 7 and 8. Output terminals Y0, Y1, Y2, and Y3 are arranged.

  A plurality of address decoder memory paths capable of supplying valid memory signals are provided to the memories 7 and 8 from the first to fourth address decoder output terminals Y0, Y1, Y2, and Y3, respectively. Has a first address decoder inter-memory path L1 that can connect the first address decoder output terminal Y0 and the first memory terminals BE0 # and CE #. Further, a second address decoder inter-memory path L2 that can connect the second address decoder output terminal Y1 and the second memory terminal BE1 # is provided.

  Further, the third address decoder output terminal Y2 and the third memory terminals BE0 # and CE # can be connected, and the third switching address decoder inter-memory path L3 in which the path switching resistive element R7 can be mounted, and the fourth address decoder The output terminal Y3 and the third memory terminal CE # can be connected to each other and the path switching resistance element R8 can be mounted between the 4-3 address decoder memory path L43, the fourth address decoder output terminal Y3, and the fourth memory terminal. And a fourth address decoder inter-memory path L4 to which BE1 # can be connected.

  An MPU address decoder path capable of supplying an instruction signal from the first and second MPU output terminals A23 and A24 to the first and second address decoder input terminals A and B is provided, and the processor address decoder path is connected to the first MPU output. An address signal supply path 10a, 11a capable of supplying an address signal from the terminal A23 to the memories 7, 8 and an instruction signal can be supplied from the first MPU output terminal A23 to the first address decoder input terminal A, and a path switching resistance element R4 Can be mounted on the first instruction signal path A23-A and the second instruction signal path on which the instruction signal can be supplied from the second MPU output terminal A24 to the second address decoder input terminal B and the path switching resistor element R5 can be mounted. A24-B, the first MPU output terminal A23 to the first address decoder input terminal A and the second address decoder. A common instruction signal can be supplied to the input terminal B and the common path switching resistance element R6C can be mounted. The first common instruction signal path A23-AB from the second MPU output terminal B to the first address decoder input terminal A A common instruction signal can be supplied to the second address decoder input terminal B, and includes a second common instruction signal path A24-AB on which the common path switching resistance element R6C can be mounted.

  According to this configuration, the first memory chip 1, 2, 5 is incorporated, the first memory 7 having the first and second memory terminals BE 0 #, BE 1 #, CE #, NC, and the second memory chip 3. 4 and 6 and a second memory 8 having third and fourth memory terminals BE0 #, BE1 #, CE #, NC, and an address signal from the processor to the first memory 7 and the second memory 8. And an effective memory signal is generated by an address decoder 17 to which an instruction signal output from the processor is input, and the first memory chips 1, 2, 5 and second memory used by the processor are generated by the effective memory signal. In the printed circuit board mounting circuit for selecting any one of the chips 3, 4, 6, each of the memories 7, 8 may include two or one chip, 8 Even if there is a difference in the number of address signal lines due to a difference in, using the same printed circuit board PCB, it can be constructed printed circuit mounting substrate in accordance with each case.

  Further, the path switching resistance elements R4, R5, R6, R7, and R8 constituting the path between the address decoder memories and the path between the processor address decoders may be provided at five locations, the number of arrangement locations is small, and the path between the address decoder memories. A printed circuit board mounting circuit can be provided in which the SI analysis man-hours of L1, L2, L3, L4, and L43 do not increase.

(Other embodiments)
The present invention is not limited to the above-described embodiments, and can be modified or expanded as follows. For example, in each of the embodiments described above, a flash memory (flash EEPROM) is used as the memory. This memory is an evolution of the EEPROM, and differs greatly from the conventional EEPROM in that a part or all of the data is rewritten in a batch when the data is rewritten. However, the present invention is not limited to the use of flash memory, and other memories may be used. Further, it can be used not only for storing a vehicle instrument program and image data but also for other purposes.

1, 2, 5 First memory chip 3, 4, 6 Second memory chip 7 First memory 7R First memory mounting area 8 Second memory 8R Second memory mounting area 10a, 11a Address signal supply path 15 Processor ( MPU)
15R processor mounting area 17 address decoder 17R address decoder mounting area A first address decoder input terminal A0-A22 address bus connection terminal AS address signal B second address decoder input terminal BE0 #, CE # first memory terminal BE1 #, NC first 2 memory terminals BE0 #, CE # 3rd memory terminal BE1 #, NC 4th memory terminal PCB Printed circuit board R6 1st path switching resistance element R4 2nd path switching resistance element R2 3rd path switching resistance element R3 4th Path switching resistance element R6C Common path switching resistance element S1 instruction signal S1C common instruction signal Y0 first address decoder output terminal Y1 second address decoder output terminal Y2 third address decoder output terminal Y3 fourth address decoder output terminal

Claims (5)

A first memory mounting area on which a first memory is mounted and having at least two memory terminals;
A second memory mounting area on which a second memory is mounted and having at least two memory terminals;
A processor mounting area in which a processor that supplies an address signal for specifying an address to the first memory and the second memory and outputs an instruction signal is mounted;
An address decoder mounting area on which an address decoder that receives the instruction signal from the processor and outputs an effective memory signal that enables one of the memory terminals is mounted;
The address decoder
A first address decoder input terminal and a second address decoder input terminal connected to the processor;
In addition, a first address decoder output terminal and a second address decoder output terminal are connected to the memory terminal of the first memory mounting area, and a third address decoder output terminal and a second address decoder output terminal are connected to the memory terminal of the second memory mounting area. 4 address decoder output terminal is connected,
When the instruction signal of “0” value is input to the first address decoder input terminal and the instruction signal of “0” value is input to the second address decoder input terminal, the first address decoder output terminal Outputting the effective memory signal;
When the instruction signal of “1” value is input to the first address decoder input terminal and the instruction signal of “0” value is input to the second address decoder input terminal, the second address decoder output terminal Outputting the effective memory signal;
When the instruction signal of “0” value is input to the first address decoder input terminal and the instruction signal of “1” value is input to the second address decoder input terminal, the third address decoder output terminal Outputting the effective memory signal;
When the instruction signal of “1” value is input to the first address decoder input terminal and the instruction signal of “1” value is input to the second address decoder input terminal, the fourth address decoder output terminal In the printed circuit board that outputs the effective memory signal,
In a first mounting state in which a fixed signal having a value of “0” is input to the first address decoder input terminal instead of the instruction signal, a first path switching resistance element that grounds the first address decoder input terminal can be mounted. And
In a second mounting state in which the first address decoder input terminal is not grounded, the first path switching resistance element is removed, and the second path switching is performed by inputting the instruction signal from the processor to the first address decoder input terminal. Resistance elements can be mounted,
One of the first mounting state and the second mounting state is selected.   In the first mounting state in which the first path switching resistive element is mounted, the path for inputting the instruction signal from the processor to the first address decoder input terminal is disconnected, and the first and second paths from the processor are disconnected. The printed circuit board according to claim 1, further comprising an address signal supply path for inputting the address signal to each of the memory terminals in each of two memory areas.   The circuit further comprises a pair of paths for inputting the instruction signal from the processor to the second address decoder input terminal, and a third and fourth path switching resistive element can be mounted to switch the paths. Item 3. The printed circuit board according to item 1 or 2. A first memory mounting area on which a first memory is mounted and having at least two memory terminals;
A second memory mounting area on which a second memory is mounted and having at least two memory terminals;
A processor mounting area in which a processor that supplies an address signal for specifying an address to the first memory and the second memory and outputs an instruction signal is mounted;
An address decoder mounting area on which an address decoder that receives the instruction signal from the processor and outputs an effective memory signal that enables one of the memory terminals is mounted;
The address decoder
A first address decoder input terminal and a second address decoder input terminal connected to the processor;
In addition, a first address decoder output terminal and a second address decoder output terminal are connected to the memory terminal of the first memory mounting area, and a third address decoder output terminal and a second address decoder output terminal are connected to the memory terminal of the second memory mounting area. 4 address decoder output terminal is connected,
When the instruction signal of “0” value is input to the first address decoder input terminal and the instruction signal of “0” value is input to the second address decoder input terminal, the first address decoder output terminal Outputting the effective memory signal;
When the instruction signal of “1” value is input to the first address decoder input terminal and the instruction signal of “0” value is input to the second address decoder input terminal, the second address decoder output terminal Outputting the effective memory signal;
When the instruction signal of “0” value is input to the first address decoder input terminal and the instruction signal of “1” value is input to the second address decoder input terminal, the third address decoder output terminal Outputting the effective memory signal;
When the instruction signal of “1” value is input to the first address decoder input terminal and the instruction signal of “1” value is input to the second address decoder input terminal, the fourth address decoder output terminal In the printed circuit board that outputs the effective memory signal,
In the first mounting state in which the instruction signal common to the first address decoder input terminal and the second address decoder input terminal is input from the processor, a common path connected to the first and second address decoder input terminals The switching resistance element can be mounted,
In the second mounting state in which the individual instruction signals are respectively input to the first and second address decoder input terminals, the common path switching resistance element is removed,
One of the first and second address decoder input terminals is selected.   In the first mounting state in which the common path switching resistive element is mounted, a path for inputting the instruction signal from the processor to the first address decoder input terminal is cut off, and the first and second from the processor are disconnected. The printed circuit board according to claim 4, further comprising an address signal supply path for inputting the address signal to each one of the memory terminals in a memory area.

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