JP2013033884A - Laminated semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve observation accuracy of a signal waveform.SOLUTION: A plurality of electrode pads (P100) of a first semiconductor device comprise first connection pads. A plurality of electrode pads (P200) of a second semiconductor device comprise second and third connection pads and observation pads which are electrically connected. In the case where a first semiconductor device (10) is laminated on a second semiconductor device (20) such that a partial region that is a part of one surface of the second substrate (21) is shaded by a first substrate (11) when viewed from above, the first connection pads overlap the second connection pads when viewed from above. In the case where the first semiconductor device (10) is laminated on the second semiconductor device (20) such that the partial region is exposed from the first substrate (11) when viewed from above, the first connection pads overlap the third connection pads when viewed from above. The observation pads are arranged in the partial region.

Description

  The present invention relates to a stacked semiconductor device.

  In recent years, high-density mounting of semiconductor devices has progressed, and there is a tendency that a stacked semiconductor device having a POP (Package on Package) structure is formed by stacking a plurality of semiconductor devices. In such a stacked semiconductor device, it is important to observe a signal transmitted between the semiconductor devices in order to inspect the operation state and signal quality of the semiconductor device. In Patent Document 1, one surface of the lower semiconductor device is expanded so that one surface of the lower semiconductor device spreads outside the upper semiconductor device in plan view, and observed on the outer peripheral portion of one surface of the lower semiconductor device. The formation of a pad is described.

JP 2008-124080 A

  However, when the configuration described in Patent Document 1 is adopted in an actual use product (a stacked semiconductor device that is actually used), the observation pad is always exposed to the outside in the actual use product. May be easily analyzed. Therefore, an inspection product (a laminated semiconductor device used exclusively for inspection) is manufactured separately from the actual product, and the signal waveform is observed using the inspection product. In this case, the greater the difference in configuration between the actual product and the inspection product, the greater the difference in signal transmission characteristics between the actual product and the inspection product. It was difficult.

  Therefore, an object of the present invention is to provide a stacked semiconductor device that can reduce a difference in signal transmission characteristics between an actual use product and an inspection product and can improve the observation accuracy of a signal waveform. .

  According to one aspect of the present invention, a stacked semiconductor device includes a first semiconductor device including a rectangular first substrate and a plurality of electrode pads formed on one surface of the first substrate; A second semiconductor device including a second substrate having a shape and a plurality of electrode pads formed on one surface of the second substrate, wherein the first semiconductor device includes the first and second semiconductor devices. The substrate is stacked on the second semiconductor device such that one surface of each of the substrates faces each other, and the plurality of electrode pads of the first semiconductor device include a first connection pad, and the second semiconductor device The plurality of electrode pads of the device includes second and third connection pads and an observation pad that are electrically connected to each other, and a partial region that is a part of one surface of the second substrate in plan view The first semiconductor device is shielded by a first substrate When stacked on the second semiconductor device, the first connection pad overlaps the second connection pad in the plan view, and the partial region is exposed from the first substrate in the plan view. When the first semiconductor device is stacked on the second semiconductor device as described above, the first connection pad overlaps the third connection pad in the plan view, and the observation pad is the partial region. Placed in.

  In the above laminated semiconductor device, when the laminated semiconductor device is configured, the shielding and exposure of the observation pad can be switched, so that the actual use product (the actually used laminated semiconductor device) and the inspection product (used exclusively for inspection) Both stacked semiconductor devices) can be configured. Thereby, the difference in configuration between the actual use product and the inspection product can be reduced, so that the difference in the signal transmission characteristics between the actual use product and the inspection product can be reduced, and as a result, The observation accuracy of the signal waveform can be improved.

  The plurality of electrode pads of the first semiconductor device include fourth and fifth connection pads, and the plurality of electrode pads of the second semiconductor device include a common pad, and the portion in the plan view When the first semiconductor device is stacked on the second semiconductor device so that the region is shielded by the first substrate, the fourth connection pad overlaps the common pad in the plan view, When the first semiconductor device is stacked on the second semiconductor device so that the partial region is exposed from the first substrate in the plan view, the fifth connection pad is in the plan view. It may overlap with the common pad. With this configuration, the number of electrode pads formed on one surface of the second substrate of the second semiconductor device can be reduced.

  Note that the potential of the common pad may be constant. By configuring in this way, signal collision can be avoided.

  As described above, it is possible to reduce the difference in signal transmission characteristics between the actually used product and the inspection product, and it is possible to improve the observation accuracy of the signal waveform.

FIG. 3 is a cross-sectional view illustrating a structural example of the stacked semiconductor device according to the first embodiment. FIG. 3 is a plan view showing a structural example of a first semiconductor device according to the first embodiment. FIG. 6 is a plan view showing a structural example of a second semiconductor device according to the first embodiment. FIG. 4 is a plan view for explaining a connection state between electrode pads of the second semiconductor device shown in FIG. 3. 2 is a plan view for explaining a case where a stacked semiconductor device is configured by stacking the first semiconductor device shown in FIG. 2 on the second semiconductor device shown in FIG. 3 so that the partial region is shielded in a plan view. . (A) Sectional drawing in the AA line of the laminated semiconductor device shown in FIG. (B) Sectional drawing in the BB line of the laminated semiconductor device shown in FIG. 2 is a plan view for explaining a case where a stacked semiconductor device is configured by stacking the first semiconductor device shown in FIG. 2 on the second semiconductor device shown in FIG. 3 so that a partial region is exposed in plan view. . (A) Sectional drawing in the AA line of the laminated semiconductor device shown in FIG. (B) Sectional drawing in the BB line of the laminated semiconductor device shown in FIG. FIG. 6 is a plan view showing a structure example of a first semiconductor device according to Embodiment 2. FIG. 6 is a plan view showing a structural example of a second semiconductor device according to Embodiment 2. The top view for demonstrating the connection state between the electrode pads of the 2nd semiconductor device shown in FIG. 9 is a plan view for explaining a case where a stacked semiconductor device is formed by stacking the first semiconductor device shown in FIG. 9 on the second semiconductor device shown in FIG. 10 so that the partial region is shielded in plan view. . The top view for demonstrating the case where a laminated semiconductor device is comprised by stacking the 1st semiconductor device shown in FIG. 9 on the 2nd semiconductor device shown in FIG. 10 so that a partial region may be exposed in planar view. . FIG. 9 is a plan view showing a structural example of a first semiconductor device according to a modification of the second embodiment. FIG. 9 is a plan view showing a structure example of a second semiconductor device according to a modification of the second embodiment. 14 is a plan view for explaining a case where a stacked semiconductor device is configured by stacking the first semiconductor device shown in FIG. 14 on the second semiconductor device shown in FIG. 15 so that the partial region is shielded in plan view. . 14 is a plan view for explaining a case where a stacked semiconductor device is configured by stacking the first semiconductor device shown in FIG. 14 on the second semiconductor device shown in FIG. 15 so that the partial region is exposed in plan view. .

  Hereinafter, embodiments will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 shows an example of the structure of a stacked semiconductor device according to the first embodiment. This stacked semiconductor device includes a first semiconductor device 10 and a second semiconductor device 20. The first semiconductor device 10 includes a rectangular substrate 11, a plurality of electrode pads P <b> 100 formed on one surface of the substrate 11, and a semiconductor chip 12 formed on the other surface of the substrate 11. The second semiconductor device 20 includes a rectangular substrate 21, a plurality of electrode pads P <b> 200 formed on one surface of the substrate 21, and a semiconductor chip (not shown) formed on one surface of the substrate 21. The first semiconductor device 10 is stacked on the second semiconductor device 20 so that one surface of each of the substrates 11 and 21 (that is, the surface on which the electrode pads P100 and P200 are formed) is opposed to each other. Here, the substrates 11 and 21 have the same square shape in plan view. The semiconductor chip 12 may be stored inside the substrate 11. The same applies to the semiconductor chip included in the semiconductor device 21.

[First semiconductor device]
As shown in FIG. 2, a plurality of electrode pads P <b> 101 to P <b> 120 are formed on one surface of the substrate 11 of the first semiconductor device 10. The electrode pads P101 to P120 are arranged in a rectangular frame shape so as to surround the semiconductor chip 12 in plan view. Here, the electrode pad P102 is rotated 45 ° counterclockwise around the electrode pad P104 about the substrate normal passing through the reference point R1 (that is, a straight line extending perpendicularly from the reference point R1 to the substrate 11). It is disposed at a position (that is, a position where the electrode pad P104 exists after rotation). Similarly, the electrode pads P104, P107, P109, P112, P114, P117, and P119 have substrate normals that pass through the reference point R1 through the electrode pads P107, P109, P112, P114, P117, P119, and P102, respectively. The shaft is arranged at a position rotated 45 ° counterclockwise.

[Second Semiconductor Device]
As shown in FIG. 3, a plurality of electrode pads P201 to P220, P301, P303,..., P320, T220, T201, T202, and a semiconductor chip 22 are formed on one surface of the substrate 21 of the second semiconductor device 20. Is done. The electrode pads P201 to P220 are arranged in a rectangular frame shape so as to surround the semiconductor chip 22 in plan view. The electrode pads P301, P303,..., P320 are also arranged in a rectangular frame shape so as to surround the semiconductor chip 22 in plan view. Here, the electrode pad P301 is disposed at a position obtained by rotating the electrode pad P201 counterclockwise by 45 ° about the substrate normal passing through the reference point R2. Similarly, the electrode pads P303, P305,..., P320 are positions obtained by rotating the electrode pads P203, P205,..., P220 counterclockwise by 45 ° about the substrate normal passing through the reference point R2. Placed in. Furthermore, the electrode pads T220, T201, T202 (observation pads) are arranged in a partial region R21 that is a part of one surface of the substrate 21. Here, the partial regions R21 to R24 pass through the reference points R1 and R2 from the state where the first semiconductor device 10 is stacked on the second semiconductor device 20 so that the sides of the substrates 11 and 21 coincide in plan view. This is an area that is exposed when the substrate 11 is rotated 45 ° counterclockwise about the substrate normal line.

  As shown in FIG. 4, the electrode pads P220, P320, T220 are electrically connected to each other via package wiring or the like. That is, the electrode pads P220, P320, T220 constitute the same potential net. Similarly, the electrode pads P201, P301, and T201 are electrically connected to each other, and the electrode pads P202 and T202 are electrically connected to each other. The electrode pads P203, P205, P206, P208, P210, P211, P213, P215, P216, and P218 are electrically connected to the electrode pads P303, P305, P306, P308, P310, P311, P313, P315, P316, and P318, respectively. It may be connected, or may be electrically connected to an observation pad corresponding to each (for example, an electrode pad disposed in any of the partial regions R21 to R24).

(Shielding lamination)
FIG. 5 illustrates a case where a stacked semiconductor device is configured by stacking the first semiconductor device 10 on the second semiconductor device 20 so that the partial regions R21 to R24 of the substrate 21 are shielded by the substrate 11 in plan view (shielding). In the case of lamination). Here, when the first semiconductor device 10 is stacked on the second semiconductor device 20 so that the sides of the substrates 11 and 21 coincide with each other in a plan view, the partial regions R21 to R24 of the substrate 21 are the substrate in the plan view. 11 is shielded. In this case, the electrode pads T220, T201, T202 (observation pads) are shielded by the substrate 11 in plan view.

  The electrode pad P101 (first connection pad) of the first semiconductor device 10 overlaps the electrode pad P201 (second connection pad) of the second semiconductor device 20 in plan view. Similarly, the electrode pads P103, P105, P106, P108, P110, P111, P113, P115, P116, P118, and P120 (first connection pads) of the first semiconductor device 10 are the second in the plan view. The electrode pads P203, P205, P206, P208, P210, P211, P213, P215, P216, P218, and P220 (second connection pads) of the semiconductor device 20 respectively overlap. Furthermore, the electrode pad P102 (fourth connection pad) of the first semiconductor device 10 overlaps the electrode pad P202 (common pad) of the second semiconductor device 20 in plan view. Similarly, the electrode pads P104, P107, P109, P112, P114, P117, and P119 (fourth connection pads) of the first semiconductor device 10 are the electrode pads P204, Overlaps P207, P209, P212, P214, P217, and P219 (common pad). For example, as shown in FIG. 6A, the electrode pads P101, P102, P103, P104, and P105 are electrically connected to face the electrode pads P201, P202, P203, P204, and P205, respectively.

  The electrode pads P301, P303, P305, P306, P308, P310, P311, P313, P315, P316, P318, and P320 (third connection pads) of the second semiconductor device 20 are electrode pads P101 to P101 in plan view. Does not overlap any of P120. For example, as shown in FIG. 6B, the electrode pads P301, P303, and P305 do not face any of the electrode pads of the first semiconductor device 10 and are electrically cut off.

(Exposed lamination)
FIG. 7 illustrates a case where a stacked semiconductor device is configured by stacking the first semiconductor device 10 on the second semiconductor device 20 such that the partial regions R21 to R24 of the substrate 21 are exposed from the substrate 11 in plan view (exposure). In the case of lamination). Here, the substrate normal line passing through the reference points R1 and R2 from the state where the first semiconductor device 10 is stacked on the second semiconductor device 20 so that the sides of the substrates 11 and 21 coincide in plan view is used as an axis. When the substrate 11 is rotated 45 ° counterclockwise, the partial regions R21 to R24 of the substrate 21 are exposed from the substrate 11 in plan view. In this case, the electrode pads T220, T201, T202 (observation pads) are exposed from the substrate 11 in plan view.

  The electrode pad P101 (first connection pad) of the first semiconductor device 10 overlaps the electrode pad P301 (third connection pad) of the second semiconductor device 20 in plan view. Similarly, the electrode pads P103, P105, P106, P108, P110, P111, P113, P115, P116, P118, and P120 of the first semiconductor device 10 are the electrode pads P303 of the second semiconductor device 20 in plan view. , P305, P306, P308, P310, P311, P313, P315, P316, P318, and P320, respectively. Furthermore, the electrode pad P104 (sixth connection pad) of the first semiconductor device 10 overlaps the electrode pad P202 (common pad) of the second semiconductor device 20 in plan view. Similarly, the electrode pads P107, P109, P112, P114, P117, P119, and P102 (sixth connection pads) of the first semiconductor device 10 are the electrode pads P204 of the second semiconductor device 20 in plan view. Overlaps P207, P209, P212, P214, P217, and P219. For example, as shown in FIG. 8B, the electrode pads P101, P102, P103, P104, and P105 are electrically connected to face the electrode pads P301, P219, P303, P202, and P305, respectively.

  The electrode pads P201, P203, P205, P206, P208, P210, P211, P213, P215, P216, P218, and P220 (first connection pads) of the second semiconductor device 20 are electrode pads P101 to P101 in plan view. Does not overlap any of P120. For example, as shown in FIG. 8A, the electrode pads P201, P203, and P205 are not opposed to any of the electrode pads of the first semiconductor device 10 and are electrically cut off.

  As described above, since the shielding and exposure of the observation pads (electrodes T220, T201, T202) can be switched when configuring the laminated semiconductor device, the actual use product (the actually used laminated semiconductor device) and the inspection article Both (multilayer semiconductor devices used exclusively for inspection) can be configured. Thereby, the difference in configuration between the actual use product and the inspection product can be reduced, so that the difference in the signal transmission characteristics between the actual use product and the inspection product can be reduced, and as a result, The observation accuracy of the signal waveform can be improved.

  In addition, it is conceivable to modify the laminated semiconductor device by adding a signal lead line for observing the signal waveform or inserting a signal observation jig between the semiconductor devices. This leads to an increase in manufacturing cost and a decrease in yield. On the other hand, in the first embodiment, since both the actual use product and the inspection product are manufactured by the same manufacturing process, the yield is improved as compared with the case where the actual use product and the inspection product are manufactured by separate manufacturing processes. it can.

  Further, in the stacked semiconductor device of Patent Document 1, one surface of the lower semiconductor device is expanded by extending one surface of the lower semiconductor device so that one surface of the lower semiconductor device spreads outside the upper semiconductor device in plan view. Since the observation pad is formed on the outer periphery of the semiconductor device, it is difficult to reduce the area of one surface of the lower semiconductor device. On the other hand, in the stacked semiconductor device according to the first embodiment, since one surface of the substrate 21 of the second semiconductor device 20 does not need to be expanded, the scale of the stacked semiconductor device can be reduced. The substrates 11 and 21 may have the same shape or different shapes.

  In addition, since the stacking method can be switched, the degree of freedom in designing the housing structure of the stacked semiconductor device can be improved. For example, when a stacked semiconductor device is mounted on a product in the mobile field, the reference point from the state in which the first semiconductor device 10 is stacked on the second semiconductor device 20 so that the sides of the substrates 11 and 21 coincide in plan view. By configuring the stacked semiconductor device by stacking the first semiconductor device 10 on the second semiconductor device 20 by rotating the substrate 11 counterclockwise by 45 ° around the substrate normal passing through R1 and R2 as an axis In some cases, interference by the internal antenna can be avoided. In addition, by configuring the stacked semiconductor device by exposed stacking, heat is less likely to be trapped inside the stacked semiconductor device than when the stacked semiconductor device is configured by shielding stacking, and heat dissipation can be improved.

[Common pad]
Further, the common pads (P202, P204, P207, P209, P212, P214, P217, and P219) of the second semiconductor device 20 are the first in a plan view, regardless of whether they are a shielding stack or an exposed stack. It overlaps with the electrode pad of the semiconductor device 10. By forming such a common pad, the number of electrode pads formed on one surface of the second substrate 21 can be reduced. Note that a common pad may not be formed on one surface of the second substrate 21.

  The common pads (P202, P204, P207, P209, P212, P214, P217, and P219) are a power pad (an electrode pad to which a power supply voltage is applied), a ground pad (an electrode pad to which a ground voltage is applied), NC It is preferably used as any one of pads (electrode pads that are not electrically connected to other devices). In other words, the common pad potential is preferably constant. By configuring in this way, signal collision can be avoided. The common pad may be used as a signal pad for transmitting a signal. In this case, it is preferable to use either one of the two electrode pads (two electrode pads of the first semiconductor device 10) corresponding to the common pad as the NC pad.

[Same potential net]
Note that the electrode pads P220, P320, and T220 are preferably electrically connected to each other so that the topology (electrical path state) does not change between the shielded laminate and the exposed laminate. Specifically, the electrode pad P320 passes through the electrode pad T220 from the electrode pad P220 so that the wiring distance between the electrode pad P220 and the electrode pad T220 is equal to the wiring distance between the electrode pad P320. By arranging the wiring with a single stroke, the difference in waveform quality between the shielded laminate and the exposed laminate can be reduced. The same applies to the electrode pads P201, P301, and T201.

(Embodiment 2)
In the stacked semiconductor device according to the second embodiment, the first semiconductor device 30 shown in FIG. 9 is stacked on the second semiconductor device 40 shown in FIG. 10 so that one surfaces of the substrates 11 and 21 face each other. Consists of.

[First semiconductor device]
As shown in FIG. 9, a plurality of electrode pads P <b> 401 to P <b> 412, P <b> 501 to P <b> 512 are formed on one surface of the substrate 11 of the first semiconductor device 30. The other configuration of the first semiconductor device 30 is the same as that of the first semiconductor device 10 shown in FIG. The electrode pads P401 to P412 are arranged in a circular frame shape so as to surround the semiconductor chip 12 in plan view. The electrode pads P501 to P512 are also arranged in a circular frame shape so as to surround the semiconductor chip 12 in plan view. Here, the electrode pad P501 is disposed at a position obtained by rotating the electrode pad P401 counterclockwise by 45 ° about the substrate normal passing through the reference point R3 (that is, the position where the electrode pad P401 exists after rotation). The Similarly, the electrode pads P502 to P512 are disposed at positions obtained by rotating the electrode pads P402 to P412 by 45 ° counterclockwise about the substrate normal passing through the reference point R3. Here, the electrode pads P401 to P412 are used as signal pads to which signals are applied, and the electrode pads P501 to P512 are used as NC pads (electrode pads that are not electrically connected to other devices). The electrode pads P401 to P412 can be classified into electrode pad groups G41 to G44, and the electrode pads P501 to P512 can be classified into electrode pad groups G51 to G54.

[Second Semiconductor Device]
As shown in FIG. 10, a plurality of electrode pads P601 to P612, P701 to P712, T601 to T603, and the semiconductor chip 22 are formed on one surface of the substrate 21 of the second semiconductor device 40. The other configuration of the second semiconductor device 40 is the same as that of the second semiconductor device 20 shown in FIG. The electrode pads P601 to P612 are arranged in a circular frame shape so as to surround the semiconductor chip 22 in plan view. The electrode pads P701 to P712 are also arranged in a circular frame shape so as to surround the semiconductor chip 22 in plan view. Here, the electrode pad P701 is disposed at a position obtained by rotating the electrode pad P601 counterclockwise by 45 ° about the substrate normal passing through the reference point R4. Similarly, the electrode pads P702 to P712 are arranged at positions obtained by rotating the electrode pads P602 to P612 counterclockwise by 45 ° about the substrate normal passing through the reference point R4. Furthermore, the electrode pads T601 to T603 (observation pads) are arranged in the partial region R21. The electrode pads P601 to P612 can be classified into electrode pad groups G61 to G64, and the electrode pads P701 to P712 can be classified into electrode pad groups G71 to G74.

  As shown in FIG. 11, the electrode pads P601, P701, and T601 are electrically connected to each other via a package wiring or the like. Similarly, the electrode pads P602, P702, and T602 are electrically connected to each other, and the electrode pads P603, P703, and T603 are electrically connected to each other. Note that the electrode pads P604 to P612 may be electrically connected to the electrode pads P704 to P712, respectively, and corresponding observation pads (for example, electrode pads arranged in any of the partial regions R21 to R24). May be electrically connected.

(Shielding lamination)
FIG. 12 shows a case where a stacked semiconductor device is configured by stacking the first semiconductor device 30 on the second semiconductor device 40 so that the partial regions R21 to R24 of the substrate 21 are shielded by the substrate 11 in plan view. ing. Here, when the first semiconductor device 30 is stacked on the second semiconductor device 40 so that the sides of the substrates 11 and 21 coincide with each other in a plan view, the partial regions R21 to R24 of the substrate 21 are the substrate in the plan view. 11 is shielded. In this case, the electrode pads T601 to T603 are shielded by the substrate 11 in plan view.

  Further, the electrode pad groups G41, G42, G43, and G44 overlap with the electrode pad groups G61, G62, G63, and G64, respectively, in plan view. On the other hand, the electrode pad groups G51, G52, G53, and G54 overlap the electrode pad groups G71, G72, G73, and G74, respectively, in plan view.

(Exposed lamination)
FIG. 13 shows a case where a stacked semiconductor device is configured by stacking the first semiconductor device 30 on the second semiconductor device 40 so that the partial regions R21 to R24 of the substrate 21 are exposed from the substrate 11 in plan view. ing. Here, the substrate normal passing through the reference points R3 and R4 from the state where the first semiconductor device 30 is stacked on the second semiconductor device 40 so that the sides of the substrates 11 and 21 coincide in plan view is used as an axis. When the substrate 11 is rotated 45 ° counterclockwise, the partial regions R21 to R24 of the substrate 21 are exposed from the substrate 11 in plan view. In this case, the electrode pads T601 to T603 are exposed from the substrate 11 in plan view. The electrode pad groups G41, G42, G43, and G44 overlap the electrode pad groups G71, G72, G73, and G74, respectively, in plan view. On the other hand, the electrode pad groups G51, G52, G53, and G54 overlap with the electrode pad groups G64, G61, G62, and G63, respectively, in plan view.

  As described above, since the shielding and exposure of the observation pads (electrodes T601, T602, and T603) can be switched when configuring the stacked semiconductor device, both the actual use product and the inspection product can be configured. Thereby, the difference in configuration between the actual use product and the inspection product can be reduced, so that the difference in the signal transmission characteristics between the actual use product and the inspection product can be reduced, and as a result, The observation accuracy of the signal waveform can be improved.

  A plurality of other electrode pads arranged concentrically around the reference point R4 may be further formed on one surface of the substrate 21 of the second semiconductor device 40. In this case, the role of the electrode pad may be changed for each circle such as a circle used as a power supply pad, a circle used as a ground pad, and a circle used as a signal pad.

(Modification of Embodiment 2)
In the stacked semiconductor device according to the modification of the second embodiment, the first semiconductor device 30a shown in FIG. 14 is replaced with the second semiconductor device 40a shown in FIG. 15 so that the one surfaces of the substrates 11 and 21 face each other. Composed by stacking on.

[First semiconductor device]
As shown in FIG. 14, a plurality of electrode pads P401 to P403, P501 to P503, and P801 to P818 are formed on one surface of the substrate 11 of the first semiconductor device 30a. The other configuration of the first semiconductor device 30a is the same as the configuration of the first semiconductor device 30 shown in FIG. The electrode pads P801 to P818 are arranged in a circular frame shape so as to surround the semiconductor chip 12 in plan view. The electrode pads P801 to P818 can be classified into electrode pad groups G81 to G86. The electrode pad group G82 is disposed at a position obtained by rotating the electrode pad group G81 45 ° counterclockwise about the substrate normal passing through the reference point R3. Similarly, the electrode pad groups G83 to G86 are disposed at positions obtained by rotating the electrode pad groups G82 to G85 by 45 ° counterclockwise about the substrate normal passing through the reference point R3.

  Here, the semiconductor chip 12 includes a memory device (for example, a DDR memory) having four memory blocks Byte0, Byte1, Byte2, and Byte3. The electrode pad group G41 is electrically connected to the semiconductor chip 12, and is used as a signal pad for transmitting a control signal (for example, a clock signal, an address signal, a control command, etc.). The four electrode pad groups G81, G82, G83, and G84 are electrically connected to the four memory blocks Byte0, Byte1, Byte2, and Byte3 included in the semiconductor chip 12, respectively. The electrode pad groups G51, G85, and G86 are used as NC pads.

[Second Semiconductor Device]
As shown in FIG. 15, a plurality of electrode pads P601 to P603, P701 to P703, T601 to T603, P901 to P918, and the semiconductor chip 22 are formed on one surface of the substrate 21 of the second semiconductor device 40a. . The other configuration of the second semiconductor device 40a is the same as that of the second semiconductor device 40 shown in FIG. The electrode pads P901 to P918 are arranged in a circular frame shape so as to surround the semiconductor chip 22 in plan view. The electrode pads P901 to P918 can be classified into electrode pad groups G91 to G96. The electrode pad group G92 is disposed at a position obtained by rotating the electrode pad group G91 by 45 ° counterclockwise about the substrate normal passing through the reference point R4. Similarly, the electrode pad groups G93 to G96 are disposed at positions obtained by rotating the electrode pad groups G92 to G95 counterclockwise by 45 ° about the substrate normal passing through the reference point R4.

  Here, it is assumed that the semiconductor chip 22 outputs a control signal for controlling the memory device included in the semiconductor chip 12. The electrode pad groups G61 and G71 are electrically connected to the semiconductor chip 22 and are used as signal pads for transmitting control signals. The electrode pad groups G61 and G71 are equivalent to each other. The electrode pad groups G91 and G95 are electrically connected to the semiconductor chip 22. The electrode pad groups G91 and G95 are equivalent to each other. The electrode pad groups G92, G93, and G94 are electrically connected to the semiconductor chip 22. The electrode pad group G96 is used as an NC pad. The wiring extending from the semiconductor chip 22 may be branched into two and connected to the electrode pad groups G61 and G71. A signal path between the semiconductor chip 22 and each of the electrode pad groups G61 and G71 may be connected to the semiconductor chip. 22 may be switched. The same applies to the electrode pad groups G91 and G95.

(Shielding lamination)
FIG. 16 shows a case where a stacked semiconductor device is configured by stacking the first semiconductor device 30a on the second semiconductor device 40a so that the partial regions R21 to R24 of the substrate 21 are shielded by the substrate 11 in plan view. ing. In this case, the electrode pad groups G41, G51, G81, G82,..., G86 overlap with the electrode pad groups G61, G71, G91, G92,. That is, the semiconductor chip 22 supplies a control signal to the semiconductor chip 21 via the electrode pad groups G61 and G41. Further, the semiconductor chip 22 reads / writes data from / to the memory block Byte0 via the electrode pad groups G81, G91. Similarly, reading / writing of data with respect to the memory block Byte1 is executed via the electrode pad groups G82 and G92, and reading / writing of data with respect to the memory block Byte2 is executed via the electrode pad groups G83 and G93. Reading / writing of data with respect to the block Byte3 is executed via the electrode pad groups G84 and G94. Since the electrode pad group G71 is electrically connected to the electrode pad group G51 used as the NC pad, the control signal from the semiconductor chip 22 is not transmitted by mistake. The electrode pad group G95 is electrically connected to an electrode pad group G85 used as an NC pad.

(Exposed lamination)
FIG. 17 shows a case where a stacked semiconductor device is configured by stacking the first semiconductor device 30a on the second semiconductor device 40a so that the partial regions R21 to R24 of the substrate 21 are exposed from the substrate 11 in plan view. ing. In this case, the electrode pad groups G41, G51, G81, G82,..., G86 overlap with the electrode pad groups G71, G91, G92, G93,. That is, the semiconductor chip 22 supplies a control signal to the semiconductor chip 21 via the electrode pad groups G71 and G41. Further, the semiconductor chip 22 reads / writes data from / to the memory block Byte0 via the electrode pad groups G84 and G95. Similarly, data read / write with respect to the memory block Byte1 is executed via the electrode pad groups G81 and G92, and data read / write with respect to the memory block Byte2 is executed via the electrode pad groups G82 and G93. Reading / writing of data with respect to block Byte3 is performed via electrode pad group G83, G94. In this way, signal replacement is performed in units of memory blocks. Since the electrode pad group G61 is electrically connected to the electrode pad group G86 used as the NC pad, the control signal from the semiconductor chip 22 is not transmitted by mistake. The electrode pad group G91 is electrically connected to an electrode pad group G51 used as an NC pad.

  The memory blocks Byte0, Byte1, Byte2, and Byte3 may be in byte units or word units.

(Other embodiments)
In the above embodiment, the reference points R1, R2 (or R3, R4) are determined from the state in which the first semiconductor device is stacked on the second semiconductor device so that the sides of the substrates 11, 21 coincide in plan view. Although an example in which the substrate 11 is rotated 45 ° counterclockwise with the passing substrate normal as an axis has been described, the stacking method (rotation angle, stacking position, etc.) is arbitrary, and the electrode depends on the stacking method. What is necessary is just to arrange a pad.

  As described above, the stacked semiconductor device described above can improve the observation accuracy of signal waveforms, and thus can be applied to various fields.

10 Semiconductor device (first semiconductor device)
11 Substrate (first substrate)
12 Semiconductor chips P100, P101 to P120 Electrode pad 20 Semiconductor device (second semiconductor device)
21 Substrate (second substrate)
22 Semiconductor chips P200, P201 to P220, P301 to P320 Electrode pads P401 to P412, P501 to P512 Electrode pads P601 to P612, P701 to P712 Electrode pads P801 to P818 Electrode pads P901 to P918 Electrode pads

Claims (6)

A first semiconductor device including a rectangular first substrate and a plurality of electrode pads formed on one surface of the first substrate;
A second semiconductor device including a rectangular second substrate and a plurality of electrode pads formed on one surface of the second substrate;
The first semiconductor device is stacked on the second semiconductor device such that one surface of each of the first and second substrates faces each other,
The plurality of electrode pads of the first semiconductor device include a first connection pad,
The plurality of electrode pads of the second semiconductor device include second and third connection pads and an observation pad that are electrically connected to each other,
When the first semiconductor device is stacked on the second semiconductor device so that a partial region that is a part of one surface of the second substrate in a plan view is shielded by the first substrate, In the plan view, the first connection pad overlaps the second connection pad,
When the first semiconductor device is stacked on the second semiconductor device so that the partial region is exposed from the first substrate in the plan view, the first connection pad in the plan view is Overlapping the third connection pad;
The stacked semiconductor device, wherein the observation pad is disposed in the partial region. In claim 1,
The plurality of electrode pads of the first semiconductor device include fourth and fifth connection pads,
The plurality of electrode pads of the second semiconductor device include a common pad,
When the first semiconductor device is stacked on the second semiconductor device so that the partial region is shielded by the first substrate in the plan view, the fourth connection pad is in the plan view. Overlapping the common pad,
When the first semiconductor device is stacked on the second semiconductor device so that the partial region is exposed from the first substrate in the plan view, the fifth connection pad in the plan view is A laminated semiconductor device overlaid on the common pad. In claim 2,
A laminated semiconductor device, wherein the common pad has a constant potential. In claim 3,
A signal applied to each of the fourth and fifth connection pads can be interchanged with each other. In claim 4,
The first semiconductor device further includes first and second memory blocks,
The fourth connection pad is electrically connected to the first memory block,
The stacked semiconductor device, wherein the fifth connection pad is electrically connected to a second memory block. In claim 3,
The second semiconductor device further includes a semiconductor chip,
The stacked semiconductor device, wherein the semiconductor chip selectively receives a signal applied to each of the fourth and fifth connection pads.

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