JP2013026305A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which ensures precise patterning of a line space pattern and a wide pattern, even if both patterns are mixed.SOLUTION: In the manufacturing method of a semiconductor device, a hard mask layer is formed on a processed layer. A first mask layer is formed thereon and patterned. A carbon layer is formed in a region from where the first mask layer is removed, and patterned. Pattern width of the carbon layer is reduced by etching the carbon layer partially. A second mask layer is formed of the same material as that of the first mask layer, and etched so as to leave the second mask layer on both side faces of the pattern of the carbon layer. The carbon layer sandwiched by the patterns of the second mask layer is removed. A hard mask layer is patterned using the patterns of the first and second mask layers as a mask. The patterns of the first and second mask layers are removed. The processed layer is patterned using the hard mask layer as a mask.

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  Nonvolatile semiconductor memory devices using semiconductor elements such as EEPROM, AND flash memory, NOR flash memory, NAND flash memory, etc. have been widely known. Among them, the NAND flash memory is advantageous for high integration because each memory cell shares a source / drain diffusion layer.

  However, in order to promote higher integration of the NAND flash memory, there is a limit to fine processing technology, particularly lithography technology for transferring a pattern to a semiconductor substrate. As a technique for breaking the limit of the lithography technique, there is a side wall transfer technique which is a kind of “double patterning”. The sidewall transfer technique is a technique in which a pattern narrower than the line pattern width is formed on both side surfaces of a line pattern formed by using the limits of the lithography technique, and the pattern is processed using this pattern as a mask.

  In addition, for example, when a fine line space pattern and a wide pattern are mixed, such as the gate electrode of the memory cell transistor and the gate electrode of the selection transistor at the end of the memory cell array, both are used in the same lithography process. It is difficult to pattern by this. This is due to the fact that the optimum lithography conditions for the two differ. For this reason, a technique of forming a fine line space pattern and other patterns by different lithography processes may be used.

JP 2010-153872 A JP 2010-245173 A

  The problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device that processes both patterns with high precision even when a line space pattern and a pattern wider than the line space pattern coexist.

  In the method for manufacturing a semiconductor device according to the embodiment, a processing layer is formed on a semiconductor substrate, a hard mask layer is formed on the processing layer, a first mask layer is formed on the hard mask layer, The first mask layer is patterned, a carbon layer is formed in a region where the first mask layer is removed, the carbon layer is patterned, and a pattern of the carbon layer is partially formed by a first etching process. Etching to reduce the width of the pattern of the carbon layer, forming a second mask layer of the same material as the first mask layer so as to cover the upper surface and both side surfaces of the pattern of the carbon layer, The second mask layer is etched by the etching process to remove the second mask layer on the upper surface of the carbon layer pattern, and to the front side surfaces of the carbon layer pattern. The second mask layer is left, the carbon layer sandwiched between the patterns of the second mask layer is removed by a third etching process, and the pattern of the first mask layer and the pattern of the second mask layer are removed. The hard mask layer is patterned using the mask as a mask, the first mask layer pattern and the second mask layer pattern are removed by a fourth etching process, and the hard mask layer pattern is used as the mask to be processed. Pattern the layer.

It is process drawing which shows the principal part of the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process drawing which shows the principal part of the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a schematic cross section which shows the manufacturing method of the semiconductor device of 2nd Embodiment.

(First embodiment)
In the method for manufacturing a semiconductor device of this embodiment, a layer to be processed is formed over a semiconductor substrate, and a hard mask layer is formed over the layer to be processed. Then, a first mask layer is formed on the hard mask layer, and the first mask layer is patterned. Then, a carbon layer is formed in the region where the first mask layer has been removed, and the carbon layer is patterned. Then, the carbon layer is partially etched by the first etching process to reduce the pattern width of the carbon layer. Then, a second mask layer made of the same material as that of the first mask layer is formed so as to cover the upper surface and both side surfaces of the pattern of the carbon layer, and the second mask layer is etched by the second etching process, and the carbon layer The second mask layer on the upper surface of the pattern is removed, and the second mask layer is left on both side surfaces of the carbon layer pattern. Then, the carbon layer sandwiched between the patterns of the second mask layer is removed by the third etching process. Then, the hard mask layer is patterned using the pattern of the first mask layer and the pattern of the second mask layer as a mask. Then, the pattern of the first mask layer and the pattern of the second mask layer are removed by the fourth etching process. Further, the layer to be processed is patterned using the pattern of the hard mask layer as a mask.

  Note that in this embodiment, an example in which a NAND flash memory is processed as a semiconductor device and a gate electrode layer is processed as a processing layer is described.

  When a fine line space pattern and a wide pattern are mixed, such as a gate electrode wiring (word line) of a memory cell transistor of a NAND flash memory and a gate electrode wiring of a selection gate transistor adjacent thereto Therefore, it becomes difficult to set lithography conditions for patterning both at a time with high accuracy. According to the manufacturing method of the present embodiment, a wide pattern is formed first, and then a fine line space pattern is formed. Further, the same material is used for the mask layer in the middle of processing in both patterns, and the final etching of the layer to be processed is performed by using the mask layer without shoulder drop. Thereby, even when a fine line space pattern and a wide pattern are mixed, both can be processed with high accuracy.

  FIG. 1 is a process diagram showing the main part of the semiconductor device manufacturing method of the present embodiment. 2 to 15 are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment. 4 to 15 show cross sections perpendicular to the word line direction of the gate electrode of the memory cell transistor and the gate electrode of the select gate transistor.

  In this specification, the gate electrode of the memory cell transistor is also referred to as a memory cell gate electrode, and the gate electrode of the selection gate transistor is also referred to as a selection gate electrode.

  First, as shown in FIG. 2, a gate electrode layer which is a layer to be processed is formed (S102). The gate electrode layer has a stacked structure of the gate insulating film 12, the floating gate electrode 14, the intergate insulating film 16, the control gate electrode 18, and the gate mask insulating film 20 on the semiconductor substrate 10.

  An opening 22 is provided by removing a part of the inter-gate insulating film 16, and the floating gate electrode 14 and the control gate electrode 18 are in physical contact and are also electrically connected. The gate electrode layer in the region where the opening 22 is provided will later constitute the selection gate electrode.

  The semiconductor substrate is, for example, p-type silicon. The gate insulating film 12 is a silicon oxide film formed by thermal oxidation, for example. The floating gate electrode 14 is, for example, a polycrystalline silicon film doped with phosphorus (P) formed by LPCVD (Low-Pressure-Chemical-Vapor-Deposition) method. The inter-gate insulating film 16 is, for example, an ONO (Oxide-Nitride-Oxide) film. The control gate electrode 18 is a polycrystalline silicon layer 18 formed by LPCVD, for example. The gate mask insulating film 20 is a silicon nitride film formed by LPCVD, for example.

  Further, an amorphous silicon (amorphous silicon) film 24 is formed on the gate electrode layer as a hard mask layer (S104). The amorphous silicon film 24 is formed by, for example, the LPCVD method. It is also possible to apply a polycrystalline silicon film to the hard mask layer.

  On the amorphous silicon film 24, a silicon oxide film 26 is formed as a first mask layer (S106). The silicon oxide film 26 is a TEOS (Tetraethyl orthosilicate) film formed by LPCVD, for example.

  Next, as shown in FIG. 3, a resist pattern 28 for patterning the silicon oxide film 26 is formed by lithography (S108). This pattern is a pattern for forming the selection gate electrode.

  Next, as shown in FIG. 4, using the resist pattern 28 as a mask, the silicon oxide film 26 is etched and patterned by RIE (Reactive Ion Etching) (S110).

  Next, as shown in FIG. 5, the resist pattern 28 is removed, and a carbon layer 30 is formed in the region where the silicon oxide film 26 has been removed (S112). Here, the carbon layer 30 is comprised with the material which has carbon (C) as a main component.

  The carbon layer 30 is formed, for example, by planarizing an amorphous carbon film formed by a spin coating method or a CVD (Chemical Vapor Deposition) method by a CMP (Chemical Mechanical Polishing) method. At the time of planarization by the CMP method, the silicon oxide film 26 becomes a stopper film.

  Next, as shown in FIG. 6, a resist pattern 32 for patterning the carbon layer 30 is formed by lithography (S114). This pattern is a pattern for forming a memory cell gate electrode.

  Next, as shown in FIG. 7, the carbon layer 30 is etched and patterned by the RIE method using the resist pattern 32 as a mask (S116).

  Next, as shown in FIG. 8, the resist pattern 32 is peeled off.

  Next, as shown in FIG. 9, in the first etching process, the pattern of the carbon layer 30 is partially etched to reduce the pattern width of the carbon layer 30. That is, so-called slimming is performed (S118). This etching is performed by ashing, for example.

  Next, as shown in FIG. 10, a second mask layer of the same material as the first mask layer is formed so as to cover the upper surface and both side surfaces of the pattern of the carbon layer 30. Since the first mask layer is the silicon oxide film 26, the silicon oxide film 34 is also formed as the second mask layer (S120). The silicon oxide film 34 is a TEOS film formed by LPCVD, for example.

  In the present specification, the “same material” means materials having the same main composition and similar characteristics to processes such as etching. Even if there is a slight difference in the chemical composition ratio, a difference in the type of impurities contained, or a difference in the content, materials having similar characteristics to the process shall be regarded as “the same material”.

  Next, as shown in FIG. 11, in the second etching process, the entire surface of the silicon oxide film 34 as the second mask layer is etched by the RIE method (S122). Then, the silicon oxide film 34 on the upper surface of the pattern of the carbon layer 30 is removed, and the silicon oxide film 34 is left on both side surfaces of the pattern of the carbon layer 30 by leaving the side walls.

  In this way, a pattern of the silicon oxide film 34 of the second mask layer, which is narrower than the pattern of the silicon oxide film 26 that is the first mask layer, is formed. In other words, the pattern width of the first mask layer is wider than the pattern width of the second mask layer. Note that the silicon oxide film 34 remains on both side surfaces of the pattern of the silicon oxide film 26 by leaving the side walls.

  Next, as shown in FIG. 12, in the third etching process, the carbon layer 30 sandwiched between the patterns of the silicon oxide film 34 as the second mask layer is removed (S124). This etching process is performed by ashing, for example.

  Next, as shown in FIG. 13, the amorphous silicon film 24 as the hard mask layer is patterned using the pattern of the silicon oxide film 26 as the first mask layer and the pattern of the silicon oxide film 34 as the second mask layer as a mask. (S126). This patterning is performed by etching by the RIE method.

  Next, as shown in FIG. 14, in the fourth etching process, the pattern of the silicon oxide film 26 that is the first mask layer and the pattern of the silicon oxide film 34 that is the second mask layer are removed (S128). This etching is performed, for example, by wet etching using a hydrofluoric acid solution.

  Next, as shown in FIG. 15, the gate electrode layer, which is a layer to be processed, is patterned using the pattern of the amorphous silicon film 24, which is a hard mask layer, as a mask (S130). This patterning is performed by etching using the RIE method. By this patterning, the gate electrode layer is processed, and the memory cell gate electrode MC and the selection gate electrode SG are formed. The amorphous silicon film 24 is used as an etching mask during the etching of the gate mask insulating film 20 in the gate electrode layer. However, after the gate mask insulating film 20 is processed once, the control gate electrode 18, It may disappear during the etching of the inter-gate insulating film 16 and the floating gate electrode 14.

  As described above, in the manufacturing method of the semiconductor device of the present embodiment, the amorphous silicon film 24 is patterned by applying the sidewall transfer technique using the carbon layer 30 as a core material and the silicon oxide film 34 as a sidewall material. By selecting carbon that can be removed by combustion by ashing as the core material, it is possible to suppress the collapse of the side wall material in the core material removal step as compared with the process of removing the core material by wet etching.

  According to the method for manufacturing a semiconductor device of the present embodiment, a silicon oxide film made of a single material is used as a mask material when etching the amorphous silicon film 24 serving as a hard mask layer. Therefore, for example, as compared with the case where the mask material for forming the memory cell gate electrode MC and the mask material for forming the selection gate electrode SG are made of different materials, the processing becomes easier and the processing accuracy is improved. Processing is easy because a single mask material has fewer restrictions on etching conditions than two or more mask materials.

  In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the silicon oxide films 26 and 34 formed by leaving the sidewall are removed before patterning the gate electrode layer using the amorphous silicon film 24 as a mask material. For this reason, when patterning the gate electrode layer, processing is possible without using a mask material having a shape with a shoulder portion dropped. Therefore, the problem that the width of the memory cell gate electrode changes every other line and the taper shape of the select gate electrode becomes prominent is less likely to occur due to the shoulder fall of the mask material. Therefore, dimensional variation and shape variation of the gate electrode layer are suppressed.

  In this embodiment, the processing without using the mask material with the shape of the shoulder part is made possible by adopting a silicon oxide film that is easy to be removed by wet etching as a side wall material of the side wall transfer technology. by.

  Further, according to the method of manufacturing the semiconductor device of the present embodiment, the pattern of the fine line and space memory cell gate electrode MC repeated at the same pitch and the selection gate electrode SG wider than the memory cell gate electrode are separately provided. The lithography process is used. Therefore, it becomes possible to apply an optimum lithography condition to each pattern, and the processing accuracy is improved.

  In addition, according to the method for manufacturing a semiconductor device of the present embodiment, lithography of the select gate electrode SG is performed before lithography of the memory cell gate electrode MC. This facilitates the use of a single material silicon oxide film as a mask material when etching the amorphous silicon film 24 to be a hard mask layer. In addition, since the pattern of the selection gate electrode SG having a large width and a large space is formed first, and lithography alignment (alignment) of the memory cell gate electrode MC is performed on this pattern, alignment of lithography becomes easy. Therefore, the amount of misalignment between patterns is suppressed, and highly accurate processing is realized. In addition, the number of rework due to the misalignment exceeding a predetermined range can be reduced.

  Furthermore, according to the manufacturing method of the semiconductor device of the present embodiment, the pattern of the selection gate electrode SG is made a leading edge, and the pattern of the fine memory cell gate electrode MC is made afterward. Thereby, the mask pattern for forming the fine memory cell gate electrode MC can be prevented from falling in the process after the formation.

(Second Embodiment)
In the method of manufacturing a semiconductor device according to the present embodiment, when patterning a carbon layer, a photomask in which a line space pattern continuous from a position corresponding to the carbon layer is provided also at a position corresponding to the first mask layer is used. To expose. Further, after the third etching process, the first mask layer is further patterned. Other than the above, the second embodiment is the same as the first embodiment. Therefore, a part of the description overlapping with that of the first embodiment is omitted.

  According to the present embodiment, during lithography of the memory cell gate electrode MC, the pattern is formed in a self-aligned manner with respect to the pattern of the selection gate electrode SG. Therefore, the lithography of the memory cell gate electrode MC is further facilitated.

  FIG. 16 is a process diagram showing the main part of the method for manufacturing the semiconductor device of the present embodiment. FIGS. 17 to 30 are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment. 17 to 30 show cross sections of the memory cell gate electrode and the select gate electrode perpendicular to the word line direction.

  First, as shown in FIG. 17, a gate electrode layer which is a layer to be processed is formed (S102). The gate electrode layer has a laminated structure of the insulating film 12, the floating gate electrode 14, the intergate insulating film 16, the control gate electrode 18, and the gate mask insulating film 20 on the semiconductor substrate 10. An opening 22 is provided by removing a part of the inter-gate insulating film 16.

  Further, an amorphous silicon (amorphous silicon) film 24 is formed on the gate electrode layer as a hard mask layer (S104).

  On the amorphous silicon film 24, a silicon oxide film 26 is formed as a first mask layer (S106).

  Next, a resist pattern 40 for patterning the silicon oxide film 26 is formed by lithography (S108). This pattern is a pattern for forming the selection gate electrode. The resist pattern 40 is a pattern that defines the gate end of the select gate electrode on the memory cell electrode side.

  Next, as shown in FIG. 18, using the resist pattern 40 as a mask, the silicon oxide film 26 is etched and patterned by the RIE method (S110).

  Next, as shown in FIG. 19, the resist pattern 40 is peeled off, and the carbon layer 30 is formed in the region where the silicon oxide film 26 is removed (S112).

  Next, as shown in FIG. 20, a resist pattern 42a for patterning the carbon layer 30 is formed by lithography (S114). This pattern is a pattern for forming the gate electrode of the memory cell transistor.

  In this lithography, exposure is performed using a photomask provided with a line space pattern continuous from a position corresponding to the carbon layer 30 at a position corresponding to the pattern of the silicon oxide film 26 as the first mask layer. That is, exposure is performed with a photomask having a line space pattern of the memory cell gate electrode up to a position where the selection gate electrode is originally formed, as in a virtual pattern 42b indicated by a dotted line in the drawing. In this photomask, a line space pattern of fine memory cell gate electrodes having the same pitch is continuously provided also in a region where a selection gate electrode is formed.

  In this case, like the virtual pattern 42b, the photomask pattern on the silicon oxide film 26 which is the first mask layer and in the vicinity thereof is not formed on the semiconductor substrate as an actual resist pattern. For this reason, the resist pattern 42a of the memory cell gate electrode can be formed in a self-aligned pattern on the selection gate electrode only in the region that should be originally formed.

  This is a phenomenon caused by a difference in reflectance between the carbon layer 30 and the silicon oxide film 26. A resist pattern can be formed by such self-alignment by appropriately selecting the process conditions in lithography such as the reflectance of the base film and the resist. Therefore, it is easier to align lithography for forming the gate electrode of the memory cell transistor.

  Next, as shown in FIG. 21, the carbon layer 30 is etched and patterned by the RIE method using the resist pattern 42a as a mask (S116).

  Next, as shown in FIG. 22, the resist pattern 32 is peeled off.

  Next, as shown in FIG. 23, the pattern width of the carbon layer 30 is reduced by partially etching the pattern of the carbon layer 30 in the first etching process. That is, so-called slimming is performed (S118).

  Next, as shown in FIG. 24, after the resist pattern 42a is peeled off, a second mask layer made of the same material as the first mask layer is formed so as to cover the upper surface and both side surfaces of the pattern of the carbon layer 30. . Since the first mask layer is the silicon oxide film 26, the silicon oxide film 34 is also formed as the second mask layer (S120).

  Next, as shown in FIG. 25, in the second etching process, the entire surface of the silicon oxide film 34 as the second mask layer is etched by RIE (S122). Then, the silicon oxide film 34 on the upper surface of the pattern of the carbon layer 30 is removed, and the silicon oxide film 34 is left on both side surfaces of the pattern of the carbon layer 30 by leaving the side walls.

  Next, as shown in FIG. 26, in the third etching process, the carbon layer 30 sandwiched between the patterns of the silicon oxide film 34 as the second mask layer is removed (S124).

  Next, as shown in FIG. 27, a resist pattern 44 for patterning the silicon oxide film 26 is formed again by lithography (S132). This pattern is a pattern for forming the selection gate electrode. The resist pattern 44 is a pattern that defines a gate end portion of the selection gate electrode opposite to the memory cell electrode.

  Next, as shown in FIG. 28, the silicon oxide film 26 is etched and patterned by the RIE method using the resist pattern 44 as a mask (S134).

  Next, after removing the resist pattern 44 as shown in FIG. 29, the hard mask layer is formed using the pattern of the silicon oxide film 26 as the first mask layer and the pattern of the silicon oxide film 34 as the second mask layer as a mask. The amorphous silicon film 24 is patterned (S126).

  Next, as shown in FIG. 30, in the fourth etching process, the pattern of the silicon oxide film 26 that is the first mask layer and the pattern of the silicon oxide film 34 that is the second mask layer are removed (S128).

  Thereafter, by patterning the gate electrode layer that is the layer to be processed using the pattern of the amorphous silicon film 24 that is the hard mask layer as a mask, the memory cell gate electrode MC and the selection gate electrode SG as shown in FIG. 15 are formed. The

  According to the present embodiment, in addition to the effects of the first embodiment, the resist pattern of the memory cell gate electrode MC can be formed on the pattern of the selection gate electrode by self-alignment. Therefore, the lithography of the memory cell gate electrode MC is further facilitated.

  The embodiments of the present invention have been described above with reference to specific examples. The above embodiment is merely given as an example, and does not limit the present invention. In the description of the embodiment, the description of the semiconductor device, the manufacturing method of the semiconductor device, etc., which is not directly necessary for the description of the present invention is omitted, but the required semiconductor device and the semiconductor device are not described. Elements relating to the manufacturing method and the like can be appropriately selected and used.

  For example, in the embodiment, the case where the processing layer is a gate electrode layer of a NAND flash memory has been described as an example. However, the processing layer is, for example, a mask material, a semiconductor substrate, a bit line, or the like for forming an element region. An interlayer insulating film or the like for forming a damascene wiring may be used.

  For example, the NAND flash memory has been described as an example of the semiconductor device. However, the present invention is applicable to any semiconductor device as long as the semiconductor device has a layout in which a line space pattern and a pattern wider than the line space pattern are mixed. Applicable.

  For example, the resist has been described by taking a single layer resist as an example, but a process using a multilayer resist may be applied.

  In addition, any semiconductor device manufacturing method that includes the elements of the present invention and that can be appropriately modified by those skilled in the art is included in the scope of the present invention. The scope of the present invention is defined by the appended claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 Gate insulating film 14 Floating electrode 16 Inter-gate insulating film 18 Control gate electrode 20 Gate mask insulating film 24 Amorphous silicon film (hard mask layer)
26 Silicon oxide film (first mask layer)
30 Carbon layer 34 Silicon oxide film (second mask layer)
MC Memory cell gate electrode SG Select gate electrode

Claims (5)

Forming a work layer on a semiconductor substrate;
Forming a hard mask layer on the layer to be processed;
Forming a first mask layer on the hard mask layer;
Patterning the first mask layer;
Forming a carbon layer in the region where the first mask layer is removed;
Patterning the carbon layer;
The carbon layer pattern is partially etched by the first etching process to reduce the width of the carbon layer pattern,
Forming a second mask layer of the same material as the first mask layer so as to cover the upper surface and both side surfaces of the pattern of the carbon layer;
The second mask layer is etched by a second etching process to remove the second mask layer on the upper surface of the carbon layer pattern, and the second mask layer is formed on both sides of the carbon layer pattern. Let it remain,
Removing the carbon layer sandwiched between the patterns of the second mask layer by a third etching process;
Patterning the hard mask layer using the pattern of the first mask layer and the pattern of the second mask layer as a mask;
Removing the pattern of the first mask layer and the pattern of the second mask layer by a fourth etching process;
A method of manufacturing a semiconductor device, wherein the layer to be processed is patterned using a pattern of the hard mask layer as a mask.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the pattern width of the first mask layer is wider than the pattern width of the second mask layer.   3. The hard mask layer according to claim 1, wherein the hard mask layer is an amorphous or polycrystalline silicon film, and the first mask layer and the second mask layer are silicon oxide films. A method for manufacturing a semiconductor device.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the first etching process and the second etching process are ashing. 5. When patterning the carbon layer, exposure is performed using a photomask provided with a line space pattern continuous from a position corresponding to the carbon layer at a position corresponding to the pattern of the first mask layer, The method of manufacturing a semiconductor device according to claim 1, wherein the first mask layer is further patterned after the etching process 3.

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