JP2008211027A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To pattern a shape at a good accuracy for processing when a micro hole pattern like a contact hole in a semiconductor integrated circuit is formed. <P>SOLUTION: A hard mask is manufactured for forming the contact hole. This hard mask is constituted by overlapping a first hard mask 32 formed in a direction parallel to an element formation region 17 with a second hard mask 34 formed in a direction intersecting the element formation region 17, these hard masks being manufactured at the other lithography steps, respectively. The first hard mask 32 and the second hard mask 34 have a stripe-shaped opening and an opening of the contact hole is formed at its intersection part. By use of the hard mask manufactured by such a process of a two-time exposure and two-time processing, it becomes possible to process a more micro and identical contact hole than patterning by a reticle of a hole-shaped pattern. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a method for manufacturing a semiconductor device, and to a method for manufacturing an electrically rewritable nonvolatile semiconductor memory device. In particular, the present invention relates to a manufacturing method of a NOR type nonvolatile semiconductor memory device.

With higher performance of semiconductor integrated circuits, microprocessors and large-capacity semiconductor memories have been developed, contributing to the progress of the information society. In particular, non-volatile semiconductor memory that can be electrically written and erased and can retain stored data even when the power is turned off is increasing the storage capacity. The media market is also surpassing.

The progress of such technology greatly contributes to the miniaturization of semiconductor integrated circuits. Photolithography technology has supported the miniaturization of semiconductor integrated circuits. Today, resolution of nanometer level is realized, and further miniaturization measures are being studied.

The photolithography technique is performed using an exposure apparatus for projecting and exposing a desired pattern onto a photoresist coated on a semiconductor wafer and an exposure mask on which a fine pattern called a reticle is formed. A contact hole pattern is considered to be difficult in this photolithography technique. A contact hole is an opening formed in an interlayer insulating layer in a semiconductor integrated circuit, and is formed to connect an upper layer wiring and a lower layer wiring. Usually, a pattern corresponding to a contact hole is formed on a reticle, and projection exposure is performed on the photoresist by one exposure using this, and a resist pattern is formed after development. Then, using the resist pattern as a mask, the interlayer insulating layer is etched to form contact holes.

In a transistor which is a main component in a semiconductor integrated circuit, fine diffusion layers called a source region and a drain region are formed. The wiring needs to form a contact through its fine diffusion layer and a contact hole formed in the interlayer insulating layer. The contact hole needs to be reliably formed on the fine diffusion layer.

In the cell array of the NOR type flash memory, memory cells MC are arranged in a matrix. Bit lines BL extend in the column direction of the memory cell array, and word lines WL and source lines LI extend in the row direction.

In the memory cell array, adjacent memory cells MC are connected in series in the column direction so that adjacent ones share a source region or a drain region. That is, adjacent memory cells MC are arranged so as to share a source region or a drain region. The bit line BL forms a drain contact DC with the drain region of the memory cells MC in the same column. The word line WL extends in the row direction, and is provided so as to form a common connection in the same row of the control gate electrode of the memory cell MC and the cell array.

As described above, in the memory cell array of the NOR type flash memory, the drain contact DC connected to the bit line BL is required at a ratio of one for two memory cells. Therefore, the drain contacts DC are periodically arranged in the memory cell array. The drain contact DC is provided at a position sandwiched between the word line WL and the element isolation region 18, and it is necessary to form a minute drain contact hole with high precision as the memory cell is miniaturized. Therefore, high processing accuracy is required for the memory cell array.

On the other hand, the diameter of the contact hole needs to be formed as wide as possible in order to reduce the contact resistance in a limited minute region. Therefore, it is desired that the contact hole has a rectangular opening. As is apparent from the layout of the memory cell array, this is for maximizing the permitted area.

However, even if a rectangular opening pattern is formed as a contact hole on a reticle used in a photolithography process, the shape of the pattern transferred to the photoresist is deformed. In practice, the resist pattern transferred by exposure has a problem that the corners of the openings are rounded, and only a substantially circular opening pattern can be formed, compared to the rectangular opening pattern formed on the reticle. The cause of this depends on the material of the photoresist, but the resolution of the exposure apparatus has a great influence.

In this case, how fine contact holes can be formed is almost determined by the capabilities of the exposure apparatus and the photoresist. In principle, when the diameter of the contact hole formed as an isolated pattern on the reticle is reduced, there is a problem that a projection pattern with sufficient resolution cannot be obtained due to the diffraction effect of light transmitted through these.

As a method for projecting and exposing a minute pattern, a cross exposure method is known in which exposure is performed twice using two reticles that intersect each other. However, since the cross exposure method repeats the exposure twice, it is necessary to repeat the alignment between the reticle and the semiconductor wafer twice, and the process controllability and productivity are poor. On the other hand, a method has been proposed in which a cross pattern having different polarization planes is formed on a reticle using polarization of light, and exposure is performed twice with different polarization directions (see, for example, Patent Document 1). ). According to this method, the alignment process between the reticle and the semiconductor wafer can be performed only once. However, in this method as well, there is no change in exposing the photoresist twice, and problems such as controllability of exposure conditions and expensive reticles remain.

Also, a plurality of types of reticles are prepared, and each reticle pattern is formed so that a contact hole pattern is formed in the common part of the light transmitting part formed in each reticle pattern, and the total exposure for the common part is performed. A multiple exposure method has been proposed in which exposure is performed by determining an exposure amount each time so that the amount exceeds the threshold value of the resist (see, for example, Patent Document 2). However, this method also has a drawback in the controllability and defects of the photoresist and is not a practical technique.
JP-A-6-118624 Japanese Patent Laid-Open No. 10-232496

The present invention provides a method for manufacturing a semiconductor device capable of accurately patterning and processing a shape when forming a fine hole pattern such as a contact hole in a semiconductor integrated circuit.

According to one embodiment of the present invention, an element isolation region and an element formation region are formed in a semiconductor substrate, a gate electrode is formed in the element formation region, and the element formation region has a one conductivity type in an outer region of the gate electrode. An impurity insulating region is formed, an interlayer insulating layer is formed on the element forming region to embed the gate electrode, and the one-conductivity type impurity region and the gate electrode are striped across the interlayer insulating layer. Forming a first hard mask having an opening pattern, having an opening pattern in a direction intersecting the first hard mask, and the opening is located on the impurity region of one conductivity type; Forming and etching the interlayer insulating layer exposed at the intersection of the opening patterns of the first hard mask and the second hard mask to penetrate the impurity region of one conductivity type. It is a manufacturing method of a semiconductor device and having forming a contact hole.

According to one embodiment of the present invention, a hard mask having a fine structure that opens a contact hole is formed by performing two photolithography processes using at least two types of reticles having a stripe pattern. Can do. By using the hard mask thus manufactured as an etching mask, a contact hole with a high aspect ratio can be formed. Further, by processing the contact hole by dry etching using the hard mask described above, high etching selectivity can be obtained compared to the resist, so that the recession of the mask pattern edge can be suppressed and a fine contact hole can be easily formed. be able to.

In the manufacturing process of the semiconductor device according to one embodiment of the present invention, a method for forming a contact hole in the interlayer insulating layer will be described. In a semiconductor integrated circuit, a contact hole connects an impurity region formed by adding one conductivity type impurity (an impurity element imparting n-type or p-type) to a semiconductor substrate and a wiring, or through an interlayer insulating layer. It is necessary to connect the wirings formed in the same way. In the present embodiment, a process of forming a contact hole by at least two photolithography processes and two hard mask processing processes is exemplified.

Hereinafter, a manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIGS. 6 to 17, (A) is a cross-sectional view corresponding to the AA ′ line shown in FIG. 5 (a view showing a cross-sectional structure of the memory cell in the channel length direction), and (B) is B- Cross-sectional view corresponding to line B ′ (showing a cross-sectional structure in the channel width direction of the memory cell), (C) is also a cross-sectional view corresponding to line CC ′ (showing a cross-sectional structure of the drain contact of the memory cell) Figure).

First, as shown in FIGS. 6A to 6C, a first silicon oxide layer 12 called a tunnel insulating film is formed on the main surface of the semiconductor substrate 10 to be a floating gate electrode of the cell in a later step. One polycrystalline silicon layer 13 is deposited. Further, a first silicon nitride layer 14 and a second silicon oxide layer 15 are sequentially formed. In this example, it is assumed that a p-type silicon substrate is used as the semiconductor substrate 10 and a p-well region 11 is formed after forming a deep n-well region in a region where a memory cell is to be formed.

Next, as shown in FIGS. 7A to 7C, a trench 16 is formed in a portion where an element isolation region is to be formed. In this step, a resist pattern that opens an element isolation region is formed on the second silicon oxide layer 15 by a photolithography step. This resist pattern is formed as a striped opening pattern extending in the column direction in the memory cell array. Using this as a mask, the second silicon oxide layer 15 and the first silicon nitride layer 14 are etched by a reactive ion etching (RIE) method. Subsequently, using the processed second silicon oxide layer 15 and first silicon nitride layer 14 as a mask, the first polycrystalline silicon layer 13, the first silicon oxide layer 12, and the semiconductor substrate 10 are etched by the RIE method. The trench 16 is formed by processing. The depth of the trench 16 is dug deeper than the p-well 11 for the purpose of element isolation.

Thereafter, an embedded insulating film is formed so that the trench 16 and the first silicon oxide layer 12, the first polycrystalline silicon layer 13, the first silicon nitride layer 14, and the second silicon oxide layer 15 are sufficiently embedded. accumulate. A silicon oxide film is selected as the buried insulating film. The deposition of the silicon oxide film is performed by a plasma CVD method using, for example, a SiH ₄ —N ₂ O-based gas or a TEOS (Tetraethyl orthosilicate) -O ₂ -based gas. Then, the first silicon nitride layer 14 is used as a stopper in polishing by the chemical mechanical polishing (CMP) method, and the deposited silicon oxide film and the second silicon oxide layer 15 are polished to flatten the surface. To be processed. By this processing, the first silicon oxide layer 12 is removed together with the buried insulating film, and the surface heights of the first silicon nitride layer 14 and the buried insulating film are made uniform. As a result, as shown in FIG. 8, an element isolation region 18 is formed by STI in which a silicon oxide film is buried in the trench 16.

FIG. 1 is a plan view of the memory cell array at the stage shown in FIG. The element isolation region 18 is formed in a stripe shape in the column direction of the memory cell array, and the element formation region 17 is provided so as to be sandwiched therebetween. In the element formation region 17, a first silicon oxide layer 12, a first polycrystalline silicon layer 13, and a first silicon nitride layer 14 are stacked.

Next, as shown in FIGS. 9A to 9C, a step of forming a two-layer gate structure is performed. From the state of FIG. 8 described above, the first silicon nitride layer 14 is removed by phosphoric acid treatment. Then, a second polycrystalline silicon layer 19 is formed. For example, SiH ₂ Cl ₂ , HCl and PH ₃ are used as source gases, and a polycrystalline silicon film to which phosphorus deposited by low pressure CVD is added is deposited. A second polycrystal silicon layer 19 is formed by forming a resist pattern on the film by a photolithography process and processing the film so as to be separated above the element isolation region 18 by dry etching. Thus, the first polycrystalline silicon layer 13 and the second polycrystalline silicon layer 19 are stacked and used as a floating gate electrode of the memory cell. As shown in FIGS. 9B and 9C, the floating gate electrode has a substantially T-shaped cross section when viewed from the BB ′ line and the CC ′ line. That is, the floating gate electrode is provided for each memory cell, and is configured to be insulated from adjacent memory cells.

Subsequently, as the inter-gate insulating layer 20, a so-called ONO layer in which, for example, a silicon oxide layer / a silicon nitride layer / a silicon oxide layer is stacked is formed by a low pressure CVD method. Further, a third polycrystalline silicon layer 21 to which phosphorus is added and a tungsten silicide (WSi) layer 22 are formed. The tungsten silicide layer 22 is deposited by CVD using WF ₆ and SiH ₄ , for example. Further, a third silicon oxide layer 23 is sequentially deposited as a hard mask when forming a two-layer gate electrode in a later step.

Next, as shown in FIGS. 10A to 10C, a two-layer gate electrode including a floating gate electrode and a control gate electrode is formed. First, a resist pattern is formed by photolithography. This resist pattern is a pattern corresponding to a word line extending in the row direction in the memory cell array. Using this resist pattern, the third silicon oxide layer 23 is processed by the RIE method. Then, using the third silicon oxide layer 23 as a mask, the tungsten silicide layer 22, the third polycrystalline silicon layer 21, the intergate insulating layer 20, the second polycrystalline silicon layer 19, and the first polycrystalline silicon layer 13 are used. The gate electrode 27 is formed by anisotropic etching using RIE.

Next, as shown in FIGS. 11A to 11C, sidewall spacers 26 are formed on the sidewalls of the gate electrode 27. First, an oxidation process is performed, and a desired thickness is formed on each side surface of the first polycrystalline silicon layer 13, the second polycrystalline silicon layer 19, the third polycrystalline silicon layer 21, and the tungsten silicide layer 22 of the gate electrode 27. Thus, the fourth silicon oxide layer 24 is formed. Thereafter, an impurity region of one conductivity type is formed. In this embodiment, a case where a low-concentration n-type impurity region 25 for forming a low-concentration drain (LDD) is formed in addition to the high-concentration n-type impurity region 28 constituting the drain region and the source region in the memory cell is illustrated. .

First, ion implantation for forming a low concentration drain (LDD) in the memory cell is performed to form a low concentration n-type impurity region 25. Next, a silicon nitride film is deposited so as to embed the gate electrode 27, and this is etched back to form sidewall spacers 26. Then, ion implantation for forming a high concentration n-type impurity region 28 is performed using the sidewall spacer 26 as a mask. In this way, the low-concentration n-type impurity region 25 is formed in the element formation region 17 on both sides of the gate electrode 27 in the region overlapping the sidewall spacer 26, and the high-concentration is formed outside the sidewall spacer 26. An n-type impurity region 28 is formed. FIGS. 11A and 11C show a cross section of a region serving as a drain in the memory cell in the high-concentration n-type impurity region 28.

FIG. 2 is a plan view of the memory cell array at this stage. The gate electrode 27 formed in the steps shown in FIGS. 10 and 11 can be regarded as a word line WL by extending in the row direction with the same layer structure in the memory cell array. The word line WL is formed so as to cross the element formation region 17 and the element isolation region 18.

Next, as shown in FIGS. 12A to 12C, a second silicon nitride layer 29 and an interlayer insulating layer 30 are formed. First, a second silicon nitride layer 29 that serves as an etching stopper when the contact is opened is formed. A boron phosphorus silicate glass (BPSG) film is deposited thereon by introducing atmospheric pressure SiH ₄ , B ₂ H ₆ , PH ₃ and O ₂ gas. After the reflow of the formed BPSG film, the interlayer insulating layer 30 is formed by performing planarization by polishing using the second silicon nitride layer 29 as a stopper until the upper surface is exposed by CMP.

Next, a mask pattern for forming a drain contact is formed. This mask pattern is formed as a hard mask pattern using a silicon oxide layer or a silicon nitride layer formed in a stripe shape. The process is shown below. The hard mask refers to a mask using a silicon oxide material (SiO ₂ ) or a silicon nitride material (Si ₃ N ₄ ).

As shown in FIGS. 13A to 13C, a first hard mask 32 is formed on the interlayer insulating layer 30 formed of a BPSG film. The first hard mask 32 is formed by depositing an insulating film such as a silicon oxide film or a silicon nitride film on the interlayer insulating layer 30. For example, a silicon oxide film is formed by a CVD method using TEOS. A resist pattern 31 is formed on the insulating film by a photolithography process. The resist pattern 31 is formed in a stripe pattern in which an opening is formed on the element formation region 17 and the opening extends in parallel with the element formation region 17. When the silicon oxide film is etched with such a resist pattern 31, a first hard mask 32 extending in parallel with the element formation region 17 is formed as shown in the plan view of FIG.

The etching depth at this time may be selectively removed from the silicon oxide film, or may be processed at such a depth that even a part of the underlying BPSG film is removed. For example, when the first hard mask 32 is silicon oxide, it is processed by CHF ₃ , CF ₄ , and CO gas with a selective ratio with the interlayer insulating layer 30 formed of the BPSG film by dry etching. be able to. The first hard mask 32 is provided on the element isolation region 18 and is formed so that the width of the opening substantially matches the width of the contact hole.

Next, as shown in FIGS. 14A to 14C, a second hard mask 34 is formed. First, after removing the resist pattern 31 on the first hard mask 32, an insulating layer for forming the second hard mask 34 is deposited. The second hard mask 34 is formed of a silicon nitride film or a silicon oxide film. For example, a silicon nitride film is deposited on the entire surface by plasma CVD using SiH ₄ and NH ₃ gas, and a resist pattern 33 is formed by a photolithography process. The resist pattern has an opening in a direction intersecting the first hard mask 32. When the silicon nitride film is etched with this resist pattern, a second hard mask 34 extending in a direction intersecting the element formation region 17 is formed as shown in the plan view of FIG.

The etching depth at this time may be selectively removed from the silicon nitride film, or may be processed at such a depth as to remove part of the first hard mask 32 underlying the silicon nitride film. For example, when the second hard mask is silicon nitride, dry etching can be performed using CHF ₃ , CF ₄ , O ₂ , or Ar. Note that the second hard mask 34 is provided so as to cross the element formation region 17 and the element isolation region 18, and is formed so that the width of the opening substantially coincides with the width of the contact hole.

By overlapping and overlapping the first hard mask 32 and the second hard mask 34 in a stripe shape, a region where the interlayer insulating layer 30 is exposed is formed at the intersection of the openings of the respective hard masks. The exposed region of the interlayer insulating layer 30 becomes a contact hole forming region. That is, by forming a hard mask by two exposures and two processing processes, a mask for forming a contact hole having a rectangular opening shape can be manufactured. In this case, each of the first hard mask 32 and the second hard mask 34 can form a pattern by high-resolution exposure, and a mask for forming a contact hole formed by superimposing both of them. Can also be of high definition.

FIGS. 13 and 14 show a process of forming the first hard mask 32 first and forming the second hard mask 34 later, but the order of manufacturing these hard masks may be reversed. However, by forming the first hard mask 32 having relatively high alignment accuracy in relation to the element formation region 17 first, it is possible to improve the contact hole position accuracy. By exposing a resist pattern for forming the first hard mask 32 on the planarized interlayer insulating layer 30, the alignment between the reticle and the semiconductor substrate is facilitated.

Note that the hard mask material can be variously combined and can be appropriately selected according to the application. For example, since a silicon nitride film is excellent in vertical workability, it is suitable as a material for a hard mask. Therefore, it is preferable to form at least one of the first hard mask and the second hard mask with silicon nitride. Further, since the silicon oxide film is excellent in etching processability, it is easy to form a fine pattern. Therefore, at least one of the first hard mask and the second hard mask can be formed using silicon oxide. Taking advantage of the characteristics of these materials, both the first hard mask and the second hard mask may be formed of silicon nitride or silicon oxide.

Further, each of the first hard mask and the second hard mask may be formed of different materials. For example, the first hard mask can be formed of silicon nitride, and the second hard mask can be formed of silicon oxide. With this combination, an antireflection effect can be obtained. Thereby, since reflection is suppressed during exposure in the photolithography process, the alignment accuracy of the reticle can be increased during exposure. In addition, the first hard mask can be formed using silicon oxide, and the second hard mask can be formed using silicon nitride. Since the second hard mask is formed on the gate electrode, there is an advantage that it is easy to form a self-aligned contact by being formed of silicon nitride.

As shown in FIGS. 15A to 15C, using the first hard mask 32 and the second hard mask 34, the interlayer insulating layer 30 is etched by the RIE method using the second silicon nitride layer 29 as a stopper. A contact hole 35 is formed. Thereafter, the second silicon nitride layer 29 at the bottom of the contact hole 35 is removed to expose the high-concentration n-type impurity region 28. For example, when the interlayer insulating layer 30 is a BPSG film, the silicon oxide film and the silicon nitride film that form the first hard mask and the second hard mask are selected by dry etching using CHF ₃ and Ar gas. It can be processed with a ratio.

The position of the contact hole 35 is defined by an opening formed by the intersection of the first hard mask 32 and the second hard mask 34. At this time, self-aligned contact may be employed. That is, it is utilized that the contact hole 35 has a shape that is positioned in a self-aligned manner by the sidewall spacer 26 as shown in FIG.

In any case, the contact hole is processed by dry etching using a hard mask formed of an inorganic material instead of a mask formed using a resin resin photoresist, so that the etching selectivity is higher than that of a resist. Therefore, the recession of the edge of the mask pattern is suppressed, and the contact hole diameter can be miniaturized. That is, a contact hole close to the original design dimension can be formed, and the planar shape of the opening can be rectangular or a shape close thereto. This is suitable for fine processing of a high aspect ratio with a deep contact hole and a small diameter. Thereby, the position of the contact hole can be prevented from being shifted from the drain region formed in the element formation region 17 and high-precision processing can be performed.

By producing a hard mask by a double exposure double processing process, it becomes possible to process a fine contact hole when patterning with a reticle with a blank pattern when using an exposure apparatus with the same resolution. . That is, it is possible to cope with miniaturization of a semiconductor integrated circuit without excessive capital investment.

Next, as shown in FIGS. 16A to 16C, the first barrier metal layer 36 and the first contact plug 37 are formed. The first barrier metal layer 36 is formed by sputtering, by stacking a titanium film, a titanium nitride film, or a titanium film and a titanium nitride film. Further, a tungsten film is deposited so as to be embedded in the contact hole by a CVD method using tungsten hexafluoride. Then, the exposed portions of the tungsten film and the titanium film are polished and planarized by the CMP method. By this step, the first contact plug 37 is formed.

Next, as shown in FIGS. 17A to 17C, a fifth silicon oxide layer 38 is deposited by a TEOS-based CVD method. Thereafter, a predetermined resist pattern is formed by a photolithography process, and a contact hole is formed in the fifth silicon oxide layer 38 at a position corresponding to the first contact plug 37 by the RIE method. Next, a second barrier metal layer 39 is deposited, and a tungsten film is deposited thereon to fill the contact hole. Then, the second contact plug 40 is formed by polishing and flattening the exposed portions of the tungsten film and the titanium film by a CMP method. After that, the element formation is completed by forming the wiring 41 corresponding to the bit line.

FIG. 5 is a plan view of the memory cell array manufactured in the above process. In the semiconductor substrate, element formation regions 17 are provided in the column direction, and element isolation regions 18 are formed between adjacent element formation regions. In the element formation region 17, a channel region of the memory cell and an impurity region of one conductivity type for forming a drain region and a source region are formed. In the memory cell array, an n-type impurity region is formed as one conductivity type impurity region.

A word line WL extending in the row direction of the memory cell array crosses the element formation region 17 and the element isolation region 18. The word line WL also serves as the gate electrode of the memory cell and has a two-layer gate structure. The bit line BL is provided above the word line WL via an interlayer insulating layer, extends in the column direction, and forms a contact with the drain region by the drain contact DC on the element formation region 17.
The drain contact DC is surrounded by the first hard mask 32 and the second hard mask 34. The drain contact DC is formed by a first contact plug 37 and a second contact plug 40 in a contact hole formed by these hard masks. A wiring 41 corresponding to a bit line is in contact with the drain contact DC and is disposed in a direction parallel to the element formation region 17.

According to this embodiment, the drain contact of the memory cell can be formed with high accuracy. In addition, since the contact hole opening shape as viewed from the plane of the semiconductor substrate can be made substantially rectangular, the contact area is increased and the contact resistance can be lowered. Note that although the first hard mask and the second hard mask are left and the subsequent wiring formation process is performed in this embodiment mode, these hard masks may be removed after a desired contact hole is formed. .

As described above, the case where the present invention is applied to a NOR type flash memory has been described as an example. However, the present invention is not limited to this, and can be similarly implemented in other semiconductor integrated circuits. That is, it can be applied to the formation of contact holes between the drain region and the source region of the transistor and between the wirings formed through the interlayer insulating layer by using a hard mask manufactured by a double exposure twice processing process. it can.

FIG. 6 is a layout diagram illustrating a part of a memory cell array of a semiconductor device according to one embodiment of the present invention, which illustrates steps up to an element formation region and an element isolation region. FIG. 10 is a layout diagram illustrating a part of a memory cell array of a semiconductor device according to one embodiment of the present invention, which illustrates a process until a word line is formed. FIG. 10 is a layout diagram illustrating part of the memory cell array of the semiconductor device according to one embodiment of the present invention, which illustrates a step of forming a first hard mask. FIG. 10 is a layout diagram showing part of the memory cell array of the semiconductor device according to one embodiment of the present invention, which shows a step of forming a second hard mask. FIG. 10 is a layout diagram showing part of the memory cell array of the semiconductor device according to one embodiment of the present invention, which shows a step of forming a second hard mask. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention.

Explanation of symbols

MC memory cell BL bit line LI source line WL word line DC drain contact 10 semiconductor substrate 11 p well 12 first silicon oxide layer 13 first polycrystalline silicon layer 14 first silicon nitride layer 15 second silicon oxide layer 16 trench 17 element formation region 18 element isolation region 19 second polycrystalline silicon layer 20 inter-gate insulating layer 21 third polycrystalline silicon layer 22 tungsten silicide layer 23 third silicon oxide layer 24 fourth silicon oxide layer 25 Low-concentration n-type impurity region 26 Side wall spacer 27 Gate electrode 28 High-concentration n-type impurity region 29 Second silicon nitride layer 30 Interlayer insulating layer 31 Resist pattern 32 First hard mask 33 Resist pattern 34 Second hard Mask 35 Contact hole 36 First barrier metal 37 the first contact plugs 38 fifth silicon oxide layer 39 a second barrier metal layer 40 and the second contact plugs 41 wires

Claims (5)

Forming an element isolation region and an element formation region on a semiconductor substrate;
Forming a gate electrode in the element formation region;
Forming an impurity region of one conductivity type in the outer region of the gate electrode in the element formation region;
Forming an interlayer insulating layer for embedding the gate electrode on the element formation region;
Forming a first hard mask having a stripe-shaped opening pattern across the impurity region of one conductivity type and the gate electrode on the interlayer insulating layer;
Forming a second hard mask having an opening pattern in a direction intersecting with the first hard mask, the opening being located on the impurity region of the one conductivity type;
Etching the interlayer insulating layer exposed at an intersection of opening patterns of the first hard mask and the second hard mask to form a contact hole penetrating the impurity region of the one conductivity type; A method of manufacturing a semiconductor device. In the semiconductor substrate on which the NOR type nonvolatile semiconductor memory cell array is formed, an element isolation region extending in one direction and an element formation region sandwiched between the element isolation regions are formed,
Forming a gate electrode across the element isolation region and the element formation region;
Forming a drain region in an outer region of the gate electrode in the element formation region;
Forming an interlayer insulating layer so as to embed the gate electrode;
Forming a first hard mask having an opening pattern in a direction parallel to the element isolation region on the interlayer insulating layer, the opening being disposed on the element formation region;
Forming a second hard mask having an opening pattern in a direction intersecting the first hard mask;
Etching the interlayer insulating layer exposed at the intersection of the opening patterns of the first hard mask and the second hard mask to form a contact hole penetrating the drain region. A method for manufacturing a semiconductor device. In claim 1 or claim 2,
At least one of the first hard mask and the second hard mask is formed of silicon nitride. In claim 1 or claim 2,
At least one of the first hard mask and the second hard mask is formed of silicon oxide. In claim 1 or claim 2,
One of the first hard mask and the second hard mask is formed of silicon nitride, and the other is formed of silicon oxide.

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