JP2008085162A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent resistance of a second gate electrode from increasing in a structure constituted to prevent short-circuiting between adjacent first gate electrodes. <P>SOLUTION: A lower part 6a of a gate of a first conductive layer 6 is inversely tapered. This can prevent short-circuiting between adjacent floating gate electrodes FG. Moreover, an upper part 6b of the gate of the first conductive layer 6 is tapered. This can achieve a structure in which no void occurs in a second conductive layer 8 when a second gate insulation film 7 or the second conductive layer 8 is formed on the upper part 6b of the gate of the first conductive layer 6. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a structure in which a gate insulating film and a gate electrode are sequentially formed on a semiconductor substrate, a groove is formed, and an element isolation insulating film is formed inside the groove, and a manufacturing method thereof.

  A first gate insulating film and a first gate electrode are sequentially formed on a semiconductor substrate, these films are divided into a plurality of parts, a groove is formed in the semiconductor substrate, and an STI (Shallow Trench Isolation) structure element is formed inside the groove. A technique for forming an isolation region has been developed (see, for example, Patent Document 1).

  According to the configuration described in Patent Document 1, since the first gate electrode is formed in a reverse tapered cross-sectional shape, the etching process of the first gate electrode is not hindered by the element isolation insulating film. Therefore, occurrence of a short circuit between the first gate electrodes due to etching residues can be prevented.

However, when the side surface of the first gate electrode, which is the material of the first gate electrode, is formed, for example, in a substantially reverse tapered shape, the second gate insulating film is isotropically formed thereon after that. When a material film for the second gate electrode is formed thereon, a void is generated in the second gate electrode formed on the second gate insulating film located between the adjacent first gate electrodes. There is a risk of it. Then, the second gate electrode becomes undesirably high in resistance.
Japanese Patent Laid-Open No. 2002-16154

  The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent a short circuit between adjacent first gate electrodes and to prevent a high resistance of the second gate electrode. And providing a manufacturing method thereof.

  A semiconductor device according to the present invention includes a semiconductor substrate having a plurality of groove portions formed on a surface layer, and a plurality of element isolation insulating films formed in the plurality of groove portions and having upper portions protruding upward from the surface of the semiconductor substrate. A first gate electrode formed on the semiconductor substrate between the upper portions of the plurality of adjacent element isolation insulating films via a first gate insulating film, and a second gate on the first gate electrode A second gate electrode formed through an insulating film, wherein the first gate electrode is located below the gate in contact with the first gate insulating film and above the gate lower part, and the second gate insulating film The upper part of the gate has a forward tapered part whose cross-sectional width dimension extends in the direction of the lower part of the gate, and the lower part of the gate has an inversely tapered part which has a cross-sectional dimension of the width in the direction of the upper part of the gate. Have It is characterized in.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first gate insulating film on a surface of a semiconductor substrate, a step of forming a first conductive layer on the first gate insulating film, Forming a groove portion in the semiconductor substrate by dividing the first gate insulating film into a plurality of parts while forming the conductive layer into an inversely tapered portion that is thinner than the upper part thereof, and separating the element into an insulating film in the groove part And a forward tapered portion so that the upper portion of the first conductive layer becomes thinner toward the upper side while leaving the reverse tapered portion with respect to the lower portion of the first conductive layer. Forming a second gate insulating film on the forward tapered portion of the first conductive layer, and forming a second conductive layer on the second gate insulating film. It is characterized by having prepared.

  According to the semiconductor device of the present invention, it is possible to prevent a short circuit between adjacent floating gate electrodes and an increase in resistance of the gate electrodes.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an equivalent circuit of a memory cell array formed in a memory cell region of a NAND flash memory device, and FIG. 2 schematically shows an arrangement state of memory cells in the memory cell region shown in FIG. It is shown by a plan view.

  In the NAND flash memory device 1 as the semiconductor device shown in FIG. 1, the memory cell array Ar includes two selection gate transistors Trs and a plurality (for example, 8) connected in series between the selection gate transistors Trs. Number: NAND cell units SU composed of n 2 (n is a positive number) memory cell transistors Trn are formed in a matrix.

The plurality of memory cell transistors Trn are formed by sharing adjacent source / drain regions.
The memory cell transistors Trn arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line (control gate line) WL. Further, the selection gate transistors Trs arranged in the X direction in FIG. 1 are commonly connected by a common selection gate line SL. Further, the select gate transistor Trs is connected to the bit line BL extending in the Y direction (corresponding to the crossing direction of the gate width direction, the gate length direction, and the bit line direction) orthogonal to the X direction in FIG. 1 via the bit line contact CB. It is connected.

  As shown in FIG. 2, the plurality of NAND cell units SU are separated from each other by an element isolation region Sb having an STI (Shallow Trench Isolation) structure. The gate electrode of the memory cell transistor Trn is at the intersection of an element formation region (active region: active area) Sa extending in the Y-axis direction and a word line WL extending in the Y-axis direction formed at a predetermined interval in the X-axis direction. Is located.

<Description of Gate Electrode Structure in Gate Electrode Formation Region GC of Memory Cell Region M of Flash Memory Device 1>
Hereinafter, description will be made with reference to FIG. 2 and FIG. 3 focusing on characteristic portions of the structure according to the present embodiment. FIG. 3 schematically shows a partial structure (see region A1 shown in FIG. 2) of the gate electrode formation region GC and the gate electrode isolation region GV shown in FIG. 2 in a perspective view.

  As shown in FIG. 3, the flash memory device 1 is partitioned and formed in both a memory cell region M and a peripheral circuit region (not shown) with respect to a p-type silicon substrate 2 as a semiconductor substrate. As shown in FIG. 2, in the memory cell region M, a plurality of gate electrode formation regions GC are arranged in parallel in the Y direction, and a gate electrode isolation region GV is formed between adjacent gate electrode formation regions GC. Is provided.

  As shown in FIG. 3, in the gate electrode formation region GC, a floating gate electrode FG and a control gate electrode CG are configured as stacked gate electrodes on the silicon substrate 2 with a first insulating film 5 interposed therebetween. Although not shown in FIG. 3, the floating gate electrode FG and the control gate electrode CG adjacent in the Y direction are each physically separated by the gate electrode isolation region GV. In this gate electrode isolation region GV, an interlayer insulating film (not shown) is embedded on the silicon substrate 2, and a stacked gate electrode adjacent in the Y direction is electrically isolated. .

  Hereinafter, the structure of the stacked gate electrode formed in the gate electrode formation region GC of the memory cell region M will be mainly described. As shown in FIG. 3, on the surface (main surface) side of the silicon substrate 2, element isolation grooves 3 are formed along the Y direction as groove portions for the plurality of element isolation regions Sb. An element isolation insulating film 4 is embedded in 3.

  The element isolation insulating film 4 has a multi-layer structure of insulating films 4b to 4d described later, and electrically isolates and isolates the floating gate electrode layer FG and the element formation region Sa adjacent in the X direction. It is provided to be separated. This element isolation insulating film 4 constitutes an element isolation region Sb having a so-called STI (Shallow Trench Isolation) structure.

  The element isolation insulating film 4 is configured to be embedded in the element isolation groove 3 of the element isolation region Sb with respect to the surface layer portion of the silicon substrate 2 and to have an upper portion 4 a protruding above the surface portion 2 a of the silicon substrate 2. . The element isolation insulating film 4 is formed so as to divide the element formation region Sa into a plurality in the X direction.

  In the element isolation insulating film 4, a silicon oxide film 4b is formed along the inner surface of the element isolation groove 3, a silicon oxide film 4c is formed along the inner surface of the silicon oxide film 4b, and a coating type insulating film is formed inside the silicon oxide film 4c. The film 4d is formed. In the upper portion 4 a of the element isolation insulating film 4, the side portion of the silicon oxide film 4 b projects on the first insulating film 5 described later. The side wall surface 4f of the upper portion 4a of the element isolation insulating film 4 protruding on the first insulating film 5 is directed from the lower end portion in contact with the first insulating film 5 toward the upper surface portion 4e of the element isolation insulating film 4. It has a forward tapered shape in which the width dimension of the cross section in the X direction is gradually narrowed. That is, the side wall surface 4 f is formed so as to be exposed upward of the silicon substrate 2. In this embodiment, the element isolation insulating film 4 has a three-layer structure. However, in the present invention, the element isolation insulating film may have a two-layer structure or a single-layer structure.

  A first insulating film 5 is formed on the silicon substrate 2 in the element formation region Sa. The first insulating film 5 is formed of a silicon oxide film by, for example, thermal oxidation, and functions as a tunnel insulating film and a first gate insulating film.

  A first conductive layer 6 is formed on the first insulating film 5. The first conductive layer 6 is made of, for example, polycrystalline silicon or amorphous silicon doped with impurities such as phosphorus. The first conductive layer 6 is formed on the first insulating film 5 between the adjacent element isolation insulating films 4 and 4 in the gate electrode formation region GC.

  The first conductive layer 6 is embedded between the side wall surfaces 4f of the element isolation insulating film 4 and is formed on the gate lower part 6a so as to be in contact with the first insulating film 5. The gate upper portion 6b is located above the upper surface portion 4e of the insulating film 4. Here, a boundary portion between the gate lower portion 6a and the gate upper portion 6b located at the same height as the height of the upper surface portion 4e of the element isolation insulating film 4 from the surface of the silicon substrate 2 is referred to as a gate intermediate portion 6aa. Since the gate lower portion 6a of the first conductive layer 6 is formed so as to be buried between the side wall surfaces 4f, the width dimension in the X direction of the lower end portion of the gate in contact with the first insulating film 5 is higher than the lower end portion of the gate. The cross-sectional shape in the X direction is narrower than the width dimension of the portion, and is configured as a reverse taper portion having a reverse taper shape. With respect to the gate lower portion 6a, the gate upper portion 6b of the first conductive layer 6 has a width dimension in the X direction at the upper end portion of the gate that is narrower than a width dimension at a portion below the upper end portion of the gate, and a cross-sectional shape in the X direction is a forward taper. It is comprised as a shape forward taper shape part. Note that the forward tapered shape used for the first conductive layer 6 is gradually narrowed upward from the gate intermediate portion 6aa side (the width is narrowed in the X-direction cross section in FIG. 3), or the lower portion of the gate 6a means a shape in which the cross-sectional dimension in the X direction widens toward the gate upper portion 6b. Further, the inversely tapered shape used for the first conductive layer 6 is gradually narrowed downward from the gate intermediate portion 6aa side (the width is narrowed in the cross section in the X direction of FIG. 3), or the upper portion of the gate The cross-sectional dimension of 6b of the X direction means the shape which spreads toward the gate lower part 6a direction.

  In other words, the first conductive layer 6 is formed in a so-called barrel shape in which the width dimension of the cross section in the X direction of the gate middle portion in the height direction is wider than the width dimension of the gate upper end portion and the gate lower end portion. The first conductive layer 6 functions as a first gate electrode and a floating gate electrode FG.

  The element isolation insulating film 4 is configured such that the upper surface position of the upper surface part 4 e is higher than the upper surface part 5 a of the first insulating film 5 formed beside the element isolation insulating film 4 and the first conductive layer 6. It is comprised lower than the upper surface part 6c.

  The second gate insulating film 7 is formed so as to cover the first conductive layer 6 and the element isolation insulating film 4. The second gate insulating film 7 is, for example, an ONO film (Oxide (oxide film layer) -Nitride (nitride film layer) -Oxide (oxide film layer)), a NONON film (Nitride-Oxide-Nitride-Oxide-Nitride), or the like. Is formed of a laminated structure of oxide film layers and nitride film layers, or an alumite material.

  The second gate insulating film 7 is configured as a conductive interlayer insulating film between the first conductive layer 6 and a second conductive layer 8 described later. The second gate insulating film 7 is formed between the floating gate electrode FG and the control gate electrode CG and functions as an inter-gate insulating film. When first and second conductive layers 6 and 8 are formed of polycrystalline silicon doped with impurities, second gate insulating film 7 functions as an interpoly insulating film.

  The second conductive layer 8 is formed so as to cover the second gate insulating film 7. The second conductive layer 8 includes a lower conductive layer 9 and an upper conductive layer 10 formed on the lower conductive layer 9.

  The lower conductive layer 9 is made of, for example, polycrystalline silicon or amorphous silicon doped with impurities such as phosphorus. The upper conductive layer 10 is made of a metal silicide such as tungsten silicide and functions as a low resistance metal layer. The second conductive layer 8 functions as a control gate electrode CG (corresponding to the second gate electrode). That is, the control gate electrode CG is configured to cover the second gate insulating film 7 and the floating gate electrode FG in the gate electrode formation region GC, and above the plurality of element formation regions Sa and element isolation regions Sb. It is formed across.

  A silicon nitride film 11 is formed on the control gate electrode CG. Although not shown, an interlayer insulating film and a bit line BL structure are formed on the silicon nitride film 11 to constitute the memory cell region M of the flash memory device 1.

Although not shown, the control gate electrode CG and the selection gate electrode SG are configured by substantially the same structure.
As described above, according to the structure according to the present embodiment, the X-direction cross section of the upper portion 4a of the element isolation insulating film 4 is a forward tapered shape, and the X-direction cross section of the gate lower portion 6a of the first conductive layer 6 is. The reverse tapered shape prevents the conductive layer from remaining in the gate electrode isolation region GV when the gate electrode isolation region GV separates the floating gate electrode FG (first gate electrode) adjacent in the Y direction. It is possible to prevent a short circuit between the floating gate electrodes FG adjacent in the Y direction. Moreover, since the gate upper portion 6b of the first conductive layer 6 has a forward tapered shape, the second conductive layer is formed on the gate upper portion 6b of the first conductive layer 6 via the second gate insulating film 7. 8 is formed on the element isolation insulating film 4 in the gate electrode formation region GC without causing voids in the second conductive layer 8 embedded between the first conductive layers 6. High resistance can be prevented.

<About manufacturing method>
Hereinafter, a method for manufacturing the above structure will be described with reference to FIGS. Although the description will focus on the features of the present embodiment, the steps described below may be omitted as necessary if the present invention can be realized, and general steps may be required during the following description steps. May be added. Further, in place of the material of each functional film, other materials may be applied as long as they are applicable.

  As shown in FIG. 4, a first insulating film 5 is formed on the silicon substrate 2 to a thickness of about 10 [nm] by a thermal oxidation method. The first insulating film 5 is a film made of, for example, a silicon oxide film and functions as a first gate insulating film. Next, as shown in FIG. 5, silicon (for example, polycrystalline silicon or amorphous silicon) to which an impurity such as phosphorus is added is deposited on the first insulating film 5 by low pressure CVD (Chemical Vapor Deposition). Thus, the first conductive layer 6 is formed with a film thickness of about 120 [nm]. The first conductive layer 6 is a layer that functions as a floating gate electrode FG and a first gate electrode.

  Next, as shown in FIG. 6, a silicon nitride film 12 is formed with a film thickness of about 70 [nm] on the first conductive layer 6 by low pressure CVD. Next, as shown in FIG. 7, a silicon oxide film 13 is formed on the silicon nitride film 12, and a resist 14 is applied thereon, and the resist 14 is formed in the Y-axis direction for forming the floating gate electrode layer FG. Patterning is performed on the predetermined region G provided along the line.

  Next, as shown in FIG. 8, the silicon oxide film 13 and the silicon nitride film 12 are removed by RIE (reactive ion etching) using the resist 14 as a mask. This removal region is a region between two (a plurality of) floating gate electrodes FG and FG adjacent to each other in the X-axis direction in FIG. 3 (between the regions G and G), and the floating gate electrode FG with respect to the X direction. This is a region for separating (dividing) into multiple parts.

Next, the resist 14 is removed by exposing the silicon substrate 2 to O ₂ plasma, and the silicon nitride film 12, the first conductive layer 6, the first insulating film 5, and the silicon substrate 2 using the silicon oxide film 13 as a mask. Are processed in the same region by the RIE method, and an element isolation groove 3 is formed in the upper portion of the silicon substrate 2. The processing conditions at this time are conditions under which the first conductive layer 6 and the silicon substrate 2 can be removed under conditions that have high selectivity with respect to the silicon oxide film 13 or the silicon nitride film 12. Since the first insulating film 5 is thinner than the silicon oxide film 13 and the silicon nitride film 12, it can be easily removed.

In addition, in this case, by adjusting the removal conditions, the cross-sectional shape of the gate lower portion 6a of the first conductive layer 6 is configured to be an inversely tapered shape. That is, first, the first etching is performed with the pressure 5 [mTorr], the output TCP 350 [W], the output bias voltage 250 [V], the gas flow rate CF ₄ = 50 [sccm], and the silicon nitride film 12 and the first conductivity. Layer 6 is removed. Next, the pressure is 12.5 [mTorr], the output TCP is 400 [W], the output bias voltage is 200 [V], and the gas flow rate is HBr / O ₂ / N ₂ / CF ₄ = 230/2/16/50 [sccm]. Second etching is performed to remove the first insulating film 5 and the silicon substrate 2. After that, overetching was performed with an output TCP 600 [W], an output bias voltage 250 [V], and a gas flow rate of HBr / O ₂ / He = 140/2/200 [sccm], as shown in FIG. The cross-sectional shape in the X direction of the conductive layer 6 is an inversely tapered shape. Here, [sccm] is an abbreviation for standard cc / min and represents a unit of flow rate.

  Next, as shown in FIG. 9, for example, the silicon oxide film 4 b is heated to 1000 ° C. in an oxygen atmosphere so that the inner surface of the element isolation trench 3, the first conductive layer 6, and the side walls of the silicon nitride film 12 are About 2 nm to 6 nm is formed.

Next, as shown in FIG. 10, a silicon oxide film 4c made of HTO (High Temperature Oxide) is formed along the inside of the silicon oxide film 4b. In this case, the film formation is performed by a LP-CVD (Low Pressure Chemical Vapor Deposition) method using a temperature condition of 800 ° C. and DCS (dichlorosilane) gas and N ₂ O.

  Subsequently, for example, a coating type insulating film 4d (for example, PSZ (polysilazane) film: coating type insulating film by SOG, coating type low dielectric constant (Low-k) interlayer insulating film) is formed by SOG (Spin on Glass) method. . In the SOG method, a chemical solution in which a silicon oxide film is melted is applied from a nozzle (not shown) while rotating the silicon substrate 2 and then baked. The reason why the SOG method is applied is that even if an overhang shape is generated in the element isolation trench 3, it can be configured without generating voids in the element isolation insulating film 4. Thereafter, for example, the coating type insulating film 4d and the silicon oxide films 4b and 4c are moved backward by treatment with a hydrofluoric acid solution diluted in a water vapor atmosphere of about 500 degrees.

  Subsequently, the films 4b to 4d are planarized by the CMP method using the silicon nitride film 12 as a stopper and heated in a nitrogen atmosphere at 900 ° C. Thus, when the films 4b to 4d are embedded in the element isolation trench 3, it can be configured without generating voids or the like, and the silicon oxide films 4b and 4c and the coating type insulating film 4d can be configured as the element isolation insulating film 4. . At this time, since the element isolation insulating film 4 is formed along the side wall surface of the first conductive layer 6 whose X-direction cross-sectional shape is reversely tapered, the X-direction cross section of the upper portion 4a of the element isolation insulating film 4 is formed. The shape is convex upward, and the side surface of the upper portion 4 a is formed in an oblique shape along the side wall surface of the first conductive layer 6.

  Since the width of the element isolation region Sb is becoming narrower with the reduction of the design rule and the miniaturization of the element, in this embodiment, the coating type insulating film 4d having good embeddability is used in combination with the silicon oxide films 4b and 4c. Thus, it is applied to the element isolation insulating film 4. For example, the coating type insulating film 4d (silicon oxide film formed by the SOG method) is applied to the lower layer side, and the silicon oxide film 4c by the HDP-CVD method is formed on the upper layer side. The insulating film 4d and the silicon oxide films 4b and 4c can be formed in the element isolation trench 3 with good embedding without generating voids, and the substantially same effect as described above can be obtained.

  Next, as shown in FIG. 11A, the uppermost portion 4aa of the upper portion 4a of the element isolation insulating film 4 is positioned below the upper surface portion 6c of the first conductive layer 6 by, for example, about 80 nm by the RIE method. Etch back up to a position above the insulating film 5. In addition, FIG.11 (b) has shown sectional drawing in alignment with the X-axis direction of Fig.11 (a). The etch back process of the uppermost portion 4aa of the element isolation insulating film 4 is performed under a condition with a low selectivity between the silicon nitride film 12 and the element isolation insulating film 4 (silicon oxide film type film). As a result, the uppermost portion 4aa of the element isolation insulating film 4 can be removed and the silicon nitride film 12 can be removed at the same time, and the side wall portion 6bb of the gate upper portion 6b of the first conductive layer 6 can be removed from the first conductive layer. 6 along the side surface of the gate upper portion 6b. Therefore, the side surface portion 6ba of the gate upper portion 6b after the removal can be formed in an oblique shape having an exposed surface on the upper side, and the first conductive is formed in the region above the upper portion 4a of the element isolation insulating film 4 after the digging process. The cross section of the gate upper portion 6b of the layer 6 can be formed as a forward tapered shape portion whose upper side is narrow (narrow) and whose lower side is thick (wide). Thereby, the cross-sectional shape of the first conductive layer 6 can be configured as a so-called barrel shape.

The uppermost portion 4aa of the element isolation insulating film 4 and the silicon nitride film 12 may be removed in separate steps. When removing the silicon nitride film 12, the silicon nitride film 12 may be removed by a phosphoric acid treatment at 150 ° C. and immersed in an NH ₄ solution.

  Next, as shown in FIG. 12, for example, an ONO (Oxide-Nitride-Oxide: oxide film-nitride film-oxide film) film isotropically formed as the second gate insulating film 7 by the low pressure CVD method. To do. Instead of the ONO film, a NONON film, a laminated structure film of a nitride film and an oxide film, alumina, or the like may be formed as the second gate insulating film 7.

  Next, as shown in FIG. 13A, polycrystalline silicon, amorphous silicon or the like to which an impurity such as phosphorus is added is deposited as a lower conductive layer 9 by a low pressure CVD method. In this case, as shown in FIG. 13B, the side surface portion 6ba of the gate upper portion 6b of the first conductive layer 6 is formed in an oblique shape having an exposed surface on the upper side, and the second gate insulating film 7 is Since it is formed along the side surface portion 6ba, it is formed in the lower conductive layer 9 between the gate upper portions 6b and 6b of the adjacent first conductive layers 6 (see, for example, the dotted line region 9a in FIG. 13B). The lower conductive layer 9 can be formed without generating voids.

  Next, as shown in FIG. 14, a tungsten silicide film, for example, is formed on the lower conductive layer 9 as the upper conductive layer 10 by the PVD method, and then the silicon nitride film 11 is formed by the low pressure CVD method. Next, as shown in FIG. 15, a photoresist 12 is applied on the silicon nitride film 11, and the photoresist 12 is processed into a desired pattern by a normal photo-etching method. At this time, the patterning region of the photoresist 12 is a gate electrode formation region GC which is a region where the gate electrodes FG and CG are to be formed.

  Using the photoresist 12 as a mask, the silicon nitride film 11 in the gate electrode isolation region GV which is a region between the adjacent gate electrode formation regions GC and GC is processed by the RIE method. Next, after removing the photoresist 12, as shown in FIG. 3, the upper conductive layer 10, the lower conductive layer 9, the second gate insulating film 7, and the first conductive layer 6 using the silicon nitride film 11 as a mask. Are simultaneously removed by anisotropic etching. At this time, each of the films 6 to 10 is removed and processed under conditions having high selectivity with respect to the silicon nitride film 11.

  In this case, the gate lower portion 6a of the first conductive layer 6 is formed in a reverse taper shape, and the upper portion 4a of the element isolation insulating film 4 is formed in a shape protruding upward, and the side wall surface of the upper portion 4a Since 4f is formed to be a surface exposed upward, the upper portion 4a of the element isolation insulating film 4 is removed when the first conductive layer 6 in the gate electrode isolation region GV is removed by anisotropic etching. All the residues of the first conductive layer 6 can be removed without leaving the side wall surface 4f. As a result, the floating gate electrodes FG and FG in the adjacent gate electrode formation region GC are not electrically connected to each other, so that no trouble occurs. The memory cell region M of the nonvolatile semiconductor memory device 1 can be configured through such a manufacturing process.

  The manufacturing method according to the present embodiment has the following features. A first insulating film 5 is formed on the main surface of silicon substrate 2 as a first gate insulating film. A first conductive layer 6 is formed on the first insulating film 5. The first insulating film 5 is divided into a plurality of parts while the first conductive layer 6 is divided into a plurality of reverse tapered shapes such that the gate lower part 6a side is thinner than the gate upper part 6b. Groove 3 is formed. An element isolation insulating film 4 is formed in the element isolation trench 3. At the same time, the element isolation insulating film 4 is formed along the side wall surface of the gate lower portion 6 a of the first conductive layer 6. The first conductive layer 6 is formed in a forward tapered shape so that the gate upper portion 6b of the first conductive layer 6 becomes narrower with respect to the upper side while leaving the reverse tapered shape of the gate lower portion 6a.

  A second gate insulating film 7 is formed isotropically on the forward tapered portion of the first conductive layer 6. A second conductive layer 8 is formed on the second gate insulating film 7. Thereafter, after a predetermined process, the upper conductive layer 10 and the lower conductive layer 9, the second gate insulating film 7, and the first conductive layer 6 are divided, but the side wall surface 4f of the upper portion 4a of the element isolation insulating film 4 is Since the upper surface 4a of the element isolation insulating film 4 is formed in a slanted shape as an exposed surface, the first conductive layer 6 does not remain as a residue. Thereby, there is no possibility of causing a problem that the adjacent floating gate electrodes FG and FG are electrically connected.

  In addition, since the gate upper portion 6b of the first conductive layer 6 is formed in a forward tapered shape, even after the second gate insulating film 7 is formed isotropically on the first conductive layer 6, Even if the second conductive layer 8 is formed on the second gate insulating film 7, the second conductive layer 8 is embedded in a region having a substantially low aspect ratio. The device isolation insulating film 4 between 6 and 6 can be configured without generating voids or the like, and the resistance of the control gate electrode CG can be prevented from being increased.

  In the step of forming the element isolation insulating film 4 in the element isolation trench 3, the element isolation insulating film 4 is also formed between the plurality of first conductive layers 6 and between the plurality of first insulating films 5 at the same time. In the step of forming a forward taper shape so that the gate upper portion 6 b of the first conductive layer 6 is thinned, the element isolation insulating film 4 between the plurality of first conductive layers 6 and between the plurality of first insulating films 5 is formed. Since the forward-tapered shape is formed so that the width of the upper portion 6c of the first conductive layer 6 is narrowed (thinned) at the same time that the uppermost portion 4aa is removed, the element isolation insulating film 4 is formed in a desired shape. At the same time, the shape of the first conductive layer 6 can be formed into a desired shape, and these can be processed in the same process. Thereby, it is not necessary to provide a new process separately.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and for example, the following modifications or expansions are possible.
Although applied to the NAND type flash memory device 1, it is needless to say that the present invention can be applied to other NOR type flash memory devices. The present invention is not limited to the flash memory, and has a stacked gate electrode structure of two layers or more. The present invention is also applicable to other semiconductor devices (for example, EPROM).

  Even if some constituent elements are deleted from all the constituent elements shown in the above embodiment, the problem described in the column of the problem to be solved by the invention can be solved and is described in the column of the effect of the invention. If the effect is obtained, the configuration requirement from which this configuration requirement is deleted can be applied as an invention.

1 is an electrical configuration diagram of a part of a memory cell region according to an embodiment of the present invention. A plan view schematically showing the structure of a partial region of the memory cell region A perspective view schematically showing a part of a gate electrode formation region and a gate electrode isolation region The perspective view which shows typically a part of gate electrode formation area and gate electrode isolation | separation area | region in one manufacturing process (the 1) A perspective view schematically showing a part of a gate electrode formation region and a gate electrode isolation region in one manufacturing process (No. 2) The perspective view which shows typically the gate electrode formation area in one manufacturing process, and a part of gate electrode isolation | separation area | region (the 3) A perspective view schematically showing a part of a gate electrode formation region and a gate electrode isolation region in one manufacturing process (No. 4) A perspective view schematically showing a part of a gate electrode formation region and a gate electrode isolation region in one manufacturing process (No. 5) FIG. 6 is a perspective view schematically showing a part of a gate electrode formation region and a gate electrode isolation region in one manufacturing process (No. 6). FIG. 7 is a perspective view schematically showing a part of the gate electrode formation region and the gate electrode isolation region in one manufacturing process (No. 7). (A) Perspective view (part 8) schematically showing part of a gate electrode formation region and a gate electrode isolation region in one manufacturing process, (b) enlarged sectional view FIG. 9 is a perspective view schematically showing a part of the gate electrode formation region and the gate electrode isolation region in one manufacturing process (No. 9). (A) Perspective view schematically showing part of a gate electrode formation region and a gate electrode isolation region in one manufacturing process (No. 10), (b) Explanatory diagram of a defect The perspective view which shows the state of the memory cell area | region in the one manufacturing process (the 11) The perspective view which shows the state of the memory cell area | region in one manufacturing process (the 12)

Explanation of symbols

  In the drawings, 1 is a flash memory device (semiconductor device), 2 is a silicon substrate (semiconductor substrate), 3 is an element isolation trench (groove), 4 is an element isolation insulating film, and 5 is a first insulating film (first gate). Insulating film), 6 is a first conductive layer (first gate electrode), 6a is a gate lower portion of the first conductive layer (reverse taper shape portion), and 6b is a gate upper portion of the first conductive layer (forward taper shape). Part), 7 is a second gate insulating film, and 8 is a second conductive layer (second gate electrode).

Claims (5)

A semiconductor substrate having a plurality of grooves formed on a surface layer;
A plurality of element isolation insulating films each embedded in the plurality of trenches and having an upper portion protruding upward from the surface of the semiconductor substrate;
A first gate electrode formed on the semiconductor substrate between the upper portions of the plurality of adjacent element isolation insulating films via a first gate insulating film;
A second gate electrode formed on the first gate electrode via a second gate insulating film,
The first gate electrode includes a gate lower portion in contact with the first gate insulating film and a gate upper portion located on the gate lower portion and in contact with the second gate insulating film. 2. A semiconductor device, comprising: a forward tapered portion whose dimension extends toward the gate lower direction, and the gate lower portion including an inverted tapered portion whose cross-sectional width dimension extends toward the gate upper direction.   The first gate electrode is configured such that the lower part of the gate is sandwiched between the upper side surfaces of the plurality of element isolation insulating films adjacent to each other, and the upper part of the gate is in contact with the second gate insulating film. The semiconductor device according to claim 1, wherein: A semiconductor substrate having a plurality of grooves formed on a surface layer;
A plurality of element isolation insulating films each embedded in the plurality of trenches and having an upper portion protruding upward from the surface of the semiconductor substrate;
A first gate electrode formed on the semiconductor substrate between the upper portions of the plurality of adjacent element isolation insulating films via a first gate insulating film;
A second gate electrode formed on the first gate electrode via a second gate insulating film,
The first gate electrode is located between a gate lower end portion in contact with the first gate insulating film, a gate upper end portion in contact with the second gate insulating film, and between the gate upper end portion and the gate lower end portion. A semiconductor device, wherein the gate intermediate portion has a cross-sectional width dimension wider than that of the gate upper end portion and that of the gate lower end portion. Forming a first gate insulating film on the surface of the semiconductor substrate;
Forming a first conductive layer on the first gate insulating film;
Forming a groove in the semiconductor substrate by dividing the first gate insulating film into a plurality of portions while dividing the first conductive layer into a plurality of inverted tapered portions that are thinner than the upper portion thereof; and
Forming an element isolation insulating film in the groove;
Forming the first conductive layer as a forward tapered shape portion so that the upper portion of the first conductive layer becomes thinner toward the upper side while leaving the reverse tapered portion with respect to the lower portion of the first conductive layer; When,
Forming a second gate insulating film on the forward tapered portion of the first conductive layer;
And a step of forming a second conductive layer on the second gate insulating film. Forming a first gate insulating film on the surface of the semiconductor substrate;
Forming a first conductive layer on the first gate insulating film;
A step of dividing the first conductive layer and the first gate insulating film in a predetermined direction by RIE and forming a groove in the semiconductor substrate, and performing over-etching after the formation of the groove, Processing the cross-sectional shape of the first conductive layer into a reverse taper shape;
Forming an element isolation insulating film in the groove and between the divided first conductive layers;
Etching back the element isolation insulating film by RIE, and processing the upper cross-sectional shape of the first conductive layer into a forward tapered shape;
Forming a second gate insulating film on the first conductive layer and the element isolation insulating film;
Forming a second conductive layer on the second gate insulating film;
A method of manufacturing a semiconductor device, comprising: dividing the second conductive layer, the second gate insulating film, and the first conductive layer in a direction intersecting the predetermined direction.

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