JP2013021576A5 - - Google Patents

Download PDF

Info

Publication number
JP2013021576A5
JP2013021576A5 JP2011154406A JP2011154406A JP2013021576A5 JP 2013021576 A5 JP2013021576 A5 JP 2013021576A5 JP 2011154406 A JP2011154406 A JP 2011154406A JP 2011154406 A JP2011154406 A JP 2011154406A JP 2013021576 A5 JP2013021576 A5 JP 2013021576A5
Authority
JP
Japan
Prior art keywords
delay
circuit
stage
adjustment
multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011154406A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013021576A (ja
JP5736261B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2011154406A priority Critical patent/JP5736261B2/ja
Priority claimed from JP2011154406A external-priority patent/JP5736261B2/ja
Publication of JP2013021576A publication Critical patent/JP2013021576A/ja
Publication of JP2013021576A5 publication Critical patent/JP2013021576A5/ja
Application granted granted Critical
Publication of JP5736261B2 publication Critical patent/JP5736261B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2011154406A 2011-07-13 2011-07-13 遅延クロック信号生成回路およびパルス生成回路 Expired - Fee Related JP5736261B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011154406A JP5736261B2 (ja) 2011-07-13 2011-07-13 遅延クロック信号生成回路およびパルス生成回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011154406A JP5736261B2 (ja) 2011-07-13 2011-07-13 遅延クロック信号生成回路およびパルス生成回路

Publications (3)

Publication Number Publication Date
JP2013021576A JP2013021576A (ja) 2013-01-31
JP2013021576A5 true JP2013021576A5 (cg-RX-API-DMAC7.html) 2014-09-11
JP5736261B2 JP5736261B2 (ja) 2015-06-17

Family

ID=47692551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011154406A Expired - Fee Related JP5736261B2 (ja) 2011-07-13 2011-07-13 遅延クロック信号生成回路およびパルス生成回路

Country Status (1)

Country Link
JP (1) JP5736261B2 (cg-RX-API-DMAC7.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6456790B2 (ja) * 2015-07-29 2019-01-23 新電元工業株式会社 半導体試験装置及び半導体試験方法
CN116155246B (zh) * 2022-12-12 2024-12-27 天津兆讯电子技术有限公司 一种高精度延迟时钟生成电路及芯片
CN116192268B (zh) * 2023-02-28 2026-03-13 香港科技大学 一种低失真pam-4光发射器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2573787B2 (ja) * 1993-05-18 1997-01-22 株式会社メガチップス パルス幅変調回路
JP2000236241A (ja) * 1999-02-16 2000-08-29 Kawasaki Steel Corp 半導体集積回路
JP2008021194A (ja) * 2006-07-14 2008-01-31 Kawasaki Microelectronics Kk クロック変調回路

Similar Documents

Publication Publication Date Title
JP2010088108A5 (cg-RX-API-DMAC7.html)
CN103258561B (zh) 半导体装置的数据输出定时控制电路
JP2013517711A5 (cg-RX-API-DMAC7.html)
JP2008206147A5 (cg-RX-API-DMAC7.html)
JP2010246092A5 (cg-RX-API-DMAC7.html)
JP2008157971A5 (cg-RX-API-DMAC7.html)
WO2012121892A3 (en) Delay circuitry
JP2010273187A5 (ja) Ｐｌｌ回路
JP2008199573A5 (cg-RX-API-DMAC7.html)
JP2011138342A (ja) 多相クロック間の相間スキュー検出回路、相間スキュー調整回路、および半導体集積回路
JP2012009097A5 (cg-RX-API-DMAC7.html)
WO2010033436A3 (en) Techniques for generating fractional clock signals
JP2013149310A5 (cg-RX-API-DMAC7.html)
JP2011055048A5 (cg-RX-API-DMAC7.html)
JP2012208342A5 (cg-RX-API-DMAC7.html)
JP2013090290A5 (cg-RX-API-DMAC7.html)
JP2016116060A5 (cg-RX-API-DMAC7.html)
JP2013021576A5 (cg-RX-API-DMAC7.html)
TW200729734A (en) Delay locked loop with selectable delay
JP2010282399A5 (cg-RX-API-DMAC7.html)
JP2016163156A5 (cg-RX-API-DMAC7.html)
WO2013052186A3 (en) Jitter suppression in type i delay-locked loops
JP2008533916A5 (cg-RX-API-DMAC7.html)
WO2008095974A3 (en) A clock circuit
JP2013074351A5 (cg-RX-API-DMAC7.html)