JP2013021262A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a highly reliable semiconductor device.SOLUTION: A manufacturing method of a semiconductor device includes the steps of: forming an insulation film on a semiconductor substrate 50; forming a laminated body 10 formed by sequentially laminating a gate electrode 20 and a hard mask 34 on the insulation film; performing ion implantation on the semiconductor substrate 50 using the laminated body 10 as a mask; forming a protection film 44 on a side surface of the laminated body 10; removing the hard mask 34 by etching; and removing the protection film 44 by etching.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In manufacturing a semiconductor device, a hard mask provided over a gate electrode may be used as a mask when ion implantation is performed on a semiconductor substrate. Patent Document 1 discloses a technique related to a hard mask that functions as a mask at the time of gate electrode formation and ion implantation. Specifically, providing a compensation film on the hard mask prevents the hard mask from being reduced when the conductive film is etched to form the gate electrode, and the hard mask has a sufficient thickness even during ion implantation. It is described that it can be made.

  In Patent Document 2, a hard mask is used in an etching process for forming a gate electrode. The technique described in Patent Document 2 is to make the thickness of the polycrystalline silicon in the pMOS region thinner than the thickness of the polycrystalline silicon in the nMOS region while suppressing variations in the thickness of the polycrystalline silicon in the pMOS region. It is.

JP 2000-100755 A JP 2009-182122 A

When ion implantation is performed on the semiconductor substrate, a hard mask is provided on the gate electrode, whereby deterioration of the gate oxide film caused by channeling can be prevented.
On the other hand, after performing ion implantation on a semiconductor substrate using a hard mask provided over the gate electrode as a mask, the hard mask may be removed by etching. In this case, when the hard mask is removed, the side surface of the gate electrode may be etched. When the side surface of the gate electrode is etched, the width of the gate electrode becomes smaller than the design value, which causes a problem that desired transistor characteristics cannot be obtained.

According to the present invention, a step of forming an insulating film on a semiconductor substrate;
Forming a stacked body in which a gate electrode and a first hard mask are sequentially stacked on the insulating film;
Performing a first ion implantation on the semiconductor substrate using the stacked body as a mask;
Forming a protective film on a side surface of the laminate;
Removing the first hard mask by etching;
Removing the protective film by etching;
A method for manufacturing a semiconductor device is provided.

  According to the present invention, the protective film is formed on the side surface of the gate electrode before the step of removing the first hard mask used when ion implantation is performed on the semiconductor substrate. For this reason, it is possible to prevent the side surface of the gate electrode from being etched when the first hard mask is removed. Therefore, a highly reliable semiconductor device can be manufactured.

  According to the present invention, a highly reliable semiconductor device can be manufactured.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment. 2 to 6 are sectional views showing a method for manufacturing the semiconductor device shown in FIG.
In the method of manufacturing a semiconductor device according to the present embodiment, a step of forming a silicon oxide film 40 on a semiconductor substrate 50 and a stacked body 10 in which a gate electrode 20 and a hard mask 34 are sequentially stacked on the silicon oxide film 40 are provided. The step of forming, the step of performing first ion implantation on the semiconductor substrate 50 using the stacked body 10 as a mask, the step of forming the protective film 44 on the side surface of the stacked body 10, and the hard mask 34 are removed by etching. And a step of removing the protective film 44 by etching.
Hereinafter, the configuration of the semiconductor device and the method for manufacturing the semiconductor device in the present embodiment will be described in detail.

As shown in FIG. 1, the semiconductor device according to this embodiment includes a semiconductor substrate 50, a gate insulating film 42, a gate electrode 20, a gate sidewall film 70, a source / drain extension region 52, and a source / drain region. 54 and a silicide layer 72 are provided.
The transistor 100 is an N-type MOSFET or a P-type MOSFET. The transistor 100 is, for example, a core transistor or an I / O transistor. The gate length of the transistor 100 is, for example, 50 nm.

  The gate insulating film 42 is provided on the semiconductor substrate 50. The gate insulating film 42 is made of, for example, a silicon oxide film. When the transistor 100 is a high voltage transistor, the thickness of the gate insulating film 42 is, for example, 10 to 20 nm. When the transistor 100 is a low voltage transistor, the thickness of the gate insulating film 42 is, for example, 1.5 to 3 nm.

The gate electrode 20 is provided on the gate insulating film 42. The gate electrode 20 is made of, for example, polycrystalline silicon. The film thickness of the gate electrode 20 is, for example, 50 to 120 nm. A silicide layer 72 is provided on the upper surface of the gate electrode 20.
A gate sidewall film 70 is formed on the sidewalls of the gate insulating film 42 and the gate electrode 20. The gate sidewall film 70 is made of, for example, a silicon oxide film.

Source / drain extension regions 52 are formed in the semiconductor substrate 50. The source / drain extension regions 52 are provided on both sides of the gate electrode 20.
A source / drain region 54 is formed in the semiconductor substrate 50. The source / drain regions 54 are provided on both sides of the gate electrode 20. The source / drain region 54 is formed outside the source / drain extension region 52 when viewed from the gate electrode 20. A silicide layer 72 is formed on the upper surface of the source / drain region 54.

Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.
First, as shown in FIG. 2A, a silicon oxide film 40 is formed on a semiconductor substrate 50 by using a thermal oxidation method or the like. The silicon oxide film 40 can be formed for each transistor type, for example.
Next, a polycrystalline silicon film 22, a silicon oxide film 36, and a polycrystalline silicon film 38 are sequentially formed on the silicon oxide film 40. Next, after forming a resist film on the polycrystalline silicon film 38, the resist film is exposed and developed for patterning. Thereby, a patterned resist film 60 is formed.

In FIG. 2A, the thickness of each layer formed is as follows. The film thickness of the silicon oxide film 40 is, for example, 10 to 20 nm. The thickness of the polycrystalline silicon film 22 is 50 to 120 nm. The film thickness of the silicon oxide film 36 is 20 to 30 nm, for example. The thickness of the polycrystalline silicon film 38 is, for example, 50 to 100 nm. In this case, the gate length of the transistor 100 included in the manufactured semiconductor device can be set to, for example, 50 nm.
As will be described later, the silicon oxide film 36 constitutes a hard mask 32 that functions as a mask in ion implantation. Similarly, the polycrystalline silicon film 38 forms a hard mask 34 that functions as a mask in ion implantation. Therefore, the film thicknesses of the silicon oxide film 36 and the polycrystalline silicon film 38 can be set to appropriate values according to the implantation energy in ion implantation described later.

Next, the polycrystalline silicon film 38, the silicon oxide film 36, and the polycrystalline silicon film 22 are sequentially removed by etching using the patterned resist film 60 as a mask. Next, the resist film 60 is removed. Thereby, as shown in FIG. 2B, the stacked body 10 formed by sequentially stacking the gate electrode 20, the hard mask 32, and the hard mask 34 can be formed on the silicon oxide film 40.
At this time, the gate electrode 20 is composed of polycrystalline silicon. The hard mask 32 is made of a silicon oxide film. The hard mask 34 is made of a polycrystalline silicon film.

Next, as illustrated in FIG. 3A, ion implantation is performed on the semiconductor substrate 50 using the stacked body 10 as a mask. Thereby, the source / drain extension regions 52 are formed.
The ion implantation is performed for each transistor type, for example, by providing a resist film on the semiconductor substrate 50. In this case, for example, ion implantation is performed separately for an N-type MOSFET and a P-type MOSFET. For example, ion implantation can be performed separately for a core transistor and an I / O transistor.

  In the present embodiment, a hard mask 32 and a hard mask 34 are provided on the gate electrode 20. Therefore, channeling can be prevented from occurring in the gate electrode 20 during the ion implantation. Note that channeling refers to a phenomenon in which ions easily enter in a specific direction because polycrystalline silicon used for a gate electrode has orientation. When channeling occurs, the insulating film located under the gate electrode may be deteriorated. That is, according to the present embodiment, it is possible to suppress the deterioration of the silicon oxide film 40.

Next, as illustrated in FIG. 3B, the protective film 44 is formed on the side surface and the upper surface of the stacked body 10. The protective film 44 can be formed by LP-CVD (Low Pressure Chemical Vapor Deposition) or ALD (Atomic Layer Deposition), for example.
The protective film 44 is made of, for example, a silicon oxide film. The film thickness of the protective film 44 is, for example, 3 to 8 nm.

Next, as shown in FIG. 4A, the protective film 44 formed on the upper surface of the stacked body 10 is removed while leaving the protective film 44 formed on the side surface of the stacked body 10. As a result, the upper surface of the hard mask 34 is exposed.
In the present embodiment, the protective film 44 is composed of a silicon oxide film. For this reason, in the step of removing the protective film 44 formed on the upper surface of the stacked body 10, together with the protective film 44, a part of the silicon oxide film 40 located in a region not overlapping with the stacked body 10 in plan view is removed. Will be.

Removal of the protective film 44 formed on the upper surface of the stacked body 10 is performed by, for example, etch back by anisotropic dry etching. In this case, for example, an etching gas composed of CHF ₃ and CH ₂ F ₂ can be used.
In addition, the film thickness of the silicon oxide film 40 formed on the semiconductor substrate 50 in the step shown in FIG. It is preferable that it is thicker. In this case, it is possible to prevent the surface of the semiconductor substrate 50 from being exposed in the step of removing the protective film 44 formed on the upper surface of the stacked body 10.

Next, as shown in FIG. 4B, the hard mask 34 is removed. The removal of the hard mask 34 is performed by dry etching, for example. The etching of the hard mask 34 can be performed under conditions where the etching rate of the polycrystalline silicon film with respect to the silicon oxide film is high.
For this reason, it is possible to suppress the removal of the protective film 44 made of the silicon oxide film provided on the side surface of the gate electrode 20 in the step of removing the hard mask 34 made of the polycrystalline silicon film. Thereby, it is possible to prevent the side surface of the gate electrode 20 from being etched.
Further, in the step of removing the hard mask 34, it is possible to suppress the removal of the hard mask 32 made of a silicon oxide film provided on the upper surface of the gate electrode 20. Thereby, it is possible to prevent the upper surface of the gate electrode 20 from being etched.

In the etching of the hard mask 34, for example, an etching gas containing HBr and O ₂ or an etching gas containing SF ₆ and N ₂ can be used. Specifically, in the etching of the hard mask 34 can be used an etching gas of Cl ₂ and HBr and _{O 2.}
By using such an etching gas, the etching rate of the polycrystalline silicon film with respect to the silicon oxide film can be increased 10 times or more. Thereby, even if the protective film 44 provided on the side surface of the gate electrode 20 is thin, the side surface of the gate electrode 20 can be sufficiently suppressed from being etched.

Next, as shown in FIG. 5A, the protective film 44 is removed. The removal of the protective film 44 is performed by wet etching, for example. For the etching of the protective film 44, for example, DHF (Diluted HF), BHF (Buffered HF), or the like can be used.
The hard mask 32 is sufficiently thicker than the protective film 44. For this reason, as shown in FIG. 5A, a part of the hard mask 32 remains on the gate electrode 20 after the step of removing the protective film 44.
Next, the silicon oxide film 40 located in a region not overlapping with the gate electrode 20 is removed. As a result, the gate insulating film 42 remains only under the gate electrode 20. Further, the surface of the semiconductor substrate 50 is exposed in a region that does not overlap with the gate electrode 20.

  Next, an insulating film is deposited on the gate electrode 20 and the semiconductor substrate 50. The insulating film is made of, for example, a silicon oxide film. Next, anisotropic dry etching is performed on the insulating film. Thereby, as shown in FIG. 5B, the gate sidewall film 70 is formed on the side surfaces of the gate electrode 20 and the gate insulating film 42. Note that the hard mask 32 formed on the gate electrode 20 is removed together with the insulating film deposited on the gate electrode 20 and the semiconductor substrate 50 by the etching process.

Next, ion implantation is performed on the semiconductor substrate 50 using the gate electrode 20 and the gate sidewall film 70 as a mask. As a result, source / drain regions 54 are formed as shown in FIG.
Next, as shown in FIG. 6B, a silicide layer 72 is formed on the gate electrode 20 and on the exposed region of the semiconductor substrate 50. That is, the silicide layer 72 is formed on the gate electrode 20 and the source / drain regions 54. The silicide layer 72 is formed by depositing a metal film such as Ti, Co, or Ni on the semiconductor substrate 50 and the gate electrode 20 and heat-treating it. By forming the silicide layer 72 on the gate electrode 20, the contact resistance of the transistor can be reduced.
Thereby, the semiconductor device according to the present embodiment is formed.

Next, the operation and effect of this embodiment will be described.
In some cases, ion implantation is performed on a semiconductor substrate using a hard mask provided over the gate electrode as a mask, and then the hard mask is removed by etching. In this case, when the hard mask is removed, the side surface of the gate electrode may be etched. This is particularly noticeable when both the gate electrode and the hard mask are formed of a polycrystalline silicon film.

  According to the present embodiment, the protective film 44 is formed on the side surface of the gate electrode 20 before the step of removing the hard mask 34 used when ion implantation is performed on the semiconductor substrate 50. That is, in the step of removing the hard mask 34, the side surface of the gate electrode 20 is protected by the protective film 44. For this reason, when removing the hard mask 34, it can suppress that the side surface of the gate electrode 20 will be etched. Therefore, a highly reliable semiconductor device can be manufactured.

  Further, according to the present embodiment, the protective film 44 is constituted by a silicon oxide film. For this reason, when removing the hard mask 34 made of a polycrystalline silicon film, the removal of the protective film 44 is suppressed by performing etching under conditions where the etching rate of the polycrystalline silicon film with respect to the silicon oxide film is high. The Thereby, when removing the hard mask 34, the side surface of the gate electrode 20 can be sufficiently protected by the protective film 44, and the side surface of the gate electrode 20 can be prevented from being etched.

  In a SoC equipped with a low-voltage transistor and a high-voltage transistor, for example, it is required to reduce the number of manufacturing steps and reduce the manufacturing cost by making the gate electrode film thickness equal in the low-voltage transistor and the high-voltage transistor . However, in a high-voltage transistor, ion implantation energy when forming a diffusion layer on a semiconductor substrate is high, and therefore channeling is likely to occur in a thin gate electrode that matches the low-voltage transistor. Ions are easily implanted into the region.

  According to the present embodiment, the source / drain extension regions 52 are formed by ion implantation using the hard mask 34 and the hard mask 32 as a mask. For this reason, even if the film thickness of the gate electrode of the high voltage transistor is made thin so as to match the gate electrode of the low voltage transistor, the occurrence of channeling in the gate electrode of the high voltage transistor during ion implantation is suppressed. It is possible to suppress the implantation of ions up to the region immediately below the gate electrode. Therefore, it is possible to provide a high-quality semiconductor device while reducing the number of manufacturing steps of the semiconductor device and reducing the manufacturing cost.

  Further, according to the present embodiment, the hard mask used for ion implantation for forming the source / drain extension regions 52 has a two-layer structure in which the hard mask 32 and the hard mask 34 are stacked. For this reason, even when the thickness of the gate electrode 20 is reduced, channeling in the gate electrode 20 can be sufficiently suppressed.

  The manufacturing method of the semiconductor device according to the second embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment, except for the method of forming the protective film 44.

A method for manufacturing a semiconductor device according to this embodiment will be described.
First, the silicon oxide film 40, the polycrystalline silicon film 22, the silicon oxide film 36, and the polycrystalline silicon film 38 are sequentially stacked on the semiconductor substrate 50. Next, the polycrystalline silicon film 38, the silicon oxide film 36, and the polycrystalline silicon film 22 are etched to form a stacked body 10 in which the hard mask 34, the hard mask 32, and the gate electrode 20 are sequentially stacked. Next, using the stacked body 10 as a mask, ion implantation is performed on the semiconductor substrate 50 to form source / drain extension regions 52. About these processes, it can carry out similarly to 1st Embodiment.

  Next, the protective film 44 is formed. The protective film 44 is formed on the side surface and the upper surface of the laminated body 10 by oxidizing the side surface and the upper surface of the laminated body 10 by exposing them to an oxygen atmosphere. Thus, since the protective film 44 is formed by oxidizing the surface of the stacked body 10 in an oxygen atmosphere, the protective film 44 having a thin film thickness of about 1 to 2 nm can be formed. The protective film 44 can be formed using, for example, oxygen ashing.

Next, the protective film 44 formed on the upper surface of the stacked body 10 is removed by, for example, etching back by anisotropic dry etching. In the etching, for example, an etching gas composed of CHF ₃ and CH ₂ F ₂ can be used.

Next, the hard mask 34 made of the polycrystalline silicon film is removed. The removal of the hard mask 34 is performed by dry etching, for example. In the dry etching, for example, an etching gas containing SF ₆ and O ₂ is used. Thereby, the etching rate of the polycrystalline silicon film with respect to the silicon oxide film becomes 10 times or more.
Therefore, in the step of removing the hard mask 34 made of the polycrystalline silicon film, the side surface of the gate electrode 20 is protected by the protective film 44 made of the silicon oxide film, and the side surface of the gate electrode 20 is prevented from being etched. can do.
Since the protective film 44 has a thin film thickness of about 1 to 2 nm, it can be removed at the same time as the hard mask 34 in the step of removing the hard mask 34.
Next, the silicon oxide film 40 located in a region not overlapping with the gate electrode 20 is removed, and a gate insulating film 42 is formed under the gate electrode 20.

Next, the gate sidewall film 70 is formed on the side surfaces of the gate electrode 20 and the gate insulating film 42. Next, source / drain regions 54 are formed by ion implantation using the gate electrode 20 and the gate sidewall film 70 as a mask. Then, a silicide layer 72 is formed on the gate electrode 20 and the source / drain regions 54. These steps can also be performed similarly to the first embodiment.
Thereby, the semiconductor device according to the present embodiment is manufactured.

Also in this embodiment, the same effect as that of the first embodiment can be obtained.
Further, according to the present embodiment, the protective film 44 is formed by oxidizing the surface of the stacked body 10 by exposure to an oxygen atmosphere. For this reason, compared with 1st Embodiment, it becomes possible to form a thin protective film by a simpler method.
Furthermore, according to the present embodiment, the protective film 44 can be a film having a thin film thickness of, for example, about 1 to 2 nm. Therefore, the protective film 44 can be removed simultaneously with the hard mask 34 in the step of removing the hard mask 34. This eliminates the need to remove the protective film 44 by wet etching. Therefore, the semiconductor device can be easily manufactured as compared with the first embodiment.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

DESCRIPTION OF SYMBOLS 10 Stack 20 Gate electrode 22 Polycrystalline silicon film 32 Hard mask 34 Hard mask 36 Silicon oxide film 38 Polycrystalline silicon film 40 Silicon oxide film 42 Gate insulating film 44 Protective film 50 Semiconductor substrate 52 Source / drain extension region 54 Source / drain Region 60 Resist film 70 Gate sidewall film 72 Silicide layer 100 Transistor

Claims (9)

Forming an insulating film on the semiconductor substrate;
Forming a stacked body in which a gate electrode and a first hard mask are sequentially stacked on the insulating film;
Performing a first ion implantation on the semiconductor substrate using the stacked body as a mask;
Forming a protective film on a side surface of the laminate;
Removing the first hard mask by etching;
Removing the protective film by etching;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the protective film is formed of a silicon oxide film. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the gate electrode and the first hard mask are made of polycrystalline silicon. In the manufacturing method of the semiconductor device according to claim 3,
In the step of forming the stacked body, the stacked body is formed by sequentially stacking the gate electrode, the second hard mask, and the first hard mask,
The second hard mask is a method for manufacturing a semiconductor device comprising a silicon oxide film. In the manufacturing method of the semiconductor device according to claim 1,
The step of forming the protective film includes a step of forming the protective film on a side surface and an upper surface of the laminate, and a step of removing the protective film formed on the upper surface of the laminate. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
The step of forming the protective film includes the step of forming the protective film on the side surface and the upper surface of the stacked body by exposing the side surface and the upper surface of the stacked body to an oxygen atmosphere to oxidize, and And a step of removing the protective film formed on the upper surface. In the manufacturing method of the semiconductor device according to claim 5 or 6,
The film thickness of the insulating film formed on the semiconductor substrate in the step of forming the insulating film is the film thickness of the protective film formed on the upper surface of the stacked body in the step of forming the protective film. A method of manufacturing a larger semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
After the step of removing the protective film,
Forming a gate sidewall film on a side surface of the gate electrode;
Performing a second ion implantation on the semiconductor substrate using the gate electrode and the gate sidewall film as a mask;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 8,
After the step of performing the second ion implantation,
A method for manufacturing a semiconductor device, comprising: forming a silicide layer on the gate electrode and on an exposed region of the semiconductor substrate.

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