JP2013021169A - Solid-state image sensor, manufacturing method therefor, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image sensor in which the signal charges of a photoelectric conversion region can be read entirely regardless of the depth position of a semiconductor substrate, and thereby the imaging characteristics are enhanced while eliminating the afterimage.SOLUTION: The solid-state image sensor includes a read gate 21r buried in a trench 17R formed in a semiconductor substrate 13 via a gate insulator 19, and a photoelectric conversion region 15r provided in the semiconductor substrate 13. Furthermore, a floating diffusion 23 is provided in the surface layer of the semiconductor substrate 13 while keeping an interval between the photoelectric conversion region 15r. In particular, a potential adjustment region 25r is provided in contact with the photoelectric conversion region 15r and the gate insulator 19. The potential adjustment region 25r has the same conductivity type as that of the semiconductor substrate 13 and the photoelectric conversion region 15r, and is an impurity region having the concentration of conductivity type lower than that of the semiconductor substrate 13 and the photoelectric conversion region 15r.

Description

  The present technology relates to a solid-state imaging device, a manufacturing method of the solid-state imaging device, and an electronic device, and in particular, a solid-state imaging device including a photoelectric conversion region at a deep position of a semiconductor substrate, a manufacturing method thereof, and further, the solid-state imaging device It relates to the electronic equipment used.

  Some solid-state imaging devices having photoelectric conversion regions have a configuration in which a plurality of photoelectric conversion regions are arranged in the depth direction of a semiconductor substrate. In such a solid-state imaging device, a trench is formed in the vicinity of a photoelectric conversion region disposed at a deep position on a semiconductor substrate, and a readout gate is disposed in the trench through a gate insulating film.

  In the solid-state imaging device having the above-described configuration, a channel is formed in the semiconductor substrate at a position along the gate insulating film from the depth position where the photoelectric conversion region is disposed to the floating diffusion. The signal charge accumulated in the photoelectric conversion region is read out to the floating diffusion through this channel by applying a voltage to the readout gate embedded in the trench (see Patent Document 1 below).

  In addition, a semiconductor substrate region in which a channel is formed between a photoelectric conversion region having an n-type impurity region disposed deep in the semiconductor substrate and a floating diffusion formed of the n-type impurity region is formed as a low concentration n. A configuration of a type impurity region is disclosed. In such a configuration, the photoelectric conversion region is completely depleted by adjusting the n-type impurity concentration, so that all signal charges can be transferred (see Patent Document 2 below).

JP 2009-295937 A JP 2010-114322 A

  However, in the solid-state imaging device having the above-described configuration, it is possible to read out all the signal charges in the photoelectric conversion region arranged at a relatively shallow position in the semiconductor substrate, but the photoelectric conversion region provided at a deep position can be read out. It is difficult to read out the signal charge. This is because when the readout gate is turned on, a region having a potential deeper than that of the channel portion is formed in a portion close to the gate insulating film in the n-type impurity region constituting the photoelectric conversion region, and the signal charge is formed in this deep region. This is because it is left behind. Such a remaining signal charge becomes a factor that generates an afterimage with respect to an image captured by the solid-state imaging device.

  Accordingly, an object of the present technology is to provide a solid-state imaging device that can read out all signal charges in the photoelectric conversion region regardless of the depth position of the semiconductor substrate, thereby improving imaging characteristics. . Moreover, this technique aims at providing the manufacturing method of such a solid-state image sensor, and the electronic device provided with such a solid-state image sensor.

  In order to achieve such an object, a solid-state imaging device of the present technology includes a readout gate embedded in a trench formed in a semiconductor substrate via a gate insulating film, a photoelectric conversion region provided in the semiconductor substrate, It has. Furthermore, a floating diffusion is provided in the surface layer of the semiconductor substrate with a space between the photoelectric conversion region. In particular, a potential adjustment region is provided in contact with the photoelectric conversion region and the gate insulating film. This potential adjustment region is an impurity region having the same conductivity type as that of the semiconductor substrate and the photoelectric conversion region, and having a concentration of the conductivity type lower than that of the semiconductor substrate and the photoelectric conversion region.

  In the solid-state imaging device having such a configuration, the potential level difference in the channel formation region along the gate insulating film is reduced as compared with the configuration in which the potential adjustment region is not provided. Further, for example, when the photoelectric conversion region, the region along the gate insulating film in the semiconductor substrate, and the potential adjustment region are all n-type, the potential of the semiconductor substrate becomes shallower than the potential adjustment region. Therefore, if the signal charges (electrons) accumulated in the photoelectric conversion region are read out to the potential adjustment region by applying a voltage to the readout gate, the signal charges (electrons) are channeled in the semiconductor substrate along the gate insulating film without hindrance. Read to the formation area.

  Moreover, this technique is also a manufacturing method of such a solid-state image sensor, and performs the following procedure. First, impurities are introduced into the semiconductor substrate. Thereby, a photoelectric conversion region is formed inside the semiconductor substrate. At the same time, a potential adjustment region having the same conductivity type as the semiconductor substrate and the photoelectric conversion region and having a lower concentration of the conductivity type than the semiconductor substrate and the photoelectric conversion region is formed in contact with the photoelectric conversion region. Next, a trench in contact with the potential adjustment region is formed in the semiconductor substrate. Thereafter, a read gate is formed in the trench through a gate insulating film. Further, by introducing impurities into the surface layer of the semiconductor substrate, a floating diffusion is formed in the vicinity of the read gate.

  Moreover, this technique is also an electronic device provided with such a solid-state image sensor.

  As described above, according to the present technology, since the potential step in the channel formation region is adjusted by the potential adjustment region, the signal charge in the photoelectric conversion region can be read to the channel formation region of the semiconductor substrate without any obstacle. As a result, in the solid-state imaging device in which the photoelectric conversion region is provided at a deep position on the semiconductor substrate, it is possible to read out all signal charges in the photoelectric conversion region, thereby preventing the occurrence of afterimage and improving the imaging characteristics. Is possible.

It is a schematic structure figure showing an example of a solid imaging device which has a solid imaging device of this art. It is the top view and sectional drawing which show the structure of the solid-state image sensor of 1st Embodiment. It is a figure explaining the drive of the solid-state image sensor of 1st Embodiment. FIG. 6 is a cross-sectional process diagram (part 1) illustrating the manufacturing procedure of the solid-state imaging element according to the first embodiment; It is sectional process drawing (the 2) which shows the manufacture procedure of the solid-state image sensor of 1st Embodiment. It is sectional drawing which shows the structure of the solid-state image sensor used as the comparative example of 1st Embodiment. It is a figure explaining the drive of the solid-state image sensor which becomes a comparative example of 1st Embodiment. It is the top view and sectional drawing which show the structure of the solid-state image sensor of 2nd Embodiment. It is a figure explaining the drive of the solid-state imaging device of 2nd Embodiment. It is sectional process drawing (the 1) which shows the manufacture procedure of the solid-state image sensor of 2nd Embodiment. It is sectional process drawing (the 2) which shows the manufacture procedure of the solid-state image sensor of 2nd Embodiment. It is sectional drawing which shows the structure of the solid-state image sensor used as the comparative example of 2nd Embodiment. It is a figure explaining the drive of the solid-state image sensor used as the comparative example of 2nd Embodiment. It is sectional drawing which shows the modification of embodiment. It is a block diagram of the electronic device of 3rd Embodiment which has a solid-state image sensor to which this technique is applied.

Hereinafter, embodiments of the present technology will be described in the following order based on the drawings.
1. 1. Schematic configuration example of a solid-state imaging device provided with the solid-state imaging device of the embodiment First embodiment (an example of a solid-state imaging device provided with a potential adjustment region)
3. Second Embodiment (Example of a solid-state imaging device provided with a pinning region overlapping with a potential adjustment region)
4). Modification 5 Third Embodiment (Example of Electronic Device Using Solid-State Image Sensor)
In addition, in each embodiment and modification, the same code | symbol is attached | subjected to a common component, and the overlapping description is abbreviate | omitted.

<< 1. Example of schematic configuration of solid-state image sensor according to embodiment >>
FIG. 1 shows a schematic configuration using a MOS type solid-state imaging device as an example of a solid-state imaging device provided with the solid-state imaging device of the present technology.

  The solid-state imaging device 1 shown in this figure has a pixel region 4 in which a plurality of pixels 3 including a photoelectric conversion region are two-dimensionally arranged on one surface of a support substrate 2. Each pixel 3 arranged in the pixel region 4 is provided with a photoelectric conversion region, a floating diffusion, a read gate, a pixel circuit composed of a plurality of other transistors (so-called MOS transistors), a capacitive element, and the like. ing. A plurality of pixels 3 may share a part of the pixel circuit.

  Peripheral circuits such as a vertical drive circuit 5, a column signal processing circuit 6, a horizontal drive circuit 7, and a system control circuit 8 are provided in the peripheral portion of the pixel region 4 as described above.

  The vertical drive circuit 5 is configured by, for example, a shift register, selects the pixel drive line 9, supplies a pulse for driving the pixel 3 to the selected pixel drive line 9, and the pixels 3 arranged in the pixel region 4. Is driven line by line. That is, the vertical drive circuit 5 selectively scans each pixel arranged in the pixel region 4 in the vertical direction sequentially in units of rows. Then, the pixel signal based on the signal charge generated according to the amount of light received in each pixel 3 is supplied to the column signal processing circuit 6 through the vertical drive line 10 wired perpendicular to the pixel drive line 9.

  The column signal processing circuit 6 is arranged for each column of pixels, for example, and performs signal processing such as noise removal on the signal output from the pixels 3 for one row for each pixel column. That is, the column signal processing circuit 6 performs signals such as correlated double sampling (CDS), signal amplification, and analog / digital conversion (AD) to remove fixed pattern noise unique to a pixel. Process.

  The horizontal drive circuit 7 is configured by, for example, a shift register, and sequentially outputs horizontal scanning pulses, thereby selecting each of the column signal processing circuits 6 in order and outputting a pixel signal from each of the column signal processing circuits 6.

  The system control circuit 8 receives an input clock and data for instructing an operation mode, and outputs data such as internal information of the solid-state imaging device 1. That is, in the system control circuit 8, based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, the clock signal and the control signal that are the reference for the operation of the vertical drive circuit 5, the column signal processing circuit 6, the horizontal drive circuit 7, and the like. Is generated. These signals are input to the vertical drive circuit 5, the column signal processing circuit 6, the horizontal drive circuit 7, and the like.

  The peripheral circuits 5 to 8 as described above and the pixel circuit provided in the pixel region 4 constitute a drive circuit that drives each pixel. Note that the peripheral circuits 5 to 8 may be arranged at positions where they are stacked in the pixel region 4.

≪2. First Embodiment >>
<Configuration of solid-state image sensor>
(Example of potential adjustment area)
2 is a diagram illustrating a configuration of the solid-state imaging device 1-1 according to the first embodiment, FIG. 2A is a schematic plan view of one pixel in the solid-state imaging device, and FIG. 2B is a cross-sectional view taken along line AA in FIG. 2A. It is a schematic sectional drawing equivalent to. Hereinafter, the configuration of the solid-state imaging device 1-1 of the first embodiment will be described based on these drawings.

  A solid-state imaging device 1-1 according to the first embodiment shown in FIG. 2 is disposed in each pixel of the above-described solid-state imaging device, and a semiconductor substrate 13 is disposed on the support substrate 2 via an insulating film 11. The semiconductor substrate 13 includes a plurality of photoelectric conversion regions 15r, 15g, and 15b. Inside the semiconductor substrate 13, two trenches 17r and 17g are provided beside the photoelectric conversion regions 15r, 15g and 15b. In these trenches 17r and 17g, embedded read gates 21r and 21g are provided via a gate insulating film 19. Further, a read gate 21 b (see a plan view) is provided on the semiconductor substrate 13 via a gate insulating film 19.

  Further, on the surface layer of the semiconductor substrate 13, three floating diffusions 23 are arranged in the vicinity of the read gates 21r, 21g, 21b. In particular, the first embodiment is characterized in that potential adjustment regions 25 r and 25 g are provided between the photoelectric conversion region 15 r and photoelectric conversion region 15 g and the gate insulating film 19.

  Next, the detailed configuration of the semiconductor substrate 13 and the components disposed inside and above the semiconductor substrate 13 will be described.

[Semiconductor substrate 13]
The semiconductor substrate 13 is a semiconductor thin film made of, for example, single crystal silicon. Here, the entire semiconductor substrate 13 is used as an n-well by configuring the semiconductor substrate 13 using n-type single crystal silicon. The n-type concentration in the semiconductor substrate 13 is slightly thin [n−]. The n-type concentration shown here is not the concentration of the n-type impurity itself, but a substantial n-type concentration. Therefore, even if the concentration of n-type impurities is high, the substantial n-type concentration is low if the concentration of p-type impurities in the region is high. This is the same in the following.

  In the first embodiment, the surface of the semiconductor substrate 13 opposite to the support substrate 2 is the light receiving surface A for the photoelectric conversion regions 15r, 15g, and 15b.

[Photoelectric conversion regions 15r, 15g, 15b]
The photoelectric conversion regions 15r, 15g, and 15b are impurity regions that are stacked in the depth direction in the semiconductor substrate 13, and the planar shape when the semiconductor substrate 13 is viewed from the light receiving surface A side is, for example, square. is there. Among these photoelectric conversion regions 15r, 15g, and 15b, the photoelectric conversion region 15r that converts light in the red region is disposed at the deepest position of the semiconductor substrate 13 and the closest position to the support substrate 2. In addition, a photoelectric conversion region 15g that converts light in the green region is disposed on the upper portion. A photoelectric conversion region 15b that converts light in the blue region is disposed closest to the surface of the semiconductor substrate 13. These are arranged in order from the longest wavelength corresponding to the photoelectric conversion region 15r for red, the photoelectric conversion region 15g for green, and the photoelectric conversion region 15b for blue in order from the support substrate 2 side.

  Further, the photoelectric conversion region 15r arranged at the deepest portion may be extended to below a trench 17g described later.

  The photoelectric conversion regions 15 r, 15 g, and 15 b arranged as described above are n-type impurity regions similar to the semiconductor substrate 13, and the n-type concentration is higher than that of the semiconductor substrate 13 [n +]. Such photoelectric conversion regions 15r, 15g, and 15b have a deeper potential than the semiconductor substrate 13 in a range not affected by the electric field.

  A p-type region 16 is disposed between the photoelectric conversion regions 15r, 15g, and 15b and on the uppermost photoelectric conversion region 15b so as to be in contact therewith. Thus, a photodiode having a pn junction is formed between each n-type photoelectric conversion region 15r, 15g, 15b and any p-type region 16 in contact therewith. Then, pn junctions between the n-type photoelectric conversion regions 15r, 15g, and 15b and the p-type region 16 are arranged at a depth corresponding to the wavelength dependency of the light absorption coefficient of light incident from the light receiving surface A. It has a configuration. However, the uppermost p-type region 16 may be provided as a layer for suppressing the interface state.

  The p-type concentration in these p-type regions 16 is high [p +]. Note that the p-type concentration shown here is not the p-type impurity concentration itself, but a substantial p-type concentration, as in the n-type concentration.

[Trench 17r, 17g]
The trenches 17r and 17g are independently provided on the sides of the photoelectric conversion regions 15r, 15g, and 15b with a space therebetween. For example, the trenches 17r and 17g are disposed at positions sandwiching the photoelectric conversion regions 15r, 15g, and 15b having a square shape from the diagonal direction.

  Of these two trenches 17r and 17g, one trench 17r is provided to penetrate the semiconductor substrate 13, and the other trench 17g is formed in a concave shape having a bottom without penetrating the semiconductor substrate 13. Yes. The depth of the recessed trench 17g is at least deeper than the green photoelectric conversion region 15g and shallower than the red photoelectric conversion region 15r. As a result, the red photoelectric conversion region 15r provided at the deepest portion of the semiconductor substrate 13 can be extended below the trench 17g, and the amount of signal charges accumulated in the photoelectric conversion region 15r can be increased.

[Gate insulating film 19]
The gate insulating film 19 is provided to cover the inner walls of the trenches 17 r and 17 g and the light receiving surface A of the semiconductor substrate 13. The gate insulating film 19 is formed using, for example, a silicon oxide film obtained by thermally oxidizing silicon, a silicon oxynitride film, or a high dielectric insulating film. The high dielectric insulating film is configured using hafnium oxide, hafnia silicate, nitrogen-added hafnium aluminate, tantalum oxide, titanium dioxide, zirconium oxide, praseodymium oxide, yttrium oxide, or the like. Each such material film is used as the gate insulating film 19 in a single layer or in a stacked state as necessary.

[Read gates 21r, 21g]
The read gates 21 r and 21 g are provided as embedded electrodes embedded in the trenches 17 r and 17 g through the gate insulating film 19, and are patterned above the light receiving surface A of the semiconductor substrate 13. Such read gates 21r and 21g are made of, for example, polysilicon (Phosphorus Doped Amorphous Silicon: PDAS) containing impurities such as phosphorus (P), or metal materials such as aluminum, tungsten, titanium, cobalt, hafnium, and tantalum. It is configured using.

[Read Gate 21b]
The read gate 21 b is provided above the light receiving surface A of the semiconductor substrate 13 via the gate insulating film 19. The read gate 21b is disposed with a space between the read gates 21r and 21g serving as buried electrodes, and is patterned with a predetermined space from the uppermost blue photoelectric conversion region 15b. Such a read gate 21b may be composed of the same material layer as the read gates 21r and 21g.

[Floating diffusion 23]
The floating diffusion 23 is an impurity region provided in the surface layer of the semiconductor substrate 13 on the light receiving surface A side, and the read gates 21r, 21g, and 21b are sandwiched between the photoelectric conversion regions 15r, 15g, and 15b. In the position. Each floating diffusion 23 arranged in this manner is an n-type impurity region similar to the semiconductor substrate 13 and the photoelectric conversion regions 15r, 15g, and 15b, and the n-type concentration is higher than that of the semiconductor substrate 13 [n +]. It is.

[Potential adjustment area 25r, 25g]
The potential adjustment regions 25r and 25g are provided between the photoelectric conversion regions 15r and 15g disposed deep in the semiconductor substrate 13 and the gate insulating film 19 that covers the sidewalls of the trenches 17r and 17g. Among these, one potential adjustment region 25r is disposed between and in contact with the red photoelectric conversion region 15r and the trench 17r, and is provided in the same depth region as the photoelectric conversion region 15r. The potential adjustment region 25r is disposed with a space between the other photoelectric conversion regions 15g and 15b and the floating diffusion 23. The other potential adjustment region 25g is disposed between and in contact with the green photoelectric conversion region 15g and the trench 17g, and is provided in the same depth region as the photoelectric conversion region 15g. The potential adjustment region 25g is disposed with a space between the other photoelectric conversion regions 15r and 15b and the floating diffusion 23.

  The potential adjustment regions 25r and 25g arranged as described above are n-type impurity regions similar to the semiconductor substrate 13 and the photoelectric conversion regions 15r, 15g, and 15b, and the n-type concentration is further higher than that of the semiconductor substrate 13. Thin [n--]. Such potential adjustment regions 25r and 25g have a shallower potential than the semiconductor substrate 13 and the photoelectric conversion regions 15r, 15g, and 15b within the range not affected by the electric field.

<Driving of solid-state image sensor>
FIG. 3 is a diagram for explaining the driving of the solid-state imaging device 1-1 having the above-described configuration. As an example, the potential of the light receiving period and the reading period in the red photoelectric conversion region 15r is shown. 3A (1) and FIG. 3A (2) are potentials at the depth position of the photoelectric conversion region 15r. On the other hand, FIG. 3B (1) and FIG. 3B (2) show the potential of the channel formation region along the gate insulating film 19. 3A (1) and 3B (1) correspond to the light receiving period (gate voltage OFF), and FIGS. 3A (2) and 3B (2) correspond to the reading period (gate voltage ON). Hereinafter, driving of the solid-state imaging device 1-1 according to the first embodiment will be described with reference to FIG. 2 together with these drawings.

  First, in the light receiving period, the gate voltage applied to the readout gate 21r is turned off. For this reason, as shown in FIG. 3A (1), at the depth position of the photoelectric conversion region 15r, the potential of the photoelectric conversion region 15r having a high n-type concentration [n +] is a potential having a concentration [n−−]. It is maintained deeper than the potential of the adjustment region 25r. As a result, the signal charge e generated by the photoelectric conversion is accumulated in the photoelectric conversion region 15r.

  On the other hand, as shown in FIG. 3B (1), in the channel formation region along the gate insulating film 19, the potential of the potential adjustment region 25 r whose n-type concentration is extremely low [n−−] is n-type concentration. However, it is kept shallower than the potential of the semiconductor substrate 13 which is slightly thin [n−].

  Next, in the read period, the positive gate voltage applied to the read gate 21r is turned ON. At this time, the potential adjustment region 25r disposed in contact with the gate insulating film 19 is more strongly affected by the electric field due to the gate voltage than the photoelectric conversion region 15r.

  Therefore, as shown in FIG. 3A (2), the gate voltage is set so that the potential of the potential adjustment region 25r is deeper than the potential of the photoelectric conversion region 15r. As a result, the signal charge e in the photoelectric conversion region 15r is read out to the potential adjustment region 25r.

  On the other hand, as shown in FIG. 3B (2), the potential adjustment region 25r and the semiconductor substrate 13 arranged along the gate insulating film 19 are affected by the gate voltage applied to the read gate 21r with the same strength. For this reason, the depth relationship of the potential between the potential adjustment region 25r and the semiconductor substrate 13 is deepened as a whole while being maintained similarly to the light receiving period. Therefore, the signal charge e read out to the potential adjustment region 25r is read out to the semiconductor substrate 13 having a deeper potential. At this time, a drain voltage is applied to the floating diffusion 23 arranged close to the read gate 21r so that the potential is deeper than that of the semiconductor substrate 13. As a result, the signal charge e in the photoelectric conversion region 15 r is read out to the floating diffusion 23.

  The above driving is similarly applied to driving of the green photoelectric conversion region 15g. The blue photoelectric conversion region 15b may be driven in the same manner as when a normal surface channel type read gate is used.

<Method for Manufacturing Solid-State Imaging Device>
4 and 5 are cross-sectional process diagrams for explaining a manufacturing procedure of the solid-state imaging device 1-1 having the above-described configuration. Hereinafter, a manufacturing procedure of the solid-state imaging device 1-1 of the first embodiment will be described based on these drawings.

[FIG. 4A]
First, as shown in FIG. 4A, a thin-film semiconductor substrate 13 provided on the support substrate 2 via an insulating film 11 is prepared. The semiconductor substrate 13 is made of n-type single crystal silicon, and the n-type concentration is slightly low [n−].

[FIG. 4B]
Next, as shown in FIG. 4B, by introducing impurities of each conductivity type into the semiconductor substrate 13, the photoelectric conversion regions 15 r and 15 g are formed inside the semiconductor substrate 13 having a slightly low n-type concentration [n−]. , 15b, p-type region 16, and potential adjustment regions 25r, 25g.

  At this time, in the formation of the photoelectric conversion regions 15 r, 15 g and 15 b, n-type impurities are further introduced into the depth regions of the semiconductor substrate 13. As a result, [n +] photoelectric conversion regions 15r, 15g, and 15b having a high n-type concentration are formed.

  Further, in the formation of the potential adjustment regions 25 r and 25 g, p-type impurities are introduced into the depth regions of the semiconductor substrate 13. As a result, the n-type concentration adjustment regions 25r and 25g having substantially low [n−−] are formed in contact with the photoelectric conversion regions 15r and 15g.

  Further, in the formation of each p-type region 16, a p-type impurity is introduced into each depth region of the semiconductor substrate 13 in such an amount that the conductivity type is inverted and becomes deep [p +]. Thereby, each p-type region 16 is formed.

  The introduction of each impurity into the semiconductor substrate 13 as described above is performed by ion implantation of each impurity whose depth is adjusted by implantation energy and subsequent activation heat treatment while limiting the area by a mask. The ion implantation may be performed in a predetermined order, and the activation heat treatment may be performed after all the ion implantations are completed.

[FIG. 4C]
Thereafter, as shown in FIG. 4C, trenches 17 r and 17 g are formed in the semiconductor substrate 13. At this time, a trench 17r in contact with the potential adjustment region 25r is formed in a state of penetrating the semiconductor substrate 13 by etching using a resist pattern (not shown) as a mask. In addition, a trench 17g that is in contact with the potential adjustment region 25g and does not reach the photoelectric conversion region 15r is formed in the semiconductor substrate 13 by etching using another resist pattern as a mask.

[FIG. 5A]
Next, as shown in FIG. 5A, a gate insulating film 19 is formed so as to cover the inner walls of the trenches 17 r and 17 g and the semiconductor substrate 13. The gate insulating film 19 is formed by a method appropriately selected depending on the material constituting the gate insulating film 19. For example, a silicon oxide film or a silicon oxynitride film is formed by thermal oxidation or thermal nitridation of the semiconductor substrate 13, and a hafnium oxide film or the like is formed by atomic layer deposition.

  Thereafter, a conductive material film 21 is formed on the gate insulating film 19 with the trenches 17r and 17g buried. The conductive material film 21 is formed by a method appropriately selected according to the material constituting the conductive material film 21. For example, a polysilicon film containing an impurity such as phosphorus (P) is formed by chemical vapor deposition, and a metal material film such as aluminum, tungsten, titanium, cobalt, hafnium, and tantalum is used. The film is formed by sputtering.

[FIG. 5B]
Next, as shown in FIG. 5B, the conductive material film 21 is subjected to pattern etching. As a result, a read gate 21r embedded in the trench 17r, a read gate 21g embedded in the trench 17g, and a read gate (21b) on the light receiving surface A of the semiconductor substrate 13 not shown here are formed. To do. At this time, the conductive material film 21 may be etched using a resist pattern not shown here as a mask. After that, annealing is performed in a chlorine atmosphere in order to terminate the interface state between the gate insulating film 19 and the semiconductor substrate 13 as necessary.

[FIG. 5C]
Thereafter, as shown in FIG. 5C, insulating side walls 22 are formed on the side walls of the read gates 21r, 21g, and (21b). The sidewall 22 is formed by forming an insulating film such as a silicon oxide film or a silicon nitride film and then etching back the insulating film. Thereafter, the floating diffusion 23 is formed on the surface layer on the light receiving surface A side of the semiconductor substrate 13 at positions where the read gates 21r, 21g, (21b) are sandwiched between the photoelectric conversion regions 15r, 15g, 15b. At this time, impurities are introduced into the surface layer of the semiconductor substrate 13 using the resist pattern (not shown) and the side wall 22 as a mask, thereby allowing the n-type high-concentration [n +] floating diffusion 23 to be formed on the side. It is formed on the side of the wall 22 by self alignment.

  As described above, the solid-state imaging device 1-1 having the configuration described above with reference to FIG. 2 is obtained.

<Effects of First Embodiment>
The solid-state imaging device 1-1 according to the first embodiment described above uses photoelectric conversion regions 15r, 15g and [n−−] potential adjustment regions 25r, 25g having a lower n-type concentration than the photoelectric conversion regions 15r, 15g. This is a configuration provided between the conversion regions 15 r and 15 g and the gate insulating film 19. As a result, the potential of the channel formation region along the gate insulating film 19 can be made deeper in the semiconductor substrate 13 than the potential adjustment regions 25r and 25g, and the signal charges (electrons) in the potential adjustment regions 25r and 25g are disturbed. It becomes possible to read out to the semiconductor substrate 13. As a result, in the solid-state imaging device 1-1 in which the photoelectric conversion regions 15r and 15g are provided at a deep position on the semiconductor substrate 13, all signal charges in the photoelectric conversion regions 15r and 15g can be read out, thereby preventing afterimages. Thus, it is possible to improve the imaging characteristics.

  For comparison, FIG. 6 shows a cross-sectional view of a solid-state imaging device having a configuration without a potential adjustment region. FIG. 7 is a diagram for explaining driving of the solid-state imaging device shown in FIG. In a solid-state imaging device not provided with a potential adjustment region, during the light receiving period, as shown in FIGS. 7A (1) and 7B (1), the potential of the photoelectric conversion region 15r having a high n-type concentration [n +]. Is maintained deeper than the potential of the semiconductor substrate 13 having the concentration [n−]. As a result, the signal charge e generated by the photoelectric conversion is accumulated in the photoelectric conversion region 15r.

  Further, by turning on the gate voltage applied to the readout gate 21r during the readout period, the potential on the gate insulating film 19 side in the photoelectric conversion region 15r is deepened as shown in FIG. 7A (2). Thereby, the signal charge e in the photoelectric conversion region 15r is read out to the gate insulating film 19 side. However, as shown in FIG. 7B (2), in the channel formation region along the gate insulating film 19, the potential depth relationship between the photoelectric conversion region 15r and the semiconductor substrate 13 is maintained as in the light receiving period. It becomes deep as a whole. For this reason, the photoelectric conversion region 15r remains deeper in potential than the semiconductor substrate 13, and the signal charge e remains in the photoelectric conversion region 15r.

≪3. Second Embodiment >>
<Configuration of solid-state image sensor>
(Example of providing a pinning area overlapping the potential adjustment area)
FIG. 8 is a diagram illustrating a configuration of the solid-state imaging device 1-2 according to the second embodiment. FIG. 8A is a schematic plan view of one pixel in the solid-state imaging device, and FIG. 8B is a schematic cross-sectional view corresponding to the AA cross section of FIG. 8A. The solid-state imaging device 1-2 of the second embodiment shown in these drawings is different from the first embodiment in that a pinning region 31 is provided in the inner wall layer of the trenches 17r and 17g, and the other configuration is the first. This is the same as in the first embodiment.

  That is, the pinning region 31 is an impurity region provided along the inner walls of the trenches 17r and 17g inside the semiconductor substrate 13, and is provided as a layer for suppressing the interface state. Such a pinning region 31 is configured as a p-type impurity region having a conductivity type opposite to that of the semiconductor substrate 13. The p-type concentration in these pinning regions 31 is high [p +].

  Each pinning region 31 as described above is an overlapping region 31 ′ partially overlapping the potential adjustment regions 25 r and 25 g at the same height as the potential adjustment regions 25 r and 25 g. Such an overlapping region 31 ′ includes impurities constituting the potential adjustment regions 25 r and 25 g whose n-type concentration is [n−−] and impurities constituting the pinning region 31 whose p-type concentration is [p +]. Including. Therefore, the p-type concentration in the overlapping region 31 ′ is slightly lower [p−], and is lower than the p-type concentration in the pinning region 31.

  Here, the potential adjustment regions 25r and 25g may be arranged so that only a part on the gate insulating film 19 side overlaps with the pinning region 31 as shown in the figure, or all of them are arranged so as to overlap with the pinning region 31. Also good.

<Driving of solid-state image sensor>
FIG. 9 is a diagram for explaining the driving of the solid-state imaging device 1-2 having the above-described configuration. As an example, the potential of the light receiving period and the reading period in the red photoelectric conversion region 15r is shown. FIG. 9A (1) and FIG. 9A (2) show the potential at the depth position of the photoelectric conversion region 15r. On the other hand, FIG. 9B (1) and FIG. 9B (2) show the potential of the channel formation region along the gate insulating film 19. 9A (1) and FIG. 9B (1) correspond to the light receiving period (gate voltage OFF), and FIGS. 9A (2) and 9B (2) correspond to the reading period (gate voltage ON). Hereinafter, the driving of the solid-state imaging device 1-2 according to the second embodiment will be described with reference to FIG. 8 together with these drawings.

  First, in the light receiving period, the gate voltage applied to the readout gate 21r is turned off. For this reason, as shown in FIG. 9A (1), the potential at the depth position of the photoelectric conversion region 15r is the photoelectric conversion region 15r having a high n-type concentration [n +], and the potential adjustment having the concentration [n−−]. The region 25r becomes shallower in the order of the overlapping region 31 ′ where the p-type concentration is slightly light [p−]. Thereby, the signal charge e generated by the photoelectric conversion is accumulated in the photoelectric conversion region 15r.

  On the other hand, as shown in FIG. 9B (1), the potential of the channel formation region along the gate insulating film 19 is such that the p-type concentration is slightly low [p-], the overlapping region 31 ', and the p-type concentration is high. It becomes shallower in the order of the pinning region 31 which is [p +]. This step follows the p-type density difference. Here, the overlapping region 31 ′ is a region in which the pinning region 31 having a high p-type concentration [p +] and the potential adjustment region 25r having a very low n-type concentration [n−−] are overlapped. is there. For this reason, the difference between the p-type concentration of the overlapping region 31 ′ and the p-type concentration of the pinning region 31 is small, and the level difference is not so large.

  Next, in the read period, the positive gate voltage applied to the read gate 21r is turned ON. At this time, the potential adjustment region 25r and the overlapping region 31 'arranged on the read gate 21r side are more strongly affected by the electric field due to the gate voltage than the photoelectric conversion region 15r.

  Therefore, as shown in FIG. 9A (2), the gate voltage is set so that the potential of the potential adjustment region 25r and the overlapping region 31 'is deeper than the photoelectric conversion region 15r. As a result, the signal charge e in the photoelectric conversion region 15r is read out to the potential adjustment region 25r and the overlapping region 31 '.

  On the other hand, as shown in FIG. 9B (2), the overlapping region 31 'and the pinning region 31 arranged along the gate insulating film 19 are affected by the gate voltage applied to the read gate 21r with the same strength. For this reason, the potential depth relationship between the overlapping region 31 ′ and the pinning region 31 is deepened as a whole while being maintained in the same manner as in the light receiving period. Therefore, the signal charge e read out to the overlapping region 31 ′ has a small step from the overlapping region 31 ′ having a slightly lower p-type concentration [p−] to the pinning region 31 having a higher p-type concentration [p +]. Is read out to the pinning area 31. At this time, a drain voltage is applied to the floating diffusion 23 arranged close to the read gate 21r so that the potential is deeper than that of the semiconductor substrate 13. As a result, the signal charge e in the photoelectric conversion region 15 r is read out to the floating diffusion 23.

  The above driving is similarly applied to driving of the green photoelectric conversion region 15g. The blue photoelectric conversion region 15b may be driven in the same manner as when a normal surface channel type read gate is used.

<Method for Manufacturing Solid-State Imaging Device>
10 and 11 are cross-sectional process diagrams for explaining the manufacturing procedure of the solid-state imaging device 1-2 having the above-described configuration. Hereinafter, a manufacturing procedure of the solid-state imaging device 1-2 of the second embodiment will be described based on these drawings.

[FIG. 10A]
First, as shown in FIG. 10A, the photoelectric conversion regions 15r, 15g, and 15b, the p-type region 16, and the potential adjustment regions 25r and 25g are formed on the semiconductor substrate 13, and the trenches 17r and 17g are further formed. The same as in the first embodiment.

[FIG. 10B]
Next, as shown in FIG. 10B, by introducing p-type impurities from the inner walls of the trenches 17r and 17g into the n-type semiconductor substrate 13 having a slightly lower n-type concentration, the inner walls of the trenches 17r and 17g are introduced. A p-type pinning region 31 having a slightly higher p-type concentration is formed. As a result, p-type impurities are also introduced into the potential adjustment regions 25r and 25g exposed on the inner walls of the trenches 17r and 17g, and the p-type overlapping region 31 having a slightly lower p-type concentration is applied to these portions. 'Form.

  The introduction of the p-type impurity as described above is performed by oblique ion implantation of each impurity whose depth is adjusted by implantation energy and subsequent activation heat treatment while limiting the area by a mask. At this time, by adjusting the ion implantation energy, the overlap of the pinning region 31 with respect to the potential adjustment regions 25r and 25g is adjusted so that the pinning region 31 overlaps part or all of the potential adjustment regions 25r and 25g. The ion implantation energy is adjusted so that the pinning region 31 is not formed beyond the potential adjustment regions 25r and 25g. After the above, the same procedure as that described with reference to FIGS. 5A to 5C in the first embodiment is performed.

[FIG. 10C]
That is, first, as shown in 10C, the gate insulating film 19 is formed so as to cover the inner walls of the trenches 17r and 17g and the semiconductor substrate 13. Next, a conductive material film 21 is formed on the gate insulating film 19 with the trenches 17r and 17g buried.

[FIG. 11A]
Next, as shown in FIG. 11A, the conductive material film 21 is subjected to pattern etching to form a read gate 21r in the trench 17r, a read gate 21g in the trench 17g, and further on the light receiving surface A here. The read gate (21b) is omitted.

[FIG. 11B]
Thereafter, as shown in FIG. 11B, insulating sidewalls 22 are formed on the sidewalls of the read gates 21r, 21g, and (21b), and then the n-type concentration is high in the surface layer on the light receiving surface A side of the semiconductor substrate 13. n +] floating diffusion 23 is formed.

  Thus, the solid-state imaging device 1-2 having the configuration described above with reference to FIG. 8 is obtained.

<Effects of Second Embodiment>
The solid-state imaging device 1-2 according to the second embodiment described above has a p-type pinning region 31 on the inner walls of the trenches 17r and 17g in which the readout gates 21r and 21g are further provided in the configuration of the first embodiment. Is provided. Thereby, as will be described below, the gate insulating film 19 is compared with the case where the [n−−] potential adjustment regions 25r and 25g having an n-type concentration extremely lower than that of the photoelectric conversion regions 15r and 15g are not provided. The potential step in the channel forming region along the line can be reduced.

  Therefore, the signal charges (electrons) read from the photoelectric conversion regions 15r and 15g to the overlapping region 31 ′ via the potential adjustment regions 25r and 25g can be easily read from the overlapping region 31 ′ toward the pinning region 31. Is possible. As a result, in the solid-state imaging device 1-2 in which the photoelectric conversion regions 15r and 15g are provided at a deep position on the semiconductor substrate 13, it is possible to read out all signal charges of the photoelectric conversion regions 15r and 15g, thereby improving the imaging characteristics. Can be achieved.

  For comparison, FIG. 12 shows a cross-sectional view of a solid-state imaging device having a configuration without a potential adjustment region. FIG. 13 is a diagram for explaining driving of the solid-state imaging device shown in FIG. In a solid-state imaging device not provided with a potential adjustment region, overlapping regions where photoelectric conversion regions 15r and 15g having high n-type density [n +] and pinning region 31 having high p-type density [p +] overlap. 31 ″ is an extremely thin p-type concentration [p−−].

  In the light receiving period of such a solid-state imaging device, as shown in FIG. 13A (1), the potential of the photoelectric conversion region 15r having a high n-type density [n +] has a very low p-type density [p It is maintained deeper than the potential of the overlapping region 31 ″ that is-]. Thereby, the signal charge e generated by the photoelectric conversion is accumulated in the photoelectric conversion region 15r.

  On the other hand, as shown in FIG. 13B (1), the potential of the pinning region 31 having a high p-type concentration [p +] is the potential of the overlapping region 31 ″ having a very low p-type concentration [p−−]. Here, the overlapping region 31 ″ is a region in which the pinning region 31 having a high p-type concentration [p +] and the photoelectric conversion region 15r having a high n-type concentration [n +] are overlapped. is there. For this reason, the p-type concentration of the overlapping region 31 ″ is greatly different from the p-type concentration of the pinning region 31, and the potential step is larger than that of the solid-state imaging device of the second embodiment described with reference to FIGS. large.

  Next, in the reading period, by turning on the gate voltage applied to the reading gate 21r, as shown in FIG. 13A (2), the value is [p−−] rather than the photoelectric conversion region 15r which is [n +]. The potential of the overlapping region 31 ″ is deepened. Thereby, the signal charge e of the photoelectric conversion region 15r is read out to the gate insulating film 19 side. However, as shown in FIG. 13B (2), the gate insulating film In the portion in contact with 19, the depth relationship of the potential between the overlapping region 31 ″ and the pinning region 31 is deepened as a whole while maintaining the same as in the light receiving period. Therefore, the potential of the pinning region 31 that is [p +] is shallower than the potential of the overlapping region 31 ″ that is [p−−], and a large step is left. Therefore, the signal charge e remains in the overlapping region 31 ″. It will be done.

<< 4. Variations >>
In FIG. 14, sectional drawing of the modifications 1-3 of the solid-state image sensor of this technique is shown. Hereinafter, each modification of a solid-state image sensor will be described based on these drawings. 14A to 14C illustrate a configuration in which each modification is applied to the solid-state imaging device 1-1 of the first embodiment, each modification is illustrated in the solid-state imaging device 1 of the second embodiment. The same applies to -2.

[Modification 1]
14A shows a configuration of a solid-state imaging device 1a in which a readout gate 21g ′ for reading a signal charge from the green photoelectric conversion region 15g is also provided in the trench 17g ′ penetrating as a first modification of the solid-state imaging device. Indicates. The semiconductor substrate 13 is provided with penetrating trenches 17r, 17g ′ at positions sandwiching the photoelectric conversion regions 15r, 15g, 15b. According to this configuration, since the depths of the through-shaped trenches 17r and 17g ′ with respect to the photoelectric conversion regions 15r, 15g, and 15b are stabilized, it is possible to obtain imaging characteristics without variations.

[Modification 2]
In FIG. 14B, as a second modification of the solid-state imaging device, a configuration of the solid-state imaging device 1b in which the readout gate 21r for reading the signal charge from the red photoelectric conversion region 15r is also a trench 17r ′ that does not penetrate the semiconductor substrate 13 is shown. Indicates. In this case, the trench 17r ′ may be formed deeper than the red photoelectric conversion region 15r.

[Modification 3]
In FIG. 14C, as a third modification of the solid-state imaging device, a solid-state imaging device 1c in which a potential adjustment region 25r is provided only in the red photoelectric conversion region 15r farthest from the floating diffusion 23 and disposed at the deepest position of the semiconductor substrate 13. The structure of is shown. In this case, the green photoelectric conversion region 15g is provided in contact with the gate insulating film 19 covering the inner wall of the trench 17g. Even in such a configuration, all signal charges are read out from the photoelectric conversion region 15r for red, which is the most difficult to read out signal charges, by being arranged at the deepest position of the semiconductor substrate 13 farthest from the floating diffusion 23. It becomes possible. In the case of this configuration, all signals are read out from the green photoelectric conversion region 15g by adjusting the gate voltage applied to the readout gate 21g.

  Note that the third modification can be combined with the first or second modification.

  In the embodiment and the modification described above, the configuration in which the present technology is applied to the solid-state imaging device having the configuration in which the readout gates 21r, 21g, and 21b and the floating diffusion 23 are provided on the light receiving surface A side of the semiconductor substrate 13 has been described. However, the present technology can be similarly applied to a so-called back-illuminated solid-state imaging device in which the reading gates 21r, 21g, and 21b and the floating diffusion 23 are provided on the surface of the semiconductor substrate 13 opposite to the light receiving surface A. In this case, a potential adjustment region may be provided so as to be in contact with the photoelectric conversion region arranged at a depth position away from the floating diffusion 23.

  In the embodiment and the modification described above, the configuration in which the present technology is applied to the solid-state imaging device having the n-type conductivity type of the semiconductor substrate 13, the photoelectric conversion regions 15r, 15g, and 15b, and the floating diffusion 23 is described. did. However, the present technology can be similarly applied to a solid-state imaging element having the opposite conductivity type. In this case, “n-type” described in the embodiment and the modified example is read as “p-type”, “p-type” is read as “n-type”, and “shallow” regarding the depth of potential is changed to “deep”. You can replace “deep” with “shallow”.

≪5. Third Embodiment >>
(Example of electronic equipment using solid-state image sensor)
The solid-state imaging device according to the present technology described in the above-described embodiments is used for electronic devices such as a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or another device having an imaging function. The solid-state imaging device can be provided.

  FIG. 15 is a configuration diagram of a camera using a solid-state image sensor as an example of an electronic apparatus according to the present technology. The camera according to the present embodiment is an example of a video camera capable of capturing still images or moving images. The camera 91 includes a solid-state imaging device 1, an optical system 93 that guides incident light to a light receiving sensor unit of the solid-state imaging device 1, a shutter device 94, a drive circuit 95 that drives the solid-state imaging device 1, and the solid-state imaging device 1. And a signal processing circuit 96 for processing the output signal.

  The solid-state imaging device 1 includes a pixel configured using the solid-state imaging device having the configuration described in the above-described embodiment and modification. The optical system (optical lens) 93 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 1. A plurality of pixels are arranged on the imaging surface, and incident light from the optical system 93 is guided to the photoelectric conversion region of the solid-state imaging device constituting the pixels. As a result, signal charges are accumulated in the photoelectric conversion region of the solid-state imaging device 1 for a certain period. Such an optical system 93 may be an optical lens system including a plurality of optical lenses. The shutter device 94 controls the light irradiation period and the light shielding period to the solid-state imaging device 1. The drive circuit 95 supplies drive signals to the solid-state imaging device 1 and the shutter device 94, and controls the signal output operation to the signal processing circuit 96 of the solid-state imaging device 1 and the shutter device by the supplied drive signal (timing signal). 94 shutter operation is controlled. That is, the drive circuit 95 performs a signal transfer operation from the solid-state imaging device 1 to the signal processing circuit 96 by supplying a drive signal (timing signal). The signal processing circuit 96 performs various signal processing on the signal transferred from the solid-state imaging device 1. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  According to the electronic device according to the present embodiment described above, by providing the solid-state imaging device with good imaging characteristics shown in the above-described embodiments and modifications, high-definition imaging in an electronic device having an imaging function can be performed. Can be achieved.

  In addition, this technique can also take the following structures.

(1)
A readout gate embedded through a gate insulating film in a trench formed in a semiconductor substrate;
A photoelectric conversion region provided inside the semiconductor substrate;
A floating diffusion provided in a surface layer of the semiconductor substrate with a gap between the photoelectric conversion region and
An impurity region having the same conductivity type as the semiconductor substrate and the photoelectric conversion region and having a concentration of the conductivity type lower than that of the semiconductor substrate and the photoelectric conversion region, the photoelectric conversion region and the gate insulating film being A solid-state imaging device having a potential adjustment region disposed in contact therewith.

(2)
The potential adjustment region is provided at the same depth position as the photoelectric conversion region. (1).

(3)
A plurality of the photoelectric conversion regions are stacked in the depth direction inside the semiconductor substrate,
The potential adjustment region is provided in contact with a photoelectric conversion region farthest from the floating diffusion among the plurality of photoelectric conversion regions. (1) or (2).

(4)
The solid-state imaging device according to (3), wherein among the plurality of photoelectric conversion regions, the photoelectric conversion region provided in contact with the potential adjustment region is a photoelectric conversion region for red light.

(5)
The solid-state imaging device according to any one of (1) to (4), wherein the readout gate is disposed in a trench provided through the semiconductor substrate.

(6)
The solid-state imaging device according to any one of (1) to (5), wherein the floating diffusion is disposed on a light receiving surface side with respect to the photoelectric conversion region in the semiconductor substrate.

(7)
The solid-state imaging device according to any one of (1) to (6), wherein the semiconductor substrate is configured with the same conductivity type as the photoelectric conversion region and the floating diffusion.

(8)
Inside the semiconductor substrate, a pinning region having a conductivity type opposite to the photoelectric conversion region is provided along the side wall of the trench,
The overlapping region in which the potential adjustment region and the pinning region overlap each other includes an impurity that constitutes the potential adjustment region and an impurity that constitutes the pinning region together (1) to (7) Image sensor.

(9)
The solid-state imaging device according to (8), wherein a part of the potential adjustment region is disposed so as to overlap the pinning region.

(10)
By introducing impurities into the semiconductor substrate, a photoelectric conversion region is formed inside the semiconductor substrate, and the same conductivity type as the semiconductor substrate and the photoelectric conversion region, and more than the semiconductor substrate and the photoelectric conversion region. Forming a potential adjustment region having a low conductivity type concentration in contact with the photoelectric conversion region;
Forming a trench in the semiconductor substrate in contact with the potential adjustment region;
Forming a read gate in the trench through a gate insulating film;
A method of manufacturing a solid-state imaging device, comprising introducing an impurity into the surface layer of the semiconductor substrate to form a floating diffusion in the surface layer of the semiconductor substrate in the vicinity of the readout gate.

(11)
The method for manufacturing a solid-state imaging device according to (10), wherein the trench is formed through the semiconductor substrate.

(12)
After forming the trench and before forming the gate insulating film and the readout gate, impurities are introduced into the semiconductor substrate from the inner wall of the trench, thereby the photoelectric conversion region along the inner wall of the trench. A method of manufacturing a solid-state imaging device according to (10) or (11), wherein a pinning region of reverse conductivity type is formed.

(13)
In forming the pinning region, the pinning region is overlapped with a part of the potential adjustment region.

(14)
A readout gate embedded through a gate insulating film in a trench formed in a semiconductor substrate;
A photoelectric conversion region provided inside the semiconductor substrate;
A floating diffusion provided in a surface layer of the semiconductor substrate with a gap between the photoelectric conversion region and
An impurity region having the same conductivity type as the semiconductor substrate and the photoelectric conversion region and having a concentration of the conductivity type lower than that of the semiconductor substrate and the photoelectric conversion region, the photoelectric conversion region and the gate insulating film being A potential adjustment region disposed in contact with each other;
An electronic apparatus comprising: an optical system that guides incident light to the photoelectric conversion region.

1-1, 1-2, 1a, 1b, 1c ... Solid-state imaging device, 13 ... Semiconductor substrate, 15r, 15g, 15b ... Photoelectric conversion region, 17r ... Trench (through), 17r '... Trench, 17g ... Trench, 17g '... trench (through), 19 ... gate insulating film, 21r, 21g ... read gate (embedded electrode), 21b ... read gate, 23 ... floating diffusion, 25r, 25g ... potential adjustment region, 31 ... pinning region, 31' ... Overlapping area, 91 ... Electronic equipment, 93 ... Optical system, A ... Light receiving surface

Claims (14)

A readout gate embedded through a gate insulating film in a trench formed in a semiconductor substrate;
A photoelectric conversion region provided inside the semiconductor substrate;
A floating diffusion provided in a surface layer of the semiconductor substrate with a gap between the photoelectric conversion region and
An impurity region having the same conductivity type as the semiconductor substrate and the photoelectric conversion region and having a concentration of the conductivity type lower than that of the semiconductor substrate and the photoelectric conversion region, the photoelectric conversion region and the gate insulating film being A solid-state imaging device having a potential adjustment region disposed in contact therewith. The solid-state imaging device according to claim 1, wherein the potential adjustment region is provided at the same depth as the photoelectric conversion region. A plurality of the photoelectric conversion regions are stacked in the depth direction inside the semiconductor substrate,
The solid-state imaging device according to claim 1, wherein the potential adjustment region is provided in contact with a photoelectric conversion region located farthest from the floating diffusion among the plurality of photoelectric conversion regions. The solid-state imaging device according to claim 3, wherein among the plurality of photoelectric conversion regions, the photoelectric conversion region provided in contact with the potential adjustment region is a photoelectric conversion region for red light. The solid-state imaging device according to claim 1, wherein the readout gate is disposed in a trench provided penetrating through the semiconductor substrate. The solid-state imaging device according to claim 1, wherein the floating diffusion is disposed on a light receiving surface side of the semiconductor substrate with respect to the photoelectric conversion region. The solid-state imaging device according to claim 1, wherein the semiconductor substrate is configured with the same conductivity type as the photoelectric conversion region and the floating diffusion. Inside the semiconductor substrate, a pinning region having a conductivity type opposite to the photoelectric conversion region is provided along the side wall of the trench,
The solid-state imaging device according to claim 1, wherein the overlapping region where the potential adjustment region and the pinning region overlap includes an impurity constituting the potential adjustment region and an impurity constituting the pinning region. The solid-state imaging device according to claim 8, wherein a part of the potential adjustment region is disposed so as to overlap the pinning region. By introducing impurities into the semiconductor substrate, a photoelectric conversion region is formed inside the semiconductor substrate, and the same conductivity type as the semiconductor substrate and the photoelectric conversion region, and more than the semiconductor substrate and the photoelectric conversion region. Forming a potential adjustment region having a low conductivity type concentration in contact with the photoelectric conversion region;
Forming a trench in the semiconductor substrate in contact with the potential adjustment region;
Forming a read gate in the trench through a gate insulating film;
A method of manufacturing a solid-state imaging device, comprising introducing an impurity into the surface layer of the semiconductor substrate to form a floating diffusion in the surface layer of the semiconductor substrate in the vicinity of the readout gate. The method for manufacturing a solid-state imaging device according to claim 10, wherein the trench is formed through the semiconductor substrate. After forming the trench and before forming the gate insulating film and the readout gate, impurities are introduced into the semiconductor substrate from the inner wall of the trench, thereby the photoelectric conversion region along the inner wall of the trench. The method for manufacturing a solid-state imaging element according to claim 10, wherein a pinning region of reverse conductivity type is formed. The method for manufacturing a solid-state imaging device according to claim 12, wherein in the formation of the pinning region, the pinning region is overlapped with a part of the potential adjustment region. A readout gate embedded through a gate insulating film in a trench formed in a semiconductor substrate;
A photoelectric conversion region provided inside the semiconductor substrate;
A floating diffusion provided in a surface layer of the semiconductor substrate with a gap between the photoelectric conversion region and
An impurity region having the same conductivity type as the semiconductor substrate and the photoelectric conversion region and having a concentration of the conductivity type lower than that of the semiconductor substrate and the photoelectric conversion region, the photoelectric conversion region and the gate insulating film being A potential adjustment region disposed in contact with each other;
An electronic apparatus comprising: an optical system that guides incident light to the photoelectric conversion region.

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