JP2013021141A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce dispersion of threshold voltages of a MISFET caused by dispersion of orientation of grains forming a metal gate electrode in a MISFET including the metal gate electrode as a part of gate electrodes.SOLUTION: By introducing carbon (C) into metal gate electrodes 4a, 4b, increase in particle size of grains in the metal gate electrodes 4a, 4b is prevented. By forming a great number of small grains in the metal gate electrodes 4a, 4b, orientation of the grains is made even and dispersion of work functions of the gate electrodes is reduced.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a technique effective when applied to the manufacture of a field effect transistor having a metal gate electrode.

  In a MISFET (Metal Insulator Semiconductor Field Effect Transistor) that is required to be miniaturized, a high-k film having a high dielectric constant is used as a part of a gate insulating film, and a part of a gate electrode. By using a metal gate electrode made of a metal material, the gate insulating film of the MISFET can be made thinner and the leakage current can be reduced. Further, it is possible to control the threshold voltage of the MISFET by changing the configuration of the high-k film and the metal gate electrode.

  Patent Document 1 (Japanese Patent Laid-Open No. 2010-109214) describes a technique for relatively easily controlling the work function of a metal gate electrode even when heat treatment is performed after the formation of the gate electrode. However, the purpose of the technique described in Patent Document 1 is to control the value of the work function so that the N-type FET and the P-type FET have different work functions, and not to suppress the work function variation. .

  In Patent Document 2 (Japanese Patent Laid-Open No. 2007-8099), an element having an electronegativity different from that of the elements constituting the gate electrode and the gate insulating film of the transistor, such as carbon (C), fluorine (F), chlorine (Cl ), Phosphorus (P), arsenic (As), or antimony (Sb) is formed to control the effective work function of the gate electrode so that the threshold voltage is optimized. ing. However, the purpose of the technique described in Patent Document 2 is to control the work function and threshold voltage value of the transistor, and not to suppress the work function variation.

  In Patent Document 3 (Japanese Patent Laid-Open No. 2006-245324), a MIS transistor having a gate electrode containing a metal carbon compound such as Ti (titanium) carbide, Ta (tantalum) carbide, or W (tungsten) carbide is formed. It is described.

  In Patent Document 4 (Japanese Patent Laid-Open No. 2004-319722), in a MISFET having a dual polymetal gate electrode in which a metal film is deposited on a silicon film, a metal film (for example, tungsten) is formed by injecting carbon into the metal film. It is described that the impurity is prevented from diffusing and thereby the threshold voltage fluctuation of the MISFET is reduced.

  In Patent Document 5 (Japanese Patent Laid-Open No. 11-224947), variation in threshold voltage of MOS (Metal Oxide Semiconductor) transistors can be prevented by forming a metal gate electrode having a crystal grain size of 30 nm or less. Have been described. Here, variation in threshold voltage of the MOS transistor is suppressed by introducing carbon into the metal gate electrode by sputtering.

JP 2010-109214 A JP 2007-8099 A JP 2006-245324 A JP 2004-319722 A Japanese Patent Laid-Open No. 11-224947

  When the MISFET is miniaturized, the channel region of the MISFET is reduced accordingly, and the number of impurities per unit volume in the channel region is increased as compared with the MISFET having a large channel region. In such a MISFET, since the distribution of impurities in the channel region varies as a whole, the threshold voltage of the MISFET (hereinafter also simply referred to as “threshold” or “Vth”) varies greatly. In contrast, when a high-k film (high dielectric constant film) is used as the gate insulating film of the MISFET and a metal gate electrode (metal electrode) is used as the gate electrode, the number of impurities introduced into the channel region is reduced. Therefore, the number of impurities in the channel region can be reduced and variation in Vth can be suppressed.

  The threshold value of the MISFET including the metal gate electrode and the high-k film is determined by the work function of the metal gate electrode and the material of the high-k film. The metal gate electrode, which is a part of the gate electrode, is composed of a plurality of metal particles, and crystals (grains) constituting each of the plurality of metal particles have different crystal orientations (orientations) even if they are adjacent grains. ). Here, when electrons pass through grains having different orientations, the work functions are different for each grain.

  In the MISFET in which the size of the gate electrode is reduced, there may be a case where the metal gate electrode is constituted by a small number of large grains having different orientations. In this case, for example, there is a high possibility that the work function is greatly different between the end of the metal gate electrode and the end on the opposite side. That is, since the work function varies depending on the location even within one metal gate electrode, the work function of the metal gate electrode varies as a whole within the metal gate electrode. The variation in the work function of the metal gate electrode causes the Vth of the MISFET having the metal gate electrode to vary, and thus there is a problem that the merit of configuring the MISFET using the high-k film and the metal gate electrode is impaired. That is, non-uniform material in the metal gate electrode causes variations in the threshold value of the MISFET. Further, when the Vth of the MISFET varies, there is a problem that the reliability of the semiconductor device is lowered and the yield of the product is reduced. These problems greatly hinder the miniaturization of the semiconductor device.

  An object of the present invention is to suppress variation in characteristics of a MISFET having a metal gate electrode.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A semiconductor device according to a preferred embodiment of the present invention includes a first metal gate electrode containing carbon formed on a semiconductor substrate with a first gate insulating film interposed therebetween,
A first channel region of a first conductivity type formed on the main surface of the semiconductor substrate immediately below the first metal gate electrode;
A first source / drain region of a second conductivity type different from the first conductivity type formed so as to sandwich the first channel region on the main surface of the semiconductor substrate;
A first charge effect transistor having

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a metal gate electrode formed in a first region on a semiconductor substrate; a channel region having a first conductivity type; and a second different from the first conductivity type. A method of manufacturing a semiconductor device including a field effect transistor having a source / drain region having a conductivity type,
(A) forming the channel region by implanting an impurity having the first conductivity type into the first region of the main surface of the semiconductor substrate;
(B) sequentially stacking an insulating film and a metal film on the semiconductor substrate;
(C) introducing carbon into the metal film;
(D) After the step (c), processing the metal film to form the metal gate electrode;
(E) implanting the second conductivity type impurity into the main surface of the semiconductor substrate to form the source / drain regions so as to sandwich the channel region;
It is what has.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to a typical embodiment, it is possible to suppress variation in characteristics of a MISFET having a metal gate electrode.

It is sectional drawing of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 4 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 7 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG. 8 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8; FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9; It is sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. FIG. 12 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13; FIG. 15 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 14; It is a top view of the semiconductor device which is Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 3 of this invention. FIG. 18 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; It is sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 4 of this invention. FIG. 20 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 19; It is sectional drawing of the semiconductor device shown as a comparative example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
This embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a CMISFET (Complementary MISFET) according to the present embodiment. A CMISFET (hereinafter simply referred to as “CMIS”) shown in FIG. 1 is an element formed on an SOC (System on a chip) semiconductor chip, for example. In FIG. 1, illustration of a laminated structure including plugs, interlayer insulating films, wirings, and the like that are higher than the semiconductor element formed on the main surface of the semiconductor substrate is omitted.

  As shown in FIG. 1, the CMIS of the present embodiment is formed on the main surface of the semiconductor substrate Sb and is divided into a plurality of regions by a plurality of element isolation regions 1 formed on the main surface of the semiconductor substrate Sb. ing. That is, the main surface of the semiconductor substrate Sb includes a region where an N-channel MISFET (N-type MISFET Qn) and a P-channel MISFET (P-type MISFET Qp) are formed.

  The N-type MISFET Qn includes a gate electrode formed on a P well 1P formed by introducing a P-type impurity (for example, B (boron)) into the main surface of the semiconductor substrate Sb via a gate insulating film 3a, and a gate electrode Extension regions 6a and diffusion layers 9a constituting source / drain regions formed by introducing N-type impurities (for example, As (arsenic)) into the main surface of the lateral semiconductor substrate Sb. The gate electrode of the N-type MISFET Qn is a polysilicon gate made of a metal gate electrode (metal gate electrode) 4a formed on the gate insulating film 3a and polysilicon (polycrystalline silicon) formed in contact with the metal gate electrode 4a. It consists of an electrode 5.

  The extension region 6a is formed on the main surface of the semiconductor substrate Sb so as to sandwich the channel region 2a on the upper surface of the P well 1P immediately below the gate electrode, and the diffusion layer 9a sandwiches the region including the channel region 2a and the extension region 6a. Are arranged as follows. The diffusion layer 9a is an N-type semiconductor region having a junction depth deeper than that of the extension region 6a and a higher impurity concentration than that of the extension region 6a. That is, the diffusion layer 9a is formed by introducing an N-type impurity (for example, As (arsenic)) deeper from the main surface of the semiconductor substrate Sb to the back surface direction of the semiconductor substrate Sb than the extension region 6a. . The P well 1P is a P-type semiconductor region having a junction depth deeper than that of the diffusion layer 9a and a relatively low impurity concentration.

  A halo region 7a in which boron (B) is introduced into a region where the junction depth is deeper than the extension region 6a and shallower than the diffusion layer 9a is formed in the semiconductor substrate Sb and on the upper surface of the P well 1P. Yes. The halo region 7a is a semiconductor region formed to prevent generation of a leak current between the source and drain, and is formed by implanting impurities of a conductivity type different from that of the source / drain region into the semiconductor substrate Sb. The halo region 7a is formed from the main surface of the semiconductor substrate Sb to the vicinity of the junction between the P well 1P and the extension region 6a.

  The gate insulating film 3a is an insulating film including a high dielectric constant film (high-k film) having a dielectric constant higher than that of a silicon oxide film or the like. Although not shown, a gate insulating film made of a silicon oxide film may be interposed between the gate insulating film 3a and the semiconductor substrate Sb.

  Similar to the N-type MISFET Qn, the P-type MISFET Qp is formed via the gate insulating film 3b on the N well 1N formed by introducing an N-type impurity (for example, As (arsenic)) into the main surface of the semiconductor substrate Sb. And the extension region 6b and the diffusion layer 9b constituting the source / drain region formed by introducing a P-type impurity (for example, B (boron)) into the main surface of the semiconductor substrate Sb. Yes. The extension region 6b and the diffusion layer 9b constitute a source / drain region of the P-type MISFET Qp. Similar to the diffusion layer 9a and the extension region 6a, the extension region 6b is formed so as to sandwich the channel region 2b of the P-type MISFET Qp. A diffusion layer 9b is formed so as to sandwich region 2b and extension region 6b. The channel region 2b is formed immediately below the gate electrode including the metal gate electrode 4b. The gate electrode of the P-type MISFET Qp includes a metal gate electrode (metal gate electrode) 4b formed on the gate insulating film 3b and a polysilicon gate electrode 5 made of polysilicon formed on the metal gate electrode 4b.

  Further, a halo region 7b in which boron (B) is introduced into a region where the junction depth is deeper than the extension region 6b and shallower than the diffusion layer 9b is formed in the semiconductor substrate Sb and on the upper surface of the N well 1N. Yes. The halo region 7b is a semiconductor region formed to prevent the occurrence of a leak current between the source and drain, and is formed by implanting impurities of a conductivity type different from that of the source / drain region into the semiconductor substrate Sb. The halo region 7b is formed from the main surface of the semiconductor substrate Sb to the vicinity of the junction between the N well 1N and the extension region 6b.

  The gate insulating film 3b is an insulating film including a high dielectric constant film (high-k film) having a dielectric constant higher than that of a silicon oxide film or the like. Although not shown, a gate insulating film made of a silicon oxide film may be interposed between the gate insulating film 3b and the semiconductor substrate Sb.

  The metal gate electrodes 4a and 4b are metal films made of, for example, titanium nitride, tungsten nitride, or nickel silicide. A sidewall 8 made of a silicon oxide film, a silicon nitride film, or a laminated film thereof is formed on the sidewall of the laminated pattern composed of the polysilicon gate electrode 5, the metal gate electrode 4a, and the gate insulating film 3a. A sidewall 8 made of a silicon oxide film, a silicon nitride film, or a laminated film thereof is also formed on the sidewall of the laminated pattern composed of the polysilicon gate electrode 5, the metal gate electrode 4b, and the gate insulating film 3b. .

  Here, carbon (C) is implanted into the metal gate electrodes 4a and 4b which are metal gate electrodes by an ion implantation method. However, carbon is not implanted into the polysilicon gate electrode 5, the gate insulating films 3a and 3b, and the semiconductor substrate Sb. That is, carbon is injected only into the metal gate electrode 4a in the N-type MISFET Qn, and carbon is injected only into the metal gate electrode 4b in the P-type MISFET Qp.

  Next, the effect of the semiconductor device of this embodiment will be described.

  A MISFET having a narrow channel region due to miniaturization of a semiconductor device contains a large number of impurities in a relatively narrow channel region. As the width of the channel region, that is, the distance between the extension regions constituting the source / drain regions, decreases, the number of impurities per unit volume in the channel region increases and the distribution of impurities in the channel region tends to vary. . In a MISFET including a large number of impurities in a narrow channel region, there is a problem that variation in threshold value (Vth) increases due to variation in the distribution of impurities in the channel region. When a large number of MISFETs are formed in a semiconductor device, a phenomenon in which threshold values (Vth) are greatly different also occurs between adjacent MISFETs. Therefore, there is a problem in that the yield of a product having a semiconductor device including those MISFETs decreases. is there.

  MISFET uses a metal material for the gate electrode to reduce power consumption while maintaining performance, and suppresses gate depletion, and a material having a high dielectric constant for the gate insulating film (high-k film) ) Can be used to ensure the physical gate insulating film thickness without changing the electrical capacitance film thickness. Further, since the threshold value can be controlled by the work function of the metal material layer (metal gate electrode) used for the gate electrode, the amount of impurities introduced into the channel region can be reduced. That is, since the threshold value of the MISFET can be reduced by reducing the work function of the gate electrode using the metal gate electrode, the MISFET can be driven even if the amount of impurities introduced into the channel region is small. . The number of impurities in the channel region can be reduced in the MISFET using the metal gate electrode and the high-k film as compared with the MISFET having a structure using only the polycrystalline silicon for the gate electrode and only the silicon oxide film for the gate insulating film. Therefore, it is possible to greatly reduce variations caused by the dispersion of impurities in the channel region.

  However, even a MISFET having a metal gate electrode has a problem that the threshold value of the MISFET varies due to the large grain size of the grains (crystals) constituting the metal gate electrode. The existence of such a problem becomes a big barrier for miniaturization of semiconductor devices, and unless this is solved, it will be difficult to manufacture a product with high integration and low cost in the future.

  As described above, a cross-sectional view of a MISFET in the case where the grain size is large is shown in FIG. 21 as a comparative example. The N-type MISFET Qx shown in FIG. 21 has substantially the same structure as the N-type MISFET Qn shown in FIG. 1. However, unlike the N-type MISFET Qn, carbon (C) is introduced into the metal gate electrode 4x of the N-type MISFET Qx. It has not been. In FIG. 21, the grains constituting the metal gate electrode 4x are shown, and the orientation (orientation) of the crystal of the grains is indicated by an arrow in each grain. As shown in FIG. 21, the crystal orientation of each grain is not constant. Here, when the grain size of the grain of the metal gate electrode 4x is large, for example, when the diameter or radius of the grain is larger than the film thickness of the metal gate electrode 4x, that is, one of the grains in the metal gate electrode 4x. The case where the lower surface and the upper surface of the grain are exposed on the lower surface and the upper surface of the metal gate electrode 4x is shown.

  The work function of the metal gate electrode 4x varies depending on the grain orientation, and the variation in the work function of the gate electrode has the property of varying the threshold value of the MISFET. Therefore, since the work function has a different value for each grain, the metal gate electrode 4x composed of a plurality of grains having a large grain size is in a state in which the work function differs between a part inside and another part.

  On the other hand, in this embodiment, since carbon is introduced into the metal gate electrodes 4a and 4b, the size of the grains constituting each of the metal gate electrodes 4a and 4b is reduced as shown in FIG. Yes. FIG. 2 is a cross-sectional view showing the same region as in FIG. 1, but shows the shape of the grains constituting each of the metal gate electrodes 4a and 4b.

  As shown in FIG. 2, the grain size in the metal gate electrodes 4a and 4b constituting the MISFET of the present embodiment is the grain size in the metal gate electrode 4x constituting the N-type MISFET Qx in FIG. Smaller than That is, the average grain size of the grains in the metal gate electrodes 4a and 4b is smaller than the average grain size of the grains in the metal gate electrode 4x as a comparative example. Therefore, when the metal gate electrodes shown in FIGS. 2 and 21 have substantially the same film thickness, the metal gate electrodes 4a and 4b shown in FIG. 2 are more than the metal gate electrode 4x shown in FIG. The number of grains in the metal gate electrode increases. Such a difference is caused by introducing carbon into the metal gate electrodes 4a and 4b in FIG. 2 to prevent the grains from growing greatly during a heat load or the like. The grain particle size referred to here refers to the largest distance among the linear distances connecting the two ends of each grain.

  Even in the MISFET of this embodiment shown in FIG. 2, the plurality of grains constituting the metal gate electrodes 4a and 4b have different orientations, and the work functions are different for each grain. However, since the number of grains in the metal gate electrode 4a and the metal gate electrode 4b is increased by keeping the grain size of the grains small, the variation in grain crystal orientation is averaged in the metal gate electrode as a whole. It becomes. Therefore, it is possible to avoid that the work function differs between a part of the metal gate electrode and another part of the metal gate electrode. In addition, it is possible to prevent the threshold voltage from varying between the MISFETs due to the work functions of the gate electrodes being greatly different between the MISFETs formed in a plurality in the semiconductor device.

  As described above, in the semiconductor device of the present embodiment, by introducing carbon into the metal gate electrode of the MISFET, the grain size of the grains constituting the metal gate electrode is reduced and the number of grains in the metal gate electrode is reduced. Increasing. Thereby, since the grain orientation is averaged, it is possible to suppress variation in work function due to variation in grain orientation. As a result, it is possible to prevent the threshold voltage of the MISFET from varying due to the variation in the work function of the gate electrode, so that the reliability of the semiconductor device can be improved. Further, since variations in the threshold value of the MISFET can be suppressed, the MISFET can be easily miniaturized and the performance of the semiconductor device can be improved.

  Next, a method for manufacturing the CMISFET that constitutes the semiconductor device of the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 3, a photolithography technique, a dry etching method, a film forming process, a CMP (Chemical Mechanical Polishing) method is performed on a semiconductor substrate Sb on which a surface protective film (not shown) is formed on the main surface. Is used to form an element isolation region 1 having a shallow groove element isolation structure. Here, the main surface of the semiconductor substrate Sb is divided into a plurality of regions by a plurality of element isolation regions 1 formed on the main surface of the semiconductor substrate Sb. That is, the main surface of the semiconductor substrate Sb has an N-type MISFET formation region 1A and a P-type MISFET formation region 1B.

  Next, as shown in FIG. 4, the main surface of the semiconductor substrate Sb in the N-type MISFET formation region 1A below the opening of the resist film formed on the semiconductor substrate Sb is formed by using a photolithography technique and an ion implantation method. Then, the P well 1P having a relatively large junction depth is formed. Similarly, an N well 1N having a relatively deep junction depth is formed on the main surface of the semiconductor substrate Sb in the P-type MISFET formation region 1B.

  The P well 1P is formed by ion implantation of a P-type impurity (for example, boron (B)) into the main surface of the semiconductor substrate Sb. At this time, by using the resist film as a mask, P-type impurities are prevented from being implanted into the main surface of the semiconductor substrate Sb in the P-type MISFET formation region 1B. The N well 1N is formed by ion-implanting N-type impurities (for example, arsenic (As) or phosphorus (P)) into the main surface of the semiconductor substrate Sb. At this time, the resist film is used as a mask so that N-type impurities are not implanted into the main surface of the semiconductor substrate Sb in the N-type MISFET formation region 1A. In this way, the P well 1P and the N well 1N are divided, but either the P well 1P or the N well 1N may be formed first.

  Next, as shown in FIG. 5, after the surface of the semiconductor substrate Sb is cleaned, the insulating film 3 and the metal film 4 are sequentially formed. The insulating film 3 is a high-k film (high dielectric constant film) containing, for example, Hf (hafnium) having a dielectric constant higher than that of the silicon oxide film. Here, in order to set the respective threshold values of the N-type MISFET and the P-type MISFET formed in a later step to the target values, the N-type MISFET formation region 1A and the P-type MISFET formation region 1B The material may be different. In that case, for example, films made of different members are arranged on the insulating film 3 in the N-type MISFET forming region 1A and the P-type MISFET forming region 1B, respectively, and heat treatment is performed in that state to perform the heat treatment on the insulating films 3 and 3. It is conceivable to react with the other film.

  The metal film 4 is made of, for example, titanium nitride, tungsten nitride, or nickel silicide, and is formed on the entire surface of the semiconductor substrate Sb by sputtering or the like after the insulating film 3 is formed. Here, in order to facilitate the patterning of the gate electrode by a later dry etching method, the metal film 4 is formed with a thickness of 20 to 50 nm.

After the metal film 4 is formed, carbon (C) is introduced into the metal film 4 by ion implantation of carbon (C) from above the main surface of the semiconductor substrate Sb. Here, the acceleration energy of ion implantation is 10 to 50 keV, the implantation amount is 10 ¹⁴ to 10 ¹⁶ cm ⁻² , and the projection range is set to exist in the metal film 4. The projection range is the depth at which the injected material has penetrated from the solid surface. That is, the projection range refers to the distance in the depth direction where ions implanted by ion implantation are implanted from the upper surface of the target to be ion implanted. That is, in the above step of implanting carbon into the metal film 4, carbon is implanted only into the metal film 4, and carbon is not implanted into the insulating film 3 and the semiconductor substrate Sb.

  Next, as shown in FIG. 6, a polysilicon film SF into which phosphorus (P) is introduced at a high concentration is formed on the metal film 4 using a CVD (Chemical Vapor Deposition) method or the like.

  Next, as shown in FIG. 7, the polysilicon film SF, the metal film 4, and the insulating film 3 are patterned using a photolithography technique and a dry etching method, so that the N-type MISFET formation region 1 </ b> A is formed from the polysilicon film SF. A gate electrode including the polysilicon gate electrode 5 and the metal gate electrode 4 a made of the metal film 4 is formed, and a gate insulating film 3 a made of the insulating film 3 is formed. Further, a gate electrode including the polysilicon gate electrode 5 made of the polysilicon film SF and the metal gate electrode 4b made of the metal film 4 is formed in the P-type MISFET formation region 1B by the same patterning process, and the gate made of the insulating film 3 is formed. An insulating film 3b is formed.

Next, as shown in FIG. 8, a resist film (not shown) that exposes the N-type MISFET formation region 1A is formed on the semiconductor substrate Sb, and is a low concentration N-type impurity on the main surface of the semiconductor substrate Sb. By implanting arsenic ions with an energy of 10 keV and an implantation amount of 1 × 10 ¹⁵ cm ⁻² , an extension region 6a which is an N ⁻ region having a junction depth shallower than that of the P well 1P is formed. Subsequently, boron ions, which are P-type impurities, are implanted into the main surface of the semiconductor substrate Sb in the N-type MISFET formation region 1A with an energy of 10 keV and an implantation amount of 2 × 10 ¹³ cm ^{−2 using} the resist film as a mask. The halo region 7a is formed in substantially the same region as the extension region 6a. The halo region 7a is a P-type semiconductor region having a junction depth deeper than that of the extension region 6a and shallower than that of the P well 1P.

Similarly, a resist film (not shown) that exposes the P-type MISFET formation region 1B is formed on the semiconductor substrate Sb, and boron fluoride ions that are P-type impurities at a low concentration are formed on the main surface of the semiconductor substrate Sb at 5 keV. The extension region 6b which is a P ⁻ region having a junction depth shallower than that of the N well 1N is formed by implanting with an energy and an implantation amount of 1 × 10 ¹⁵ cm ⁻² . Subsequently, using the resist film as a mask, arsenic, which is an N-type impurity, is implanted into the main surface of the semiconductor substrate Sb in the P-type MISFET formation region 1B with an energy of 70 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² , or By implanting phosphorus ions with an energy of 30 keV and an injection amount of 2 × 10 ¹³ cm ⁻² , a halo region 7 b is formed in substantially the same region as the extension region 6 b. The halo region 7b is an N-type semiconductor region having a junction depth deeper than that of the extension region 6b and shallower than that of the N well 1N.

  Here, the angle of the ion beam incident on the main surface of the semiconductor substrate Sb is set at the time of ion implantation for forming the extension regions 6a and 6b, which are source / drain regions, and at the time of ion implantation for forming the halo regions 7a and 7b. By tilting, the overlap between the gate electrode and the impurity-added layer, that is, the extension region and the halo region can be adjusted. Further, as in the ion implantation step described with reference to FIG. 4, either one of the extension regions 6a and 6b may be formed first.

  Next, as shown in FIG. 9, after the surface of the semiconductor substrate Sb is cleaned, an N-type MISFET formation region 1A (see FIG. 8) and a P-type MISFET formation region 1B (see FIG. 8) are formed using film formation and dry etching. 8), sidewalls 8 made of an insulating film are formed in a self-aligned manner on the respective sidewalls of the gate electrode.

Thereafter, a resist film (not shown) that exposes the N-type MISFET formation region 1A is formed on the semiconductor substrate Sb, and arsenic ions that are N-type impurities at a high concentration on the main surface of the semiconductor substrate Sb have an energy of 70 keV, 1 By implanting with an implantation amount of × 10 ¹⁶ cm ⁻² , a diffusion layer 9a is formed which is an N ⁺ region having a junction depth shallower than that of the P well 1P and deeper than that of the extension region 6a and the halo region 7a. .

Similarly, a resist film (not shown) that exposes the P-type MISFET formation region 1B is formed on the semiconductor substrate Sb, and boron ions that are P-type impurities at a high concentration on the main surface of the semiconductor substrate Sb have an energy of 30 keV, By implanting with an implantation amount of 1 × 10 ¹⁵ cm ⁻² , a diffusion layer 9b which is a P ⁺ region having a junction depth shallower than the N well 1N and deeper than the extension region 6b and the halo region 7b is formed. To do. Either the diffusion layer 9a or the diffusion layer 9b may be formed first.

  Thus, in the N-type MISFET formation region 1A (see FIG. 8), the gate electrode including the metal gate electrode 4a and the polysilicon gate electrode 5 formed on the P well 1P via the gate insulating film 3a, the source An N-type MISFET Qn having an extension region 6a constituting the drain region and a diffusion layer 9a is formed. In the P-type MISFET formation region 1B (see FIG. 8), a gate electrode composed of a metal gate electrode 4b and a polysilicon gate electrode 5 formed on the N well 1N via a gate insulating film 3b, and source / drain regions are provided. A P-type MISFET Qp having the extension region 6b and the diffusion layer 9b to be formed is formed.

  Thereafter, heat treatment is performed to activate the impurities introduced to form impurity diffusion layers such as extension regions 6a and 6b and diffusion layers 9a and 9b. In this heat treatment step, spike annealing is performed at 1050 ° C. in a nitrogen atmosphere in order to suppress diffusion of the introduced impurities. In addition to spike annealing, it is also possible to use instantaneous thermal annealing, flash annealing, annealing using a furnace body, or the like. As described with reference to FIG. 5, when carbon (C) is not implanted into the metal film 4 serving as the metal gate electrode, when the semiconductor substrate becomes high temperature by the heat treatment as described above, the grains constituting the metal gate electrode rapidly As a result of the growth, the grain size of the grains in the metal gate electrode increases as in the comparative example shown in FIG. On the other hand, in the manufacturing process of the semiconductor device of the present embodiment, by introducing carbon (C) into the metal film 4 (see FIG. 5) to be the metal gate electrodes 4a and 4b, the metal gate electrode 4a, The growth rate of the grains constituting 4b can be reduced. For this reason, the grain size of the grains constituting the metal gate electrodes 4a and 4b in the completed semiconductor device can be reduced, and the metal gate electrodes 4a and 4b can be constituted by more grains.

  Since the present invention relates to impurities introduced onto the semiconductor substrate Sb, detailed description of the subsequent steps will be omitted. After the above steps, the semiconductor device shown in FIG. Complete. That is, after obtaining the structure shown in FIG. 9, a metal silicide region is formed in a region where a contact plug is to be formed. That is, the silicide layer 10 containing, for example, nickel (Ni) or the like is formed on the surface of the polysilicon gate electrode 5 where the semiconductor film is exposed and the surface of the source / drain region of each MISFET. At this time, high-temperature annealing (heat treatment) is performed for the purpose of reacting the metal film and silicon of the semiconductor substrate Sb in order to form the silicide layer 10.

  Subsequently, an interlayer insulating film 11 is formed by depositing a silicon nitride film and an insulating film on the semiconductor substrate Sb, and then the upper surface of the interlayer insulating film 11 is planarized by a CMP method or the like. Thereafter, using a well-known technique, a contact plug 12 penetrating the interlayer insulating film 11 and electrically connected to the source / drain region of each transistor is formed, and an interlayer is formed on the interlayer insulating film 11. An insulating film 13 is formed. Subsequently, after forming a wiring groove in the interlayer insulating film 13, a wiring 14 for embedding the wiring groove is formed by using a well-known single damascene process, thereby completing the semiconductor device shown in FIG.

  In the present embodiment, in the manufacturing process of a semiconductor device having a MISFET including a metal gate electrode in the gate electrode, carbon (C) is introduced into each of the metal gate electrodes 4a and 4b, whereby the metal gate electrodes 4a and 4b are introduced. The grain size of the grains (crystals) constituting the metal gate electrodes 4a and 4b is prevented from being increased by the heat treatment process after the formation of the film. Thereby, the metal gate electrodes 4a and 4b are smaller than the case where carbon is not introduced, and contain more grains. As described above, since the grain orientation can be made uniform if the number of grains constituting the metal gate electrode is large, the occurrence of work function variations due to the grain orientation can be suppressed. As a result, variations in the work function of the gate electrode can be suppressed, so that the threshold voltage (Vth) of the MISFET including the gate electrode can be prevented from varying.

  As described above, in this embodiment, variation in the threshold value of the MISFET can be suppressed by implanting carbon (C) into the metal gate electrode constituting the MISFET by ion implantation. Therefore, the yield of semiconductor products including the MISFET is increased. Can be improved.

  In addition, since the threshold voltage of the MISFET can be prevented from varying due to the variation in work function of the gate electrode as described above, the reliability of the semiconductor device can be improved. In addition, since variation in the threshold value of the MISFET can be suppressed, the MISFET can be easily miniaturized and the performance of the semiconductor device can be improved.

(Embodiment 2)
In the above-described embodiment, the semiconductor device in which carbon is implanted into all the metal films to be the metal gate electrodes in the subsequent process has been described. In this embodiment, details of a manufacturing process for realizing a semiconductor device including the MISFET having a metal gate electrode in which carbon is not implanted depending on a region will be described with reference to FIGS. . Here, as an example, a process of forming a MISFET constituting an SRAM (Static Random Access Memory) will be described.

  First, the structure shown in FIG. 11 is obtained by performing the same processes as those described in Embodiment 1 with reference to FIGS. Here, an N-type MISFT formation region 2A, a P-type MISFET formation region 2B, an N-type MISFT formation region 2C, and a P-type MISFET formation region 2D exist on the semiconductor substrate Sb. That is, as shown in FIG. 11, a plurality of element isolation regions 1 are formed on the main surface of the semiconductor substrate Sb, and the main surface of the semiconductor substrate Sb is formed of the N-type MISFT formation region 2A and the P-type by the element isolation region 1. The region is divided into a MISFET formation region 2B, an N-type MISFT formation region 2C, and a P-type MISFET formation region 2D. A P well 1P is formed on the main surface of the semiconductor substrate Sb in the N-type MISFT formation region 2A and the N-type MISFT formation region 2C, and the main surface of the semiconductor substrate Sb in the P-type MISFET formation region 2B and the P-type MISFET formation region 2D. An N well 1N is formed on the surface.

  Here, the N-type MISFT formation region 2A is a region where an N-type MISFET constituting an input / output circuit corresponding to a high voltage is formed, and the P-type MISFET formation region 2B is a P constituting an input / output circuit corresponding to a high voltage. This is a region for forming a type MISFET. The N-type MISFT formation region 2C is a region for forming a low breakdown voltage N-type MISFET, and the P-type MISFET formation region 2D is a region for forming a low breakdown voltage P-type MISFET.

  Next, as shown in FIG. 12, insulating films 23a, 23b, 23c and 23d which are high-k films (high dielectric constant insulating films) are formed. At this time, different materials are used for the high-k film for the N-type and P-type of the MISFET in order to match the threshold value of each MISFET to be formed in a later process. Further, since the insulating films 23a and 23b in the N-type MISFT formation region 2A and the P-type MISFET formation region 2B, which are high breakdown voltage regions, become gate insulating films to which a high voltage is applied, the film thickness is increased to, for example, about 7 nm. The film thickness of the insulating films 23a and 23b is adjusted by the voltage corresponding to the input. In FIG. 12, the thicknesses of the insulating films 23a, 23b, 23c, and 23d are represented by the same size. Subsequently, a metal film 24 is formed on the main surface of the semiconductor substrate Sb.

Next, as shown in FIG. 13, the N-type MISFT formation region 2A and the P-type MISFET formation region 2B are covered with the resist film PR1 and exposed from the resist film PR1 by the photolithography technique. Carbon ions are added by ion implantation to the metal film 24 in the N-type MISFT formation region 2C and the P-type MISFET formation region 2D to form a metal film 24s made of the metal film 24. At this time, the ion implantation of carbon (C) is set so that the acceleration energy is 10 to 50 keV, the implantation amount is 10 ¹⁴ to 10 ¹⁶ cm ⁻² , and the projected range is present in the metal film. That is, carbon (C) is implanted only into the metal film 24 exposed from the resist film PR1, and carbon (C) is prevented from being introduced into structures below the metal film 24.

  Next, as shown in FIG. 14, after removing the resist film PR1 and depositing a polysilicon film to which phosphorus is added at a high concentration, patterning of the gate is performed using a photolithography technique and a dry etching method. Thus, a gate electrode including the polysilicon gate electrode 5 made of the polysilicon film and the metal gate electrode 24a made of the metal film 24 is formed in the N-type MISFT formation region 2A, and the P-type MISFET formation region 2B is formed. A gate electrode including the polysilicon gate electrode 5 made of the polysilicon film and the metal gate electrode 24b made of the metal film 24 is formed. A gate electrode including a polysilicon gate electrode 5 made of the polysilicon film and a metal gate electrode 24c made of a metal film 24s is formed in the N-type MISFT formation region 2C, and the P-type MISFET formation region 2D A gate electrode including a polysilicon gate electrode 5 made of a polysilicon film and a metal gate electrode 24d made of a metal film 24s is formed. The metal gate electrodes 24a, 24b, 24c and 24d are formed on the semiconductor substrate Sb via gate insulating films 25a, 25b, 25c and 25d, respectively. Gate insulating films 25a, 25b, 25c and 25d are high-k films made of insulating films 23a, 23b, 23c and 23d, respectively. Since the gate electrode is used for the high-breakdown-voltage MISFET of the N-type MISFT formation region 2A and the P-type MISFET formation region 2B, the gate electrode is higher than the gate electrodes of the N-type MISFT formation region 2C and the P-type MISFET formation region 2D. A long pattern is used.

Subsequent steps are the same as those described with reference to FIGS. 8 to 10 in the first embodiment, whereby the semiconductor device of the present embodiment shown in FIG. 15 is completed. That is, the extension region and the halo region are formed by using a resist film (not shown) to divide impurities into the main surfaces of the semiconductor substrates Sb of the N-type MISFT formation regions 2A and 2C and the P-type MISFET formation regions 2B and 2D. Form. In other words, boron fluoride ions are implanted into the P-type ISEFT formation regions 2B and 2D under the conditions of, for example, an energy of 5 keV and an implantation amount of 1 × 10 ¹⁵ cm ⁻² to form a P ⁻ -type extension region 26b. For example, ions are implanted under conditions of an energy of 70 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² , or phosphorus ions are implanted at an energy of 30 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² to form the halo region 27b. . Similarly, arsenic ions are implanted into the N-type MISFT formation regions 2A and 2C under the conditions of an energy of 10 keV and an implantation amount of 1 × 10 ¹⁵ cm ⁻² to form an N ⁻ -type extension region 26a. For example, ions are implanted under the conditions of an energy of 10 keV and an implantation amount of 2 × 10 ¹³ cm ⁻² to form the halo region 27a.

Thereafter, sidewalls 8 are formed on the side walls of each gate electrode, and then diffusion layers 29a and 29b for contact are formed using a resist film (not shown). Here, the N ⁺ -type diffusion layer 9a is formed by implanting arsenic ions under the conditions of an energy of 70 keV and an injection amount of 1 × 10 ¹⁵ cm ⁻² , and the P ⁺ -type diffusion layer 9b is formed by using boron ions as energy. It is formed by ion implantation under the conditions of 30 keV and implantation amount of 1 × 10 ¹⁵ cm ⁻² . Thereafter, after cleaning the main surface of the semiconductor substrate Sb, heat treatment for activating the impurities introduced into the diffusion layer or the like is performed. As a result, the N-type MISFET Qa and the P-type MISFET Qb, which are relatively high breakdown voltage MISFETs, are formed in the N-type MISFET formation region 2A and the P-type MISFET formation region 2B, respectively. The N-type MISFET formation region 2C and the P-type MISFET formation In the region 2D, an N-type MISFET Qc and a P-type MISFET Qd, which are MISFETs having a relatively low breakdown voltage, are formed. Subsequently, in the same manner as in the first embodiment, after the silicide layer 10 is formed in the region where the silicon surface is exposed, the interlayer insulating film 11, the contact plug 12, the interlayer insulating film 13, and the wiring 14 are formed.

  A plan view of the SRAM including the MISFET of the present embodiment formed as described above is shown in FIG. The semiconductor device including the SRAM shown in FIG. 16 has a storage area SR mainly having a function of storing information and an input / output area IO for performing information input / output operation. N-type MISFT formation region 2C and P-type MISFET formation region 2D are formed, and in the input / output region IO, N-type MISFTQa and P-type MISFET formation region Qb, which are high-voltage MISFETs shown in FIG. Is formed.

  The semiconductor device according to the present embodiment is characterized in that carbon (C) is injected only into the metal gate electrode of a low-breakdown-voltage MISFET that is particularly required to suppress variations in threshold voltage, and a high-breakdown-voltage MISFET that constitutes the peripheral circuit portion. This is because carbon is not implanted into the metal gate electrode. As a result, the same effect as in the first embodiment can be obtained for the low breakdown voltage MISFET. In addition, by implanting carbon into the metal gate electrode of a MISFET that does not require carbon implantation, such as a high breakdown voltage MISFET, the wiring resistance of the high breakdown voltage MISFET increases, and it is necessary to redesign the peripheral circuit section. Can be prevented.

  In other words, for example, in an SRAM using an MIS transistor formed with a minimum gate length and gate width design rule, the information write and read margins are improved from the design standard by injecting carbon into the metal gate electrode. The occurrence rate of product defects can be greatly reduced. In the carbon implantation step, the metal gate electrode formation region of the peripheral circuit portion such as the input / output region IO is covered with a resist film to suppress the introduction of impurities (carbon).

  At this time, the average grain size of the plurality of grains constituting the metal gate electrodes 24c and 24d (see FIG. 15) made of the metal film 24s (see FIG. 13) in which carbon is introduced is the metal film in which carbon is not introduced. This is smaller than the average grain size of a plurality of grains constituting the metal gate electrodes 24a and 24b (see FIG. 15) made of 24 (see FIG. 13). That is, the metal gate electrode in the peripheral circuit portion has a larger grain than the memory cell portion, but an increase in wiring resistance can be suppressed. Therefore, it is not necessary to redesign the peripheral circuit portion, and only the memory cell portion needs to be redesigned. Therefore, it is possible to provide an SOC product with a low margin defect rate in a short period.

(Embodiment 3)
In the present embodiment, details of a manufacturing process of a semiconductor device that realizes the second embodiment of the present invention will be described with reference to FIGS. Here, a manufacturing process substantially similar to that of the second embodiment will be described, but carbon is implanted into a target metal gate electrode in a different region between the present embodiment and the second embodiment. Here, description will be made assuming that an SOC is formed as the semiconductor device of the present embodiment.

  First, steps similar to those described in the second embodiment with reference to FIGS. 11 and 12 are performed. However, as shown in FIG. 17, an N-type MISFT formation region 3A, a P-type MISFET formation region 3B, an N-type MISFT formation region 3C, and a P-type MISFET formation region 3D exist on the main surface of the semiconductor substrate Sb. A P well 1P is formed on the main surface of the semiconductor substrate Sb of the N-type MISFT formation region 3A and the N-type MISFT formation region 3C, and the main surface of the semiconductor substrate Sb of the P-type MISFET formation region 3B and the P-type MISFET formation region 3D. An N well 1N is formed on the surface. Further, a high-k film (high dielectric constant insulating film) is formed on the main surface of the semiconductor substrate Sb of the N-type MISFT formation region 3A, P-type MISFET formation region 3B, N-type MISFT formation region 3C, and P-type MISFET formation region 3D. Insulating films 23a, 23b, 23c and 23d are formed. A metal film 24 is formed on the insulating films 23a, 23b, 23c and 23d.

  Here, the N-type MISFT formation region 3A is a region where a high-voltage N-type MISFET is formed, and the P-type MISFET formation region 2B is a region where a high-voltage P-type MISFET is formed. The N-type MISFT formation region 2C is a region for forming a low breakdown voltage N-type MISFET, and the P-type MISFET formation region 2D is a region for forming a low breakdown voltage P-type MISFET.

Next, as shown in FIG. 17, the P-type MISFET formation regions 3B and 3D are covered with a resist film PR2 by photolithography, and the metal film 24 in the N-type MISFT formation regions 3A and 3D exposed from the resist film PR2 is formed. Carbon ions are added by ion implantation to form a metal film 34 s made of the metal film 24. At this time, the ion implantation of carbon (C) is set so that the acceleration energy is 10 to 50 keV, the implantation amount is 10 ¹⁴ to 10 ¹⁶ cm ⁻² , and the projected range is present in the metal film. That is, carbon (C) is implanted only into the metal film 24 and carbon (C) is prevented from being introduced into structures below the metal film 24. The semiconductor device of the present embodiment is characterized in that carbon is implanted only into the metal film constituting the N-type MISFET formed in the subsequent process as described above. Here, a method of injecting carbon only into the metal gate electrode of the N-type MISFET will be described, but conversely, carbon may be injected only into the metal gate electrode of the P-type MISFET.

  Next, as shown in FIG. 18, after removing the resist film PR2, the steps described with reference to FIGS. 14 to 15 are performed to complete the semiconductor device of the present embodiment. That is, a polysilicon film is formed on the metal films 24 and 34s, and patterning is performed to form a gate electrode. At this time, a metal gate electrode 34a made of a metal film 34s is formed on the gate insulating film 25a made of the insulating film 23a in the N-type MISFT forming region 3A, and a gate insulating film made of the insulating film 23b is formed in the P-type MISFET forming region 3B. A metal gate electrode 34b made of the metal film 24 is formed on the film 25b. Further, a metal gate electrode 34c made of a metal film 34s is formed on the gate insulating film 25c made of the insulating film 23c in the N-type MISFT forming region 3C, and a gate insulating film made of the insulating film 23d is formed in the P-type MISFET forming region 3D. A metal gate electrode 34d made of the metal film 24 is formed on 25d.

  Thereafter, an extension region, a halo region, a sidewall, a diffusion layer, a silicide layer, an interlayer insulating film, a contact plug, a wiring, and the like of each MISFET formation region are formed, thereby completing the semiconductor device of the present embodiment shown in FIG. To do.

  The feature of the semiconductor device of this embodiment is that an impurity (carbon) is added only to the metal gate electrode of the MISFET, in which the variation in threshold value is particularly large when carbon (C) is not introduced into the metal gate electrode. By suppressing the increase in grain size, it is possible to suppress the work function variation due to the grain orientation in the metal gate and to reduce the threshold variation of the MISFET.

  Further, impurities are prevented from being introduced by masking the peripheral circuit portion and the metal gate electrode that does not require countermeasures by carbon implantation with a resist film or the like in the carbon implantation process. As a result, in the MISFET having a metal gate electrode into which carbon (C) is not introduced, an increase in wiring resistance can be suppressed. Therefore, it is not necessary to redesign the peripheral circuit portion, and it is possible to provide an SOC product with a low margin defect rate in a short period of time. That is, for example, the gate electrode of the P-type MISFET formation region 3D (see FIG. 17) shown in FIG. 18 is not a gate electrode that functions as a part of the MISFET, but for supplying a specific potential to the gate electrode of another MISFET. In the case of a conductor portion that functions as a wiring, it is not necessary to introduce carbon (C) for the purpose of preventing variation in threshold value even for a gate wiring that does not function as a MISFET. Therefore, by preventing carbon (C) from being implanted into the gate wiring including the metal gate electrode, it is possible to prevent the wiring resistance of the gate wiring from increasing.

  Thus, carbon (C) is not introduced into all metal gate electrodes, but carbon (C) is classified according to the characteristics and roles of the gate electrodes, thereby preventing an increase in wiring resistance. it can. Similarly, by performing carbon (C) separation, it is possible to save the trouble of redesigning the peripheral circuit portion, and thus it is possible to prevent an increase in manufacturing cost of the semiconductor device.

(Embodiment 4)
The semiconductor device according to the present embodiment has substantially the same structure as that of the semiconductor device according to the first embodiment, and impurities introduced into the metal gate electrode for the purpose of reducing the variation in threshold value of the MISFET are made of substances other than carbon. A semiconductor device will be described.

  In the manufacturing process of the semiconductor device according to the present embodiment, the process described with reference to FIG. 4 in the first embodiment is first performed.

Next, as shown in FIG. 19, the insulating film 3 and the metal film 4u are sequentially formed on the semiconductor substrate Sb in the same manner as described with reference to FIG. Subsequently, impurities are ion-implanted into the metal film 4u. Unlike the first to third embodiments, fluorine (F), which is a halogen element, is used as an impurity for suppressing the growth of grains constituting the metal film 4u. Ion implantation of chlorine (Cl) or nitrogen (N) which is an inert element. At this time, it is important to adjust the acceleration energy within the range of 10 to 100 keV by the ions to be implanted so that the ion-implanted element does not leak into the insulating film 3 and the semiconductor substrate Sb. The amount of the impurity added is about 1 × 10 ¹⁵ cm ⁻² .

  The subsequent steps are the same as those described in Embodiment Mode 1 with reference to FIGS. 6 to 10, whereby the semiconductor device shown in FIG. 20 is completed. The semiconductor device shown in FIG. 20 has substantially the same structure as the semiconductor device shown in FIG. 10, but the impurity species introduced into the metal gate electrode is different from that of the first embodiment. The metal film 4u (see FIG. 19) in the N-type MISFET formation region 1A and the P-type MISFET formation region 1B is patterned to form metal gate electrodes 4p and 4q, respectively.

  In the semiconductor device of the present embodiment, it is possible to suppress an increase in the grain size of the metal gate electrode of the MISFET. As a result, the work function variation due to the grain orientation in the metal gate electrode can be suppressed, and the threshold value of the MISFET can be suppressed. The variation can be reduced, and the same effect as in the first embodiment can be obtained. Thus, in order to suppress the threshold variation of the MISFET, the element implanted into the metal gate electrode may be fluorine (F), chlorine (Cl), or nitrogen (N) in addition to carbon (C).

  As mentioned above, the invention made by the present inventors has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the fourth embodiment, the effect of the present invention is obtained by introducing fluorine (F), chlorine (Cl), or nitrogen (N) into the metal gate electrode, but the second embodiment or the third embodiment. Even in the semiconductor device described in the above, by introducing fluorine (F), chlorine (Cl), or nitrogen (N) into the metal gate electrode, the same effects as those in Embodiment 2 or Embodiment 3 can be obtained. it can.

  The present invention is effective when applied to a manufacturing technique of a semiconductor device including a MISFET having a metal gate electrode.

1 Element isolation region 1A, 2A, 2C, 3A, 3CA N-type MISFET formation region 1B, 2B, 2D, 3B, 3D P-type MISFET formation region 1N N well 1P P well 2a, 2b Channel region 3 Insulating film 3a, 3b Gate Insulating film 4, 4u Metal film 4a, 4b, 4p, 4q, 4x Metal gate electrode 5 Polysilicon gate electrode 6a, 6b Extension region 7a, 7b Halo region 8 Side wall 9a, 9b, 29a, 29b Diffusion layer 10 Silicide layer 11 , 13 Interlayer insulating film 12 Contact plug 14 Wirings 23a-23d Insulating films 24, 24s, 34s Metal films 24a-24d, 34a-34d Metal gate electrodes 25a-25d Gate insulating films 26a, 26b Extension regions 27a, 27b Halo region IO input Output region PR1, PR2 cash register Doo film Qa, Qc, Qn, Qx N-type MISFET
Qb, Qd, Qp P-type MISFET
SF Polysilicon film SR Storage area Sb Semiconductor substrate

Claims (20)

A first metal gate electrode containing carbon formed on a semiconductor substrate via a first gate insulating film;
A first channel region of a first conductivity type formed on the main surface of the semiconductor substrate immediately below the first metal gate electrode;
A first source / drain region of a second conductivity type different from the first conductivity type formed so as to sandwich the first channel region on the main surface of the semiconductor substrate;
A semiconductor device comprising: a first charge-effect transistor having:   2. The semiconductor device according to claim 1, wherein the first gate insulating film includes a high dielectric constant film having a dielectric constant higher than that of the silicon oxide film.   2. The semiconductor device according to claim 1, wherein, of the semiconductor substrate, the first gate insulating film, and the first metal gate electrode, only the first metal gate electrode is introduced with carbon.   2. The semiconductor device according to claim 1, wherein a polysilicon gate electrode is formed on the first metal gate electrode in contact with the first metal gate electrode.   The semiconductor device according to claim 1, wherein the first metal gate electrode includes titanium nitride, tungsten nitride, or nickel silicide. A second metal gate electrode formed on the semiconductor substrate via a second gate insulating film;
A second channel region formed in the main surface of the semiconductor substrate immediately below the second metal gate electrode;
A second source / drain region formed so as to sandwich the second channel region on the main surface of the semiconductor substrate;
A second field effect transistor having
2. The semiconductor device according to claim 1, wherein, of the first metal gate electrode and the second metal gate electrode, only the first metal gate electrode is introduced with carbon.   7. The semiconductor according to claim 6, wherein an average grain size of the plurality of grains constituting the first metal gate electrode is smaller than an average grain size of the plurality of grains constituting the second metal gate electrode. apparatus. A first metal gate electrode containing a halogen element formed on a semiconductor substrate via a first gate insulating film;
A first channel region of a first conductivity type formed on the main surface of the semiconductor substrate immediately below the first metal gate electrode;
A first source / drain region of a second conductivity type different from the first conductivity type formed so as to sandwich the first channel region on the main surface of the semiconductor substrate;
A semiconductor device comprising: a first charge-effect transistor having:   9. The semiconductor device according to claim 8, wherein the halogen element is fluorine or chlorine. A first metal gate electrode including an inert element formed on a semiconductor substrate via a first gate insulating film;
A first channel region of a first conductivity type formed on the main surface of the semiconductor substrate immediately below the first metal gate electrode;
A first source / drain region of a second conductivity type different from the first conductivity type formed so as to sandwich the first channel region on the main surface of the semiconductor substrate;
A semiconductor device comprising: a first charge-effect transistor having:   The semiconductor device according to claim 10, wherein the inert element is nitrogen. A semiconductor device including a metal gate electrode formed in a first region on a semiconductor substrate, a channel region having a first conductivity type, and a field effect transistor having a source / drain region having a second conductivity type different from the first conductivity type A manufacturing method of
(A) forming the channel region by implanting an impurity having the first conductivity type into the first region of the main surface of the semiconductor substrate;
(B) sequentially stacking an insulating film and a metal film on the semiconductor substrate;
(C) introducing carbon into the metal film;
(D) After the step (c), processing the metal film to form the metal gate electrode;
(E) implanting the second conductivity type impurity into the main surface of the semiconductor substrate to form the source / drain regions so as to sandwich the channel region;
A method for manufacturing a semiconductor device, comprising:   13. The method of manufacturing a semiconductor device according to claim 12, wherein in the step (c), carbon is implanted into the metal film using an ion implantation method.   13. The method of manufacturing a semiconductor device according to claim 12, wherein in the step (c), carbon is introduced only into the metal film. (C1) before the step (c), further comprising a step of covering the upper surface of the metal film in a second region different from the first region with a mask,
13. The semiconductor device according to claim 12, wherein in the step (c), carbon is implanted into only part of the metal film exposed from the mask by implanting carbon into the metal film from above the mask. Production method.   The average grain size of the grains constituting the metal gate electrode made of the metal film in the first region into which carbon has been implanted in the step (c) is the same as that of the metal film in the second region into which carbon has not been implanted. 16. The method of manufacturing a semiconductor device according to claim 15, wherein the grain size is smaller than an average grain size of the grains. A semiconductor device including a metal gate electrode formed in a first region on a semiconductor substrate, a channel region having a first conductivity type, and a field effect transistor having a source / drain region having a second conductivity type different from the first conductivity type A manufacturing method of
(A) forming the channel region by implanting an impurity having the first conductivity type into the first region of the main surface of the semiconductor substrate;
(B) sequentially stacking an insulating film and a metal film on the semiconductor substrate;
(C) introducing a halogen element into the metal film;
(D) After the step (c), processing the metal film to form the metal gate electrode;
(E) implanting the second conductivity type impurity into the main surface of the semiconductor substrate to form the source / drain regions so as to sandwich the channel region;
A method for manufacturing a semiconductor device, comprising: The halogen element is fluorine or chlorine;
18. The method of manufacturing a semiconductor device according to claim 17, wherein in the step (c), the halogen element is implanted into the metal film by using an ion implantation method. A semiconductor device including a metal gate electrode formed in a first region on a semiconductor substrate, a channel region having a first conductivity type, and a field effect transistor having a source / drain region having a second conductivity type different from the first conductivity type A manufacturing method of
(A) forming the channel region by implanting an impurity having the first conductivity type into the first region of the main surface of the semiconductor substrate;
(B) sequentially stacking an insulating film and a metal film on the semiconductor substrate;
(C) introducing an inert element into the metal film;
(D) After the step (c), processing the metal film to form the metal gate electrode;
(E) implanting the second conductivity type impurity into the main surface of the semiconductor substrate to form the source / drain regions so as to sandwich the channel region;
A method for manufacturing a semiconductor device, comprising: The inert element is nitrogen;
20. The method of manufacturing a semiconductor device according to claim 19, wherein in the step (c), the inert element is implanted into the metal film by using an ion implantation method.

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