JP2013005227A - Solid state image sensor, camera, and drive method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high S/N ratio and a large saturation charge amount at the same time in a solid state image sensor using charge transfer elements and a camera.SOLUTION: In the output part of floating diffusion layer type of a charge transfer element, two floating diffusion layers 7, 10 and two reset gates 9, 11 are alternately disposed in series, so that when the two reset gates 9, 11 are driven, two kinds of detection capacities, large and small, are realized. This results in two signals being synthesized from one signal charge by reading it out as signal with large and small detection capacities. Furthermore, the respective signals are processed in correlative double sampling circuits 18, 19.

Description

  The present invention relates to a solid-state imaging device, a camera, and a driving method thereof. In particular, the present invention relates to a solid-state image pickup device using a charge transfer device such as a CCD that achieves both a high S / N ratio (signal-to-noise ratio) and a large charge handling amount, a camera using the solid-state image pickup device, and a driving method thereof. Is.

  The floating diffusion layer method is mainly used in the output part of a charge transfer element such as a CCD. In the floating diffusion layer method, the transferred signal charge is accumulated in the floating diffusion layer. This potential change is output as a signal by the source follower amplifier connected to the floating diffusion layer. A detection capacitor for converting the signal charge into a voltage is defined as a C farad. The detection capacitance includes a capacitance of the floating diffusion layer, an input capacitance of the source follower amplifier, and a parasitic capacitance such as a wiring. If the charge amount of the signal charge is Q coulomb, the potential of the floating diffusion layer, that is, the potential of the detection capacitor changes by Q / C volts.

  Although the floating diffusion layer method is said to have low noise, noise components are reset noise generated when resetting the floating diffusion layer, thermal noise of the source follower amplifier, and 1 / f noise. Reset noise and 1 / f noise can be suppressed by performing correlated double sampling, but thermal noise remains. The S / N ratio of the signal voltage to the thermal noise is proportional to 1 / C. That is, the smaller the detection capacitance C, the higher the signal voltage and the higher the S / N ratio. However, there is a problem that if the detection capacitance C is reduced, the maximum amount of charge handled is reduced. In general, since the input voltage of an analog-digital converter (ADC) is limited to about 1 volt, a signal voltage of 1 volt or more is saturated. In other words, the maximum amount of charge handled is proportional to the detection capacitor C, and there is a drawback that it decreases as the detection capacitor C decreases.

  Therefore, according to a certain conventional technique, the floating diffusion layer is coupled to a single or a plurality of diffusion regions by a single or a plurality of switch elements, and the detection capacitance is changed by appropriately switching these switch elements. Accordingly, a high S / N ratio can be obtained in a dark photographing scene, while a large saturation can be obtained in a bright photographing scene (see Patent Document 1).

JP-A-5-251480

  The technique of the above-mentioned Patent Document 1 has a problem that it is not possible to cope with a part where a dark and high S / N ratio is desired in one shooting scene and a part where a bright and large saturation is desired.

  An object of the present invention is to provide a solid-state imaging device, a camera, and a driving method thereof that can achieve both a high S / N ratio and a large saturation.

  A solid-state imaging device driving method according to a first aspect of the present invention includes a charge transfer element that transfers a signal charge to an output unit, and an amplifier that is provided adjacent to a terminal end of the charge transfer element and that outputs a signal. The connected first floating diffusion layer, the first reset gate provided adjacent to the first floating diffusion layer, and the first reset gate provided adjacent to the opposite side of the first floating diffusion layer. A second floating diffusion layer formed on the second floating diffusion layer adjacent to the opposite side of the first reset gate, and the second floating diffusion layer on the second reset gate. And a reset drain provided adjacent to the opposite side of the solid-state imaging device, wherein the final storage electrode of the charge transfer device is turned on and the first reset gate is turned on at a first time. Level, second The gate gate is set to the on level, the final storage electrode of the charge transfer element is set to the on level, the first reset gate is set to the on level, and the second reset gate is set to the off level at the second time. The final storage electrode of the charge transfer element is set to the on level, the first reset gate is set to the off level set to a channel level deeper than 0 volts, and the second reset gate is set to the off level at the time of The final storage electrode of the charge transfer element is set to an off level at the time, the first reset gate is set to the off level, and the second reset gate is set to an off level, and the final storage electrode of the charge transfer element is set to a fifth time. Are set to an off level, the first reset gate is set to an on level, and the second reset gate is set to an off level. And performing periodically.

  A camera according to a second aspect of the present invention includes a charge transfer element that transfers a signal charge to an output unit, and a first that is provided adjacent to a terminal end of the charge transfer element and connected to an amplifier for signal output. A floating diffusion layer; a first reset gate provided adjacent to the first floating diffusion layer; and a second floating gate provided adjacent to the first reset gate opposite to the first floating diffusion layer. A diffusion layer; a second reset gate provided adjacent to the second floating diffusion layer opposite to the first reset gate; and a second reset gate opposite to the second floating diffusion layer. A solid-state imaging device having a reset drain provided adjacent thereto, and a correlated double sampling circuit to which the output of the amplifier is input.

  According to a third aspect of the present invention, there is provided a camera driving method comprising: a charge transfer element that transfers signal charges to an output unit; and an amplifier that is provided adjacent to a terminal end of the charge transfer element and that outputs a signal. The first floating diffusion layer, the first reset gate provided adjacent to the first floating diffusion layer, and the first reset gate provided adjacent to the opposite side of the first floating diffusion layer. A second floating diffusion layer; a second reset gate provided adjacent to the second floating diffusion layer on a side opposite to the first reset gate; and the second floating diffusion layer on the second reset gate. A method of driving a camera, comprising: a solid-state imaging device having a reset drain provided adjacent to the opposite side; and a correlated double sampling circuit to which an output of the amplifier is input. Final storage of charge transfer device The electrode is set to the on level, the first reset gate is set to the on level, and the second reset gate is set to the on level. At the second time, the final storage electrode of the charge transfer element is set to the on level, and the first reset gate is set to the on level. On level, the second reset gate is set to the off level, the final storage electrode of the charge transfer element is set to the on level at the third time, and the first reset gate is set to the channel level deeper than 0 volt. Level, and the second reset gate is set to an off level, the high gain reset level is output from the amplifier, the high gain reset level is clamped by the correlated double sampling circuit, and the fourth time is The final storage electrode of the charge transfer element is turned off, the first reset gate is turned off, the second Each set gate is set to an off level, the high gain signal level is output from the amplifier, the high gain signal level is sampled by the correlated double sampling circuit, and the final charge transfer element is terminated at a fifth time. The storage electrode is set to the off level, the first reset gate is set to the on level, and the second reset gate is set to the off level. The low gain signal level is output from the amplifier, and the low gain signal level is set to the correlation level. The sampling is performed periodically by the double sampling circuit.

  According to a fourth aspect of the present invention, there is provided a camera according to a first aspect of the present invention, comprising: a charge transfer element that transfers a signal charge to an output unit; A floating diffusion layer; a first reset gate provided adjacent to the first floating diffusion layer; and a second floating gate provided adjacent to the first reset gate opposite to the first floating diffusion layer. A diffusion layer; a second reset gate provided adjacent to the second floating diffusion layer opposite to the first reset gate; and a second reset gate opposite to the second floating diffusion layer. A solid-state imaging device having a reset drain provided adjacent thereto, and first and second correlated double sampling circuits to which outputs of the amplifier are respectively input.

  According to a fifth aspect of the present invention, there is provided a camera driving method comprising: a charge transfer element that transfers signal charges to an output unit; and an amplifier that is provided adjacent to a terminal end of the charge transfer element and that outputs a signal. The first floating diffusion layer, the first reset gate provided adjacent to the first floating diffusion layer, and the first reset gate provided adjacent to the opposite side of the first floating diffusion layer. A second floating diffusion layer; a second reset gate provided adjacent to the second floating diffusion layer on a side opposite to the first reset gate; and the second floating diffusion layer on the second reset gate. A camera driving method comprising: a solid-state imaging device having a reset drain provided adjacent to the opposite side; and first and second correlated double sampling circuits to which outputs of the amplifier are respectively input. At the first time The final storage electrode of the transfer element is set to an on level, the first reset gate is set to an on level, and the second reset gate is set to an on level, and the final storage electrode of the charge transfer element is set to an on level at a second time. The first reset gate is set to the on level, the second reset gate is set to the off level, the low gain reset level is output from the amplifier, and the low gain reset level is clamped by the first correlated double sampling circuit. At the third time, the final storage electrode of the charge transfer element is set to the on level, the first reset gate is set to the off level set to a channel level deeper than 0 volts, and the second reset gate is set to the off level. The reset level for high gain is output from the amplifier, and the reset level for high gain is Clamping is performed by the second correlated double sampling circuit, and at the fourth time, the final storage electrode of the charge transfer element is set to the off level, the first reset gate is set to the off level, and the second reset gate is set to the off level. The signal level for high gain is output from the amplifier, the signal level for high gain is sampled by the second correlated double sampling circuit, and the final storage electrode of the charge transfer element is turned off at a fifth time, The first reset gate is set to the on level, the second reset gate is set to the off level, the low gain signal level is output from the amplifier, and the low gain signal level is sampled by the first correlated double sampling circuit. It is characterized by performing this periodically.

  A solid-state imaging device according to a sixth aspect of the present invention is provided adjacent to a charge transfer element that transfers signal charges to an output unit and a terminal of the charge transfer element, and is connected to an amplifier for signal output A first floating diffusion layer; a first reset gate provided adjacent to the first floating diffusion layer; and a first reset gate provided adjacent to the first reset gate on a side opposite to the first floating diffusion layer. Two floating diffusion layers; a second reset gate provided adjacent to the second floating diffusion layer opposite to the first reset gate; and the second reset gate opposite to the second floating diffusion layer A reset drain provided adjacent to the side, and a capacitor formed of a polysilicon electrode or a metal electrode and connected to the second floating diffusion layer.

  A solid-state imaging device according to a seventh aspect of the present invention is provided with a charge transfer element that transfers a signal charge to an output unit, and is provided adjacent to a terminal end of the charge transfer element, and is connected to an amplifier for signal output A first floating diffusion layer; a first reset gate provided adjacent to the first floating diffusion layer; and a first reset gate provided adjacent to the first reset gate on a side opposite to the first floating diffusion layer. Two floating diffusion layers; a second reset gate provided adjacent to the second floating diffusion layer opposite to the first reset gate; and the second reset gate opposite to the second floating diffusion layer A solid-state imaging device having a reset drain provided adjacent to the side, wherein the channel potential of the first reset gate is shallower than the channel potential of the second reset gate.

  According to the present invention, a solid-state imaging device that achieves both a high S / N ratio and a large saturation even when a part that wants to realize a dark and high S / N ratio and a part that requires a bright and large saturation coexist in one shooting scene. A camera and a driving method thereof can be provided.

1 is a schematic plan view of a solid-state imaging device according to a first embodiment of the present invention. It is a schematic sectional drawing of the solid-state image sensor of FIG. FIG. 2 is a drive timing diagram of the solid-state image sensor of FIG. 1. FIG. 2 is a potential distribution diagram at time t1 of the solid-state imaging device of FIG. FIG. 3 is a potential distribution diagram at time t2 of the solid-state imaging device of FIG. FIG. 3 is a potential distribution diagram at time t3 of the solid-state imaging device of FIG. FIG. 3 is a potential distribution diagram at time t4 of the solid-state imaging device of FIG. FIG. 3 is a potential distribution diagram at time t5 of the solid-state imaging device of FIG. It is a schematic circuit diagram of the camera which concerns on the 2nd Embodiment of this invention. FIG. 10 is a drive timing diagram of the camera of FIG. 9. It is a schematic circuit diagram of the camera which concerns on the 3rd Embodiment of this invention. It is a drive timing diagram of the camera of FIG. It is a schematic plan view of the solid-state image sensor which concerns on the 4th Embodiment of this invention. It is a schematic sectional drawing of the solid-state image sensor of FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<< First Embodiment >>
1 and 2 are a schematic plan view and a schematic cross-sectional view of a CCD output unit of the solid-state imaging device 100 according to the first embodiment of the present invention. A transfer electrode of a two-phase drive CCD from the left side on the main surface of a p-type silicon substrate 1 (or a p-type well provided on an n-type substrate not shown). An output electrode 6 is formed adjacent to the paired H1 electrode 4, the same H2 electrode 5, and the H2 electrode 5 which is the final transfer electrode of the CCD. An n-type first floating diffusion layer 7 is formed adjacent to the output electrode 6. A contact is provided on the first floating diffusion layer 7 and is electrically connected to the source follower amplifier 8. On the right side of the first floating diffusion layer 7, a first reset gate 9, an n-type second floating diffusion layer 10, a second reset gate 11, and an n-type reset drain 12 are formed adjacent to each other. The CCD is a buried type, and an n-type buried channel is provided on the surface of the silicon substrate 1 below the H1 electrode 4, the H2 electrode 5 and the output electrode 6. In order to set the threshold voltage, n-type doped layers are respectively provided on the surface of the silicon substrate 1 below the first reset gate 9 and the second reset gate 11. These are created in the same process as the buried channel.

  FIG. 3 is a drive timing chart of the solid-state imaging device 100 of FIG. 4, 5, 6, 7, and 8 are potential distribution diagrams at times t1, t2, t3, t4, and t5 in the drive timing chart.

  At time t1, as shown in FIG. 4, the H2 electrode 5 is on level and signal charges are accumulated. The first reset gate 9 and the second reset gate 11 are turned on, and the first floating diffusion layer 7, the channel below the first reset gate 9, the second floating diffusion layer 10, and the second reset gate 11 below The channel is the same as the potential of the reset drain 12.

  At time t2, as shown in FIG. 5, the second reset gate 11 is turned off, and the first floating diffusion layer 7, the channel under the first reset gate 9, and the second floating diffusion layer 10 are in a floating state. Become. The total of these capacitances and the input capacitance of the source follower amplifier 8 and parasitic capacitances such as wiring becomes a detection capacitance. This is the reset level when the output of the source follower amplifier 8 at time t2 is a large detection capacitor. At time t5, signal charges are detected with a large detection capacity.

  At time t3, as shown in FIG. 6, the first reset gate 9 is turned off, and the first floating diffusion layer 7 and the second floating diffusion layer 10 are electrically separated from each other. The total capacitance of the capacitance of the first floating diffusion layer 7, the input capacitance of the source follower amplifier 8, and the parasitic capacitance such as wiring becomes a detection capacitance. This is the reset level when the output of the source follower amplifier 8 at time t3 is a small detection capacitor. At time t4, the signal charge is detected with a small detection capacitor.

  At time t4, as shown in FIG. 7, the H2 electrode 5 is turned off, and the signal charge is transferred to the first floating diffusion layer 7 through the output electrode 6. The amount of signal charge stored in the first floating diffusion layer 7 is determined by the off-level channel potential of the first reset gate 9. A rough hatched portion from the upper left to the lower right indicates electrons existing before the signal charge is transferred. A fine hatched portion from the upper right to the lower left indicates the signal charge (electrons) transferred. This is a case where the signal charge amount is smaller than the signal charge amount stored in the first floating diffusion layer 7. In this case, the output of the source follower amplifier 8 is a signal output in the case of a small detection capacity. When the signal charge amount is larger than the signal charge amount stored in the first floating diffusion layer 7, a part of the signal charge flows into the second floating diffusion layer 10 through the off-level channel of the first reset gate 9. The channel potential of the first reset gate 9 is preferably deeper than the channel potential of the output electrode 6. The signal charge (electrons) in this situation is shown by a fine hatched portion from the upper left to the lower right. In this case, the output of the source follower amplifier 8 does not output a signal corresponding to the signal charge amount and becomes a saturated value.

  At time t5, as shown in FIG. 8, the first reset gate 9 is turned on, and the first floating diffusion layer 7, the channel under the first reset gate 9, and the second floating diffusion layer 10 have one capacitance. It becomes. The output of the source follower amplifier 8 is a signal output when the detection capacity is large.

  By periodically repeating the operation from time t1 to time t5, a pair of an output signal having a small detection capacity and an output signal having a large detection capacity can be sequentially obtained.

  In the camera, an output signal from a small detection capacitor and an output signal from a large detection capacitor are combined. For an output signal with a small detection capacity, set the threshold value below the saturation charge amount of the small detection capacity, use the output signal from the small detection capacity up to the threshold value, and increase the detection capacity above the threshold value. Use the output signal from.

<< Second Embodiment >>
FIG. 9 is a schematic circuit diagram of a camera according to the second embodiment of the present invention. The same reference numerals as those in FIG. 2 denote the same components. The output of the source follower amplifier 8 is input to the correlated double sampling circuit 14 and then input to the ADC 15. The correlated double sampling circuit 14 is provided with a sample switch 16 and a clamp switch 17. The reset level clamped via the clamp switch 17 is subtracted from the signal level sampled via the sample switch 16, and the result is output. It is based on the reset level. The output signal of the correlated double sampling circuit 14 is converted into a digital signal by the ADC 15 and goes to a signal processing circuit (not shown).

  FIG. 10 is a drive timing chart of the camera of FIG. The same reference numerals as those in FIG. 3 indicate the same components and meanings. The driving of the clamp switch 17 and the sample switch 16 added to FIG. 3 will be described.

  At time t3, the clamp switch 17 is turned on, and the reset level in the case of a small detection capacitor output from the source follower amplifier 8 is clamped via the clamp switch 17.

  At time t4, the clamp switch 17 is turned off, the sample switch 16 is turned on, and the signal level in the case of a small detection capacitance output from the source follower amplifier 8 is sampled via the sample switch 16. The reset level in the case of the small detection capacitor clamped at the time t3 is subtracted from the signal level in the case of the sampled small detection capacitor, is output from the correlated double sampling circuit 14, and is converted into a digital signal by the ADC 15. .

  At time t5, the sample switch 16 is turned on again, and the signal level in the case of a large detection capacity output from the source follower amplifier 8 is sampled via the sample switch 16. The reset level in the case of the small detection capacitor clamped at the time t3 is subtracted from the signal level in the case of the sampled large detection capacitor, is output from the correlated double sampling circuit 14, and is converted into a digital signal by the ADC 15. .

  The digitized signal in the case of a small detection capacity and the signal in the case of a large detection capacity are synthesized by a signal processing circuit. For an output signal with a small detection capacity, set the threshold value below the saturation charge amount of the small detection capacity, use the output signal from the small detection capacity up to the threshold value, and increase the detection capacity above the threshold value. Use the output signal from.

  Since the signal level from the small detection capacitor performs correlated double sampling based on the reset level from the small detection capacitor, the reset noise and the 1 / f noise of the source follower amplifier 8 are suppressed. On the other hand, since the signal level from the large detection capacitor performs correlated double sampling based on the reset level from the small detection capacitor, the 1 / f noise of the source follower amplifier 8 is suppressed, but the reset noise is sufficiently suppressed. is not. A signal level from a large detection capacity is used when the amount of light is large. When the amount of light is large, the light shot noise increases and becomes larger than the reset noise. For this reason, it is possible to deal with many shooting scenes even if the reset noise is not sufficiently suppressed with respect to the signal level from a large detection capacity.

<< Third Embodiment >>
FIG. 11 is a schematic circuit diagram of a camera according to the third embodiment of the present invention. 2 and 9 indicate the same components. The output of the source follower amplifier 8 is input to two correlated double sampling circuits, that is, a first correlated double sampling circuit 18 and a second correlated double sampling circuit 19, and then to the first ADC 20 and the second ADC 21, respectively. The signal is input and converted into a digital signal, which is not shown, but goes to a signal processing circuit. The first correlated double sampling circuit 18 is provided with a first sample switch 22 and a first clamp switch 24. The second correlated double sampling circuit 19 is provided with a second sample switch 23 and a second clamp switch 25.

  FIG. 12 is a drive timing chart of the camera of FIG. 3 and 10 indicate the same components and meanings. The driving of the first clamp switch 24, the first sample switch 22, the second clamp switch 25, and the second sample switch 23 added to FIG. 3 will be described.

  At time t <b> 2, the first clamp switch 24 is turned on, and the reset level in the case of a large detection capacitance output from the source follower amplifier 8 is clamped via the first clamp switch 24.

  At time t3, the second clamp switch 25 is turned on, and the reset level in the case of a small detection capacitance output from the source follower amplifier 8 is clamped via the second clamp switch 25.

  At time t4, the second sample switch 23 is turned on, and the signal level in the case of a small detection capacity output from the source follower amplifier 8 is sampled via the second sample switch 23. The reset level in the case of the small detection capacitor clamped at time t3 is subtracted from the signal level in the case of the small detection capacitor sampled, and is output from the second correlated double sampling circuit 19, and is converted into a digital signal by the second ADC 21. Converted.

  At time t <b> 5, the first sample switch 22 is turned on, and the signal level in the case of a large detection capacity output from the source follower amplifier 8 is sampled via the first sample switch 22. The reset level in the case of the large detection capacitor clamped at the time t2 is subtracted from the signal level in the case of the large detection capacitor sampled, and is output from the first correlated double sampling circuit 18, and is converted into a digital signal by the first ADC 20. Converted.

  The digitized signal in the case of a small detection capacity and the signal in the case of a large detection capacity are synthesized by a signal processing circuit. For an output signal with a small detection capacity, set the threshold value below the saturation charge amount of the small detection capacity, use the output signal from the small detection capacity up to the threshold value, and increase the detection capacity above the threshold value. Use the output signal from.

  Since the signal level from the small detection capacitor performs correlated double sampling based on the reset level from the small detection capacitor, the reset noise and the 1 / f noise of the source follower amplifier 8 are suppressed. Since the signal level from the large detection capacitor is correlated double sampling based on the reset level from the large detection capacitor, both the reset noise and the 1 / f noise of the source follower amplifier 8 are suppressed. For this reason, an image with a high S / N ratio in which reset noise is suppressed from a dark part of a shooting scene in which a signal from a small detection capacity is used to a bright part in a shooting scene in which a signal from a large detection capacity is used. can get.

<< Fourth Embodiment >>
A small detection capacity is required to be as small as the miniaturization technology allows to achieve a high S / N ratio. On the other hand, it is desirable to set the large detection capacity to several times to 10 times the small detection capacity. For this reason, the capacity of the second floating diffusion layer 10 is required to be large. When the capacitance is increased by increasing the diffusion layer, there are disadvantages that the area is increased and the chip cost is increased, the dark current generated in the second floating diffusion layer 10 is increased, and the reset time constant is increased.

  13 and 14 are a schematic plan view and a schematic cross-sectional view of the CCD output unit of the solid-state imaging device 110 according to the fourth embodiment of the present invention. The same reference numerals as those in FIGS. 1 and 2 denote the same components. An additional capacitor 26 is connected to the second floating diffusion layer 10. The additional capacitor 26 is a capacitor formed of a polysilicon electrode or a metal electrode. A contact hole is provided on the second floating diffusion layer 10, and the second floating diffusion layer 10 and the lower electrode of the additional capacitor 26 are connected through vias. The upper electrode of the additional capacitor 26 is connected to a DC power source or ground.

  In the case of a capacitor formed of a polysilicon electrode or a metal electrode, it can be formed on another circuit, and the capacitor can be divided and the capacitor itself can be formed in multiple layers to reduce the area. Is possible. Further, unlike the diffusion layer capacitance, the dark current does not increase. Furthermore, particularly when a metal electrode is used, the electrical resistance is small, and an increase in time constant at reset can be suppressed.

<< Fifth Embodiment >>
A solid-state imaging device according to a fifth embodiment of the present invention will be described with reference to FIGS. 1 and 2. In the first to fourth embodiments, the channel of the first reset gate 9 and the channel of the second reset gate 11 are formed in the same process and have the same impurity distribution. In the solid-state imaging device 100 of the fifth embodiment, the channel potential of the first reset gate 9 is made shallower than the channel potential of the second reset gate 11.

  The image quality is improved by using a signal with a large S / N ratio and a small detection capacity for as many portions as possible of the shooting scene. For this purpose, it is preferable to increase the saturation of a small detection capacity. For this purpose, the channel potential of the first reset gate 9 is made shallower than the channel potential of the second reset gate 11.

  As described above with reference to the embodiment, according to the present invention, a high S / N ratio can be obtained by using a signal read with a small detection capacity for a dark portion in one shooting scene. Further, for a bright portion, a large saturation can be obtained by using a signal read with a large detection capacity. Further, by using one or two correlated double sampling circuits, a signal with a high S / N ratio in which reset noise and 1 / f noise of the source follower amplifier are suppressed can be obtained.

  The solid-state imaging device can be applied to both an area-type solid-state imaging device in which pixels are arranged in a two-dimensional manner and a linear solid-state imaging device in which pixels are arranged in a one-dimensional manner.

  Various configurations have been proposed for solid-state imaging devices. This can be applied when the charge transfer immediately before the output unit is a CCD or BBD (Bucket Brigade Device). In other words, it can be applied to CCD image sensors such as interline transfer type CCD image sensor, frame transfer type CCD image sensor, FIT type (frame interline transfer type) CCD image sensor, charge sweep device (CSD), charge priming device. (CPD) and BBD image sensor.

1 Silicon substrate 5 Final storage electrode (H2 electrode)
7 first floating diffusion layer 8 source follower amplifier 9 first reset gate 10 second floating diffusion layer 11 second reset gate 12 reset drain 14 correlated double sampling circuit 16 sample switch 17 clamp switch 18 first correlated double sampling circuit 19 Second correlated double sampling circuit 22 First sample switch 23 Second sample switch 24 First clamp switch 25 Second clamp switch 26 Additional capacitance 100, 110 Solid-state imaging device

Claims (7)

A charge transfer element for transferring a signal charge to an output unit; a first floating diffusion layer provided adjacent to a terminal of the charge transfer element and connected to an amplifier for signal output; and the first floating diffusion layer A first reset gate provided adjacent to the first floating gate, a second floating diffusion layer provided adjacent to the first reset gate on a side opposite to the first floating diffusion layer, and a second floating diffusion layer provided on the second floating diffusion layer. A second reset gate provided adjacent to the opposite side of the first reset gate; and a reset drain provided adjacent to the second reset gate opposite to the second floating diffusion layer. A method for driving a solid-state imaging device,
At a first time, the final storage electrode of the charge transfer element is set to on level, the first reset gate is set to on level, and the second reset gate is set to on level,
At a second time, the final storage electrode of the charge transfer element is set to an on level, the first reset gate is set to an on level, and the second reset gate is set to an off level.
At a third time, the final storage electrode of the charge transfer element is set to an on level, the first reset gate is set to an off level set to a channel level deeper than 0 volts, and the second reset gate is set to an off level,
At a fourth time, the final storage electrode of the charge transfer element is set to an off level, the first reset gate is set to the off level, and the second reset gate is set to an off level.
At a fifth time, the final storage electrode of the charge transfer element is set to an off level, the first reset gate is set to an on level, and the second reset gate is set to an off level periodically. A method for driving a solid-state imaging device. A charge transfer element for transferring a signal charge to an output unit; a first floating diffusion layer provided adjacent to a terminal of the charge transfer element and connected to an amplifier for signal output; and the first floating diffusion layer A first reset gate provided adjacent to the first floating gate, a second floating diffusion layer provided adjacent to the first reset gate on a side opposite to the first floating diffusion layer, and a second floating diffusion layer provided on the second floating diffusion layer. A second reset gate provided adjacent to the opposite side of the first reset gate; and a reset drain provided adjacent to the second reset gate opposite to the second floating diffusion layer. A solid-state image sensor;
And a correlated double sampling circuit to which the output of the amplifier is input. A charge transfer element for transferring a signal charge to an output unit; a first floating diffusion layer provided adjacent to a terminal of the charge transfer element and connected to an amplifier for signal output; and the first floating diffusion layer A first reset gate provided adjacent to the first floating gate, a second floating diffusion layer provided adjacent to the first reset gate on a side opposite to the first floating diffusion layer, and a second floating diffusion layer provided on the second floating diffusion layer. A second reset gate provided adjacent to the opposite side of the first reset gate; and a reset drain provided adjacent to the second reset gate opposite to the second floating diffusion layer. A method for driving a camera comprising a solid-state imaging device and a correlated double sampling circuit to which the output of the amplifier is input,
At a first time, the final storage electrode of the charge transfer element is set to on level, the first reset gate is set to on level, and the second reset gate is set to on level,
At a second time, the final storage electrode of the charge transfer element is set to an on level, the first reset gate is set to an on level, and the second reset gate is set to an off level.
At a third time, the final storage electrode of the charge transfer element is set to an on level, the first reset gate is set to an off level set to a channel level deeper than 0 volts, and the second reset gate is set to an off level, The high gain reset level is output from the amplifier, the high gain reset level is clamped by the correlated double sampling circuit,
At a fourth time, the final storage electrode of the charge transfer element is set to the off level, the first reset gate is set to the off level, and the second reset gate is set to the off level, and the high gain signal level is set from the amplifier. Output, and the signal level for high gain is sampled by the correlated double sampling circuit,
At a fifth time, the final storage electrode of the charge transfer element is set to an off level, the first reset gate is set to an on level, and the second reset gate is set to an off level, and a low gain signal level is output from the amplifier. And periodically sampling the low gain signal level with the correlated double sampling circuit. A charge transfer element for transferring a signal charge to an output unit; a first floating diffusion layer provided adjacent to a terminal of the charge transfer element and connected to an amplifier for signal output; and the first floating diffusion layer A first reset gate provided adjacent to the first floating gate, a second floating diffusion layer provided adjacent to the first reset gate on a side opposite to the first floating diffusion layer, and a second floating diffusion layer provided on the second floating diffusion layer. A second reset gate provided adjacent to the opposite side of the first reset gate; and a reset drain provided adjacent to the second reset gate opposite to the second floating diffusion layer. A solid-state image sensor;
A camera, comprising: first and second correlated double sampling circuits to which outputs of the amplifier are respectively input. A charge transfer element for transferring a signal charge to an output unit; a first floating diffusion layer provided adjacent to a terminal of the charge transfer element and connected to an amplifier for signal output; and the first floating diffusion layer A first reset gate provided adjacent to the first floating gate, a second floating diffusion layer provided adjacent to the first reset gate on a side opposite to the first floating diffusion layer, and a second floating diffusion layer provided on the second floating diffusion layer. A second reset gate provided adjacent to the opposite side of the first reset gate; and a reset drain provided adjacent to the second reset gate opposite to the second floating diffusion layer. A camera driving method comprising: a solid-state imaging device; and first and second correlated double sampling circuits to which outputs of the amplifier are input,
At a first time, the final storage electrode of the charge transfer element is set to on level, the first reset gate is set to on level, and the second reset gate is set to on level,
At a second time, the final storage electrode of the charge transfer element is set to an on level, the first reset gate is set to an on level, and the second reset gate is set to an off level, and a low gain reset level is output from the amplifier. The low gain reset level is clamped by the first correlated double sampling circuit,
At a third time, the final storage electrode of the charge transfer element is set to an on level, the first reset gate is set to an off level set to a channel level deeper than 0 volts, and the second reset gate is set to an off level, A high gain reset level is output from the amplifier, and the high gain reset level is clamped by the second correlated double sampling circuit;
At a fourth time, the final storage electrode of the charge transfer element is set to the off level, the first reset gate is set to the off level, and the second reset gate is set to the off level, and the high gain signal level is set from the amplifier. And output the high gain signal level by the second correlated double sampling circuit,
At a fifth time, the final storage electrode of the charge transfer element is set to an off level, the first reset gate is set to an on level, and the second reset gate is set to an off level, and a low gain signal level is output from the amplifier. And periodically sampling the low gain signal level with the first correlated double sampling circuit. A charge transfer element for transferring signal charges to the output unit;
A first floating diffusion layer provided adjacent to a terminal end of the charge transfer element and connected to an amplifier for signal output;
A first reset gate provided adjacent to the first floating diffusion layer;
A second floating diffusion layer provided adjacent to the first reset gate on a side opposite to the first floating diffusion layer;
A second reset gate provided on the second floating diffusion layer adjacent to the opposite side of the first reset gate;
A reset drain provided adjacent to the second reset gate opposite to the second floating diffusion layer;
A solid-state imaging device comprising a capacitor formed of a polysilicon electrode or a metal electrode and connected to the second floating diffusion layer. A charge transfer element for transferring a signal charge to an output unit; a first floating diffusion layer provided adjacent to a terminal of the charge transfer element and connected to an amplifier for signal output; and the first floating diffusion layer A first reset gate provided adjacent to the first floating gate, a second floating diffusion layer provided adjacent to the first reset gate on a side opposite to the first floating diffusion layer, and a second floating diffusion layer provided on the second floating diffusion layer. A second reset gate provided adjacent to the opposite side of the first reset gate; and a reset drain provided adjacent to the second reset gate opposite to the second floating diffusion layer. A solid-state imaging device,
A solid-state imaging device, wherein a channel potential of the first reset gate is shallower than a channel potential of the second reset gate.

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