JP2011199534A - Driving method of ccd solid-state imaging element, and image-pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an imaged picture signal having high S/N by shortening an electron multiplication drive time.SOLUTION: The signal charges corresponding to the amount of received light are read in a charge transfer path. A potential well 3, which is deeper than a potential well 1 on the charge transfer path where signal charges are accumulated, is formed on the charge transfer path via a potential barrier wall 4. The signal charge in the potential well 1 is dropped into the potential well 3 by making the potential barrier wall 4 disappear. At the same time, at least one continuous electron multiplying potential well 5 whose depth is identical to that of the potential well 3, is formed on the charge transfer path via a potential barrier wall 6, before the completion of driving of electron multiplication. The depth of the potential well 3 is restored to the depth of the potential well 1, after completion of driving of the electron multiplication, and then the potential barrier wall 6 is caused to continuously disappear so that the signal charge in the potential well 3 is dropped into the continuous electron multiplying potential well 5 for electron multiplication.

Description

  The present invention relates to a CCD (Charge Coupled Device) type solid-state imaging device driving method and imaging apparatus that perform electron multiplication driving on a charge transfer path.

  In recent CCD type solid-state imaging devices, the number of mounted pixels usually exceeds 10 million pixels, and each pixel is miniaturized, and the amount of signal charge that can be detected by one pixel is reduced.

  If the amount of signal charge is small, the signal may be amplified by an amplifier at the latter stage of the image sensor. However, the amplification by the amplifier also amplifies the noise component, so the S / N cannot be increased. Therefore, as described in Patent Documents 1 and 2 below, signal charges are multiplied by electrons on the charge transfer path, and amplified by the amount of signal charges.

  FIG. 10 is an explanatory diagram of conventional electron multiplication driving. By applying a vertical transfer pulse as shown in FIG. 10A to the transfer electrode of the vertical charge transfer path, a potential well as shown in FIG. 10B is formed.

  In FIG. 10, the signal charge 2 to be amplified is accumulated in the potential well 1 below the electrodes V2 and V3 at time t0. When a high voltage is applied to the electrode V5 that is two electrodes ahead at time t1, a deep potential well 3 is formed under the electrode V5. Therefore, when the potential barrier 4 under the electrode V4 disappears at time t4, the signal charge 2 in the potential well 1 falls into the deep potential well 3, and an electron multiplication phenomenon occurs.

  Since the electron multiplication factor amplified by one electron multiplication drive is as small as, for example, “1.01”, the electron multiplication drive is repeated 50 times and 100 times. Even if the electronic image magnification of one time is 1.01, it is 2.7 times if it is repeated 100 times. FIG. 10B shows an example in which the electron multiplication drive is continuously performed twice, and this operation is repeated 50 times.

  In order to perform the electron multiplication drive on the charge transfer path, it is necessary to leave the signal charge on the charge transfer path for such a long time. However, if the signal charge accumulated in the potential well is kept on the charge transfer path for a long time, the dark current (noise component) increases and the S / N deteriorates. Therefore, the time for performing the electron multiplication drive is made as short as possible. There is a request to do.

  The deep potential well 3 shown in FIG. 10B is not formed at the moment when a high voltage is applied to the electrode V5. As shown in FIG. 11, even if a high voltage is applied to the electrode V5 at time t1, the deep potential well 3 shown in FIG. The deep potential well 3 is not formed unless a certain amount of time elapses from time t2 to t3. This is the “waiting period before multiplication” described at the bottom of FIG. 10A, which is a time required for forming a deep potential well, and is an obstacle to shortening the electron multiplication driving time.

Japanese Patent Laid-Open No. 7-176721 JP 2007-325181 A

  An object of the present invention is to provide a driving method and an imaging apparatus for a CCD solid-state imaging device capable of shortening the electron multiplication driving time and obtaining a high S / N captured image signal.

  According to the driving method of the CCD solid-state imaging device of the present invention, the signal charge corresponding to the amount of received light is read out to the charge transfer path, and the second potential well deeper than the first potential well on the charge transfer path where the signal charge is accumulated. Is formed on the charge transfer path through a potential barrier, the signal charge in the first potential well is dropped into the second potential well by eliminating the potential barrier, and electron multiplication is performed. Before the completion of the electron multiplication driving, at least one continuous electron multiplication potential well having the same depth as the second potential well is formed on the charge transfer path through the potential barrier, and the electron multiplication driving is finished. After the depth of the second potential well is returned to the depth of the first potential well later, the potential barrier between the second potential well and the potential well for continuous electron multiplication is continuously formed. The signal charge in the second potential well is eliminated and the signal charge is And performing electron multiplication plunge to continue photomultiplier for potential in the well.

  An image pickup apparatus according to the present invention includes a CCD solid-state image pickup device, and a control unit that applies a pulse voltage to the CCD solid-state image pickup device by the driving method described above to form the potential well and eliminate the potential barrier. It is characterized by that.

  According to the present invention, since the electron multiplication drive time can be shortened, a high S / N captured image signal can be obtained.

1 is a functional block diagram of a digital camera (imaging device) according to a first embodiment of the present invention. It is a surface schematic diagram of the CCD type solid-state imaging device shown in FIG. It is explanatory drawing of the electron multiplication drive method which concerns on 1st Embodiment of this invention. It is a principle explanatory view shown in FIG. It is explanatory drawing of the electron multiplication drive method which concerns on 2nd Embodiment of this invention. It is explanatory drawing of the electron multiplication drive method which concerns on 3rd Embodiment of this invention. It is explanatory drawing of the electron multiplication drive method which concerns on 4th Embodiment of this invention. It is explanatory drawing of the electron multiplication drive method which concerns on 5th Embodiment of this invention. It is explanatory drawing of the electron multiplication drive method which concerns on 6th Embodiment of this invention. It is explanatory drawing of the conventional electron multiplication drive method. FIG. 11 is an explanatory diagram of a process of forming a potential well for electron multiplication in FIG. 10.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a functional block diagram of an imaging apparatus (digital camera) according to the first embodiment of the present invention. The imaging device 20 includes a CCD solid-state imaging device 21 that converts a subject light image into captured image data of an electrical signal, and analog image data output from the solid-state imaging device 21 for automatic gain adjustment (AGC) or correlation. An analog signal processing unit 22 that performs analog processing such as multiple sampling processing, an analog / digital conversion unit (A / D) 23 that converts analog image data output from the analog signal processing unit 22 into digital image data, and system control described later A drive control unit (including a timing generator) 24 that controls the drive of the A / D 23, the analog signal processing unit 22, and the solid-state imaging device 21 according to an instruction from the unit (CPU) 29; Is provided.

  The digital camera according to the present embodiment further includes a digital signal processing unit 26 that takes in digital image data output from the A / D 23 and performs interpolation processing, white balance correction, RGB / YC conversion processing, and the like. A compression / expansion processing unit 27 that compresses or reversely compresses image data, a display unit 28 that displays menus, displays through images and captured images, and a system control unit that controls the entire digital camera ( CPU) 29, an internal memory 30 such as a frame memory, and a media interface (I / F) unit 31 that performs interface processing between a recording medium 32 that stores JPEG image data and the like, and a bus that interconnects them 40, and an operation unit 33 for inputting an instruction from the user is connected to the system control unit 29. It has been.

  FIG. 2 is a schematic view of the surface of the CCD type solid-state imaging device 21 shown in FIG. A solid-state imaging device 21 formed on a semiconductor substrate (a p-well layer thereof) has a plurality of photodiodes (pixels) 22 arranged in a two-dimensional array. In the present embodiment, a so-called honeycomb pixel array is formed in which the odd-numbered pixel rows are formed with a shift of 1/2 pixel pitch with respect to the even-numbered pixel rows. A vertical charge transfer path (VCCD) 23 is formed in a meandering manner so as to avoid each pixel along each pixel column.

The vertical charge transfer path 23 is formed by a buried channel formed in the semiconductor substrate along each pixel column and a transfer electrode film 23a formed thereon via a gate oxide film (not shown). The transfer electrode films 23a at the same vertical stage position of each vertical charge transfer path 23 are electrically connected in the horizontal direction so that the same transfer pulse voltage Vi (i = 1 to 16) is applied. In the illustrated example, the same transfer pulse is applied every 16 stages, and the solid-state imaging device 21 of this embodiment is driven in 16 phases.
A horizontal charge transfer path (HCCD) 24 is formed along the transfer direction end of each vertical charge transfer path 23, and the signal charge transferred along each vertical charge transfer path 23 is transferred to the horizontal charge transfer path 24. The At the end of the horizontal charge transfer path 24 in the transfer direction, there is formed an amplifier 25 that outputs a voltage value signal corresponding to the charge amount of the signal charge transferred in the horizontal direction as a captured image signal.

  In the solid-state imaging device 21 of the present embodiment, the signal charge accumulated in each pixel according to the amount of received light is read out in a multi-field manner. During this time, the signal charge read out to the vertical charge transfer path is driven by electron multiplication. To do. This drive is performed by the CPU 29 in FIG. 1 applying a required electron multiplication drive pulse to the vertical charge transfer path via the drive control unit 24.

  Note that R, G, and B described above each pixel 22 in FIG. 2 indicate the color of the color filter (R = red, G = green, B = blue). Each extending arrow indicates a direction in which the signal charge is read (direction of the reading electrode).

  In the above-described embodiment, the solid-state image sensor 21 having a so-called honeycomb pixel array has been described. Of course, the present invention can also be applied to a solid-state image sensor in which each pixel is arranged in a square lattice. Further, although the terms “vertical” and “horizontal” have been described, this means only “one direction” along the surface of the semiconductor substrate and “a direction substantially perpendicular to the one direction”.

  FIG. 3 is a diagram for explaining electron multiplication driving according to the present embodiment. FIG. 3A shows a vertical transfer pulse applied to the vertical transfer electrode 23a (in this example, an electron separate from the transfer in the vertical direction). FIG. 3B is a diagram showing the change of the potential well formed by the electron multiplication drive pulse and the movement of the accumulated charge.

  In this embodiment, in a state where signal charges are accumulated in the potential well 1 below the electrodes V2 and V3, a high voltage is applied to the electrode V5 that is two electrodes ahead and the electrode V7 that is four electrodes ahead at time t1. Two deep potential wells 3 and 5 are formed. Then, at time t4, the potential barrier 4 below the electrode V4 disappears, the signal charge in the potential well 1 is dropped into the potential well 3, and electron multiplication is performed. At time t8, the potential well 3 into which the signal charge is put is shallow. Return to potential well.

  When the potential barrier 6 below the electrode V6 between the potential well 3 and the potential well 5 disappears at the next time t9, the signal charge in the potential well 3 is transferred into the potential well (continuous electron multiplication potential well) 5. The second electron multiplication is performed.

  A waiting period before multiplication in the embodiment of FIG. 3 until a deep voltage well 3 is formed by applying a high voltage to the electrode V5, and the signal charge in the potential well 1 is dropped into the potential well 3 to perform electron multiplication. Is the same as the prior art described in FIG. However, in this embodiment, since the potential well 5 is formed simultaneously with the potential well 3, the waiting period until the signal charge is dropped in the potential well 5 and the second electron multiplication is performed can be omitted. Electron multiplication drive can be performed in a short time.

  The conventional electron multiplication drive described in FIG. 10 and the electron multiplication drive of the embodiment of FIG. 3 will be described in further detail.

  The electron multiplication drive is composed of two periods, a standby period before multiplication and a multiplication period, as described at the bottom of FIG. By applying a high voltage to the electrode at time t1, the potential of the p-well layer corresponding to GND on the substrate side rises transiently. Then, with time, it converges to the original potential.

  Since the potential of the vertical charge transfer path is determined on the basis of the p well layer potential, the potential of the vertical charge transfer path also varies with the variation of the p well layer potential. For this reason, if electron multiplication is performed during the period in which the p-well layer potential is fluctuating, there arises a problem that a desired multiplication factor cannot be obtained. This is as described with reference to FIG.

  In order to prevent this, a standby period before multiplication is provided, and the system waits until the potential well reaches the required depth. FIG. 10 is an example in which the multiplication operation is performed twice, and two high voltage applications (time t1, time t9) are performed. Therefore, the fluctuation of the p-well layer potential occurs twice, and the standby period for suppressing each fluctuation is provided twice in total. However, as a side effect of providing this standby period, the time required to complete the electron multiplication operation is extended, the dark current generated in the vertical charge transfer path is increased, and the signal S / N is deteriorated.

  In contrast, in the present embodiment (FIG. 3), application of a high voltage to the two electrodes that perform electron multiplication is started simultaneously at time tl. As a result, the potential of the p-well layer potential can be changed only once, the standby period is only once, and the time until the electron multiplication operation is completed (as described above, the total time is 50 times or 100 times. The number of times of electron multiplication is required) can be shortened.

  As a result, the dark current generated in the vertical charge transfer path can be reduced as compared with the conventional example, and the S / N of the output signal can be improved.

  Consider the time required for the fluctuation of the p-well layer potential to settle. An RC circuit as shown in FIG. 4 is considered as a simple model for examining how the fluctuation of the p-well layer potential is reduced.

  “C” represents the capacitance of the p-well layer, and “R” represents the resistance of the p-well layer. The p-well layer is capacitively coupled to the substrate (OFD terminal: overflow drain terminal). When a high voltage pulse is applied to form a deep potential well, the charge Q is charged in the p-well layer. As a result, a voltage V0 is generated at the point A.

The time dependence of the voltage at point A is
V_A = V0 * exp (-R * C * t)
It is represented by In order not to affect the multiplication factor, it is assumed that the potential at the point A needs to be equal to or lower than Vs (here, Vs <V0). Time required to reach this state = convergence time T is
T = 1 / (R * C) * ln (V0 / Vs)
It is represented by

On the other hand, when a high voltage pulse is applied to a plurality of electrodes as in this embodiment, a charge Q ′ (Q ′> Q) is charged, and a voltage V0 ′ (V0 ′> V0) is generated at point A. To do. The time dependence of the voltage at point A in this case is
V_A '= V0' * exp (-R * C * t)
It is represented by When the convergence time T ′ is calculated in the same manner as the previous calculation,
T ′ = 1 / (R * C) * ln (V0 ′ / Vs)
So that
T '/ T = ln (V0' / Vs) / ln (V0 / Vs)
It becomes.

For example, considering the case of V0 ′ = 2 * V0 (when a high voltage pulse is applied to two electrodes, Q ′ = 2Q),
T '/ T = 1 + ln (2) / ln (V0 / Vs)
It becomes. When a range where this is smaller than 2 is obtained,
Vs <V0 / 2
It becomes.

  In other words, the voltage Vs that does not affect the multiplication factor is not more than half of the initial p-well layer potential when a high voltage pulse is applied to one electrode. For example, when increasing the multiplication factor by increasing the number of multiplication pulse applications or increasing the multiplication pulse voltage, a lower voltage Vs that does not affect the multiplication factor is required. Therefore, the multiplication driving method as in the present embodiment is effective.

  As described above, according to the present embodiment, by reducing the number of times the p-well layer potential is changed, the time until the electron multiplication operation is completed can be shortened, and the dark current generated in the vertical charge transfer path is reduced. Can be reduced as compared with the prior art, and the S / N of the output signal can be improved.

  FIG. 5 is an explanatory diagram of a second embodiment of the present invention, FIG. 5 (a) is a timing chart of an electron multiplication pulse, and FIG. 5 (b) is a diagram showing the state of potential well formation and electron multiplication. It is.

  The difference from the embodiment of FIG. 3 is the number of times of electron multiplication. In this embodiment, a high voltage is applied to the electrodes V5, V7, and V9 at time t1 to form deep potential wells 3, 5, and 7, Electron multiplication is performed three times in succession. In the present embodiment, the potential well 5 and the potential well 7 serve as a potential well for continuous electron multiplication. For this reason, a multiplication factor and S / N higher than the embodiment of FIG. 3 can be obtained.

  However, since the multiplication factor is high, it is necessary to set the initial input charge amount smaller than that in the embodiment of FIG. 3 so as not to exceed the maximum charge amount that can be handled in the vertical charge transfer path.

  Therefore, the S / N and dynamic range can be optimized by switching the number of times of multiplication according to the ISO sensitivity setting of the camera (imaging device 20). For example, the embodiment of FIG. 3 is an electron multiplying drive when the relatively low ISO sensitivity is set, and the embodiment of FIG. 5 is an electron multiplying drive when the relatively high ISO sensitivity is set. Good to do.

  In this way, the S / N and dynamic range can be optimized by switching the number of times of multiplication performed continuously in accordance with the ISO sensitivity setting of the camera. In the embodiment of FIG. 5, electron multiplication is performed three times using three consecutive deep potential wells. However, if there is a vacancy on the charge transfer, it is continuous even five times. You may do it.

  6A and 6B are explanatory diagrams of a third embodiment of the present invention, in which FIG. 6A is a timing chart of an electron multiplication pulse, and FIG. 6B is a diagram showing states of potential well formation and electron multiplication. It is.

  A difference from the embodiment of FIG. 3 is that a high voltage (for example, +15 V) is applied to the electrodes V5 and V7 at time t1 to form deep potential wells 3 and 5, and at the same time, a voltage ( For example, -8V) is applied.

  As a result, it is possible to cancel even a part of the influence of the multiplication pulse changing to the positive side on the p-well layer. Therefore, the fluctuation of the p-well layer potential can be suppressed in a shorter time, thereby shortening the time required for the entire electron multiplication drive and further improving the S / N.

  7A and 7B are explanatory diagrams of a fourth embodiment of the present invention, FIG. 7A is a timing chart of an electron multiplication pulse, and FIG. 7B is a diagram showing states of potential well formation and electron multiplication. It is.

  In the present embodiment, unlike the embodiment of FIG. 3, an example of electron multiplication drive in an 8-phase drive solid-state imaging device is given. The aim of this embodiment is to efficiently perform electron multiplication (in terms of time) within a range equal to or longer than the repetition period of the vertical charge transfer path.

  In the present embodiment, at time t12, the second electron multiplication pulse falling is applied to the electrode V7, and at the same time, the electron multiplication pulse applied to the subsequent electrodes V1 and V3 is raised. As a result, the influence of the rise of the electron multiplication pulse on the p-well layer can be partially canceled, and the fluctuation of the p-well layer potential can be suppressed in a shorter time, which is necessary for the entire electron multiplication drive. It is possible to shorten the time required.

  Moreover, the signal charge that has been multiplied by the electron at time t9 can be dropped into the next deep potential well 9 without any waiting time before multiplication, and the electron multiplication can be performed. In this example, the repetition period of the vertical charge transfer path (in this example, Since 8-phase driving is used, it is possible to efficiently perform electron multiplication within a range of at least the cycle of each of the eight transfer electrodes.

  According to this embodiment, the number of times of electron multiplication can be increased while efficiently suppressing fluctuations in the potential of the p-well layer in a shorter time even in a range longer than the repetition period of the vertical charge transfer path. Can be further improved.

  FIG. 8 is an explanatory diagram of a fifth embodiment of the present invention, FIG. 8 (a) is a timing chart of electron multiplication pulses, and FIG. 8 (b) is a diagram showing states of potential well formation and electron multiplication. It is.

  The feature of this embodiment is at time t11. In this embodiment, simultaneously with the fall of the second electron multiplication pulse applied to the electrode V7, the electron multiplication pulse of the subsequent electrodes V9 and V11 is raised, and the electron multiplication pulse of the electrode V4 is also raised. It is lowered.

  In the present embodiment, as in the embodiment of FIG. 6, the influence of the rising of the electron multiplication pulse on the p-well layer can be canceled. Therefore, the fluctuation of the p-well layer potential can be suppressed in a shorter time, thereby shortening the time required for the entire electron multiplication drive and further improving the S / N.

  FIG. 9 is an explanatory diagram of a sixth embodiment of the present invention. FIG. 9A is a timing chart of an electron multiplication pulse, and FIG. 9B is a diagram showing states of potential well formation and electron multiplication. It is.

  This embodiment is an eight-phase drive embodiment, similar to the embodiment of FIG. The aim of this embodiment is also to efficiently perform electron multiplication (in terms of time) within a range equal to or longer than the repetition period of the vertical charge transfer path.

  In the embodiments so far, at least two continuous deep potential wells for electron multiplication are formed simultaneously. However, in this embodiment, at least two continuous deep potential wells for electron multiplication are formed with a time difference. It differs in the formation point.

  That is, the application of the electron multiplication pulse at time t1 was performed only on the V5 electrode, and the application of the second electron multiplication pulse was performed on the electrode V7 during the application of the first electron multiplication pulse at time t6. That is, the electron multiplication period and the standby period before multiplication are overlapped. Thereby, the standby period before electron multiplication required for the whole electron multiplication drive can be shortened.

  To apply this embodiment when performing electron multiplication using three continuous deep potential wells as in the embodiment of FIG. 5, the third electron multiplication is applied during the second electron multiplication pulse application. What is necessary is just to apply the double pulse and overlap the electron multiplication period and the waiting period before multiplication.

  According to the present embodiment, the standby period before electron multiplication required for the entire electron multiplication drive can be efficiently shortened even in a range longer than the repetition period of the vertical charge transfer path.

  As described above, the driving method of the CCD solid-state imaging device according to the embodiment of the present invention reads the signal charge corresponding to the amount of received light to the charge transfer path and stores the first potential on the charge transfer path in which the signal charge is accumulated. A second potential well deeper than the well is formed on the charge transfer path through a potential barrier, and the signal charge in the first potential well is dropped into the second potential well by eliminating the potential barrier. And at least one continuous electron multiplication potential well having the same depth as that of the second potential well is formed on the charge transfer path through a potential barrier before the end of the electron multiplication driving. After the completion of the electron multiplication drive, the second potential well and the continuous electron multiplication potential well are successively returned after returning the depth of the second potential well to the depth of the first potential well. The potential barrier between the second potential well and the second potential well Characterized in that the signal charges of the inner performing electron multiplication plunge into the continuous electron multiplying a potential in the well.

  The CCD solid-state imaging device driving method of the embodiment is characterized in that the second potential well and at least one continuous electron multiplication potential well are formed simultaneously.

  Further, in the driving method of the CCD solid-state imaging device of the embodiment, the second potential well and the continuous electron multiplication potential well are formed with a time difference, and the electron multiplication using the second potential well is performed. The potential well for continuous electron multiplication is formed during double driving.

  In addition, the CCD solid-state imaging device driving method according to the embodiment includes at least the continuous electron multiplication potential well when performing electron multiplication using the second potential well and the continuous electron multiplication potential well. A subsequent potential well for continuous electron multiplication is formed through a potential barrier, and electron multiplication is continuously performed at least three times using the potential well for continuous electron multiplication.

  The CCD solid-state imaging device according to the embodiment includes a driving method in which electron multiplication is continuously performed at least twice by the driving method described above, and at least three times in succession by the driving method described above. The driving method for performing electron multiplication is switched according to the ISO sensitivity of the imaging apparatus.

  Further, in the driving method of the CCD solid-state imaging device of the embodiment, when a high voltage pulse is applied to the electrode corresponding to the potential well in order to form the deep potential well, the timing is the same as the application of the high voltage pulse. A voltage pulse having a polarity opposite to that of the high voltage pulse is applied to another electrode different from the electrode.

  In the driving method of the CCD solid-state imaging device of the embodiment, when a high voltage pulse is applied to the electrode corresponding to the potential well in order to form the deep potential well, at the same timing as the end of the application of the high voltage pulse. A high voltage pulse for forming a deep potential well for performing next electron multiplication is applied to another electrode different from the electrode.

  Further, in the driving method of the CCD solid-state imaging device of the embodiment, when a high voltage pulse is applied to the electrode corresponding to the potential well in order to form the deep potential well, the timing is the same as the application of the high voltage pulse. A voltage pulse having a polarity opposite to that of the high voltage pulse is applied to another electrode different from the electrode, and the next electron multiplication is applied to the electrode and another electrode different from the other electrode at the same timing as the application of the high voltage pulse. A high voltage pulse for forming a deep potential well to be applied is applied.

  In addition, the imaging apparatus according to the embodiment applies a pulse voltage to the CCD solid-state imaging device and the CCD solid-state imaging device according to any of the above-described driving methods to form the potential well and eliminate the potential barrier. And a control means for performing.

  According to the embodiment described above, the electron multiplication drive time can be shortened, and a high S / N captured image signal can be obtained.

  The method for driving a CCD type solid-state imaging device according to the present invention can perform a required number of times of electron multiplication in a short time and can obtain a high S / N image signal, so that a digital still camera or a digital video camera can be obtained. It is useful when applied to general imaging devices such as camera-equipped mobile phones, electronic devices with cameras such as PDAs and notebook computers, and endoscopes.

3, 5, 7, 9 Deep potential well 2 for electron multiplication Signal charge 4, 6 Potential barrier 20 Imaging device 21 CCD type solid-state imaging device 22 Pixel (photoelectric conversion device: photodiode)
23 Vertical charge transfer path (VCCD)
23a Vertical transfer electrode 24 Horizontal charge transfer path (HCCD)
26 Digital Signal Processing Unit 29 System Control Unit (CPU)

Claims (9)

  A signal charge corresponding to the amount of received light is read out to the charge transfer path, and a second potential well deeper than the first potential well on the charge transfer path in which the signal charge is accumulated is formed on the charge transfer path through a potential barrier. The signal charge in the first potential well is dropped into the second potential well while eliminating the potential barrier, and electron multiplication is performed, and the second potential before the end of driving of the electron multiplication is completed. At least one continuous electron multiplication potential well having the same depth as the well is formed on the charge transfer path through a potential barrier, and after the electron multiplication driving is finished, the depth of the second potential well is increased. The signal charge in the second potential well is eliminated by continuously removing the potential barrier between the second potential well and the continuous electron multiplication potential well after returning to the depth of one potential well. Into the potential well for continuous electron multiplication The driving method of the CCD solid-state imaging device performing multiplication.   2. The method for driving a CCD solid-state imaging device according to claim 1, wherein the second potential well and at least one continuous electron multiplication potential well are simultaneously formed.   2. The method of driving a CCD solid-state imaging device according to claim 1, wherein the second potential well and the potential well for continuous electron multiplication are formed with a time difference, and the second potential well is used. A method for driving a CCD solid-state imaging device, wherein the potential well for continuous electron multiplication is formed during electron multiplication driving.   4. The method of driving a CCD solid-state imaging device according to claim 1, wherein electron multiplication is performed using the second potential well and the potential well for continuous electron multiplication. Sometimes, at least the successive electron multiplication potential well is formed with a potential barrier for the next successive electron multiplication through a potential barrier, and the electron multiplication potential well is also used at least three times in succession. A method for driving a CCD solid-state imaging device.   A driving method for performing electron multiplication at least twice in succession by the driving method for a CCD type solid-state imaging device according to any one of claims 1 to 3, and a driving method for continuously driving by a driving method according to claim 4. A method for driving a CCD solid-state imaging device that switches between a driving method for performing electron multiplication at least three times in accordance with the ISO sensitivity of the imaging device.   6. The method for driving a CCD type solid-state imaging device according to claim 1, wherein a high voltage pulse is applied to an electrode corresponding to the potential well in order to form the deep potential well. A method of driving a CCD solid-state imaging device, wherein a voltage pulse having a polarity opposite to that of the high voltage pulse is applied to another electrode different from the electrode at the same timing as the application of the high voltage pulse.   6. The method for driving a CCD type solid-state imaging device according to claim 1, wherein a high voltage pulse is applied to an electrode corresponding to the potential well in order to form the deep potential well. A method for driving a CCD solid-state imaging device, wherein a high voltage pulse is applied to form a deep potential well for performing next electron multiplication on another electrode different from the electrode at the same timing as the end of the application of the high voltage pulse.   6. The method for driving a CCD type solid-state imaging device according to claim 1, wherein a high voltage pulse is applied to an electrode corresponding to the potential well in order to form the deep potential well. A voltage pulse having a polarity opposite to that of the high voltage pulse is applied to another electrode different from the electrode at the same timing as the application of the high voltage pulse, and the electrode and the separate electrode are applied at the same timing as the application of the high voltage pulse. Drive method for a CCD type solid-state imaging device, in which a high voltage pulse for forming a deep potential well for performing next electron multiplication is applied to another electrode different from the above.   A pulse voltage is applied to the CCD solid-state imaging device and the driving method according to any one of claims 1 to 8 to form the potential well and eliminate the potential barrier. An imaging device comprising control means.

Images