JP2013004927A - Wafer mapping device and wafer mapping method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wafer mapping device which can quickly and surely detect whether a semiconductor substrate protrudes from a container vessel.SOLUTION: In the wafer mapping device in an embodiment, an illumination optical system irradiates a linear slit light intersecting a wafer side face at right angles on plural spots of each wafer. First and second image pickup units photograph the wafer side face having the linear slit light irradiated thereon as first and second shot images. When the first and the second shot images are photographed, a containment state detection unit calculates the amount of protrusion of the wafer from the container vessel by a trigonometrical survey method. When only one of the first and the second shot images is photographed, the containment state detection unit compares an image formed position at which a reflected light of the linear slip light forms an image on an image plane with a reference position to determine whether the wafer protrudes from the container vessel.

Description

  Embodiments described herein relate generally to a wafer mapping apparatus and a wafer mapping method.

  In a semiconductor manufacturing apparatus, when a wafer is transferred between a storage container (FOUP) which is a wafer transfer carrier and the semiconductor manufacturing apparatus, after the FOUP is connected to the semiconductor manufacturing apparatus, the transfer robot stores the wafer in the FOUP. Is confirmed (mapping process).

  In such a mapping process, it is detected in which slot in the FOUP the wafer is stored, whether the wafer is not accommodated in an oblique direction, or whether the wafer has jumped out of the FOUP.

  In the conventional wafer mapping method, a pair of photosensors attached to the end effect tip of the robot arm is moved to a position slightly overlapping the wafer arc portion. Thereafter, the presence or absence of a wafer in each slot was detected by moving the robot arm up and down in the wafer loading direction.

However, under the situation where the transfer robot is constantly carrying wafers, there are the following problems.
1. Since the mapping process includes a robot operation, it takes a long time to detect the wafer storage state.
2. Only one wafer can be detected at a time.
3. Mapping processing cannot be performed in parallel with the wafer transfer operation.

  In addition, when performing wafer mapping by image processing using a camera, there is a problem that it is impossible to detect whether or not the wafer is protruding from the FOUP if the camera fails. Due to the above four problems, it has not been possible to detect at high speed and reliably whether or not the wafer has jumped out of the FOUP. For this reason, it is desired to detect at high speed and reliably whether or not the wafer has jumped out of the FOUP.

JP 2005-64515 A

  The problem to be solved by the present invention is to provide a wafer mapping apparatus and a wafer mapping method capable of detecting at high speed and reliably whether or not a wafer has jumped out of a storage container.

  According to an embodiment, a wafer mapping apparatus is provided. The wafer mapping apparatus includes an illumination optical system, a first imaging unit, a second imaging unit, and a storage state detection unit. The illumination optical system emits linear slit light that intersects perpendicularly to the longitudinal direction of the side surface of the semiconductor substrate in a state where the storage container storing the semiconductor substrate is mounted on the mounting table. Irradiate a plurality of locations on the side surface of each semiconductor substrate from the part side. The first imaging unit is disposed at a first position and images a side surface of the semiconductor substrate irradiated with the linear slit light. The second imaging unit is arranged at a second position and images a side surface of the semiconductor substrate irradiated with the linear slit light. The storage state detection unit stores the semiconductor substrate using at least one of a first captured image captured by the first imaging unit and a second captured image captured by the second imaging unit. Detect the stored state in the container. Furthermore, the storage state detection unit uses both the first captured image and the second captured image when both the first captured image and the second captured image are captured. Then, the amount of protrusion of the semiconductor substrate from the storage container is calculated by a triangulation method. In addition, when only one of the first captured image and the second captured image is captured, the storage state detection unit may detect the linear slit light based on the captured image. It is determined whether or not the semiconductor substrate has jumped out of the storage container by comparing an image forming position where the reflected light of the image is formed on the image surface with a reference position of the image forming position.

FIG. 1 is a top view illustrating an example of a semiconductor manufacturing apparatus according to the embodiment. FIG. 2 is a perspective view showing a configuration example of the wafer loading mechanism and the wafer mapping mechanism. FIG. 3 is a block diagram showing the configuration of the wafer mapping apparatus. FIG. 4 is a flowchart showing a wafer mapping processing procedure. FIG. 5 is a diagram showing the relationship between the camera placement position and the wafer measurement position. FIG. 6 is a diagram for explaining camera image acquisition processing. FIG. 7 is a diagram for explaining measurement point extraction processing. FIG. 8 is a diagram for explaining processing for acquiring wafer presence / absence information and cross slot information. FIG. 9 is a diagram for explaining an arrangement example of cameras. FIG. 10 is a diagram for explaining a method of calculating the pop-out distance of a wafer using triangulation. FIG. 11 is a diagram for explaining the process of determining whether or not a wafer has popped out when one of the cameras fails. FIG. 12 is a diagram illustrating the operation timing of the semiconductor manufacturing apparatus. FIG. 13 is a diagram illustrating an arrangement example of cameras when a plurality of FOUPs are set in the wafer loading mechanism. FIG. 14 is a diagram illustrating a hardware configuration of the wafer mapping apparatus. FIG. 15 is a top view illustrating another configuration example of the semiconductor manufacturing apparatus according to the embodiment.

  Exemplary embodiments of a wafer mapping apparatus and a wafer mapping method will be explained below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

(Embodiment)
FIG. 1 is a top view illustrating an example of a semiconductor manufacturing apparatus according to the embodiment. The semiconductor manufacturing apparatus 100X is, for example, a sheet type apparatus such as a dry etching apparatus, and is disposed in a semiconductor manufacturing facility.

  The semiconductor manufacturing apparatus 100 </ b> X detects the storage state of the wafer W having a substantially disk shape in the FOUP (Front-Opening Unified Pod) 8. Then, the semiconductor manufacturing apparatus 100X generates wafer presence / absence information, cross slot information, and wafer pop-out information as information indicating the storage state (information on wafer mapping) of the wafer W. The wafer presence / absence information is information indicating whether or not the wafer W is stored in the FOUP 8. The cross slot information is information indicating whether or not the wafer W is stored in an oblique direction with respect to the slot in the FOUP 8. The wafer pop-out information includes pop-out determination information indicating whether or not the pop-out distance of the wafer W jumping out from the FOUP 8 is within an allowable range, and pop-out distance information indicating how much the wafer W has jumped out of the FOUP 8. And.

  The semiconductor manufacturing apparatus 100X according to the present embodiment detects the storage state of the wafer W in the FOUP 8 by using the two cameras 2L and 2R. If one camera fails, the other camera stores the wafer W. Detect state.

  When the semiconductor manufacturing apparatus 100X detects the retracted state of the wafer W by the two cameras 2L and 2R (in the normal state), how far the wafer W has jumped out of the FOUP 8 as the wafer pop-out information. Is detected. Further, when the semiconductor manufacturing apparatus 100X detects the stored state of the wafer W by either one of the cameras 2L and 2R (in the case of an abnormal state), whether or not the wafer W has jumped out of the FOUP 8 as wafer pop-out information. Is detected.

  The semiconductor manufacturing apparatus 100X includes a wafer loading mechanism 3, a wafer mapping mechanism 1X, a process processing mechanism 5, and a control device 30X. The wafer loading mechanism 3 includes a transfer robot 4 and a FOUP mounting table 7.

  The FOUP 8 is a carrier in which the wafer W is stored when the wafer (semiconductor substrate) W is transferred. When processing such as etching is performed on the wafer W in the FOUP 8 by the process processing mechanism 5, the FOUP 8 is mounted on the FOUP mounting table (load port) 7. The respective wafers W are stored in the FOUP 8 so that the centers of the wafers W are aligned in the coaxial direction and the main surfaces of the wafer W are aligned in parallel at substantially equal intervals. In other words, the wafers W are stacked so as to be aligned in the same direction in the FOUP 8. When the wafer is processed by the process processing mechanism 5, the FOUP 8 is placed on the FOUP mounting table 7 so that the main surface of each wafer W is in the horizontal direction. In the semiconductor manufacturing apparatus 100X, after the FOUP 8 is mounted on the FOUP mounting table 7, the storage state of the wafer W in the FOUP 8 is detected.

  The transfer robot 4 transfers the wafers W in the FOUP 8 one by one to the process processing mechanism 5 and also transfers the wafers W that have been etched by the process processing mechanism 5 one by one into the FOUP 8 one by one. The transfer robot 4 includes a robot arm 41, and transfers the wafer W between the process processing mechanism 5 and the FOUP 8 with the wafer W placed on the robot arm 41.

  The wafer mapping mechanism 1X includes a wafer mapping apparatus 10X, two cameras 2L and 2R, and three illumination optical systems 9A, 9B, and 9C. Each of the illumination optical systems 9A to 9C has a function of irradiating light (slit light to be described later) to the wafer W in the FOUP 8, and includes illumination devices, lenses, and the like. The illumination optical systems 9A to 9C irradiate the side surface of the wafer W with a slit light when the cameras 2L and 2R capture images. The illumination optical systems 9A, 9B, and 9C irradiate slit lights on the left side, center, and right side of the side surface (peripheral part) of the wafer W stored in the FOUP 8, respectively. In addition, three illumination optical systems 9A to 9C may be configured by one illumination device, or each illumination optical system 9A to 9C may be configured separately.

  The camera 2L images the side surface of the wafer W from the left side, and the camera 2R images the side surface of the wafer W from the right side. The cameras 2L and 2R image the reflected light from the wafer W by imaging the side surface of the wafer W.

  The wafer mapping apparatus 10X is a computer or the like that determines the storage state of the wafer W in the FOUP 8 using images (reflected light positions) captured by the cameras 2L and 2R. The wafer mapping apparatus 10X sends the storage state (wafer mapping result) of the wafer W to the control apparatus 30X.

  The process processing mechanism 5 includes a carry-in / out unit 38 and three process chambers 35 to 37. The wafer W taken out from the FOUP 8 by the transfer robot 4 is carried into the carry-in / out unit 38.

  The carry-in / out unit 38 includes a vacuuming unit (not shown) that vacuums the room, and a vacuum-side transfer robot (not shown) that transfers the wafer W to any of the process chambers 35 to 37. .

  The wafer W carried into the carry-in / out unit 38 is Air Locked by the carry-in / out unit 38, evacuated by the vacuum drawing unit, and carried to any one of the process chambers 35 to 37 by the vacuum side carrying robot. The wafer W that has been etched in the process chambers 35 to 37 is sent to the loading / unloading section 38 by the vacuum-side transfer robot, and is returned from the loading / unloading section 38 to the FOUP 8 by the transfer robot 4.

  The control device 30X is a computer that controls the wafer loading mechanism 3, the wafer mapping mechanism 1X, and the process processing mechanism 5. When the control device 30X detects that the FOUP 8 is mounted on the FOUP mounting table 7 by a sensor (not shown) or the like, the control device 30X instructs the wafer mapping mechanism 1X to execute wafer mapping. Specifically, the control device 30X instructs the illumination optical systems 9A to 9C to irradiate illumination light (slit light). Thereby, the slit light from the illumination optical systems 9 </ b> A to 9 </ b> C is irradiated onto the side surface of the wafer W.

  The control device 30X instructs the cameras 2L and 2R to capture an image. Thereby, the cameras 2L and 2R image the side surfaces of all the wafers W. In addition, the control device 30X instructs the wafer mapping device 10X to perform wafer mapping based on images captured by the cameras 2L and 2R.

  Further, the control device 30X controls the transfer robot 4 based on the wafer mapping result by the wafer mapping mechanism 1X. For example, when the wafer W has jumped out from the FOUP 8 by a predetermined distance, an instruction is sent to the transfer robot 4 to take out the wafer W at a position corresponding to this jump-out distance.

  FIG. 2 is a perspective view showing a configuration example of the wafer loading mechanism and the wafer mapping mechanism. FIG. 2 shows a case where the wafer mapping apparatus 10X and the control apparatus 30X are configured by one computer. Further, the connection between the cameras 2L and 2R and the computer (wafer mapping apparatus 10X, control apparatus 30X) and the connection between the transfer robot 4 and the computer are not shown.

  In the wafer mapping mechanism 1X, for example, illumination optical systems 9A, 9B, and 9C are arranged on the heads of the cameras 2L and 2R or in the vicinity thereof so as to face the FOUP 8. For example, the cameras 2L and 2R and the illumination optical systems 9A and 9C are arranged so that the set of the camera 2L and the illumination optical system 9A and the set of the camera 2R and the illumination optical system 9C are symmetrical with respect to the FOUP 8. Is done. An illumination optical system 9B is disposed between the camera 2L and the camera 2R (on a symmetrical axis of symmetry).

  In the present embodiment, the wafer mapping mechanism 1X performs wafer mapping of the wafer W independently of the transfer of the wafer W by the wafer loading mechanism 3. For this reason, the transfer robot 4 of this embodiment can concentrate on the transfer of the wafer W, and does not need to perform an operation for wafer mapping.

  The loading process of the wafer W is performed based on the wafer mapping result by the wafer mapping mechanism 1X. For example, the transfer robot 4 is operated so as to take out the wafer W from a slot in which it is determined that the wafer W is stored in the FOUP 8.

  FIG. 3 is a block diagram showing the configuration of the wafer mapping apparatus. The wafer mapping apparatus 10X includes an image input unit 11, a wafer detection method determination unit 12, a measurement point extraction unit 13, a wafer presence determination unit 15, a cross slot determination unit 16, a wafer jump distance calculation unit 17, a wafer jump determination unit 18, and a wafer. A mapping result output unit 19, a setting information input unit 20, and a reference pixel position storage unit 21 are provided.

  The image input unit 11 inputs images sent from the cameras 2L and 2R and sends them to the wafer detection method determination unit 12 and the measurement point extraction unit 13. The wafer detection method determination unit 12 determines whether or not the cameras 2L and 2R are out of order based on the images sent from the cameras 2L and 2R. For example, the wafer detection method determination unit 12 determines that the camera 2L has failed when an image from the camera 2L is not sent, and the camera 2R has failed when an image from the camera 2R has not been sent. It is determined that When one of the cameras 2L and 2R has failed, the wafer detection method determination unit 12 sends failure information indicating the failed cameras 2L and 2R to the measurement point extraction unit 13.

  The measurement point extraction unit 13 extracts an image (measurement point) indicating the position of the wafer W from images sent from the cameras 2L and 2R. The measurement point extraction unit 13 sends the position of the extracted measurement point to the wafer presence / absence determination unit 15 and the cross slot determination unit 16.

  The measurement point extraction unit 13 associates the position of the measurement point with the cameras 2L and 2R when failure information is not received from the wafer detection method determination unit 12 (when the cameras 2L and 2R are not broken down). To the wafer pop-out distance calculation unit 17. The position of the measurement point in this case is both the position detected based on the image from the camera 2L and the position detected based on the image from the camera 2R.

  In addition, the measurement point extraction unit 13 extracts the failure information from the wafer detection method determination unit 12 (when either one of the cameras 2L and 2R has failed), extracted from the image of the camera that has not failed. The position of the measurement point and the failure information are sent to the wafer jump-out determination unit 18. The position of the measurement point in this case is a position detected based on an image from a camera that has not failed.

  The setting information input unit 20 inputs the reference position of the measurement point and stores it in the reference pixel position storage unit 21. The reference position of the measurement point is the pixel position of the measurement point (hereinafter referred to as the reference pixel position) detected by the cameras 2L and 2R when the wafer W is stored at a normal position in the FOUP 8 (when there is no protrusion). is there. For example, the position of the measurement point is actually detected in a state where the wafer W is stored in the normal position in the FOUP 8 in advance, and the detection result is set as the reference pixel position. As the reference pixel position, a reference pixel position for the camera 2L and a reference pixel position for the camera 2R are set in advance. Note that the reference pixel position may be calculated based on the irradiation direction of the slit light from the illumination optical systems 9A to 9C, the arrangement positions of the cameras 2L and 2R, the normal position of the wafer W, and the like. The reference pixel position storage unit 21 is a memory that stores the reference pixel position.

  The wafer presence / absence determination unit 15 determines, for each slot, whether or not the wafer W is stored in the FOUP 8 based on the position of at least one measurement point. The wafer presence / absence determination unit 15 sends the determination result to the wafer mapping result output unit 19 as wafer presence / absence information.

  The cross slot determination unit 16 determines, for each wafer W, whether or not the wafer W is stored in an oblique direction with respect to the slot in the FOUP 8 based on the position of at least one measurement point. The cross slot determination unit 16 sends the determination result to the wafer mapping result output unit 19 as cross slot information.

  The wafer jump-out distance calculation unit 17 calculates how far the wafer W has jumped out of the FOUP 8 as the jump-out distance information based on the positions of the measurement points detected using the cameras 2L and 2R. Wafer pop-out distance calculation unit 17 sends pop-out distance information to wafer pop-out determination unit 18.

  When receiving the pop-out distance information from the wafer pop-out distance calculation unit 17, the wafer pop-out determination unit 18 and the pop-out distance threshold (pixel distance threshold) and the calculated pop-out distance (detected inter-pixel distance) To determine whether the pop-out distance is within the allowable range. The threshold of the pop-out distance is stored, for example, in the reference pixel position storage unit 21 or the like.

  When the pop-out distance is within the allowable range, the wafer pop-out determination unit 18 sends the pop-out determination information indicating that the pop-out distance is within the allowable range and the pop-out distance information to the wafer mapping result output unit 19 as wafer pop-out information. send.

  When the pop-out distance is outside the allowable range, the wafer pop-out determination unit 18 sends pop-out determination information indicating that the pop-out distance is out of the allowable range to the wafer mapping result output unit 19 as wafer pop-out information.

  In addition, when the position of the measurement point is received from the measurement point extraction unit 13, the wafer jump-out determination unit 18 compares the position of the measurement point with the reference pixel position, and calculates a position difference. The wafer jump-out determination unit 18 determines whether or not the position of the measurement point is within an allowable range by comparing the calculated position difference with a position difference threshold value. The position difference threshold value is stored in, for example, the reference pixel position storage unit 21.

  The wafer jump-out determination unit 18 determines whether or not the wafer W has jumped out based on whether or not the position of the measurement point is within an allowable range. The wafer pop-out determination unit 18 determines that the wafer W is popping out when the position of the measurement point is not within the allowable range, and determines that the wafer W is not popping out when within the allowable range.

  The wafer mapping result output unit 19 sends wafer presence / absence information, cross slot information, and wafer pop-out information to the control device 30X. In the case where the wafer mapping apparatus 10X includes a display device such as a liquid crystal monitor, wafer presence / absence information, cross slot information, and wafer pop-out information may be displayed on the display device.

  The control device 30X includes a load control unit 31 that controls the wafer load mechanism 3, a process control unit 32 that controls the process processing mechanism 5, and a mapping control unit 33 that controls the wafer mapping mechanism 1X.

  The load control unit 31 performs control related to loading of the wafer W (movement and stop of the transfer robot 4 and stop of transfer) based on the wafer presence / absence information, cross slot information, and wafer pop-out information.

  The load control unit 31 has a wafer removal position control unit 34. The wafer take-out position control unit 34 sends an instruction to the transfer robot 4 to take out the wafer W at the position of the pop-out distance based on the pop-out distance information in the wafer pop-out information.

  FIG. 4 is a flowchart showing a wafer mapping processing procedure. When processing such as etching is performed by the process processing mechanism 5, the FOUP 8 is mounted on the FOUP mounting table 7. When the control device 30X detects that the FOUP 8 is mounted on the FOUP mounting table 7 using a sensor or the like, the control device 30X instructs the wafer mapping mechanism 1X to execute wafer mapping. Thereby, the slit light from the illumination optical systems 9 </ b> A to 9 </ b> C is irradiated onto the side surface of the wafer W. Then, the cameras 2L and 2R take an image of the side surface of the wafer W, thereby acquiring a camera image (wafer image) (step S10).

  The image input unit 11 of the wafer mapping apparatus 10X inputs images sent from the cameras 2L and 2R, and sends them to the wafer detection method determination unit 12 and the measurement point extraction unit 13. The wafer detection method determination unit 12 determines whether or not the cameras 2L and 2R are out of order based on whether images are sent from the cameras 2L and 2R. When one of the cameras 2L and 2R has failed, the wafer detection method determination unit 12 determines that wafer mapping is performed with the other camera that has not failed (wafer jump distance is not calculated). Further, when both the cameras 2L and 2R have not failed, the wafer detection method determination unit 12 determines that both cameras 2L and 2R perform wafer mapping (calculate the wafer jump-out distance). Thereby, the detection method of the storage state of the wafer W is determined (step S20).

  The wafer detection method determination unit 12 sends failure information indicating the failed cameras 2L and 2R to the measurement point extraction unit 13 when at least one of the cameras 2L and 2R has failed. The measurement point extraction unit 13 extracts measurement points from the camera images sent from the cameras 2L and 2R (step S30). The measurement point extraction unit 13 sends the position of the extracted measurement point to the wafer presence / absence determination unit 15 and the cross slot determination unit 16.

  Further, the measurement point extraction unit 13 pops out the wafer with the position of the measurement point corresponding to the camera 2L and the position of the measurement point corresponding to the camera 2R when no failure information is received from the wafer detection method determination unit 12. This is sent to the distance calculation unit 17. At this time, the measurement target point and the cameras 2L and 2R are associated with each other so that the position of each measurement point can be distinguished from which camera 2L and 2R is imaged. Sent.

  On the other hand, when receiving the failure information from the wafer detection method determination unit 12, the measurement point extraction unit 13 indicates the position of the measurement point extracted from the image of the camera that has not failed and the failure information, and the wafer jump-out determination unit 18. Send to.

  The wafer presence / absence determination unit 15 determines, for each slot, whether or not the wafer W is stored in the FOUP 8 (the presence or absence of the wafer W) based on the position of the measurement point (step S40). The wafer presence / absence determination unit 15 sends the determination result to the wafer mapping result output unit 19 as wafer presence / absence information.

  The cross slot determining unit 16 determines, for each wafer W, whether or not the wafer W is stored in an oblique direction with respect to the slot in the FOUP 8 based on the position of the measurement point (step S50). The cross slot determination unit 16 sends the determination result to the wafer mapping result output unit 19 as cross slot information.

  When the wafer jump-out distance calculation unit 17 receives the position of the measurement point from the measurement point extraction unit 13, the wafer jump-out distance calculation unit 17 determines that the cameras 2L and 2R have not failed (No in step S60). In this case, the wafer pop-out distance calculation unit 17 calculates pop-out distance information as the pop-out distance of the wafer W based on the positions of the measurement points detected using the cameras 2L and 2R (step S70). Wafer pop-out distance calculation unit 17 sends pop-out distance information to wafer pop-out determination unit 18.

  The wafer pop-out determination unit 18 receives the pop-out distance information from the wafer pop-out distance calculation unit 17 and, when no failure information is received, compares the pop-out distance threshold with the calculated pop-out distance. It is determined whether or not the pop-out distance is within an allowable range (step S80).

  When the pop-out distance is within the allowable range, the wafer pop-out determination unit 18 sends the pop-out determination information indicating that the pop-out distance is within the allowable range and the pop-out distance information to the wafer mapping result output unit 19 as wafer pop-out information. send.

  When the pop-out distance is outside the allowable range, the wafer pop-out determination unit 18 sends pop-out determination information indicating that the pop-out distance is out of the allowable range to the wafer mapping result output unit 19 as wafer pop-out information.

  On the other hand, when the wafer pop-out determination unit 18 receives the position of the measurement point and the failure information from the measurement point extraction unit 13, the wafer pop-out determination unit 18 indicates that one of the cameras 2L and 2R has failed. Judgment is made (step S60, Yes). In this case, the wafer pop-out determination unit 18 compares the position of the measurement point with the reference pixel position (step S90). When the camera 2L is out of order (when the camera 2L is specified in the failure information), the wafer pop-out determination unit 18 determines the reference pixel position of the camera 2R, the position of the measurement point acquired from the camera 2R, Compare Further, when the camera 2R is out of order (when the camera 2R is designated by the failure information), the wafer pop-out determination unit 18 and the position of the measurement point acquired from the camera 2L are displayed. And compare.

  Thereby, the wafer jump-out determination unit 18 performs the jump-out determination of the wafer W based on the position of the measurement point detected using the camera not indicated by the failure information and the reference pixel position (step S80). . Specifically, the wafer jump-out determination unit 18 compares the position of the measurement point with the reference pixel position, and calculates a position difference. Then, the wafer jump-out determination unit 18 determines whether or not the position of the measurement point is within the allowable range by comparing the calculated position difference with the position difference threshold value. The wafer jump-out determination unit 18 determines whether or not the wafer W has jumped out based on whether or not the position of the measurement point is within an allowable range.

  The wafer mapping result output unit 19 outputs wafer presence / absence information, cross slot information, and wafer pop-out information to the control device 30X as a wafer mapping result (step S100). The load control unit 31 of the control device 30X performs control related to loading of the wafer W based on wafer presence / absence information, cross slot information, and wafer pop-out information.

  Specifically, the wafer W is taken out from the slot in which it is determined by the wafer presence / absence information that the wafer W is stored in the FOUP 8. If it is determined by the cross slot information that the wafer W is stored in an oblique direction with respect to the slot in the FOUP 8 (stored across a plurality of slots), the wafer mapping apparatus 10X and the like An error is output. Further, when it is determined by the wafer pop-out information that the wafer W is popping out from the FOUP 8, if the wafer W pop-out distance is within an allowable range, the wafer W pick-up process corresponding to the wafer W pop-out distance is performed. Done. Specifically, the wafer take-out position control unit 34 sends an instruction to the transfer robot 4 to take out the wafer W at the position of the pop-out distance based on the pop-out distance information in the wafer pop-out information. Further, when the jumping distance of the wafer W is outside the allowable range, an error output or the like is performed from the wafer mapping apparatus 10X or the like.

  Next, a method for detecting the stored state of the wafer W (a method for calculating wafer presence / absence information, cross slot information, and wafer pop-out information) will be described. In the present embodiment, the principle of triangulation is used when calculating the pop-out distance information of the wafer pop-out information. For this reason, the semiconductor manufacturing apparatus 100X includes two cameras 2L and 2R.

  FIG. 5 is a diagram showing the relationship between the camera placement position and the wafer measurement position. FIG. 5 shows a triangulation geometry. In the semiconductor manufacturing apparatus 100X, the two cameras 2L and 2R are arranged in parallel at positions separated by the inter-camera distance d. In FIG. 5, instead of the cameras 2L and 2R, a left camera field of view Cl and a right camera field of view Cr are illustrated. In FIG. 5, the horizontal direction of the open surface of the FOUP 8 (surface of the wafer W take-out port) is indicated by the X direction, the vertical direction is indicated by the Y direction, and the depth direction of the FOUP 8 is indicated by the Z direction. Accordingly, both the left camera field of vision Cl and the right camera field of view Cr are oriented in a direction parallel to the XY plane.

  As shown in FIG. 2, illumination optical systems 9A to 9C are arranged to face the FOUP 8 above or near the heads of the cameras 2L and 2R. The illumination optical systems 9A to 9C are configured using, for example, LED illumination and a rectangular slit mask. The rectangular slit mask is a mask for irradiating the side surface of the wafer W with rectangular illumination light, and the longitudinal direction of the rectangle is the stacking direction (vertical direction) of the wafers W.

  The illumination light emitted from the illumination optical systems 9A to 9C is irradiated to the left side, the center, and the right side of the side surface of the wafer W as slit light (lattice light light that is linear slit light), respectively. The slit light from the illumination optical system 9A is irradiated to the measurement target point 26A on the left side of the wafer W among the measurement target points P of the wafer W. Similarly, the slit light from the illumination optical system 9B is irradiated to the measurement target point 26B in the center of the wafer W, and the slit light from the illumination optical system 9C is irradiated to the measurement target point 26C on the right side of the wafer W.

  Then, the slit light is reflected at each measurement target point P and is incident on the left camera visual field Cl and the right camera visual field Cr at the position of the focal length f. For example, the reflected light 25L at the measurement target point P (X, Y, Z) is detected as the measurement point Pl (X1, Y1, Zl) in the left camera visual field Cl, and the measurement target point P (X, Y, Z). The reflected light 25R is detected as a measurement point Pr (Xr, Yr, Zr) in the right camera visual field Cr.

Next, the stored state detection procedure for the wafer W will be described. The stored state detection process of the wafer W is performed in the following order of 1-4.
1. In order to eliminate measurement errors due to lens aberration, the cameras 2L and 2R are corrected in advance.
2. Irradiation is performed from the illumination optical systems 9 </ b> A to 9 </ b> C so that the slit light overlaps perpendicularly to the tangential direction of the circumference of the wafer W in the FOUP 8. At this time, among the slit lights irradiated on the wafer W, the light reflected from the outer peripheral portion of each wafer W and the surrounding state are imaged in the left camera visual field Cl and the right camera visual field Cr.
3. After binarizing these camera images, only the portion (image) of the light reflected from the outer peripheral portion of the wafer W is extracted and set as the position of the measurement target point (measurement points Pl and Pr).
4). From the camera image obtained at this time, the arrangement (protrusion distance) of the wafer W in the FOUP 8 is measured by triangulation.

  Next, a triangulation method using image processing will be described. In the triangulation method using image processing, each process is performed in the order of (1) camera image acquisition, (2) measurement point extraction, and (3) wafer storage information acquisition.

(1) Acquisition of Camera Image Acquisition of a camera image is performed by acquiring an image obtained when each wafer W in the FOUP 8 is irradiated with a plurality of slit lights from the illumination optical systems 9A to 9C. FIG. 6 is a diagram for explaining camera image acquisition processing. 6A shows the wafer W and the slit light 51, and FIG. 6B shows a reflected light detection region set in the camera image.

  6A shows the wafer W (side surface) viewed from the open surface (opening) side of the FOUP 8. FIG. When the FOUP 8 is viewed from the open surface side, the respective wafers W are stored in the FOUP 8 so that the main surfaces face each other. When acquiring a camera image, the slit lights 51A to 51C are irradiated on the wafer W so that the longitudinal direction of the side surface of the wafer W and the longitudinal direction of the slit lights 51A to 51C are perpendicular to each other. The slit lights 51 </ b> A to 51 </ b> C are illumination lights emitted from the illumination optical systems 9 </ b> A to 9 </ b> C, respectively, and irradiate the left side, the center, and the right side of the side surface of the wafer W, respectively.

  Only the light hitting the outer peripheral portion (measurement target point P) is reflected on the wafer W, and as shown in FIG. 6B, the measurement point 53P for the measurement target point on the wafer W is imaged as a camera image. . The measurement point 53P here corresponds to one of the measurement points Pl and Pr shown in FIG.

  In the wafer W, reflection occurs in a predetermined range every time, so that areas where reflected light is expected to be imaged in the camera visual fields Cl and Cr are set as detection areas 52A to 52C. The detection areas 52A to 52C are areas where the reflected lights of the slit lights 51A to 51C are detected, respectively. Thereby, the measurement point 53P for the measurement target point P on the left side of the side surface of each wafer W is imaged in the detection region 52A. Similarly, in the detection areas 52B and 52C, the measurement point 53P with respect to the measurement target point P at the center and right side of the side surface of each wafer W is imaged.

(2) Extraction of measurement points Since the acquired camera image contains measurement noise or diffuse reflection light from the periphery of the measurement object (measurement target point P), the stored state of the wafer W by triangulation is detected as it is. It is difficult to do. Therefore, in the present embodiment, the measurement point extraction unit 13 performs binarization / emphasis processing on the measurement point 53P from the acquired data (camera image).

  FIG. 7 is a diagram for explaining measurement point extraction processing. In FIG. 7A, an image of the measurement point 53P and an image of the measurement noise 55 are shown as camera images. Each camera pixel 54 in the camera image is represented by a gray value of, for example, 256 gradations or more. For this reason, the measurement point extraction unit 13 performs a binarization / enhancement process in which the gray value below the threshold is set to 0 for each camera pixel 54 and the gray value above the threshold is corrected to the maximum value (256 or the like). To do. Thereby, noise is removed and the measurement point 53P is emphasized, so that the measurement point extraction unit 13 extracts the emphasized measurement point.

  FIG. 7B shows a camera image after binarization / enhancement processing. In the camera image after binarization / enhancement processing, the measurement points 53P of each wafer W are displayed in the detection areas 52A to 52C.

(3) Acquisition of wafer storage information The wafer storage information is information relating to the loading of the wafer W (information obtained by the mapping process), (3-1) wafer presence / absence information, (3-2) cross slot information, (3 -3) Includes wafer pop-out information.

(3-1) Wafer Presence Information and (3-2) Acquisition Method of Cross Slot Information FIG. 8 is a diagram for explaining processing for acquiring wafer presence information and cross slot information. FIG. 8A is a diagram for explaining a process for acquiring wafer presence / absence information, and FIG. 8B is a diagram for explaining a process for acquiring cross slot information.

  The presence / absence of the wafer W in each slot is confirmed on the binarized / enhanced camera image. For example, the wafer presence / absence determination unit 15 sets a determination region for each slot arranged at a predetermined interval L. FIG. 8A shows the determination area 61 for the slot number (N5). The wafer presence / absence determination unit 15 sets a determination area 61 for all slots (slot numbers (N1) to (N25)) in the FOUP 8 and scans each determination area 61. Then, the wafer presence / absence determination unit 15 determines the presence / absence of a wafer for each slot, using as a wafer presence / absence determination condition whether or not three light spots can be detected in a horizontal row in the determination region 61.

  At this time, the wafer presence / absence determination unit 15 may consider only the reflection point having a certain area as the recognition target of the measurement point 53P in consideration of the irradiation width of the slit light. Thereby, noise that could not be removed by the binarization / enhancement process can be removed from the measurement target.

  Note that a camera image obtained by imaging the wafer W in a normal storage state is set as a reference camera image, and pattern matching is performed between the reference camera image and the captured camera image. The presence / absence of a wafer may be determined accordingly.

  Further, the cross slot determination unit 16 determines whether or not the wafer W is stored in an oblique direction with respect to the slot in the FOUP 8 (cross slot). As shown in FIG. 8B, when the determination area 61 is scanned when there is a cross slot, measurement points 53P appear only in either the right side or the left side. For this reason, when the cross slot determination unit 16 detects the measurement point 53P from only one of the right side and the left side, the cross slot determination unit 16 detects the cross slot by the combination of the slot numbers.

  For example, in the case of FIG. 8B, in the slot number (N11), the measurement point 53P is detected from the right side, and the measurement point 53P is not detected from the left side. In the slot number (N10), the measurement point 53P is detected from the left side, and the measurement point 53P is not detected from the right side. Therefore, the cross slot determination unit 16 detects that a cross slot has occurred between the slot with the slot number (N10) and the slot with the slot number (N11).

(3-3) Acquisition of wafer pop-out information The wafer pop-out distance calculation unit 17 uses a triangulation method in order to calculate wafer pop-out information in each slot. In applying the triangulation method, in the semiconductor manufacturing apparatus 100X, it is necessary to arrange the cameras 2L and 2R at predetermined positions.

  FIG. 9 is a diagram for explaining an arrangement example of cameras. As shown in FIG. 9, the image plane of the camera 2L is the left image plane 73L, and the image plane of the camera 2R is the left image plane 73R. The optical axis of the camera 2L is the optical axis 72L, and the optical axis of the camera 2R is the optical axis 72R. The optical center of the camera 2L is the optical center 74L, and the optical center of the camera 2R is the optical center 74R. A line connecting the optical center 74L and the optical center 74R is a base line.

  In this embodiment, since the jumping distance of the wafer W is calculated using the triangulation method, two cameras 2L and 2R having the same specifications are arranged, and the cameras 2L and 2R are arranged so that the optical axes 72L and 72R are parallel to each other. And the cameras 2L and 2R are arranged such that the optical centers 74L and 74R are separated by a distance d in the X direction.

  In this case, the epipolar line on the camera 2L side is the epipolar line 75L, and the epipolar line on the camera 2R side is the epipolar line 75R. A plane connecting the optical center 74L, the optical center 74R, and the measurement target point P is an epipolar plane 76.

  Next, a method for calculating the jump distance of the wafer W using triangulation will be described. FIG. 10 is a diagram for explaining a method of calculating the pop-out distance of a wafer using triangulation. Here, the case where the jumping distance of the wafer W is calculated with respect to the measurement target point P (x, z) on the wafer W will be described. The wafer position z is calculated from the camera coordinates when viewed from the two camera fields of view for one measurement target point P.

  In FIG. 10, the optical centers of the cameras 2L and 2R are indicated by optical centers O and O ', and the intersections between the optical axis and the image planes of the cameras 2L and 2R are indicated by central points Oi and Oi'. The intersection of the line connecting the measurement target point P and the optical center O and the image plane of the camera 2L is the pixel position L, and the distance from the pixel position L to the center point Oi is xl. Similarly, the intersection of the line connecting the measurement target point P and the optical center O ′ and the image plane of the camera 2R is the pixel position R, and the distance from the pixel position R to the center point Oi ′ is −xr. .

  The distance from the line (baseline) connecting the optical centers O and O 'to the image planes of the cameras 2L and 2R is the focal length f. The position in the Z direction (depth direction) of the wafer W viewed from the image planes of the cameras 2L and 2R is the wafer position z. Here, a point where a line extending from the measurement target point P in the X-axis direction and the optical axis of the camera 2L intersect is indicated by Pz.

In this case, ΔPLR∽ΔPOO ′. Therefore, the following relationship holds. That is, the relational expression (A) is established from ΔPLR∽ΔPOO ′, the relational expression (B) is derived from the relational expression (A), and the relational expression (C) is derived from the relational expression (B).
PL / PO = LR / OO '(A)
(PO−LO) / PO = (OO′−OiL−ROi ′) / OO ′ (B)
LO / PO = (xl−xr) / d (C)

Further, ΔOLOi∽ΔOPPz. Therefore, the following relationship holds. That is, the relational expression (D) is established from ΔOLOi∽ΔOPPz, and the relational expression (E) is derived from the relational expression (D).
LO / PO = OiO / PzO (D)
LO / PO = f / z (E)

Further, from the relational expressions (C) and (E), the following relation is established. That is, the relational expression (F) is established from the relational expressions (C) and (E), and the relational expression (G) is derived from the relational expression (F).
f / z = (xl−xr) / d (F)
z = fd / (xl−xr) (G)

  In the relational expression (G), when the parallax Dx = xl−xr and z is smaller than a predetermined value, it is determined that the wafer W has jumped out of the FOUP 8. Thus, the presence or absence of the protrusion of the wafer W is determined based on the wafer position z.

  When the wafer W protrudes from the FOUP 8 by a predetermined distance, the control device 30X sends an instruction to the transfer robot 4 to take out the wafer W at a position corresponding to the wafer position z.

  When determining whether or not the wafer W has popped out, the relationship between the error on the image and the distance estimation error may be considered. This relationship is expressed by the following equations (1) and (2) when the distance estimation error is Δz.

  In this way, the distance estimation error Δz is proportional to the square of the wafer position z and inversely proportional to the baseline.

  Next, the process of determining whether or not the wafer W has popped out when one of the cameras 2L and 2R has failed will be described. FIG. 11 is a diagram for explaining the process of determining whether or not a wafer has popped out when one of the cameras fails. In addition, illustration of the slit light irradiated from the illumination optical system 9B is abbreviate | omitted here.

  In FIG. 11, a wafer W1 is a wafer stored at a normal position in the FOUP 8, and a wafer W2 is a wafer protruding from the FOUP 8 by a predetermined distance.

  For example, the illumination optical system 9A is disposed on the left side of the camera 2L (outside the epipolar plane 76 described in FIG. 9), and the illumination optical system 9C is disposed on the right side of the camera 2R (outside the epipolar plane 76 described in FIG. 9). Place it in. The illumination optical systems 9A and 9C may be disposed at any position other than on the optical axes of the cameras 2L and 2R.

  Thereby, in the case of the wafer W1, the slit light 27L from the illumination optical system 9A is reflected by the measurement target point 81L of the wafer W1 and imaged at the pixel position 83L on the left image plane. Similarly, in the case of the wafer W1, the slit light 27R from the illumination optical system 9C is reflected by the measurement target point 81R of the wafer W1 and imaged at the pixel position 83R on the right image plane.

  In the case of the wafer W2, the slit light 27L from the illumination optical system 9A is reflected by the measurement target point 82L of the wafer W2 and imaged at the pixel position 84L on the left image plane. Similarly, in the case of the wafer W2, the slit light 27R from the illumination optical system 9C is reflected by the measurement target point 82R of the wafer W2 and imaged at the pixel position 84R on the right image plane.

  As described above, the pixel position serving as the measurement point on the image plane is shifted between the position of the wafer W being the position of the wafer W1 and the case of being the position of the wafer W2. Specifically, when the slit light 27L is irradiated onto the wafers W1 and W2, the pixel position 83L and the pixel position 84L are shifted by the inter-pixel distance a1. Similarly, when the slit light 27R is irradiated onto the wafers W1 and W2, the pixel position 83R and the pixel position 84R are shifted by the inter-pixel distance a2.

  For this reason, in this embodiment, the presence / absence of the protrusion of the wafer W is determined based on the inter-pixel distance a1 or the inter-pixel distance a2. Specifically, a threshold for the inter-pixel distance is set in advance as a threshold for the pop-out distance, and a reference pixel position is set in advance. Then, the wafer jump-out determination unit 18 calculates the inter-pixel distances a1 and a2 by comparing the pixel position imaged by one of the cameras 2L and 2R with the reference pixel position. Further, the wafer pop-out determination unit 18 determines whether or not the pop-out distance is within an allowable range based on the threshold of the inter-pixel distance and the inter-pixel distances a1 and a2.

  When setting the threshold of the inter-pixel distance and the reference pixel position, the FOUP 8 and the wafer W are set on the FOUP mounting table 7 so that the wafer W does not protrude from the FOUP 8. Thereafter, the reflected light when the slit light irradiated from the illumination optical systems 9A and 9C is incident in the direction perpendicular to the circumferential tangential direction (horizontal direction) of the wafer W is imaged by the cameras 2L and 2R. deep. The pixel position of the reflected light imaged here becomes the reference pixel position (the position of the test image data). The reference pixel position is set for each of the cameras 2L and 2R.

  In addition, the inter-pixel distance corresponding to the allowable range of the pop-out distance is calculated. Then, the calculated inter-pixel distance is set as a threshold for the inter-pixel distance. The threshold for the inter-pixel distance is set for each of the cameras 2L and 2R.

  Note that the threshold of the inter-pixel distance may be set by another method. For example, the wafer W is set at an allowable limit protruding position, and the reflected light reflected from the wafer W in this state is imaged by the cameras 2L and 2R. The pixel position of the reflected light imaged here becomes the pixel position at the allowable limit. In this case, the difference between the reference pixel position and the permissible limit pixel position is set as a threshold for the inter-pixel distance.

  When determining whether or not the wafer W has popped out, a camera image is picked up by the same method as in the case of setting a threshold for the distance between pixels. Specifically, when the camera 2L fails, the reflected light of the slit light is imaged by the camera 2R. Then, the wafer pop-out determination unit 18 determines whether or not the wafer W has popped out using the pixel position of the reflected light imaged and the threshold value of the inter-pixel distance and the reference pixel position set in the camera 2R. .

  Similarly, when the camera 2R fails, the reflected light of the slit light is imaged by the camera 2L. Then, the wafer pop-out determination unit 18 determines whether or not the wafer W has popped out using the pixel position of the captured reflected light and the threshold value of the inter-pixel distance and the reference pixel position set in the camera 2L. .

  It should be noted that the image of any detection region among the detection regions 52A to 52C may be used for the presence / absence determination of the wafer W. For example, when the presence / absence determination of the wafer W is performed using the camera 2L, the detection region 52A is used, and when the presence / absence determination of the wafer W is performed using the camera 2R, the detection region 52C is used.

  Here, the operation timing of the semiconductor manufacturing apparatus 100X will be described. FIG. 12 is a diagram illustrating the operation timing of the semiconductor manufacturing apparatus. FIG. 12 shows a timing chart for the operations of the process chambers 35 to 37, the loading / unloading unit 38, the transfer robot 4, and the wafer mapping mechanism 1X.

  The transfer robot 4 is a transfer robot on the atmosphere side, and transfers the wafer W in the FOUP 8 to the loading / unloading unit 38 of the process processing mechanism 5. The wafer W is Air Locked at the loading / unloading unit 38. While the wafer W is Air Locked, evacuation is performed in the loading / unloading unit 38. During this period, the wafer W cannot be transferred to the loading / unloading unit 38 by the transfer robot 4. For this reason, the transfer of the wafer W to the loading / unloading unit 38 by the transfer robot 4 and the Air Lock (evacuation) in the loading / unloading unit 38 are alternately performed.

  After the evacuation is completed, the wafer W is transferred to one of the process chambers 35 to 37 by the vacuum side transfer robot. And in the process chambers 35-37, after the wafer W is carried in, the process (wafer processing) to the wafer W is performed.

  In the present embodiment, wafer mapping and wafer W transfer processing are performed at independent timings. For this reason, the wafer mapping may be performed at any timing. In other words, the wafer mapping is performed without waiting for the completion of the transfer of the wafer W, and the wafer W is transferred without waiting for the completion of the wafer mapping.

  By the way, when the wafer mapping cannot be performed during the transfer of the wafer W, it is necessary to perform the wafer mapping at a timing other than during the transfer of the wafer W. For this reason, the wafer mapping is performed after the completion of the transfer of the wafer W. Further, it is necessary to carry the wafer W at a timing other than wafer mapping. For this reason, the wafer W is transferred after the completion of the wafer mapping.

  If the wafer loading mechanism 3 has a plurality of FOUP mounting tables 7 and a plurality of FOUPs 8 can be set on the wafer loading mechanism 3, the inside of the plurality of FOUPs 8 may be imaged by one camera.

  FIG. 13 is a diagram illustrating an arrangement example of cameras when a plurality of FOUPs are set in the wafer loading mechanism. When the wafer load mechanism 3 has a plurality of FOUP mounting tables 7A to 7C, the FOUP mounting table 7A has the FOUP 80A mounted thereon, the FOUP mounting table 7B has the FOUP 80B mounted thereon, and the FOUP mounting table 7C has a FOUP mounting table 7C mounted thereon. A FOUP 80C is placed.

  In this case, two cameras are imaged with one camera. For example, the wafer 2 in the FOUP 80A is imaged by the camera 2A and the camera 2B, the wafer W in the FOUP 80B is imaged by the camera 2B and the camera 2C, and the wafer W in the FOUP 80C is imaged by the camera 2C and the camera 2D.

  The positional relationship between the cameras 2A and 2B and the FOUP 80A, the positional relationship between the cameras 2B and 2C and the FOUP 80B, and the positional relationship between the cameras 2C and 2D and the FOUP 80C are the same as the positional relationship between the cameras 2L and 2R and the FOUP 8, respectively.

  When manufacturing a semiconductor device (semiconductor integrated circuit), the FOUP 8 is set in various semiconductor manufacturing apparatuses, and wafer processing is performed in each semiconductor manufacturing apparatus. Specifically, a film is formed on the wafer W by a film forming apparatus, and a resist is applied to the wafer W by a resist coating apparatus. Then, the exposure apparatus exposes the wafer W using a mask. Thereafter, the developing device develops the wafer W to form a resist pattern on the wafer W. Then, the etching apparatus etches the lower layer side of the wafer W using the resist pattern as a mask. Thereby, an actual pattern corresponding to the resist pattern is formed on the wafer W. When manufacturing a semiconductor device, a film formation process, a resist coating process, an exposure process, a development process, an etching process, and the like are repeated for each layer.

  Next, the hardware configuration of the wafer mapping apparatus 10X will be described. FIG. 14 is a diagram illustrating a hardware configuration of the wafer mapping apparatus. The wafer mapping apparatus 10X includes a CPU (Central Processing Unit) 91, a ROM (Read Only Memory) 92, a RAM (Random Access Memory) 93, a display unit 94, and an input unit 95. In the wafer mapping apparatus 10X, these CPU 91, ROM 92, RAM 93, display unit 94, and input unit 95 are connected via a bus line.

  The CPU 91 determines a pattern using a wafer mapping program 97 which is a computer program. The display unit 94 is a display device such as a liquid crystal monitor, and displays the camera image, wafer presence / absence information, cross slot information, wafer pop-out information, and the like shown in FIG. 7B based on an instruction from the CPU 91. The input unit 95 includes a mouse and a keyboard, and inputs instruction information (such as parameters necessary for detecting the storage state of the wafer W) externally input by the user. The instruction information input to the input unit 95 is sent to the CPU 91.

  The wafer mapping program 97 is stored in the ROM 92 and loaded into the RAM 93 via the bus line. FIG. 14 shows a state in which the wafer mapping program 97 is loaded into the RAM 93.

  The CPU 91 executes a wafer mapping program 97 loaded in the RAM 93. Specifically, in the wafer mapping apparatus 10X, the CPU 91 reads the wafer mapping program 97 from the ROM 92 and expands it in the program storage area in the RAM 93 in accordance with an instruction input from the input unit 95 by the user, and executes various processes. . The CPU 91 temporarily stores various data generated during the various processes in a data storage area formed in the RAM 93.

  The wafer mapping program 97 executed by the wafer mapping apparatus 10X includes a wafer detection method determination unit 12, a measurement point extraction unit 13, a wafer presence / absence determination unit 15, a cross slot determination unit 16, a wafer jump distance calculation unit 17, and a wafer jump determination unit. The module configuration includes 18, which are loaded onto the main storage device and are generated on the main storage device.

  In the present embodiment, the illumination optical systems 9A to 9C are described as being arranged above the cameras 2L and 2R or outside the cameras 2L and 2R. However, the illumination optical systems 9A to 9C are located at any position. You may arrange. Moreover, although the case where the three illumination optical systems 9A to 9C are arranged has been described, two illumination optical systems 9A and 9C may be arranged.

  In the present embodiment, when one of the cameras 2L and 2R fails, the wafer W pops out based on the inter-pixel distance that is the distance between the measured pixel position and the reference pixel position. Although the presence or absence is determined, the jumping distance of the wafer W may be calculated based on the inter-pixel distance. In this case, the correspondence between the inter-pixel distance and the protrusion distance of the wafer W is set in advance. Then, the wafer jump-out distance calculation unit 17 calculates the jump-out distance of the wafer W based on the calculated inter-pixel distance and the correspondence relationship. In this embodiment, the slit light is applied to the wafer W, but normal illumination light that does not pass through the slit may be applied to the wafer W.

  In the present embodiment, the wafer mapping apparatus 10X and the control apparatus 30X are configured separately, but the wafer mapping apparatus 10X may be provided in the control apparatus 30X. FIG. 15 is a top view illustrating another configuration example of the semiconductor manufacturing apparatus according to the embodiment. Note that, among the constituent elements in FIG. 15, the constituent elements that achieve the same functions as those of the semiconductor manufacturing apparatus 100X shown in FIG.

  The semiconductor manufacturing apparatus 100Y includes a wafer loading mechanism 3, a wafer mapping mechanism 1Y, a process processing mechanism 5, and a control device 30Y. The wafer mapping mechanism 1Y has cameras 2L, 2R and illumination optical systems 9A, 9B, 9C, and the control device 30Y has a wafer mapping device 10Y. Further, the wafer mapping apparatus 10Y has the same function as the wafer mapping apparatus 10X.

  In the control device 30Y, when the process processing control device that controls the process processing mechanism 5 and the wafer load control device that controls the wafer load mechanism 3 have different configurations, the wafer mapping device 10Y includes a process processing control device and It may be incorporated in any of the wafer load control devices.

  The control device 30Y includes process processing control software (program) for controlling the process processing mechanism 5, and the wafer mapping device 10Y may be mounted (software mounting) in the process processing control software.

  The control device 30Y includes wafer load control software (program) for controlling the wafer load mechanism 3, and the wafer mapping device 10Y may be mounted (software mounting) in the wafer load control software.

  Thus, in this embodiment, the semiconductor manufacturing apparatus 100X includes two or more cameras and an illumination optical system, and performs wafer mapping using triangulation by image processing. And wafer mapping processing can be separated. Thereby, wafer mapping can be performed without stopping the transfer of the wafer W. Therefore, in the semiconductor manufacturing apparatus 100X, the wafer processing throughput can be improved even when the transfer of the wafer W controls the wafer processing.

  In addition, even when a failure or trouble occurs in one of the cameras by holding the captured camera image (test image data) with 25 wafers W stored in the FOUP 8 in advance. The stored state of the wafer W can be acquired by performing pattern matching between the other camera image and the test image data. Thereby, even when triangulation cannot be performed, the acquisition function of the wafer storage state can be maintained, and as a result, the downtime of the semiconductor manufacturing apparatus 100X can be reduced.

  In the present embodiment, since the presence / absence of the wafer W is detected by image processing, the presence / absence of the wafer in each slot can be detected at high speed in units of lots. In addition, since wafer mapping is performed using image processing, it is possible to detect the presence / absence of the cross slot and the protrusion of the wafer W simultaneously with the presence / absence detection of the wafer W.

  As described above, according to the embodiment, wafer mapping is performed using image processing, and when a failure / trouble occurs in one camera, the presence or absence of the wafer W is detected using the other camera. It is possible to detect at high speed and reliably whether or not W has jumped out of the FOUP 8.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1X, 1Y ... Wafer mapping mechanism, 2L, 2R ... Camera, 3 ... Wafer loading mechanism, 4 ... Transfer robot, 5 ... Process processing mechanism, 9A-9C ... Illumination optical system, 10X, 10Y ... Wafer mapping device, 12 ... Wafer Detection method determination unit, 13 ... measurement point extraction unit, 15 ... wafer presence / absence determination unit, 16 ... cross slot determination unit, 17 ... wafer projection distance calculation unit, 18 ... wafer projection determination unit, 25L, 25R ... reflected light, 26A- 26C, 81L, 81R, P ... measurement target point, 27L, 27R, 51A to 51C ... slit light, 30X, 30Y ... control device, 34 ... wafer removal position controller, 52A-52C ... detection area, 53P, Pl, Pr ... measurement point, 61 ... determination area, 73L, 73R ... left image plane, 83L, 83R, 84 , 84R, L, R ... pixel positions, 100X, 100Y ... semiconductor manufacturing device, a1, a2 ... inter-pixel distance, W, W1, W2 ... wafer

Claims (6)

Linear slit light that intersects perpendicularly to the longitudinal direction of the side surface of the wafer in a state where the storage container storing the wafer is mounted on the mounting table is transmitted from the opening side of the storage container to the side surface of each wafer. An illumination optical system that irradiates multiple locations;
A first imaging unit arranged at a first position and imaging a side surface of the wafer irradiated with the linear slit light;
A second imaging unit arranged at a second position and imaging a side surface of the wafer irradiated with the linear slit light;
The storage state of the wafer in the storage container is detected using at least one of the first captured image captured by the first imaging unit and the second captured image captured by the second imaging unit. A storage state detector that performs
With
The storage state detector
When both the first captured image and the second captured image are captured, the triangulation method is used to triangulate the wafer with the first captured image and the second captured image. Calculate the amount of protrusion from the containment vessel,
When only one of the first captured image and the second captured image is captured, the reflected light of the linear slit light is combined on the image plane based on the captured image. A wafer mapping apparatus, wherein a determination is made as to whether or not the wafer has jumped out of the storage container by comparing an image forming position to be imaged with a reference position of the image forming position.   The storage state detection unit detects in which slot in the storage container the wafer is stored using at least one of the first captured image and the second captured image. The wafer mapping apparatus according to claim 1.   The storage state detection unit detects presence or absence of a wafer stored across a plurality of slots in the storage container using at least one of the first captured image and the second captured image. The wafer mapping apparatus according to claim 1, wherein:   The storage state detection unit performs image processing on an image region in the vicinity of a position where reflected light of the linear slit light is detected in the image region of the first or second captured image, thereby the wafer. The wafer mapping apparatus according to claim 1, wherein a storage state of the storage container in the storage container is detected. Linear slit light that intersects perpendicularly to the longitudinal direction of the side surface of the wafer in a state where the storage container storing the wafer is mounted on the mounting table is transmitted from the opening side of the storage container to the side surface of each wafer. An illumination step for illuminating multiple locations;
The first imaging unit disposed at the first position images the side surface of the wafer irradiated with the linear slit light, and the second imaging unit disposed at the second position includes the line. An imaging step of imaging the side surface of the wafer irradiated with the slit-shaped slit light;
The storage state of the wafer in the storage container is detected using at least one of the first captured image captured by the first imaging unit and the second captured image captured by the second imaging unit. A storage state detection step to perform,
Including
The storage state detection step includes:
When both the first captured image and the second captured image are captured, the triangulation method is used to triangulate the wafer with the first captured image and the second captured image. Calculate the amount of protrusion from the containment vessel,
When only one of the first captured image and the second captured image is captured, the reflected light of the linear slit light is combined on the image plane based on the captured image. A wafer mapping method characterized by determining whether or not the wafer has jumped out of the storage container by comparing an imaging position to be imaged with a reference position of the imaging position. 6. The wafer mapping method according to claim 5, further comprising: a transfer step of taking out the wafer from a position corresponding to the pop-out amount when the pop-out amount is calculated.

Images