JP2012530966A - コンパクトな演算処理要素を用いたプロセッシング - Google Patents

コンパクトな演算処理要素を用いたプロセッシング Download PDF

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JP2012530966A
JP2012530966A JP2012516227A JP2012516227A JP2012530966A JP 2012530966 A JP2012530966 A JP 2012530966A JP 2012516227 A JP2012516227 A JP 2012516227A JP 2012516227 A JP2012516227 A JP 2012516227A JP 2012530966 A JP2012530966 A JP 2012530966A
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processing
precision
input
processor
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JP2012530966A5 (cg-RX-API-DMAC10.html
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ベイツ、ジョゼフ
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シンギュラー コンピューティング、エルエルシー
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/4833—Logarithmic number system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/5235—Multiplying only using indirect methods, e.g. quarter square method, via logarithmic domain
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
  • Image Processing (AREA)
  • Multi Processors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2012516227A 2009-06-19 2010-06-16 コンパクトな演算処理要素を用いたプロセッシング Pending JP2012530966A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US21869109P 2009-06-19 2009-06-19
US61/218,691 2009-06-19
US12/816,201 2010-06-15
US12/816,201 US8150902B2 (en) 2009-06-19 2010-06-15 Processing with compact arithmetic processing element
PCT/US2010/038769 WO2010148054A2 (en) 2009-06-19 2010-06-16 Processing with compact arithmetic processing element

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JP2012530966A true JP2012530966A (ja) 2012-12-06
JP2012530966A5 JP2012530966A5 (cg-RX-API-DMAC10.html) 2014-06-19

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JP2012516227A Pending JP2012530966A (ja) 2009-06-19 2010-06-16 コンパクトな演算処理要素を用いたプロセッシング
JP2014077372A Active JP6184897B2 (ja) 2009-06-19 2014-04-03 コンパクトな演算処理要素を用いたプロセッシング
JP2017144389A Active JP6371451B2 (ja) 2009-06-19 2017-07-26 コンパクトな演算処理要素を用いたプロセッシング
JP2018132055A Active JP6599522B2 (ja) 2009-06-19 2018-07-12 コンパクトな演算処理要素を用いたプロセッシング
JP2019182315A Active JP6796177B2 (ja) 2009-06-19 2019-10-02 コンパクトな演算処理要素を用いたプロセッシング
JP2020189077A Active JP7273018B2 (ja) 2009-06-19 2020-11-13 コンパクトな演算処理要素を用いたプロセッシング
JP2022200644A Active JP7565998B2 (ja) 2009-06-19 2022-12-15 コンパクトな演算処理要素を用いたプロセッシング
JP2024172506A Pending JP2025004087A (ja) 2009-06-19 2024-10-01 コンパクトな演算処理要素を用いたプロセッシング
JP2026071571A Pending JP2026116339A (ja) 2009-06-19 2026-04-23 コンパクトな演算処理要素を用いたプロセッシング

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JP2017144389A Active JP6371451B2 (ja) 2009-06-19 2017-07-26 コンパクトな演算処理要素を用いたプロセッシング
JP2018132055A Active JP6599522B2 (ja) 2009-06-19 2018-07-12 コンパクトな演算処理要素を用いたプロセッシング
JP2019182315A Active JP6796177B2 (ja) 2009-06-19 2019-10-02 コンパクトな演算処理要素を用いたプロセッシング
JP2020189077A Active JP7273018B2 (ja) 2009-06-19 2020-11-13 コンパクトな演算処理要素を用いたプロセッシング
JP2022200644A Active JP7565998B2 (ja) 2009-06-19 2022-12-15 コンパクトな演算処理要素を用いたプロセッシング
JP2024172506A Pending JP2025004087A (ja) 2009-06-19 2024-10-01 コンパクトな演算処理要素を用いたプロセッシング
JP2026071571A Pending JP2026116339A (ja) 2009-06-19 2026-04-23 コンパクトな演算処理要素を用いたプロセッシング

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US (20) US8150902B2 (cg-RX-API-DMAC10.html)
EP (3) EP3410291B1 (cg-RX-API-DMAC10.html)
JP (9) JP2012530966A (cg-RX-API-DMAC10.html)
KR (1) KR101235997B1 (cg-RX-API-DMAC10.html)
CN (2) CN105760135B (cg-RX-API-DMAC10.html)
BR (1) BRPI1011808A2 (cg-RX-API-DMAC10.html)
CA (1) CA2768731C (cg-RX-API-DMAC10.html)
WO (1) WO2010148054A2 (cg-RX-API-DMAC10.html)

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JP2014199665A (ja) * 2009-06-19 2014-10-23 シンギュラー コンピューティング、エルエルシー コンパクトな演算処理要素を用いたプロセッシング
CN105843586A (zh) * 2016-04-02 2016-08-10 严发宝 一种高速数据采集实时加除计算实现方法
WO2024247749A1 (ja) * 2023-06-01 2024-12-05 ソニーセミコンダクタソリューションズ株式会社 演算装置、信号処理装置及び信号処理回路

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