JP2012508980A - Off-center deposition of organic semiconductors in organic semiconductor devices - Google Patents

Abstract

  The present disclosure provides a method of making a thin film semiconductor device such as a transistor, the method comprising: a) providing a substrate (60) that supports first and second conductive zones (10, 20). Wherein the first and second conductive zones (10, 20) define a channel (50) therebetween, which channel (50) is connected to any of the conductive zones (10, 20). And b) depositing individual aliquots of the solution containing the organic semiconductor (40) adjacent to or on the channel (50) The majority of the solution being deposited on one side of the channel (50) rather than on the channel (50). In some embodiments of the present disclosure, the solution is deposited entirely on one side of the channel (50) rather than on the channel (50), and further, the solution is in a band having a length less than the channel length. Is deposited. The present disclosure further provides thin film semiconductor devices such as transistors.

Description

  The present invention relates to the manufacture of organic semiconductor devices by ink jet printing or similar fluid deposition processes and devices so made.

  In recent years, research efforts aimed at using organic materials as semiconductors rather than conventional inorganic materials such as silicon and gallium arsenide have been made ever more. Among other advantages, the use of organic materials can reduce the cost of manufacturing electronic devices and can achieve a wide range of applications, including display backplanes, integrated circuit RFID tags, In addition, a flexible substrate can be used as a support for the electronic circuit of the sensor.

  Various organic semiconductor materials have been studied, and the most common are condensed aromatic ring compounds represented by acenes. At least some of these organic semiconductor materials have performance characteristics such as charge carrier mobility, on / off current ratio, and subthreshold voltage that are equal to or greater than amorphous silicon-based devices. . These materials are often deposited because they are not very soluble in most solvents. When organic semiconductors are deposited from a solution (such as in a solution with an organic solvent), good or optimal performance characteristics have been difficult to achieve.

  US Pat. No. 6,690,029 B1 discloses a substituted pentacene and an electronic device made using the substituted pentacene.

  WO 2005/055248 A2 discloses certain substituted pentacenes and polymers used in top gate thin film transistors.

  US patent application Ser. No. 11 / 275,366, filed Dec. 28, 2005, the disclosure of which is incorporated herein by reference, generally discloses a fully ink-jet printed thin film transistor and methods for making and using the same. References that may be applicable to inkjet printing of organic semiconductors include Lim et al., “Self-Organization of Ink-jet. Ink-printed triisopropylsilylethynylpentacene by evaporation-induced flow in dry droplets. -Printed Triisopropylsilylethynyl Pentacene via Evaporation-Induced Flows in a Drying Droplet), Advanced Materials (Adv. Funct. Mater.), 2008, 18, pages 229-234.

  Several organic device materials have also been reported that use unique device shapes, such as concentric rings or Corbino shapes. References that may fall under such technology include Klauk et al., “Pentacene Organic Thin-Film Transistors for Circuits and Display Applications”, IEEE Electronic Devices Bulletin (IEEE Transactions on Electron Devices, Vol. 46, No. 6 (Vol. 46, No. 6), June 1999, pages 1258 to 1263, and Meijer et al., “Dopant density measurement in disordered organic field effect transistors”. determination in disordered organic field-effect transistors), J. App. Physics, Vol. 93, No. 8 (Vol. 93, No. 8), April 15, 2003, pages 4831-4835. .

  US patent application Ser. No. 11/275367, filed Dec. 28, 2005, the disclosure of which is incorporated herein by reference, generally discloses a thin film transistor having a bottom-gate shape and methods for making and using the same. is there.

  US Provisional Application No. 61/057715 filed May 30, 2008, the disclosure of which is incorporated herein by reference, generally refers to silylethynylpentacene, silylethynylpentacene-containing compositions, and silylethynylpentacenes. For example, a method of manufacturing as an organic semiconductor and a method of using the same are disclosed.

  US Provisional Application No. 61/060595, filed June 11, 2008, the disclosure of which is incorporated herein by reference, generally discloses the use of a mixed solvent system to deposit organic semiconductors. .

  US Provisional Application No. 61/076186, filed June 27, 2008, the disclosure of which is incorporated herein by reference, generally describes a method for growing an organic semiconductor layer, a method for fabricating an organic semiconductor device, and thereby The layers and devices that are formed are disclosed.

  The present disclosure provides a method of making a thin film semiconductor device, the method comprising: a) providing a substrate that supports first and second conductive zones, the first and second The conductive zones define a channel therebetween, the channel demarcating no more than 75% around any conductive zone, and in some embodiments, no more than 50%. And b) depositing individual aliquots of a solution containing an organic semiconductor adjacent to or on the channel, the aliquot providing the organic semiconductor to a single thin film semiconductor device, The process includes depositing on one side of the channel rather than on the channel. In some embodiments, the boundary between the channel and each of the conductive zones is substantially straight and substantially parallel. In some embodiments, the thin film semiconductor device is a transistor, the first conductive zone is a source, and the second conductive zone is a drain. In some embodiments, over 60% of the solution, in some embodiments over 70%, in some embodiments over 80%, in some embodiments over 90%, some In embodiments, 100% is deposited on one side of the channel rather than on the channel. In some embodiments, individual aliquots are deposited in the form of a plurality of droplets, typically by ink jet printing. In some such embodiments, at least 60% of the droplets, in other embodiments at least 70%, in other embodiments at least 80%, in other embodiments at least 90%, other In embodiments, 100% is deposited on one side of the channel rather than on the channel. In some embodiments, individual aliquots of the solution containing the organic semiconductor are wetted after deposition and then have a length no greater than 10 times the channel length. In some embodiments, individual aliquots of a solution containing an organic semiconductor are deposited in a band having a length less than the channel length.

  In some embodiments of the present disclosure, individual aliquots of a solution containing an organic semiconductor are deposited on one side of the channel entirely rather than on the channel, and the solution has a length less than the channel length. Deposited in the band. Such a method not only works effectively, but also results in improved results.

  The present disclosure further provides a thin film semiconductor device, wherein the thin film semiconductor device is a) a substrate supporting first and second conductive zones, the first and second conductive zones comprising A substrate that defines no more than 75% around any conductive zone, and in some embodiments more than 50%, and b) the channel A discrete semiconductor layer with an organic semiconductor located on and adjacent to the channel, acting as a single thin film semiconductor device, with the majority of the discrete semiconductor layer being on one side of the channel rather than on the channel And a semiconductor layer. In some embodiments, the boundary between the channel and each of the conductive zones is substantially straight and substantially parallel. In some embodiments, the thin film semiconductor device is a transistor, the first conductive zone is a source, and the second conductive zone is a drain. In some embodiments, the device further comprises a gate and a dielectric layer. In some embodiments, over 55% of individual semiconductor layers, in other embodiments over 60%, in other embodiments over 65%, in other embodiments over 70%, other implementations More than 75% in the form and more than 80% in other embodiments are on one side of the channel rather than on the channel. In some embodiments, the individual semiconductor layers have a length no greater than 10 times the channel length.

  The present disclosure provides a method of fabricating a pair of thin film semiconductor devices, the method comprising: a) providing a substrate, the substrate comprising i) first and second conductive zones. A first and second conductive zone defined by a first channel therebetween; and ii) a third and fourth conductive zone between the second channel Supporting the third and fourth conductive zones defining b), b) separate aliquots of the solution containing the organic semiconductor adjacent to the first and second channels or the first and Depositing on the second channel, wherein the aliquot provides the organic semiconductor to exactly two single thin film semiconductor devices, and the majority of the solution is in the first channel rather than on the first channel. Most of the solution is deposited on one side and the second Not on channel are deposited on one side of the second channel, and a step.

  The present disclosure further provides a pair of thin film semiconductor devices, the pair of thin film semiconductor devices comprising: a) a substrate, and i) first and second conductive zones between them. And ii) a third and a fourth conductive zone defining a second channel therebetween, a third and a second conductive zone defining a first channel; A substrate supporting a fourth conductive zone; and b) a separate semiconductor layer comprising an organic semiconductor located on and adjacent to the first and second channels, Acts exactly as two single thin film semiconductor devices, most of the individual semiconductor layers are on one side of the first channel rather than on the first channel, and most of the individual semiconductor layers are second Present on one side of the second channel rather than on the other channel, And a another semiconductor layer.

2 is a photomicrograph of an inkjet printed thin film transistor according to the present disclosure, further described in Example 1. FIG. 2 is a schematic diagram of an inkjet printed thin film transistor according to the present disclosure based on the micrograph of FIG. A photomicrograph of a comparative inkjet-printed thin film transistor, further described in Comparative Example 2C. FIG. 2 is a photomicrograph of an all inkjet printed backplane, further described in Example 1. FIG. FIG. 6 schematically represents a matrix of pixels designed to inkjet print individual aliquots of organic semiconductor solution, further described in Example 1 and Comparative Example 2C. The graph which shows the value of the mobility of the transistor of Example 1 and Comparative Example 2C. The graph which shows the subthreshold voltage value of the transistor of Example 1 and Comparative Example 2C. The graph which shows the on / off electric current value of the transistor of Example 1 and Comparative Example 2C.

  The present disclosure provides a method of making a thin film semiconductor device, the method comprising: a) providing a substrate that supports first and second conductive zones, the first and second The conductive zones define a channel between them, the channel does not delimit more than 75% of the periphery of any conductive zone, and b) individual solutions of the organic semiconductor Depositing an aliquot of the organic semiconductor into a single thin film semiconductor device, with the majority of the solution being on one side of the channel rather than on the channel. And depositing a process. The present disclosure further provides a thin film semiconductor device, wherein the thin film semiconductor device is a) a substrate supporting first and second conductive zones, the first and second conductive zones comprising Defining a channel between the substrate and the channel does not delimit more than 75% around any conductive zone; and b) an organic semiconductor located on and adjacent to the channel Individual semiconductor layers that act as a single thin film semiconductor device, with the majority of the individual semiconductor layers comprising individual semiconductor layers that reside on one side of the channel rather than on the channel.

  The thin film device may be any suitable semiconductor device, including a diode, a triode such as a transistor, or other multi-terminal device. Most commonly, this device is a transistor. If the device is a transistor, the first conductive zone is typically a source electrode and the second conductive zone is typically a drain electrode. A transistor typically includes a gate electrode. A transistor typically includes a dielectric layer interposed between a gate and a semiconductor layer.

  This thin film device is disclosed in U.S. Patent Application No. 11/275367, filed December 28, 2005, the disclosure of which is incorporated herein by reference, top contact / bottom gate, bottom contact / bottom gate, top It may have any suitable shape, including contact / top gate or bottom contact / top gate shapes. In some embodiments, the thin film device has a top contact / bottom gate shape. In some embodiments, the thin film device has a bottom contact / bottom gate shape. In some embodiments, the thin film device has a top contact / top gate shape. In some embodiments, the thin film device has a bottom contact / top gate shape.

  Referring to FIG. 2, in some embodiments, a device according to the present disclosure includes a channel 50 having a length A and a width B, the channel 50 being bounded by two conductive zones 10 and 20. ing. It should be noted that, according to standard terminology in the art, the term “length” means that the distance between the conductive zones is the smaller dimension of the channel, ie smaller than “width”. However, it refers to the distance between the conductive zones. If the device is a transistor, these conductive zones 10 and 20 are typically source and drain electrodes. In the embodiment shown in FIG. 2, the device is configured on a substrate 60 in a bottom contact / bottom gate configuration. In this configuration, the conductive layer patterned to form gate 30 is patterned to form a dielectric layer (transparent in FIG. 1 and thus invisible in FIG. 2), source 10 and drain 20. Following the formed second conductive layer and finally the individual semiconductor layer 40, it is applied to the substrate 60.

  Referring to FIG. 2, channel length A is the distance across channel 50 from one conductive zone 10 to another conductive zone 20. In general, the channel length is substantially constant. In some embodiments, the substantially constant channel length is constant in the design and varies only with variations in material and external conditions. In some embodiments, the substantially constant channel length is ± 25% from a constant value, in other embodiments ± 20%, in other embodiments ± 15%, in other embodiments ± 10%, in other embodiments ± 5%, in other embodiments ± 2.5%, and in other embodiments ± 1%.

  Referring to FIG. 2, the individual semiconductor layer 40 has a length C that is approximately five times the channel length A. It should be noted that the term “length” means that the dimension of the individual semiconductor layer 40 parallel to the length direction of the channel is the smaller dimension of the individual semiconductor layer 40, ie, “width”. Even when it is small, it refers to the dimension of the individual semiconductor layer 40 parallel to the length direction of the channel. In some embodiments, the length C of the individual semiconductor layer 40 is between 2 and 50 times the channel length A. In some embodiments, the length C of the individual semiconductor layer 40 is 3 to 20 times the channel length A. In some embodiments, the length C of the individual semiconductor layer 40 is 4 to 10 times the channel length A.

  In some embodiments, the channel width is taken so that the channel has a substantially constant channel length throughout its width. In some embodiments, the channel width is taken so that the channel covers the gate electrode throughout its width. In some embodiments, the channel width is taken so that the channel is occupied by the semiconductor material throughout its width. In some embodiments, the channel width is taken so that the channel meets a certain combination of the previous conditions throughout its width. In some embodiments, including the embodiment shown in FIG. 2, the channel width B is such that the channel 50 covers the gate electrode 30 and has a substantially constant channel length A throughout its width. , And to be occupied by semiconductor materials. In the embodiment shown in FIG. 2, the channel width B terminates at the upper end where the channel 50 is not occupied by the semiconductor material, and the channel width B is a channel length where the channel 50 is substantially constant. It terminates at the lower end that does not have A.

  In some embodiments, the boundary between the channel 50 and each of the conductive zones 10 and 20 is substantially straight, substantially parallel, or substantially straight and substantially. Parallel to

  In this disclosure, conductive zones are distinguished from vias or conductive traces that can be electrically connected to the conductive zones. In some embodiments, the conductive zone may be defined as only the portion of the source or drain electrode that covers the gate electrode. The channel does not delimit more than 75% around any conductive zone. The channel of the device according to the present disclosure is one that does not form a concentric ring shape or a Corbino shape. In some embodiments, the channel does not delimit more than 60% around any conductive zone. In some embodiments, the channel does not delimit more than 50% around any conductive zone. In some embodiments, the channel does not delimit more than 40% around any conductive zone.

  Referring to FIG. 2, in some embodiments, a device according to the present disclosure comprises a separate semiconductor layer 40 comprising an organic semiconductor. The individual semiconductor layer 40 is located adjacent to or on the channel 50, and most of the individual semiconductor layer 40 exists on one side of the channel 50 instead of on the channel 50. As used herein, “one side” means one side of the channel, not just above the channel. In the embodiment shown in FIG. 2, it can be seen that the oval long axis centerline formed by the individual semiconductor layer 40 lies on the conductive zone 10 rather than on the channel 50, and thus Most are present on one side of the channel 50 rather than on the channel 50, that is, most of the lateral regions of the individual semiconductor layer 40 are on one side, and the lateral regions project onto a plane parallel to the substrate. You may conclude that this is In some embodiments, over 55% of individual semiconductor layers, in other embodiments over 60%, in other embodiments over 65%, in other embodiments over 70%, other implementations More than 75% in form, more than 80% in other embodiments, more than 85% in other embodiments, and more than 90% in other embodiments are present on one side of the channel rather than on the channel. It should be noted that in this measurement the channel is considered infinite with respect to width.

  In another embodiment, a separate semiconductor layer serves as each of the two back-to-back thin film semiconductor devices. In such embodiments, individual semiconductor layers are disposed between the channels of two back-to-back thin film semiconductor devices. With respect to each of the two channels, the majority of the individual semiconductor layers reside on one side of the channel rather than on the channel. In some embodiments, over 55% of the individual semiconductor layers, in other embodiments over 60%, in other embodiments over 65%, in other embodiments over 70%, other embodiments Is more than 75% in other embodiments, more than 80% in other embodiments, more than 85% in other embodiments, and more than 90% in other embodiments on one side of each channel rather than on each channel. In such embodiments, the individual semiconductor layers may later be separated into two parts, each serving as a device. This separation may be by any suitable means, including cutting or chopping with knives, lasers, etc., or chemical means to remove or non-conduct the central portion of the individual semiconductor layer. .

  The individual semiconductor layer includes an organic semiconductor material. US Patent No. 6,690,029, US Patent Application No. 11/275366, filed December 28, 2005, US Patent Application No. 11/275367, filed December 28, 2005, May 30, 2008 Any suitable organic semiconductor material may be used, including those described in US Provisional Application No. 61/057715, US Provisional Application No. 61/060595, filed June 11, 2008. Often, the disclosures of these patents, patent applications, and provisional patent applications are incorporated herein by reference. The semiconductor material may be a functionalized pentacene compound according to Formula I.

Each R ¹ is individually selected from H and CH ₃ and each R ² is a branched or unbranched linear or cyclic C2-C18 alkane, branched or unbranched C1-C18 alkyl alcohol, branched or unbranched, linear or cyclic C2~C18 alkenes, C4 -C8 aryl or heteroaryl, C5～C32 alkylaryl or alkylheteroaryl, ferrocenyl, or ^SiR ₃ is from ₃ those selected individually, each ^{R 3} Are individually selected from hydrogen, branched or unbranched C1-C10 alkanes, branched or unbranched linear or cyclic C1-C10 alkyl alcohols, or branched or unbranched C2-C10 alkenes. In general, each R ¹ is H. Generally, each R ² is SiR ³ ₃ . More generally, each R ² is SiR ³ ₃ and each R ³ is individually selected from a branched or unbranched linear or cyclic C1-C10 alkane or alkene. Most commonly, this compound is 6,13-bis (triisopropylsilylethynyl) pentacene (TIPS-pentacene) as shown in Formula II.

In some embodiments, each ^{R 2} is intended to be individually selected from _{^{-SiR 4 x R 5 y R 6}} z.

Each R ⁴ includes (i) a branched or unbranched substituted or unsubstituted C1-C8 alkyl group, (ii) a substituted or unsubstituted cycloalkyl group, or (iii) a substituted or unsubstituted cycloalkylalkylene 5 group. Each R ⁵ includes (i) a branched or unbranched substituted or unsubstituted C2-C8 alkenyl group, (ii) a substituted or unsubstituted cycloalkyl group, or (iii) a substituted or unsubstituted cycloalkylalkylene group. Each R ⁶ is (i) hydrogen, (ii) branched or unbranched substituted or unsubstituted C2-C8 alkynyl group, (iii) substituted or unsubstituted cycloalkyl group, (iv) substituted or unsubstituted cycloalkylalkylene A group, (v) a substituted aryl group, (vi) a substituted or unsubstituted arylalkylene group, (vii) A cetyl group or (viii) a substituted or unsubstituted heterocycle containing at least one of O, N, S and Se in the ring, x = 1 or 2, y = 1 or 2, z = 0 or 1 And (x + y + z) = 3.

  The individual semiconductor layers usually contain a compound of formula I or formula II in an amount of 0.1% to 99% by weight.

  In some embodiments, the individual semiconductor layers may include additional materials such as suitable polymers. In some embodiments, a polymer additive is greater than 1.0 at 1 kHz, more typically greater than 3.3, more typically greater than 3.5, more typically greater than 4.0. Has a dielectric constant. The polymer generally has a molecular weight of at least 1,000, more typically at least 5,000. Common polymers include poly (4-cyanomethylstyrene) and poly (4-vinylphenol). In some embodiments, cyanopullulan may be used.

  Common polymers also include those described in US Patent Publication No. 2004/0222412 A1, which is incorporated herein by reference. The polymers described herein include substantially non-fluorinated organic polymers having repeat units of the formula

Where
Each R ¹ is an organic group containing H, Cl, Br, I, an aryl group, or a crosslinkable group,
Each R ² is H, an aryl group, or R ⁴ , respectively;
Each R ³ is H or methyl,
Each R ⁵ is an alkyl group, halogen, or R ⁴ ;
Each R ⁴ is an organic group comprising at least one CN group and having a molecular weight of from about 30 to about 200 per CN group;
n = 0-3,
Provided that at least one repeat unit of the polymer comprises R ⁴ .

  Other polymers that can be used include polystyrene, poly (α-methylstyrene), poly (α-vinylnaphthalene), poly (vinyltoluene), polyethylene, cis-polybutadiene, polypropylene, polyisoprene, poly (4-methyl- 1-pentene), poly (4-methylstyrene), poly (chlorotrifluoroethylene), poly (2-methyl-1,3-butadiene), poly (p-xylylene), poly (α-α-α'- α′tetrafluoro-p-xylylene), poly [1,1- (2-methylpropane) bis (4-phenyl) carbonate], poly (cyclohexyl methacrylate), poly (chlorostyrene), poly (2,6-dimethyl) -1,4-phenylene ether), polyisobutylene, poly (vinylcyclohexane), poly (vinyl cinnamon) G), poly (4-vinyl biphenyl), poly (1,2-butadiene), polyphenylene, poly (methyl methacrylate), and polyvinyl phenol.

  Copolymers of the above materials can also be useful. For example, mention may be made of a polymer comprising styrene and α-methylstyrene, styrene, α-methylstyrene and butadiene. Both random copolymers or block copolymers can be used. Exemplary copolymers include poly (ethylene / tetrafluoroethylene), poly (ethylene / chlorotrifluoroethylene), fluorinated ethylene / propylene copolymer, polystyrene-co-α-methylstyrene, ethylene / ethyl acrylate copolymer, poly (styrene) / 10% butadiene), poly (styrene / 15% butadiene), poly (styrene / 2,4 dimethyl styrene), commercially available from Dow Chemical under the trademark TOPAS (all grades), etc. Cyclic olefin copolymers, branched or unbranched polystyrene-block-polybutadiene, polystyrene-block (polyethylene-ran-butylene) -block-polystyrene, polystyrene-block-polybutadiene-block-polystyrene Polystyrene- (ethylene-propylene) -diblock-copolymers (eg, KRATON-G1701E from Kraton Polymers US LLC of Houston, TX), poly (propylene-co-ethylene), and Poly (styrene-co-methyl methacrylate) can be mentioned, but is not limited thereto.

  Individual semiconductor layers may contain this polymer in an amount of 0 to 99.9 wt%, more typically 10 to 90 wt%, more typically 20 to 50 wt%.

  In the disclosed method, individual aliquots of a solution containing an organic semiconductor are deposited adjacent to or on the channel. In one general embodiment, each such aliquot provides an organic semiconductor to a single thin film semiconductor device.

  As noted above, any suitable organic semiconductor may be used.

  In some embodiments, the solution may further comprise a polymer as described above. In some embodiments, a semiconductor crystal growth solution is used as disclosed in US Provisional Application No. 61/076186, filed June 27, 2008, the disclosure of which is incorporated herein by reference. May be.

  Any suitable solvent may be used and these solvents can include ketones, aromatic hydrocarbons, and the like, and mixtures thereof. In general, the solvent is an organic solvent. In general, the solvent is an aprotic solvent. Suitable solvents include but are not limited to toluene, ethylbenzene, butylbenzene, chlorobenzene, dichlorobenzene, anisole, tetrahydronaphthalene, cyclohexanone, and mixtures thereof. In some single solvent embodiments, the solution contains at least 95% by weight of a single solvent.

  Mixed solvent systems may be used as disclosed in US Provisional Application No. 61/060595, filed June 11, 2008, the disclosure of which is incorporated herein by reference.

  Any suitable amount of organic semiconductor may be deposited by the disclosed method or may be present in the disclosed device. By increasing the amount, a thicker and / or more crystalline semiconductor layer can be produced in the final device. In some embodiments, the volume of individual aliquots of the solution containing the organic semiconductor is between 15 pL and 40 nL. In some embodiments, the volume of an individual aliquot of the solution containing the organic semiconductor is at least 15 pL, more typically at least 25 pL, more typically at least 50 pL, more typically at least 250 pL; In some embodiments, it is 500 pL or more. In some embodiments, the volume of individual aliquots of the solution containing the organic semiconductor is 40 nL or less, more typically 10 nL or less, more typically 4 nL or less, and more typically 1 nL or less.

  In the method of the present disclosure, individual aliquots of a solution containing an organic semiconductor may be deposited in any suitable manner. In some embodiments, this individual aliquot is deposited as a single drop or droplet. Such embodiments can include ink jet printing, micropipetting, flexographic printing, and the like. In some embodiments, this individual aliquot is deposited in the form of a plurality of droplets. Such embodiments can also include ink jet printing, micropipetting, flexographic printing, and the like.

  Inkjet printing for printing photographs, including multicolor photographs, is well known. Ink jet printing can accurately position very small drops of ink. In the practice of the present invention, any suitable ink jet printing system may be used, including thermal, piezoelectric, and continuous ink jet systems. Most commonly, piezoelectric ink jet systems are used. Inks useful for ink jet printing generally do not contain fine particles with a size greater than 500 nm, and more generally do not contain fine particles with a size greater than 200 nm.

  In the disclosed method, individual aliquots of a solution containing an organic semiconductor are deposited adjacent to or on the channel, with the majority of the solution being deposited on one side of the channel rather than on the channel. As used herein, the term “one side” means one side outside the channel. As used herein, the position of deposition is the initial position of deposition, regardless of subsequent flow or wetting. In some embodiments of the method according to the present disclosure, more than 55% of the solution is more than 60% in other embodiments, more than 65% in other embodiments, more than 70% in other embodiments, etc. More than 75% in other embodiments, more than 80% in other embodiments, more than 85% in other embodiments, more than 90% in other embodiments, more than 95% in other embodiments, Deposited on one side of the channel, not on the channel. In some embodiments, all solutions are deposited on one side of the channel rather than on the channel. Embodiments in which individual aliquots are deposited in the form of a plurality of droplets can include ink jet printing, but in those embodiments, more than 50% of the droplets and in other embodiments more than 55%. However, in other embodiments, over 60%, in other embodiments over 65%, in other embodiments over 70%, in other embodiments over 75%, other embodiments Greater than 80% in other embodiments, greater than 85% in other embodiments, greater than 90% in other embodiments, and greater than 95% in other embodiments are deposited on one side of the channel rather than on the channel. The In some embodiments, all droplets are deposited on one side of the channel rather than on the channel.

  In some embodiments of the method according to the present disclosure, individual aliquots of a solution containing an organic semiconductor have a length of about 5 times the channel length after deposition and wetting on the surface. In some embodiments, the length is 2 to 50 times the channel length. In some embodiments, the length is 3 to 20 times the channel length. In some embodiments, the length is 4 to 10 times the channel length.

  In some embodiments of the method according to the present disclosure, an inkjet print layer, such as a gate, dielectric, source / drain and semiconductor layer, is typically printed from an image consisting of a linear matrix of pixels, the linear matrix being an inkjet Define the deposition position of the deposition solution. In some embodiments of the method according to the present disclosure, the image of the deposition location of the solution containing the organic semiconductor has a length that is 0.05 to 5 times the channel length. It should also be noted here that the term “length” is parallel to the length of the channel, even if the image length of the deposition site is the smaller dimension, ie smaller than “width”. Refers to dimensions. In some embodiments of the method according to the present disclosure, the image of the deposition location of the solution containing the organic semiconductor has a length less than the channel length. In some embodiments of the method according to the present disclosure, the image of the deposition location of the solution containing the organic semiconductor has a length that is less than half the channel length. In some embodiments of the method according to the present disclosure, the image of the deposition position of the solution containing the organic semiconductor has a length of 0.1 to 0.9 times the channel length. In some embodiments of the method according to the present disclosure, the deposition location of the solution containing the organic semiconductor has a length of 0.05 to 5 times the channel length. In some embodiments of the method according to the present disclosure, the deposition location of the solution containing the organic semiconductor has a length less than the channel length. In some embodiments of the method according to the present disclosure, the deposition location of the solution containing the organic semiconductor has a length that is less than half of the channel length. In some embodiments of the method according to the present disclosure, the deposition position of the solution containing the organic semiconductor has a length of 0.1 to 0.9 times the channel length.

  Thus, from the above, in some embodiments of the method according to the present disclosure, the solution containing the organic semiconductor is deposited completely outside the channel and deposited in a band having a length less than the channel length. Will be.

  Objects and advantages of the present invention will be further illustrated by the following examples, but the specific materials and amounts described in these examples, as well as other conditions and details, should be construed to unduly limit the present invention. Should not.

  Unless otherwise noted, all reagents were obtained or available from Aldrich Chemical Co., Milwaukee, Wis. And may be synthesized by known methods.

(Examples 1 and 2C)
A sheet containing two backplanes was fabricated by inkjet printing all layers, ie, gate, dielectric, source / drain and semiconductor layers, onto a flexible polymer substrate by the process described below. Each backplane accommodated 8 columns × 15 rows of transistors (120 transistors in total) at a pitch of 3.0 mm. FIG. 4 is a digital photograph of one of the inkjet printed backplanes.

  The first backplane of the two backplanes, Example 1, is representative of the present disclosure, and the second backplane, Comparative Example 2C, is for comparison.

  From an image made with Adobe® Photoshop® (Adobe Systems, San Jose, Calif.), Each inkjet printed layer, ie, gate, dielectric, source / drain, and semiconductor layers. Printed. Each image was created as a linear matrix of pixels for use in a 702 dpi (276 pixels per cm) printing system. Thus, each pixel had an initial width of 36.2 micrometers.

  The source / drain layer images included transistor channels with a channel length of 6 pixels or 217 micrometers. Upon printing, the source / drain layer material was laterally wetted and the channel length was reduced to a length of about 128 micrometers in the printed backplane. The average measurement channel lengths of Examples 1 and 2C were 120 micrometers and 136 micrometers, respectively. The average measurement channel widths of Examples 1 and 2C were 780 micrometers and 910 micrometers, respectively.

  The image of the semiconductor layer was designed to deposit individual aliquots of organic semiconductor solution, each providing organic semiconductor to a single transistor. FIG. 5 schematically represents the semiconductor image used for each aliquot, which is 25 pixels wide and 2 pixels long, with 18 drops of organic semiconductor solution deposited on the backplane. 18 print pixels representing Each drop had a volume of 30 pL so as to have a total volume of 540 pL. When printed, this matrix of droplets wets laterally to form a single continuous deposit that is approximately oval in shape and has a width of about 1200 micrometers, It had a length of about 650 micrometers. These deposits are visible as translucent ovoids in both FIGS. 1 and 3 and are represented by reference numeral 40 in FIG. 2 based on FIG.

  In the backplane of Comparative Example 2C, the semiconductor image width is centered with respect to the overall channel width. FIG. 3 is a photomicrograph of a transistor in the backplane of Comparative Example 2C.

  In the backplane of Example 1, the width of the semiconductor image was offset by 5 pixels or about 180 micrometers from the center of the channel. This offset is not in the printing process but in the design of the semiconductor image itself. Therefore, the semiconductor solution was not deposited directly into the channel by ink jet printing. Instead, the printed droplet matrix wetted laterally to form a single continuous deposit that spread throughout the channel. 1 is a photomicrograph of one transistor in the backplane of Example 1. FIG.

  Examination of FIGS. 1 and 3 suggests that the edge of each deposit had a strong crystalline morphology and the center was amorphous. Therefore, the offset semiconductor deposit in Example 1 appears to place a substantial amount of crystalline material throughout the channel. Examination of FIGS. 1 and 3 suggests that the image of the rectangular semiconductor layer, resulting in an oval deposit of semiconductor material, exhibits stronger parallelism of the crystal structure on the longer side than on the shorter side. Is done. Accordingly, it is considered that a longer side is generated and the longer side is arranged over the entire channel in the same manner as in Example 1, so that a more parallel crystalline substance is arranged over the entire channel. As described in the quantitative test results following the process description below, the transistor of Example 1 showed dramatically improved fluidity compared to the transistor of Comparative Example 2C.

Process An 8 inch × 8 inch (20.3 cm × 20.3 cm) piece of Dupont Teonex® Q65 of 4 mil (0.1 mm) thick PEN film was secured between two pieces of stainless steel. These two pieces of stainless steel are clamped around the PEN film. These clamps help minimize PEN film shrinkage throughout the process. In order to reduce particle contamination and to provide a constant surface energy to the clean surface, both sides of the clamped PEN film were washed multiple times with absolute ethanol. After cleaning, the clamped film was secured with four screws to an XY deposition system on an aluminum vacuum table. After placing the clamped film in the system, the film was washed once more with ethanol.

  A Spectra-Dimatix SX3-128 printhead was then inserted into the system. The SX3-128 print head has 128 jets with a droplet volume of 10 pL. The print head was filled with about 20.0 mL of Cabot Ag-IJ-G-100-S1 silver conductor ink for inkjet. This material served as the gate layer for the backplane. After the print head was placed in the system, its height and saber angle were adjusted. The print head height was adjusted about 1.0 mm above the surface of the PEN film. The saber angle was adjusted to obtain the desired 702 dpi resolution. After they were completed, the substrates were aligned. The corner of the stainless steel clamp was used as the starting point or origin. A 1.0 inch (2.5 cm) offset was set in the negative x and y directions from the origin. This was the position at which the printhead began printing the conductive ink or gate layer pattern.

  Prior to application of the conductive ink, the substrate was pre-shrinked. The purpose of pre-shrinking the substrate was to improve alignment. As the film shrinks during heat curing of each layer, subsequent layer alignment is affected. This preshrink process involved heating the film from the bottom and top of the substrate. Heating from below was performed using an online hot plate set at 125 ° C. Heating from above the substrate was performed using a 500 watt / inch (196.9 watt / cm) infrared lamp. When the hot plate reached 125 ° C., the infrared lamp was scanned five times across the substrate at a speed of 2.0 inches / second (5.1 cm / second) and a power level of 100%. This process took 25 seconds and the maximum temperature of the substrate reached 140 ° C., which was recorded with an infrared pyrometer.

  After completion of the preshrink process, the substrate / aluminum platen was cooled to a temperature of 45 ° C. in preparation for the deposition of the silver gate layer. Printing the silver ink while the platen is at a high temperature prevents the silver ink from being excessively wet on the PEN film substrate. When the patterned gate layer was deposited on the substrate, the patterned gate layer was positioned at 45 ° C. for 5.0 minutes. This allowed the material to settle and thus form a more uniform layer for later deposition processes.

  After the silver was in place for 5 minutes, the silver was sintered with an online hot plate and an infrared lamp. The hot plate was set to 125 ° C., and then the pattern image was scanned 5 times with an infrared lamp at a speed of 2.0 inches / second (5.1 cm / second) at 100% power. The purpose of heating the substrate to 125 ° C. before sintering the silver with the infrared lamp was to reduce the sintering time. It took about 25 seconds to sinter the silver with an infrared lamp. After sintering the silver, the temperature of the hot plate was set to 150 ° C. The substrate was kept at this temperature for 10 minutes. The purpose of this step was to make sure that all solvents did not contain silver nanoparticle ink, 20% Ag, 40% ethanol and 40% ethylene glycol.

  The next layer in the fabrication of all inkjet printing backplanes was the dielectric layer. After the gate layer was heat cured, the SX3-128 print head was removed and replaced with a Spectra-Dimatix SE-128 print head. This print head was used for printing dielectric materials. The dielectric material was zirconia acrylate in isophorone. SE-128 has 128 jets and a droplet volume of 30 pL. The height was set about 1.0 mm above the substrate, and the saber angle was set so that a resolution of 702 dpi was obtained. The platen temperature was lowered to 26 ° C. If the dielectric layer is printed at a temperature that is too high, the wettability decreases. Insufficient wettability can cause holes in the dielectric layer, which can cause unwanted short circuits in the thin film transistor.

  Prior to printing the dielectric layer, a test print was performed to align the dielectric layer with respect to the pattern gate layer. This test print was compared to another test print printed with the gate layer. The measurement difference between the two test prints determined where the dielectric layer printing started.

  When alignment was complete, a blanket coating of dielectric material was printed over the gate layer. When printing was complete, the material was immediately dried, cured and dried again. A first drying process or pre-baking was performed using an online hot plate and an infrared lamp. When the hot plate reached a temperature of 75 ° C., the printed image was scanned with an infrared lamp at a speed of 2.0 inches / second (5.1 cm / second) at a power of 40%. The infrared step in this process was cold, because increasing the strength of this step can cause the dielectric layer to be “covered” and contain the solvent. Therefore, most of the drying was performed by heat from under the substrate. After scanning the sample with an infrared lamp, the platen temperature was maintained at 75 ° C. for an additional 10 minutes. This step in the process was used to remove the remaining solvent. After removing the solvent from the dielectric material, the dielectric material was cured or crosslinked at a platen temperature of 45 ° C. This was achieved using a 250 nm wavelength UV germicidal lamp while purging with nitrogen for 401 seconds. The last drying step or post-bake uses the same process steps as the pre-bake described above, except that the image was scanned with an infrared lamp five times at 2.0 inches / second (5.1 cm / second), 100% power. Using.

  After the dielectric layer was completed, the SE-128 printhead was removed from the system and replaced with a SX3-128 printhead for source and drain layer deposition. The source / drain layer was also printed with a Cabot Silver. The height of the print head was adjusted approximately 1.0 mm above the substrate, and the saber angle was set so that a resolution of 702 dpi was obtained. The source / drain layer was printed twice.

  In order to print the first source / drain layer, the aluminum platen was cooled to 45 ° C. and alignment was performed in the same manner as described above for the dielectric layer. When printing was complete, the platen temperature was raised to 60 ° C. over 30 seconds. This caused the silver to sinter along the edges before the material was fully sintered at higher temperatures. After 30 seconds, the platen temperature was raised to 150 ° C. over 10 minutes.

  Secondly, with respect to the source / drain layer to be printed, not all images or features were printed twice. The drain line was printed only once, but the source pad was printed twice. Due to the non-uniformity after sintering of the first layer, the source pad was printed twice. The platen was set at 150 ° C. for 10 minutes to sinter the silver.

  Prior to the semiconductor printing process, the platen was cooled to 30 ° C. and the dielectric material and source / drain contacts were surface treated. Using a pipette, high purity toluene was deposited on the surface of the entire sample and the sample was left for 1.0 minute. After 1.0 minute, toluene was removed by blowing off with an air can. Next, a 1.0 mmol perfluorothiophenol solution in high purity toluene was deposited on the entire sample surface and allowed to stand for 1.0 minute. The solution was removed by blowing off with an air can. The previous step was then repeated. In the last step, high purity toluene was deposited over the entire surface of the substrate for 20 seconds. After 20 seconds, toluene was blown from the sample using an air can. This treatment removed any residue on the contact and gave the semiconductor solution favorable surface energy.

  When the surface treatment was completed, the SX3-128 print head was removed from the system and replaced with an SE-128 print head. A printhead was filled with a solution of 1.0 wt% polystyrene, 2.0 wt% organic semiconductor, 6,13-bis (triisopropylsilylethynyl) pentacene in n-butylbenzene. Height and saber angle were adjusted to the above specifications. The semiconductor layer alignment was completed as described above for the other layers.

  Prior to the semiconductor deposition, a preheating process was started to remove toluene and toluene remaining on the substrate after the surface treatment. This preheating process was completed by passing the on-line infrared lamp six times at 2.0 inches / second (5.1 cm / second) and 80 percent power. Upon completion, the platen was cooled to 30 ° C.

  As described above, 18 drops or 540 pL of semiconductor solution was deposited on each transistor.

Results Transistors were measured with a saturated I _d -V _g curve. The gate voltage was biased from 10V to 40V and the drain voltage was set to -40V. The average mobility of the transistor of Comparative Example 2C was 0.042 cm ² / V-s, whereas the average mobility of the transistor of Example 1 was 0.11 cm ² / V-s. FIG. 6 is a graph showing mobility values of the transistors of Example 1 and Comparative Example 2C. Transistors according to the present disclosure showed higher mobility. FIG. 7 is a graph showing the sub-threshold voltage values of the transistors of Example 1 and Comparative Example 2C. Transistors according to the present disclosure exhibited lower subthreshold voltages. FIG. 8 is a graph showing values of on / off current ratios of the transistors of Example 1 and Comparative Example 2C. Transistors according to the present disclosure operated with higher on / off current ratio values.

  Various modifications and alterations of this invention will become apparent to those skilled in the art without departing from the scope and spirit of this invention. In addition, it should be understood that the present invention is not unduly limited to the exemplary embodiments described herein.

Claims (27)

A method for fabricating a thin film semiconductor device comprising:
a) providing a substrate supporting the first and second conductive zones, wherein the first and second conductive zones define a channel therebetween, the channel A process that does not delimit more than 75% around the conductive zone; and
b) depositing individual aliquots of a solution containing an organic semiconductor adjacent to or on the channel, wherein the aliquot provides the organic semiconductor to a single thin film semiconductor device; Are deposited on one side of the channel rather than on the channel.   The method of claim 1, wherein the channel does not demarcate more than 50% around any conductive zone.   The method of claim 1, wherein a boundary between the channel and each of the conductive zones is substantially straight and substantially parallel.   The method of claim 1, wherein the thin film semiconductor device is a transistor, the first conductive zone is a source, and the second conductive zone is a drain.   The method of claim 1, wherein more than 70% of the solution is deposited on one side of the channel rather than on the channel.   The method of claim 1, wherein more than 90% of the solution is deposited on one side of the channel rather than on the channel.   The method of claim 1, wherein all of the solution is deposited on one side of the channel rather than on the channel.   The method of claim 1, wherein the individual aliquots are deposited in the form of a plurality of droplets.   The method of claim 8, wherein the droplets are deposited by ink jet printing.   The method of claim 9, wherein at least 70% of the droplets are deposited on one side of the channel rather than on the channel.   The method of claim 9, wherein at least 90% of the droplets are deposited on one side of the channel rather than on the channel.   The method of claim 9, wherein all of the droplets are deposited on one side of the channel rather than on the channel.   The channel of claim 1, wherein the channel has a channel length, and individual aliquots of the solution containing the organic semiconductor are wetted after deposition and then have a length no greater than 10 times the channel length. The method described.   The method of claim 1, wherein the channel has a channel length, and individual aliquots of a solution containing the organic semiconductor are deposited in a band having a length less than the channel length.   The channel has a channel length, and individual aliquots of a solution containing the organic semiconductor are deposited in a band having a length less than the channel length, and all of the solution is on the channel. The method of claim 1, wherein the method is deposited on one side of the channel instead. A thin film semiconductor device,
a) a substrate that supports first and second conductive zones, wherein the first and second conductive zones define a channel therebetween, the channel of which of the conductive zones A substrate that does not delimit the border with more than 75% of the surroundings
b) a discrete semiconductor layer comprising an organic semiconductor located on and adjacent to the channel, which acts as a single thin film semiconductor device, the majority of the discrete semiconductor layers being on the channel And a separate semiconductor layer present on one side of the channel.   17. The device of claim 16, wherein the channel does not delimit more than 50% around any conductive zone.   The device of claim 16, wherein a boundary between the channel and each of the conductive zones is substantially straight and substantially parallel.   The device of claim 16, wherein the thin film semiconductor device is a transistor, the first conductive zone is a source, and the second conductive zone is a drain.   The device of claim 19, further comprising a gate and a dielectric layer.   The method of claim 16, wherein more than 55% of the individual semiconductor layers are on one side of the channel rather than on the channel.   The method of claim 16, wherein more than 60% of the individual semiconductor layers are on one side of the channel rather than on the channel.   The method of claim 16, wherein more than 70% of the individual semiconductor layers are on one side of the channel rather than on the channel.   The method of claim 16, wherein more than 80% of the individual semiconductor layers are on one side of the channel rather than on the channel.   The device of claim 16, wherein the channel has a channel length, and the individual semiconductor layer has a length no greater than 10 times the channel length. A method of fabricating a pair of thin film semiconductor devices,
a) a step of preparing a substrate, wherein the substrate is
i) first and second conductive zones, defining a first channel therebetween, and first and second conductive zones;
ii) supporting the third and fourth conductive zones, wherein the third and fourth conductive zones define a second channel therebetween;
b) depositing individual aliquots of a solution containing an organic semiconductor adjacent to or on the first and second channels, wherein the aliquots are accurately An organic semiconductor is provided to two single thin film semiconductor devices, the majority of the solution being deposited on one side of the first channel rather than on the first channel, the majority of the solution being the second Depositing on one side of the second channel rather than on the other channel. A pair of thin film semiconductor devices,
a) a substrate,
i) first and second conductive zones, defining a first channel therebetween, and first and second conductive zones;
ii) a substrate supporting third and fourth conductive zones, wherein the third and fourth conductive zones define a second channel therebetween;
b) Separate semiconductor layers comprising organic semiconductors located on and adjacent to the first and second channels, exactly as two single thin film semiconductor devices Most of the individual semiconductor layers are present on one side of the first channel rather than on the first channel, and most of the individual semiconductor layers are not on the second channel A pair of thin film semiconductor devices comprising: a separate semiconductor layer present on one side of the second channel.

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