JP2012257024A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that reduces a through current.SOLUTION: In the semiconductor device which includes a plurality of semiconductor chips having respective output sections for outputting data, wiring connected to each of the output sections, and a reception section for receiving the data from each of the plurality of semiconductor chips via the wiring, and which drives the output sections in order, each of the output sections has a variable on-state resistance value, and outputs the data to the wiring with the on-state resistance value set at a first resistance value during a first period from the start of drive of its own to a timing before the start of drive of the output section to be driven next, and outputs the data to the wiring with the on-state resistance value set at a second resistance value higher than the first resistance value during a second period from the time point of passage of the first period to the end of drive of its own.

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device having a stacked structure in which a plurality of semiconductor chips are stacked.

  A semiconductor device having a stacked structure in which a plurality of semiconductor chips are stacked is known.

  In this type of conventional semiconductor device, as shown in FIGS. 1, 2, and 21 of Patent Document 1, a plurality of stacked semiconductor chips (core chips) are connected to each other through through electrodes. In each semiconductor chip, a data control unit in the semiconductor chip outputs data to the interface chip via the through electrode. Note that the data control unit functions as an output driver.

JP 2011-82450 A

  In the semiconductor device described in Patent Document 1, a case is considered in which the core chip CC1 continuously outputs “L” data after the core chip CC0 outputs “H” data.

  In this case, ideally, at the same time when the data control circuit 54 (hereinafter referred to as “data control circuit 540”) that outputs “H” data in the core chip CC0 is turned OFF (off), “ It is desirable that the data control circuit 54 (hereinafter referred to as “data control circuit 541”) for outputting L ″ data is turned on.

  However, such an ideal operation is actually difficult. For example, the output period of the “H” data of the core chip CC0 (that is, the data control circuit 540 is ON) due to the difference in the stacking position of the core chips CC0 and CC1 when viewed from the interface chip IF and the slight difference in characteristics between the chips. Period) and an output period of “L” data of the core chip CC1 (that is, a period in which the data control circuit 541 is ON) may overlap.

  When this overlap occurs, a through current flows from the core chip CC0 outputting “H” data to the core chip CC1 outputting “L” data. Specifically, a through current flows from the data control circuit 540 to the data control circuit 541 through the through electrode TSV1.

  In a general design, the period during which such a through current flows is very small, but there is a desire to reduce the through current in order to bring the power consumption closer to the ideal state.

The semiconductor device of the present invention includes a plurality of semiconductor chips each provided with an output unit for outputting data, a wiring connected to each of the output units, and the data from each of the plurality of semiconductor chips via the wiring. And a receiving unit that receives the output, wherein the output unit is sequentially driven,
Each of the output units can change the resistance value in the on state, and during a first period from the start of its own drive to the timing before the start of the drive of the output unit that starts driving next to itself The resistance value in the on state is set to the first resistance value, and the data is output to the wiring. During the second period from the time when the first period has elapsed to the end of the self driving, the on state is The resistance value at the time is set to a second resistance value larger than the first resistance value, and the data is output to the wiring.

  According to the present invention, each output unit is driven in order so that a part of the drive period overlaps with a part of the drive period of the other output units, and is in the ON state during the first period from the start of the drive. The resistance value at the time is set to the first resistance value, and data is output to the wiring. During the second period from the time when the first period has elapsed until the end of driving, the resistance value in the ON state is set to be higher than the first resistance value. The second resistance value is set to a larger value and data is output to the wiring.

  Therefore, for example, in a situation where overlap occurs in the drive period of the output units that are driven in order, the output unit that has been driven first (hereinafter referred to as the “first output unit”) has the second on-resistance value. An output section that is driven with the resistance value set and driven later (hereinafter referred to as “second output section”) is driven with the on-resistance value set to the first resistance value.

  For this reason, even if the first output unit and the second output unit output different levels of data in a situation where there is an overlap in the drive period of the first output unit and the second output unit, the first data Since the resistance value in the ON state of the output unit is not the first resistance value but the second resistance value having a large resistance value, the through-flow flowing between the first output unit and the second output unit via the wiring The current can be reduced.

1 is a block diagram illustrating a semiconductor device 10 according to an embodiment of the present invention. It is a figure for demonstrating the penetration electrode TSV. It is the figure which showed data control circuit 54A. It is a timing chart for demonstrating operation | movement when the core chip CC1 drives following the drive of the core chip CC0. It is the figure which showed the simulation result about the through current which flows through wiring TSVA.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a semiconductor device 10 according to an embodiment of the present invention.

  In the semiconductor device 10, the data control circuit 54A provided in each of the core chips CC0 to CC7 is driven in turn, and a part of the driving period overlaps with a part of the driving period of the other data control circuit 54A. Each of the data control circuits 54A can change the resistance value in the ON state. Each of the data control circuits 54A outputs the data to the wiring TSVA by setting the resistance value in the on state to the first resistance value at the initial stage of the driving period, and then sets the resistance value in the on state to the first resistance value. The data is output to the wiring TSVA with the second resistance value larger than the value.

  In this embodiment, each data control circuit 54A has two output drivers having different resistance values in the on state and connected in parallel. In each data control circuit 54A, two data drivers are provided at the initial stage of the driving period. The output driver is driven, and thereafter, the output driver having a small resistance value in the ON state is driven out of the two output drivers.

  First, the overall configuration of the semiconductor device 10 will be described.

  In FIG. 1, the semiconductor device 10 according to the present embodiment has a structure in which eight core chips CC0 to CC7 that are semiconductor chips, one interface chip IF that is a receiving unit, and one interposer IP are stacked. Have

  The core chips CC0 to CC7 and the interface chip IF are semiconductor chips using a silicon substrate, and all of them are electrically connected to adjacent chips vertically by a large number of through silicon vias TSV (Through Silicon Via) penetrating the silicon substrate. Yes.

  FIG. 2 is a diagram for explaining the through silicon via TSV.

  Most of the through silicon vias TSV provided in the core chips CC0 to CC7 are formed by short-circuiting the upper and lower through silicon vias TSV1 provided at the same position in plan view as seen from the stacking direction, as shown in FIG. It is configured as a single wiring. The wiring constituted by the through silicon via TSV1 is connected to the internal circuit 4 (for example, the data control circuit 54A) in the core chips CC0 to CC7.

  On the other hand, as shown in FIG. 2B, some of the through silicon vias TSV are not directly connected to the other through silicon via TSV2 provided at the same position in plan view, It is connected via an internal circuit 5 provided in CC7.

  Further, as shown in FIG. 2C, the other part of the through silicon vias TSV is short-circuited with the other through silicon vias TSV provided at different positions in plan view. In this type of through silicon via TSV3, the internal circuits 6 of the core chips CC0 to CC7 are connected to the through silicon via TSV3a provided at a predetermined position P in plan view.

  The core chips CC0 to CC7 have a so-called front-end function (front-end function) that interfaces with the outside of the circuit blocks included in a 1 Gb DDR3 (Double Data Rate 3) SDRAM (Synchronous Dynamic Random Access Memory). Semiconductor chip.

  The interface chip IF is a semiconductor chip in which only the front end portion is integrated.

  The interposer IP is a circuit board made of resin.

  The interposer IP includes external terminals such as clock terminals 11a and 11b, clock enable terminal 11c, command terminals 12a to 12e, address terminal 13, data input / output terminal 14, data strobe terminals 15a and 15b, calibration terminal 16, and power supply. Terminals 17a and 17b are provided. These external terminals are all connected to the interface chip IF and are not directly connected to the core chips CC0 to CC7 except for the power supply terminals 17a and 17b.

  The interface chip IF includes a clock generation circuit 21, a DLL circuit 22, an input / output buffer circuit 23, a calibration circuit 24, a data latch circuit 25, a command input buffer 31, a command decoder 32, and defective chip information holding. A circuit 33, an address input buffer 41, a mode register 42, a power-on detection circuit 43, a layer address setting circuit 44, and a layer address control circuit 45 are included.

  Each of the core chips CC0 to CC7 includes a layer address generation circuit 46, a layer address comparison circuit (chip information comparison circuit) 47, a memory cell array 50, a row decoder 51, a column decoder 52, a sense circuit 53, and a data control. Circuit 54A, test input / output circuit 55, row control circuit 61, column control circuit 62, control logic circuit 63, mode register 64, test command decoder 65, internal voltage generation circuit 70, , A power-on detection circuit 71, test pads TP1 to TP6, and input buffers B1 and B2.

  The clock terminals 11a and 11b are terminals to which external clock signals CK and / CK are supplied, respectively. The clock enable terminal 11c is a terminal to which a clock enable signal CKE is input. The external clock signals CK and / CK and the clock enable signal CKE are supplied to the clock generation circuit 21.

  In the present specification, a signal having “/” at the beginning of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, external clock signal CK and external clock signal / CK are complementary signals.

  The clock generation circuit 21 generates an internal clock signal ICLK. The internal clock signal ICLK is supplied not only to the various circuit blocks in the interface chip IF but also to the core chips CC0 to CC7 in common via the through silicon vias TSV.

  The DLL circuit 22 generates an input / output clock signal LCLK. The input / output clock signal LCLK is supplied to the input / output buffer circuit 23. The DLL function is used to control the front end with the signal LCLK whose synchronization with the outside is matched when the semiconductor device 10 communicates with the outside.

  The command terminals 12a to 12e are terminals to which a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a chip select signal / CS, and an on-die termination signal ODT are supplied, respectively. These command signals are supplied to the command input buffer 31.

  The command input buffer 31 supplies a command signal to the command decoder 32.

  The command decoder 32 generates various internal commands ICMD by holding, decoding, and counting command signals in synchronization with the internal clock ICLK. The internal command ICMD is supplied to various circuit blocks in the interface chip IF, and is also commonly supplied to the core chips CC0 to CC7 via the through silicon vias TSV.

  The address terminal 13 is a terminal to which address signals A0 to A15 and BA0 to BA2 are supplied. Address signals A0 to A15 and BA0 to BA2 are supplied to an address input buffer 41.

  The output of the address input buffer 41 is supplied in common to the core chips CC0 to CC7 via each through silicon via TSV. When the entry is made in the mode register set, the address signals A0 to A15 are supplied to the mode register 42. The address signals BA0 to BA2 (bank addresses) are decoded by an address decoder (not shown) provided in the interface chip IF, and the bank selection signal B obtained thereby is supplied to the data latch circuit 25.

  The data input / output terminal 14 is a terminal for inputting / outputting read data or write data DQ0 to DQ15. The data strobe terminals 15a and 15b are terminals for inputting / outputting strobe signals DQS and / DQS. The data input / output terminal 14 and the data strobe terminals 15 a and 15 b are connected to the input / output buffer circuit 23.

  The input / output buffer circuit 23 includes an input buffer IB and an output buffer OB. The input / output buffer circuit 23 inputs / outputs read data or write data DQ0 to DQ15 and strobe signals DQS and / DQS in synchronization with the input / output clock signal LCLK.

  When the input / output buffer circuit 23 receives the internal on-die termination signal IODT from the command decoder 32, the input / output buffer circuit 23 causes the output buffer OB to function as a termination resistor.

  Furthermore, when the input / output buffer circuit 23 receives the impedance code DRZQ from the calibration circuit 24, the input / output buffer circuit 23 designates the impedance of the output buffer OB. The input / output buffer circuit 23 includes a well-known FIFO circuit.

  The calibration circuit 24 includes a replica buffer RB having the same circuit configuration as the output buffer OB. Upon receiving the calibration signal ZQ from the command decoder 32, the calibration circuit 24 performs a calibration operation by referring to the resistance value of an external resistor (not shown) connected to the calibration terminal 16. The calibration operation is an operation for matching the impedance of the replica buffer RB with the resistance value of the external resistor, and the impedance code DRZQ is supplied to the input / output buffer circuit 23. Thereby, the impedance of the output buffer OB is adjusted to a desired value.

  The input / output buffer circuit 23 is connected to the data latch circuit 25.

  The data latch circuit 25 includes a FIFO circuit (not shown) that realizes a FIFO function that operates by latency control that realizes a well-known DDR function, and a multiplexer MUX (not shown).

  The data latch circuit 25 serially converts the parallel read data supplied from the core chips CC0 to CC7 and converts the serial write data supplied from the input / output buffer circuit 23 to parallel.

  The power supply terminals 17a and 17b are terminals to which power supply potentials VDD and VSS are respectively supplied, and are connected to the power-on detection circuit 43 and also connected to the core chips CC0 to CC7 through the through silicon via TSV.

  The power-on detection circuit 43 is a circuit that detects power-on, and activates the layer address control circuit 45 when power-on is detected.

  The layer address control circuit 45 is a circuit for changing the layer address according to the I / O configuration of the semiconductor device 10. The layer address control circuit 45 controls the change of address allocation according to the number of I / Os, and is commonly connected to the core chips CC0 to CC7 via the through silicon vias TSV.

  The layer address setting circuit 44 is connected to the core chips CC0 to CC7 through the through silicon via TSV. The layer address setting circuit 44 is cascade-connected to the layer address generation circuit 46 of the core chips CC0 to CC7 using the through silicon via TSV2 of the type shown in FIG. 2B, and is set to the core chips CC0 to CC7 during the test. It plays the role of reading the layer address.

  The defective chip information holding circuit 33 holds the chip number when a defective core chip that does not operate normally is found after assembly. The defective chip information holding circuit 33 is connected to the core chips CC0 to CC7 through the through silicon via TSV. The defective chip information holding circuit 33 is connected to the core chips CC0 to CC7 while being shifted using the through silicon via TSV3 of the type shown in FIG.

  The memory cell array 50 is divided into 8 banks. A bank is a unit that can accept commands individually. In the memory cell array 50, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections. In FIG. 1, only one word line WL, one bit line BL, and one memory cell MC are shown.

  Selection of the word line WL is performed by the row decoder 51. The bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 53. Selection of the sense amplifier SA is performed by the column decoder 52.

  The row decoder 51 is controlled by a row address supplied from the row control circuit 61.

  The row control circuit 61 includes an address buffer 61a that receives a row address supplied from the interface chip IF via the through silicon via TSV. The row address buffered by the address buffer 61a is supplied to the row decoder 51. The The address signal supplied through the through silicon via TSV is supplied to the row control circuit 61 and the like through the input buffer B1.

  The row control circuit 61 also includes a refresh counter 61b. When a refresh signal is issued from the control logic circuit 63, the row address indicated by the refresh counter 61b is supplied to the row decoder 51.

  The column decoder 52 is controlled by a column address supplied from the column control circuit 62.

  The column control circuit 62 includes an address buffer 62a that receives a column address supplied from the interface chip IF via the through silicon via TSV, and supplies the column address buffered by the address buffer 62a to the column decoder 52. The column control circuit 62 also includes a burst counter 62b that counts the burst length.

  The sense amplifier SA selected by the column decoder 52 is further connected to the data control circuit 54A via some amplifiers (such as sub-amplifiers and data amplifiers) not shown. The data control circuit 54A receives a control signal that is an internal command ICMD supplied from the interface chip IF via the through silicon via TSV, and operates based on this control signal.

  Thus, read data is output from the data control circuit 54A during the read operation, and write data is input to the data control circuit 54A during the write operation. The data input / output unit of each data control circuit 54A and the interface chip IF are connected in parallel via a wiring TSVA. Note that the wiring TSVA is a through electrode of the type shown in FIG.

  The control logic circuit 63 receives the internal command ICMD supplied from the interface chip IF through the through silicon via TSV, and controls the operations of the row control circuit 61, the column control circuit 62, and the data control circuit 54A based on the internal command ICMD. A layer address comparison circuit (chip information comparison circuit) 47 is connected to the control logic circuit 63.

  The layer address comparison circuit 47 includes a SEL (chip selection information) which is a part of an address signal supplied from the interface chip IF via the through silicon via TSV, and a layer address LID (chip identification) set in the layer address generation circuit 46. Information) and whether or not the core chip is an access target.

  In the layer address generation circuit 46, a unique layer address is set to each of the core chips CC0 to CC7 at the time of initialization. The layer address generation circuit 46 is supplied with a defective chip signal DEF from the defective chip information holding circuit 33 through the through silicon via TSV.

  The defective chip signal DEF is supplied to the core chips CC0 to CC7 using the through silicon via TSV3 of the type shown in FIG. The defective chip signal DEF is a signal that is activated when the core chip is a defective chip. When the core chip is activated, the layer address generation circuit 46 uses a layer address that is not incremented instead of an incremented layer address. Transfer to the lower core chip.

  The defective chip signal DEF is also supplied to the control logic circuit 63. When the defective chip signal DEF is activated, the operation of the control logic circuit 63 is completely stopped.

  The output of the control logic circuit 63 is also supplied to the mode register 64. Thereby, when the output of the control logic circuit 63 indicates the mode register set, the set value of the mode register 64 is overwritten by the address signal. Thereby, the operation mode of the core chips CC0 to CC7 is set.

  The internal voltage generation circuit 70 is supplied with power supply potentials VDD and VSS. The internal voltage generation circuit 70 receives the power supply potentials VDD and VSS and generates various internal voltages.

  The internal voltage generated by the internal voltage generation circuit 70 includes an internal voltage VPERI (≈VDD) used as an operation power supply for various peripheral circuits, an internal voltage VARY (<VDD) used as an array voltage of the memory cell array 50, and the word line WL. An internal voltage VPP (> VDD) or the like which is an activation potential is included.

  The power-on detection circuit 71 resets various internal circuits when detecting power-on.

  The peripheral circuits included in the core chips CC0 to CC7 operate in synchronization with the internal clock signal ICLK supplied from the interface chip IF through the through silicon via TSV. The internal clock signal ICLK is supplied to various peripheral circuits via the input buffer B2.

  In the present embodiment, the core chips CC0 to CC7 are provided with several test pads TP and a test command decoder 65, and address signals, test data, and command signals can be input from the test pads TP. ing.

  The test pad TP includes a test pad TP1 to which a clock signal is input, a test pad TP2 to which an address signal is input, a test pad TP3 to which a command signal is input, a test pad TP4 for inputting / outputting test data, and data A test pad TP5 for inputting / outputting a strobe signal and a test pad TP6 for supplying a power supply potential are included.

  Next, the data control circuit 54A provided in each of the core chips CC0 to CC7 will be described.

  Each data control circuit 54A is sequentially driven one by one, and a part of the driving period overlaps a part of the driving period of the other data control circuit 54A.

  FIG. 3 shows the data control circuit 54A.

  In FIG. 3, the data control circuit 54A is an example of an output unit.

  The data control circuit 54A includes output drivers 54A1 and 54A2 connected in parallel.

  The output driver 54A1 is an example of a first data output unit. The output driver 54A1 includes NAND circuits NAND1 and NAND2, a NOR circuit NOR1, inverters INV1 to INV3, a PMOS transistor PMOS1, and an NMOS transistor NMOS1.

  The output driver 54A1 receives the control signals DSP1_p and PCLKOER_p and the output data signals DOUTBPjk and DOUTBNjk. The output driver 54A1 receives the control signals DSP1_p and PCLKOER_p from the interface chip IF as the internal command ICMD via the through silicon via TSV and the control logic circuit 63. The control signals DSP1_p and PCLKOER_p are generated by the command decoder 32 in the interface chip IF.

  The output driver 54A1 is activated when both the control signals DSP1_p and PCLKOER_p are “H”.

  When the output driver 54A1 is in an active state and the output data signals DOUTBPjk and DOUTBNjk are “L”, the PMOS transistor PMOS1 is turned on and the NMOS transistor NMOS1 is turned off, and the level of the output data is the potential VDDQ (“H”). It becomes.

  When the output data signals DOUTBPjk and DOUTBNjk are “H” in the active state, the output driver 54A1 is turned off, the PMOS transistor PMOS1 is turned off, the NMOS transistor NMOS1 is turned on, and the output data level becomes the potential VSSQ (“L” )).

  The output driver 54A2 is an example of a second data output unit. The output driver 54A2 includes a NAND circuit NAND3, a NOR circuit NOR2, inverters INV4 to INV6, a PMOS transistor PMOS2, and an NMOS transistor NMOS2.

  The output driver 54A2 receives the control signal DSP0_p and the output data signals DOUTBPjk and DOUTBNjk. The output driver 54A2 receives the control signal DSP0_p as the internal command ICMD from the interface chip IF via the through silicon via TSV and the control logic circuit 63. The control signal DSP0_p is generated by the command decoder 32 in the interface chip IF.

  The output driver 54A2 is activated when the control signal DSP0_p is “H”.

  When the output driver 54A2 is in the active state and the output data signals DOUTBPjk and DOUTBNjk are “L”, the PMOS transistor PMOS1 is turned on and the NMOS transistor NMOS1 is turned off, and the level of the output data is the potential VDDQ (“H”). It becomes.

  When the output data signals DOUTBPjk and DOUTBNjk are “H” in the active state, the output driver 54A2 is turned off, the PMOS transistor PMOS1 is turned off, the NMOS transistor NMOS1 is turned on, and the level of the output data is set to the potential VSSQ (“L” )).

  In the data control circuit 54A, the resistance value when the output driver 54A2 is on (the on-resistance value of the PMOS transistor PMOS2 and the NMOS transistor NMOS2) is the resistance value when the output driver 54A1 is on (the PMOS transistor PMOS1 and the NMOS transistor NMOS1). The output drivers 54A2 and 54A1 are provided so as to be larger than the (on-resistance value).

  In the present embodiment, the resistance value when the output driver 54A2 is in the on state is set to twice the resistance value when the output driver 54A1 is in the on state. Note that the resistance value when the output driver 54A2 is in the on state may not be twice the resistance value when the output driver 54A1 is in the on state, and may be larger than the resistance value when the output driver 54A1 is in the on state.

  In the present embodiment, the size (size) of the PMOS transistor PMOS1 is twice the size (size) of the PMOS transistor PMOS2, and the size (size) of the NMOS transistor NMOS1 is 2 times the size (size) of the NMOS transistor NMOS2. By doubling, the resistance value when the output driver 54A2 is on is set to twice the resistance value when the output driver 54A1 is on.

  Each data control circuit 54A has a period (hereinafter referred to as “first period”) from the start of its own driving to the timing before the start of driving of the data control circuit 54A that starts driving next to itself. The resistance value in the on state is set to the first resistance value (the combined value of the resistors in the on state of the output drivers 54A1 and 54A2 or the resistance value in the on state of the output driver 54A1), and the output data is output to the wiring TSVA. To do.

  Each data control circuit 54A determines the resistance value in the on state as the first resistance value during the period from the time when the first period has elapsed until the end of its own driving (hereinafter referred to as "second period"). Output data is output to the wiring TSVA with a second resistance value larger than that (resistance value when the output driver 54A2 is in the ON state).

  For example, in each data control circuit 54A, at least during the first period, the output driver 54A1 in the on state outputs the output data to the wiring TSVA, and during the second period, the output driver 54A1 is in the off state and is in the on state. Output driver 54A2 outputs the output data to the wiring TSVA.

  As described above, the semiconductor device 10 according to the present embodiment includes the plurality of semiconductor chips CC0 to CC7 each including the output unit 54A that outputs data, the wiring TSVA connected to each of the output units 54A, and the wiring TSVA. Each of the output units 54A is capable of changing the resistance value in the on state, and starts its own drive. During the first period from when the output unit 54A starts driving next to the timing before the start of driving, the resistance value in the ON state is set to the first resistance value and data is output to the wiring TSVA. During the second period from the time when the first period has elapsed until the end of the self drive, the resistance value in the on state is set to a second resistance value larger than the first resistance value, and data is output to the wiring TSVA. .

  In the semiconductor device 10 according to the present embodiment, each of the output units 54A includes a first data output unit 54A1, a second data output unit 54A2 having a resistance value in an ON state larger than that of the first data output unit 54A1, The first data output unit 54A1 and the second data output unit 54A2 are connected in parallel, and at least the first data output unit 54A1 in the ON state outputs data to the wiring TSVA during the first period. During the second period, the first data output unit 54A1 is turned off and the second data output unit 54A2 in the on state outputs data to the wiring TSVA.

  In the semiconductor device 10 according to the present embodiment, the size of the first data output unit 54A1 is larger than the size of the second data output unit 54A2.

  Next, the operation will be described. Hereinafter, an example in which the core chip CC1 is driven following the driving of the core chip CC0 will be described.

  FIG. 4 is a timing chart for explaining an operation when the core chip CC1 is driven following the driving of the core chip CC0.

  At time t1 when the data control circuit 54A (hereinafter referred to as “data control circuit 54AC0”) in the core chip CC0 starts driving, the control signals DSP0_p and DSP1_p (described as “DSP0, 1_p” in FIG. 4) in the core chip CC0. And the control signal PCLKOER both become “H”.

  Therefore, in the data control circuit 54AC0, the output drivers 54A1 and 54A2 are both activated, and output data corresponding to the output data signals DOUTBPjk and DOUTBNjk is output. In this situation, the resistance value during the on operation of the data control circuit 54AC0 is smaller than the resistance value during the on operation when only the output driver 54A2 is in the active state.

  Thereafter, when the first period P1 elapses and time t2 is reached, the control signal PCLKOER becomes “L” while maintaining the control signals DSP0_p and DSP1_p at “H”.

  Therefore, in the data control circuit 54AC0, the output driver 54A1 is deactivated (off state) while the output driver 54A2 is maintained in the activated state. Therefore, the resistance value when the data control circuit 54AC0 is turned on increases.

  In this situation, that is, in the situation where the output driver 54A1 is in the off state and the output driver 54A2 is in the on state in the data control circuit 54A in the core chip CC0, the data control circuit 54A in the core chip CC1 (hereinafter “control circuit 54AC1”). In the core chip CC1, the control signals DSP0_p and DSP1_p and the control signal PCLKOER both become “H”, and output data corresponding to the output data signals DOUTBPjk and DOUTBNjk is output.

  In the data control circuit 54AC1 in this situation, both the output drivers 54A1 and 54A2 are activated. Therefore, the resistance value when the data control circuit 54AC1 is turned on is smaller than the resistance value when only the output driver 54A2 is in the active state.

  At time t3, both the data control circuit 54AC0 (the data control circuit 54A in the core chip CC0) and the data control circuit 54AC1 (the data control circuit 54A in the core chip CC1) are on, so the data control circuit 54AC0 and the data control circuit 54AC1 Is conducted through the wiring TSVA.

  Therefore, when the output data levels of the data control circuit 54AC0 and the data control circuit 54AC1 are different, a through current flows between the data control circuit 54AC0 and the data control circuit 54AC1 via the wiring TSVA.

  However, at this time, since the resistance value of the data control circuit 54AC0 is larger than that at the start of driving, the through current flowing between the data control circuit 54AC0 and the data control circuit 54AC1 can be suppressed to a low value. Become.

  The state in which the through current flows between the data control circuit 54AC0 and the data control circuit 54AC1 is the overlap period P2 shown in FIG. 4 (the period from time t3 to time t4 when the data control circuit 54AC0 finishes driving). Last for. Thereafter, at time t4, the data control circuit 54AC0 is turned off, and thereafter, no through current flows between the data control circuit 54AC0 and the data control circuit 54AC1.

  FIG. 5 shows a state where the core chip CC0 outputs “L” output data DQ and the core chip CC1 outputs “H” output data DQ, and the core chip CC0 outputs “H” output data DQ. FIG. 10 is a diagram showing a simulation result of a through current flowing between the core chips CC0 and CC1 when the core chip CC1 outputs “L” output data DQ in a situation where

  As shown in FIG. 5, this embodiment (when the data control circuit 54A uses only the output driver 54A2 at the end of the driving period) is the original (the data control circuit 54A uses the output drivers 54A1 and 54A2 during the driving period). The through current can be suppressed to a lower value than in the case of

  Note that the through current suppression method described with reference to FIGS. 3 to 5 is not performed only in the relationship between the core chip CC0 and the core chip CC1, and for example, while the drive periods overlap as illustrated in FIG. This is also performed between core chips having data control circuits 54A that are driven in sequence.

  According to the present embodiment, each of the data control circuits 54A that are sequentially driven so that a part of the drive period overlaps with a part of the drive period of the other data control circuit 54A is the first period from the start of the drive. During this period, the resistance value in the on state is set to the first resistance value, and data is output to the wiring TSVA. During the second period from the time when the first period has elapsed to the end of driving, the resistance in the on state is The value is set to a second resistance value larger than the first resistance value, and data is output to the wiring TSVA.

  Therefore, for example, in a situation where overlap occurs in the drive periods of the two data control circuits 54AC0 and 54AC1 that are driven in sequence, the on-resistance value is set to the second resistance value in the data control circuit 54AC0 that is driven first. The data control circuit 54AC1 that is driven in a state that is driven later is driven in a state in which the on-resistance value is set to the first resistance value.

  Therefore, even when the data control circuits 54AC0 and 54AC1 output different levels of data in a situation where there is an overlap in the driving period of the data control circuits 54AC0 and 54AC1, the resistance when the data control circuit 54AC0 is in the ON state Since the value is not the first resistance value but the second resistance value having a large resistance value, the through current flowing between the data control circuits 54AC0 and 54AC1 via the wiring TSVA can be reduced.

  At the start of driving, since the resistance value when the data control circuit 54A is in the ON state is small, the output current of the data control circuit 54A is large, and the transition time of the output data can be shortened.

  In the present embodiment, each of the data control circuits 54A includes an output driver 54A1 and an output driver 54A2 whose resistance value in the on state is larger than that of the output driver 54A1. The output driver 54A1 and the output driver 54A2 are connected in parallel. During the first period, at least the output driver 54A1 in the on state outputs data to the wiring TSVA, and during the second period, the output driver 54A1 is in the off state and the output driver 54A2 in the on state wires the data. Output to TSVA.

  Therefore, each data control circuit 54A can reduce the through current flowing through the wiring TSVA by switching the output driver that is turned on during the driving period.

  In the present embodiment, the size of the output driver 54A1 is larger than the size of the output driver 54A2. Therefore, the magnitude relationship between the resistance values in the ON state of the output driver 54A1 and the output driver 54A2 can be set based on the size difference between the output driver 54A1 and the output driver 54A2.

  In the above embodiment, the DDR3 type SDRAM is used as the core chip. However, the core chip is not limited to the DDR3 type SDRAM, and may be a DRAM other than the DDR3 type, or a semiconductor other than the DRAM. It may be a memory (SRAM, PRAM, MRAM, flash memory, etc.). Further, it is not essential that all the core chips are stacked, and some or all of the core chips may be arranged in a plane while being connected to the wiring connected to the interface chip IF. Further, the number of core chips is not limited to eight.

  The semiconductor device 10 can also be applied to a semiconductor device other than a semiconductor memory. For example, a CPU (Central Processing Unit) is mounted on the interface chip, a CPU cache memory is mounted on the core chip, and a high-performance CPU can be configured by combining the interface chip and a plurality of core chips.

  In the embodiment described above, the illustrated configuration is merely an example, and the present invention is not limited to the configuration.

TSV1-3, TSVA Through electrode (wiring)
DESCRIPTION OF SYMBOLS 10 Semiconductor device 11a, 11b Clock terminal 11c Clock enable terminal 12a-12e Command terminal 13 Address terminal 14 Data input / output terminal 15a, 15b Data strobe terminal 16 Calibration terminal 17a, 17b Power supply terminal 21 Clock generation circuit 22 DLL circuit 23 Input / output Buffer circuit 24 Calibration circuit 25 Data latch circuit 31 Command input buffer 32 Command decoder 33 Defective chip information holding circuit 41 Address input buffer 42 Mode register 43 Power-on detection circuit 44 Layer address setting circuit 45 Layer address control circuit 46 Layer address generation circuit 47 layer address comparison circuit 50 memory cell array 51 row decoder 52 column decoder 53 sense circuit 54A data control circuit 54A 54A2 Output driver NAND1 to NAND3 NAND circuit NOR1 to NOR2 NOR circuit INV1 to INV6 Inverter PMOS1 to PMOS2 PMOS transistor NMOS1 to NMOS2 NMOS transistor 55 I / O circuit 61 Row control circuit 61a Address buffer 61b Refresh counter 62 Column control circuit 62a Address buffer 62b Burst counter 63 Control logic circuit 64 Mode register 65 Command decoder 70 Internal voltage generation circuit 71 Power-on detection circuits CC0 to CC7 Core chip IF Interface chip IP Interposer

Claims (3)

A plurality of semiconductor chips each provided with an output unit for outputting data; a wiring connected to each of the output units; and a receiving unit for receiving the data from each of the plurality of semiconductor chips via the wiring; A semiconductor device in which the output unit is driven in order,
Each of the output units can change the resistance value in the on state, and during a first period from the start of its own drive to the timing before the start of the drive of the output unit that starts driving next to itself The resistance value in the on state is set to the first resistance value, and the data is output to the wiring. During the second period from the time when the first period has elapsed to the end of the self driving, the on state is A semiconductor device that outputs the data to the wiring by setting a resistance value at the time to a second resistance value larger than the first resistance value. The semiconductor device according to claim 1,
Each of the output units includes a first data output unit and a second data output unit having a resistance value in an ON state larger than that of the first data output unit,
The first data output unit and the second data output unit are connected in parallel,
During the first period, at least the first data output unit in an on state outputs the data to the wiring, and during the second period, the first data output unit is in an off state and is in an on state. The semiconductor device, wherein the second data output unit outputs the data to the wiring. The semiconductor device according to claim 2,
The size of the first data output unit is a semiconductor device larger than the size of the second data output unit.

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