JP2013105996A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize a circuit operation in a laminated semiconductor device which can selectively utilize a plurality of through electrodes.SOLUTION: A semiconductor storage device 10 comprises: an interface chip IF; a plurality of core chips CC laminated on the interface chip IF; and a plurality of through electrodes TSV connecting the interface chip IF and the core chips CC. The core chip CC includes input switching circuits 240, 230 which temporarily blocks connection between a plurality of input signal lines included in the core chip CC and the plurality of through electrodes TSV before performing setting processing at the time of power-on, and connects each input signal lines with any of the plurality of through electrodes TSV in accordance with relief information indicating connection of the plurality of input signal lines and the plurality of through electrodes TSV after setting of the core chip CC.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a plurality of semiconductor chips electrically connected by through electrodes.

  The storage capacity required for semiconductor storage devices such as DRAM (Dynamic Random Access Memory) is increasing year by year. In recent years, in order to satisfy this requirement, a method has been proposed in which a plurality of memory chips are stacked and these are electrically connected through through electrodes provided on a silicon substrate (see Patent Documents 1, 2, and 3). ).

  In particular, in a semiconductor memory device of a type in which an interface chip in which a front end unit such as an interface circuit is integrated and a core chip in which a back end unit such as a memory core is integrated is read in parallel from the memory core. Since the read data is supplied to the interface chip as it is without being serially converted, a large number of through electrodes (about 4000 in the case of many) are required. However, if there is even one defect in the through electrode, the entire chip becomes defective, and all the chips become defective after lamination. For this reason, in this type of semiconductor memory device, a spare through electrode may be provided in order to prevent the entire through electrode from being defective due to a defective through electrode.

  In the semiconductor device described in Patent Document 2, one spare through electrode is assigned to a group of a plurality of through electrodes (for example, eight through electrodes). When a defect occurs in one of the through electrodes, a spare through electrode assigned to this group is used in place of the through electrode, thereby relieving the defect.

JP 2006-19328 A JP 2007-158237 A JP 2011-81887 A

  In a semiconductor device having an interface chip and a core chip as described above, in order to repair (repair) a defective through electrode, repair information stored in the interface chip (connection information for designating a usable through electrode) ) Is transferred to each core chip by the corresponding circuit of the interface chip when the power is turned on.

  Since the relief information transfer is performed by reading the relief information held in the interface chip, there is a difference between the timing when the relief information is set in the corresponding circuit of the interface chip itself and the timing when the relief information is set in the core chip. End up. The present inventor has recognized that an error signal may be input to the core chip due to this deviation, and a malfunction may occur.

  A semiconductor device according to the present invention includes a first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip, and a plurality of through electrodes that connect the first semiconductor chip and the second semiconductor chip. . The second setting circuit included in the second semiconductor chip includes a plurality of input signal lines and a plurality of through electrodes included in the second semiconductor chip before the setting process (initialization process) at power-on. After the connection is temporarily cut off and the second semiconductor chip is set (initial setting), each input signal line is connected to the plurality of through electrodes according to the second connection information indicating the connection between the plurality of input signal lines and the plurality of through electrodes. Connect with one.

  According to the present invention, in a stacked semiconductor device in which a plurality of through electrodes can be selectively used, malfunction of the core chip can be easily suppressed.

1 is a schematic cross-sectional view for explaining the structure of a semiconductor memory device according to a preferred embodiment of the present invention. FIG. 2A to FIG. 2C are diagrams for explaining the types of TSVs provided in the core chip. It is sectional drawing which shows the structure of TSV1 of the type shown to Fig.2 (a). FIG. 6 is a circuit configuration diagram when there is no defective through electrode when one through electrode can be relieved. FIG. 6 is a circuit configuration diagram when one defective through electrode exists when one through electrode can be relieved. FIG. 6 is a circuit configuration diagram when two defective through electrodes exist when two through electrodes can be relieved. FIG. 5 is a diagram showing in detail a signal path when two defective through electrodes TSV are replaced with spare through electrodes TSV in a general semiconductor memory device. It is a figure which shows in detail the signal path | route when the setting of a core chip fails. It is a figure which shows in detail the signal path | route when the setting of a core chip fails. It is a figure which shows in detail the signal path | route when the setting of a core chip fails. It is a figure which shows in detail the signal path | route when the setting of a core chip fails. It is a figure which shows in detail the signal path | route when the setting of a core chip fails. It is a figure which shows in detail the signal path | route when the setting of a core chip fails. It is a time chart when setting of a core chip fails. It is a time chart of a general setting process. In the semiconductor memory device according to the present embodiment, it is a diagram showing in detail a signal path when two defective through electrodes TSV are replaced with spare through electrodes TSV. It is a circuit diagram of a switch circuit. It is a circuit diagram of a circuit that generates an operation signal. It is a time chart of the setting process in this embodiment. In this embodiment, it is a circuit block diagram in the case of providing only one reserve penetration electrode. In the present embodiment, there is only one spare through electrode, and a circuit configuration diagram in the case where relief information is transmitted from the core chip CC to the interface chip IF. It is a block diagram which shows the circuit structure of a semiconductor memory device. It is a circuit diagram of a test mode circuit.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic cross-sectional view for explaining the structure of a semiconductor memory device 10 according to a preferred embodiment of the present invention.

  As shown in FIG. 1, the semiconductor memory device 10 according to the present embodiment has a structure in which eight core chips CC0 to CC7 having the same structure, one interface chip IF, and one interposer IP are stacked. doing. The core chips CC0 to CC7 and the interface chip IF are semiconductor chips using a silicon substrate, and all of them are electrically connected to adjacent chips vertically by a large number of through silicon vias TSV (Through Silicon Via) penetrating the silicon substrate. . On the other hand, the interposer IP is a circuit board made of resin, and a plurality of external terminals (solder balls) SB are formed on the back surface IPb thereof.

  The core chips CC0 to CC7 are semiconductor chips in which a so-called front-end unit that interfaces with the outside is deleted from among circuit blocks included in a 1 Gb DDR3 (Double Data Rate 3) SDRAM (Synchronous Dynamic Random Access Memory). . In other words, it is a semiconductor chip in which only circuit blocks belonging to the back-end part are integrated. The circuit block included in the front end unit includes a parallel / serial conversion circuit that performs parallel / serial conversion of input / output data between the memory cell array and the data input / output terminals, and a DLL (Delay Locked) that controls the input / output timing of data. Loop) circuit. Since the core chips CC0 to CC7 do not include these circuits belonging to the front end unit, the core chips CC0 to CC7 cannot be operated alone except during a test operation. An interface chip IF is required to operate the core chips CC0 to CC7.

  The interface chip IF functions as a common front end unit for the eight core chips CC0 to CC7. Therefore, all external accesses are performed via the interface chip IF, and data input / output is also performed via the interface chip IF. In the present embodiment, the interface chip IF is disposed between the interposer IP and the core chips CC0 to CC7. However, the position of the interface chip IF is not particularly limited, and may be disposed above the core chips CC0 to CC7. Alternatively, it may be arranged on the back surface IPb of the interposer IP. When the interface chip IF is arranged on the upper part of the core chips CC0 to CC7 or on the back surface IPb of the interposer IP, it is not necessary to provide the TSV in the interface chip IF.

  The interposer IP functions as a rewiring substrate for ensuring the mechanical strength of the semiconductor memory device 10 and increasing the electrode pitch. That is, the electrode 91 formed on the upper surface IPa of the interposer IP is drawn out to the back surface IPb by the through-hole electrode 92, and the pitch of the external terminals SB is expanded by the rewiring layer 93 provided on the back surface IPb. Although only two external terminals SB are shown in FIG. 1, a large number of external terminals are actually provided. The layout of the external terminal SB is the same as that in the DDR3-type SDRAM defined by the standard. Therefore, it can be handled as one DDR3-type SDRAM from an external controller.

  As shown in FIG. 1, the upper surface of the uppermost core chip CC0 is covered with NFC 94 and a lead frame 95, and the side surfaces of the core chips CC0 to CC7 and the interface chip IF are covered with an underfill 96 and a sealing resin 97. . Thereby, each chip is physically protected.

  Most of the TSVs provided in the core chips CC0 to CC7 are short-circuited with TSVs of other layers provided at the same position in a plan view seen from the stacking direction, that is, when viewed from the arrow A shown in FIG. Yes. That is, as shown in FIG. 2A, the upper and lower TSV1 provided at the same position in a plan view are short-circuited, and one wiring is constituted by these TSV1. These TSV1 provided in each of the core chips CC0 to CC7 are respectively connected to the internal circuit 4 in the core chip. Therefore, input signals (command signal, address signal, etc.) supplied from the interface chip IF to the TSV1 shown in FIG. 2A are commonly input to the internal circuits 4 of the core chips CC0 to CC7. Further, output signals (data and the like) supplied from the core chips CC0 to CC7 to the TSV1 are wired-or and input to the interface chip IF.

  On the other hand, as shown in FIG. 2B, some TSVs are not directly connected to other layers TSV2 provided at the same position in plan view, but are provided in the core chips CC0 to CC7. Connected through the internal circuit 5. That is, these internal circuits 5 provided in the core chips CC0 to CC7 are cascade-connected via the TSV2. This type of TSV2 is used to sequentially transfer predetermined information to the internal circuit 5 provided in each of the core chips CC0 to CC7. Such information includes layer address information described later.

  Further, some other TSV groups are short-circuited with TSVs of other layers provided at different positions in plan view, as shown in FIG. For this type of TSV group 3, internal circuits 6 of the core chips CC0 to CC7 are connected to a TSV 3a provided at a predetermined position P in plan view. This makes it possible to selectively input information to the internal circuit 6 provided in each core chip. Such information includes defective chip information described later.

  As described above, there are three types (TSV1 to TSV3) of TSVs provided in the core chips CC0 to CC7 shown in FIGS. As described above, most TSVs are of the type shown in FIG. 2A, and address signals, command signals, clock signals, etc. are transferred from the interface chip IF to the core chip CC0 via the TSV1 of the type shown in FIG. To CC7. Also, read data and write data are input / output to / from the interface chip IF via the TSV1 of the type shown in FIG. On the other hand, TSV2 and TSV3 of the types shown in FIGS. 2B and 2C are used to give individual information to the core chips CC0 to CC7 having the same structure.

  FIG. 3 is a cross-sectional view showing the structure of TSV1 of the type shown in FIG.

  As shown in FIG. 3, TSV1 is provided through silicon substrate 80 and interlayer insulating film 81 on the surface thereof. An insulating ring 82 is provided around TSV1, thereby ensuring insulation between TSV1 and the transistor region. In the example shown in FIG. 3, the insulating ring 82 is provided in a double manner, thereby improving the reliability.

  The end 83 of the TSV 1 on the back side of the silicon substrate 80 is covered with a back bump 84. The back bump 84 is an electrode in contact with the front bump 85 provided on the lower core chip. The surface bump 85 is connected to the end portion 86 of the TSV1 through pads P0 to P3 provided in the wiring layers L0 to L3 and a plurality of through-hole electrodes TH1 to TH3 connecting the pads. As a result, the front surface bump 85 and the rear surface bump 84 provided at the same position in plan view are short-circuited. Note that connection to an internal circuit (not shown) is made via internal wiring (not shown) drawn from pads P0 to P3 provided in the wiring layers L0 to L3.

  Next, a relief method when a defect occurs in the through electrode will be described. The relief method described below can be applied to any of the types of TSV1 to TSV3 described above.

  FIG. 4 is a schematic circuit diagram for explaining a connection relationship between the interface chip IF and the core chips CC0 to CC7, and shows a case where there is no defect in the through electrode.

  FIG. 4 shows, as an example, a portion for supplying 8-bit data D1 to D8 from the interface chip IF to the core chips CC0 to CC7. These data D1 to D8 are signals that are simultaneously output from the interface chip IF and are to be input simultaneously by the core chips CC0 to CC7, and correspond to address signals, write data, and the like.

  As shown in FIG. 4, the interface chip IF is provided with eight driver circuits 101 to 108 corresponding to the data D1 to D8, and the core chips CC0 to CC7 are provided with eight data corresponding to the data D1 to D8. Receiver circuits 201 to 208 are provided. On the other hand, in this embodiment, nine (= 8 + 1) penetrating electrodes 301 to 309 for connecting the driver circuits 101 to 108 and the receiver circuits 201 to 208 are provided. Among these through electrodes 301 to 309, the through electrode 309 is a spare through electrode, and is not used when the other through electrodes 301 to 308 are not defective.

  More specifically, the interface chip IF includes an output switching circuit 120 (hereinafter referred to as an output) that connects the output terminals of the driver circuits 101 to 108 to one of two corresponding through electrodes via the driver circuits 111 to 119. The switching circuit is also referred to as a “first setting circuit”). Here, the corresponding two through-electrodes indicate the i-th and i + 1-th through-electrodes when the end of the reference numerals of the driver circuits 101 to 108 is i (i is 1 to 8). For example, the first and second through electrodes 301 and 302 correspond to the driver circuit 101, and the second and third through electrodes 302 and 303 correspond to the driver circuit 102. For this reason, some of the through electrodes 302 to 308 correspond to two driver circuits, respectively, but the two driver circuits are not connected to one through electrode, and the connection to each through electrode is Done exclusively. Which of the corresponding two through electrodes is selected is determined by the relief signals R1 to R8.

  The relief signals R1 to R8 are assigned to the through electrodes 301 to 308, respectively, and are activated when the corresponding through electrodes are defective. Then, assuming that the activated relief signal is Rx, the i th through electrode is selected for the driver circuit whose code ends with 1 to x−1, and the driver circuit whose code ends with x to 8 For i, the i + 1 th through electrode is selected. In the example shown in FIG. 4, none of the relief signals R1 to R8 is activated, so that the output switching circuit 120 causes the output terminals of the driver circuits 101 to 108 to pass through the through electrodes 301 to 118 via the driver circuits 111 to 118, respectively. Connect to 308.

  The above connection relationship is the same on the core chips CC0 to CC7 side. That is, each of the core chips CC0 to CC7 includes an input switching circuit 220 (hereinafter, the output switching circuit is also referred to as “second setting circuit”), and the relief signal R1 as shown in the example of FIG. When none of -R8 is activated, the input switching circuit 220 connects the input terminals of the receiver circuits 201-208 to the through electrodes 301-308 via the receiver circuits 211-218, respectively.

  As described above, when there is no defect in any of the through electrodes 301 to 308, the corresponding driver circuit and receiver circuit are all connected via the path PA (only the path PA of the through electrode 301 is illustrated). become. In this case, the spare through electrode 309 is not used.

  Next, a schematic circuit when a defect occurs in the through electrode 306 will be described with reference to FIG.

  As shown in FIG. 5, when a defect occurs in the through electrode 306, based on relief information (connection information for designating usable and unusable through electrodes) held in the interface chip. Rescue signal R6 is activated. Thus, the output switching circuit 120 connects the output terminals of the driver circuits 101 to 105 to the through electrodes 301 to 305 via the driver circuits 111 to 115, respectively, while the output terminals of the driver circuits 106 to 108 are connected to the driver circuit 117, respectively. Are connected to the through electrodes 307 to 309 through. Thus, the connection relationship between the driver circuits 101 to 108 and the through electrodes 301 to 309 is shifted with the defective through electrode as a boundary.

  The above connection relationship is also the same on the core chips CC0 to CC7 side, and the input switching circuit 220 connects the input ends of the receiver circuits 201 to 205 to the through electrodes 301 to 305 via the receiver circuits 211 to 215, respectively. In response to the activation of the relief signal R6 based on the relief information supplied from the interface chip, the input terminals of the receiver circuits 206 to 208 are connected to the through electrodes 307 to 309 via the receiver circuits 217 to 219, respectively. Thus, also on the input side, the connection relationship between the receiver circuits 201 to 208 and the through electrodes 301 to 309 is shifted with a defective through electrode as a boundary.

  When there is a defect in the through electrode 306, the driver circuits 101 to 105 and the receiver circuits 201 to 205 are connected via the path PA (see FIG. 4), while the driver circuits 106 to 108 and the receiver circuits 206 to 208 are connected. Are connected via a path PB. In short, if the defective through electrode is 30x, the driver circuits 101 to 10 (x-1) and the receiver circuits 201 to 20 (x-1) are connected via the path PA, and the driver circuits 10x to 108 are connected to each other. The receiver circuits 20x to 208 are connected via a path PB.

  In other words, instead of simply replacing the defective through electrode (through electrode 306 in the example shown in FIG. 5) with a spare through electrode (through electrode 309 in the example shown in FIG. 5), the defective through electrode is used as a boundary. The connection relationship between the driver circuits 101 to 108 and the receiver circuits 201 to 208 and the through electrodes 301 to 309 is shifted. In this way, even after replacement, the output terminal of the driver circuit having a higher number is connected to the through electrode having a higher number, and the output terminal of the receiver circuit having a higher number is connected to the through electrode having a higher number. For this reason, if the i-th and i + 1-th through-electrodes are arranged adjacent to each other, for example, by arranging the through-electrodes 301 to 309 in this order, there is almost a difference in wiring length between the signal path before replacement and the signal path after replacement. Disappear. As a result, there is almost no skew due to replacement, and signal quality can be improved.

  FIG. 6 is a schematic circuit diagram for explaining the connection relationship between the interface chip IF and the core chips CC0 to CC7, and shows a case where a defect exists in the through electrodes 302 and 304. FIG.

  In the configuration shown in FIG. 6, two spare through electrodes 309 and 310 are assigned to the eight through electrodes 301 to 308. Therefore, the total number of through electrodes is ten.

  Two output switching circuits 130 and 140 (first setting circuit) are provided on the interface chip IF side, and two input switching circuits 230 and 240 (second setting circuit) are provided on the core chip CC0 to CC7 side. ing. Relief signals R11 to R18 are supplied to the output switching circuit 130 and the input switching circuit 230, whereby the output path and the input path are switched. Similarly, relief signals R21 to R29 are supplied to the output switching circuit 140 and the input switching circuit 240, whereby the output path and the input path are switched. By providing the two output switching circuits 130 and 140 and the two input switching circuits 230 and 240, the connection relationship between the driver circuits 101 to 108 and the receiver circuits 201 to 208 and the through electrodes 301 to 310 is 2 at the maximum. It is possible to shift by one.

  The relief signals R11 to R18 are signals that are activated by only one bit when one or two defects exist in the eight through electrodes 301 to 308. Specifically, when one through electrode 30x is defective, the corresponding relief signal Rx is activated, and when two through electrodes 30x and 30y (x <y) are defective, The relief signal Rx corresponding to the through electrode having a smaller number is activated. When there are three or more defects in the through electrodes 301 to 308, the present embodiment cannot be remedied. On the other hand, the relief signals R21 to R29 are signals that are activated by only one bit when there are two defects in the nine through electrodes 301 to 309. Specifically, when the two through electrodes 30x and 30y (x <y) are defective, the relief signal Ry corresponding to the through electrode having a larger number is activated. Under the above conditions, the relief signal R21 cannot be activated, so the relief signal R21 may be fixed at an inactive level. However, since it is desirable to match the number of logic stages between each driver circuit and each through electrode and between each through electrode and each receiver circuit, the relief signal R21 is used as shown in FIG. It is preferable not to omit the logic gate.

  With the above configuration, when one defect exists in the eight through electrodes 301 to 308, one connection is shifted from the defective through electrode as a boundary, and the defect is relieved. Further, when there are two defects, the connection is first shifted by one of the defective through electrodes with the lower numbered through electrode as a boundary, and further connected with the higher number of the through electrode as a boundary. The defect is relieved by shifting by one.

  In the example shown in FIG. 6, the two through electrodes 302 and 304 are defective through electrodes. In this case, the relief signal R12 and the relief signal R24 are activated. As a result, since the shift operation is first performed by the output switching circuit 130 with the through electrode 302 as a boundary, the output terminal of the driver circuit 102 is connected to the through electrode 303. Furthermore, since the shift operation is performed by the output switching circuit 140 with the through electrode 304 as a boundary, the output terminal of the driver circuit 103 is connected to the through electrode 305. The same applies to the input side.

  FIG. 7 is a diagram showing in detail a signal path when two defective through electrodes TSV are replaced with spare through electrodes TSV in the general semiconductor memory device 10. As shown in FIG. 6, a two-stage switch circuit is inserted in the signal line (output signal line) on the interface chip IF side. For example, switch circuits SW11 (n) and SW21 (n), which are part of the output switching circuits 130 and 140, are inserted in the output signal line from the driver circuit D (n) to the through silicon via TSV (n). Similarly, a two-stage switch circuit is also inserted in the signal line (input signal line) on the core chip CC side. Switch circuits SW31 (n) and SW41 (n), which are part of the input switching circuits 240 and 230, are inserted in the input signal line extending from the through silicon via TSV (n) to the receiver circuit R (n). In FIG. 5, the driver circuit D (n) corresponds to the “driver circuit 10n”, and the receiver circuit R (n) corresponds to the “receiver circuit 20n”. A serializer 500 is provided on the interface chip IF side, and a TSV relief circuit 502 is provided on the core chip CC side. The relief signals R11 to R29 of the interface chip IF are serialized by the serializer 500, supplied to the TSV relief circuit 502 via the doubled through silicon via TSV, and developed as the relief signals R11 to R29 of the core chip CC. Details will be described later.

  Hereinafter, the description will focus on the signal path from the drive circuit D (n) to the receiver circuit R (n). When there is no defective through electrode TSV, the switch circuits SW11 (n), SW21 (n), SW31 (n), and SW41 (n) are turned on. At this time, the output signal line corresponding to the drive circuit D (n) is directly connected to the through electrode TSV (n), and the through electrode TSV (n) is directly connected to the receiver circuit R (n). The switch circuit of the interface chip IF corresponds to the “first switch”, and the switch circuit on the core chip CC side corresponds to the “second switch”.

  On the other hand, when the through electrode TSV (i) and the through electrode TSV (j) are defective (i, j <n), the switch circuits SW11 (n) and SW21 (n + 1) are turned off, and instead the switch circuit SW12 (N), SW22 (n + 1) is turned on. As a result, the driver circuit D (n) is connected to the through silicon via TSV (n + 2).

  The same switching is performed on the core chip CC side, and the through silicon via TSV (n + 2) is connected to the receiver circuit R (n). Specifically, the switch circuits SW32 (n + 1) and SW42 (n) are turned on. Thus, the driver circuit D (n) and the receiver circuit R (n) are connected via the through silicon via TSV (n + 2). As described with reference to FIG. 6, the same connection shift is performed for the other driver circuits D and receiver circuits R.

  The switches SWT (n) and SWT (n + 1) are switches for connecting the receiver circuits R (n) and R (n + 1) to the test ports T (n) and T (n + 1). When the operation test is performed in the wafer state, the operation signal CTRL2 is set to low active. When the operation signal CTRL2 becomes low level, the input switching circuit 240 is forcibly turned off. As a result, the connection between the through silicon via TSV and the receiver circuit R is interrupted. Thereafter, the switches SWT (n) and SWT (n + 1) are turned on. Then, various test signals are supplied from the test ports T (n) and T (n + 1) to the core chip CC. The role of the test port will be described later.

  Information indicating how to connect the through silicon via TSV to the output signal line or the input signal line, in other words, information for setting on / off of each switch circuit (hereinafter referred to as “relief information (relief information here is defective It does not mean setting information for memory cell repair, but connection information for repair of defective through-hole electrodes) ”)) as relief signals R11 to R29 to both the interface chip IF and the core chip CC. Supplied. The relief information for the interface chip IF (information specifying on / off of the output switching circuit) is “first relief information”, and the relief information for the core chip CC (information specifying on / off of the input switching circuit) is “ This corresponds to “second relief information”.

  As shown in FIG. 7, relief information (relief signals R11 to R29) is supplied to each switch circuit from a plurality of signal lines. The relief information may be held by both the interface chip IF and the core chip CC, but in this case, it is not preferable because a storage area needs to be secured in the core chip CC. Therefore, in this embodiment, only the interface chip IF holds the repair information (first and second repair information), and the interface chip IF stores the repair information (second repair information) in the core chip CC as necessary. Supply. The relief information is supplied to each core chip via a through electrode (a multiplexed through electrode related to the serializer 500 described above: hereinafter referred to as “sub-path”) different from the through electrode TSV shown in FIG. . In the sub-path, which is a transmission path of relief information from the interface chip IF to each core chip, the relief information transmission is performed so that information can be transmitted even if one of the multiplexed penetration electrodes becomes defective by multiplexing the penetration electrodes. Ensuring certainty. A data transmission path connecting the driver circuit D and the receiver circuit R shown in FIG. 7 is called a “main path”. The sub path is used for transferring relief information held in the interface chip IF to each core chip after reset release after power-on.

  FIG. 9 is a schematic diagram of an initialization sequence after power is turned on. After the power supply VDD rises and stabilizes, the / RESET signal is asserted to a low level. Thereby, the internal circuit of the DDR3-SDRAM is initialized. Internal Node in the figure schematically shows the potential of the internal circuit, and the hatched portion is in an indefinite state, and is initialized by the / RESET signal to become the initial potential. This initialized state is the precharge standby state of the DDR3-SDRAM, and all the test modes must be reset. It is necessary to maintain the initialized state after the / RESET signal returns to the high level and the reset is released. About 500 μs is required for the waiting time from the reset release until the CKE signal (clock enable signal) is set to the high level and the clock signal can be received. Thereafter, the command can be received, an initialization command is issued from the memory controller, and an appropriate operation mode is set. The typical semiconductor memory device 10 having the replacement circuit of the through silicon via TSV in FIG. 7 includes the first relief information of the interface chip IF and the first chip from the interface chip IF to the core chip CC during the waiting time from the reset release. Second relief information is transferred. In FIG. 9, this transfer period is shown as a period during which the control signals CTRL1 and CTRL2 are at a low level. In the figure, Tp is a time required for power stabilization, Tr is a reset period, T1 is a first transfer period (first relief information transfer period), and T2 is a second transfer period (second relief information transfer). Period).

  The flow of setting the first and second relief information and the problems that occur at that time will be described with reference to FIGS. 8 (a) to 8 (f).

  FIG. 8A shows the initialized levels of the signal lines of the interface chip IF and the core chip CC after reset release. Although not particularly limited, it is assumed in this figure that the driver output D (n + 1) is reset to a high level and other driver output signals are reset to a low level. Further, in the initial state, the output switching circuits 130 and 140 and the input switching circuits 230 and 240 have the switch circuits SW11, SW21, SW31 and SW41 turned on, the switch circuits SW12, SW22, SW32 and SW42 are turned off, and the receiver inputs of the core chip CC Also for R, the driver output D of the interface chip IF is transmitted through the through silicon via TSV, the receiver input R (n + 1) is at a high level, and the other receiver input signals are at a low level.

  FIG. 8B shows a state after the control signals CTRL1 and CTRL2 transition to the low level. The switch circuits SW21 and SW22 of the interface chip IF and the switch circuits SW31 and SW32 of the core chip CC are all turned off, and the through silicon via TSV is separated so as to be in a floating state. Since no relief information is set at this time, the switch circuit SW11 of the interface chip IF is on, SW12 is off, the switch circuit SW41 of the core chip CC is on, and SW42 is off. The potential of the level keeper connected to the output of the switch circuit SW11 (n + 1) is high level, the potential of the level keeper connected to the output of the switch circuit SW11 (n) and below is low level, the switch circuit SW11 (n + 2) and The potential of the level keeper connected to the output of SW11 (n + 3) is indefinite. The indefinite state here means that it cannot be specified as either high level or low level, and does not mean an intermediate potential between high and low levels. Similarly, the potential of the level keeper connected to the output of the switch circuit SW31 (n + 1) is high, the potential of the level keeper connected to the output below the switch circuit SW31 (n) is low, and the switch circuit SW31 (n + 2). ) And the potential of the level keeper connected to the output of SW31 (n + 3) is indefinite.

  FIG. 8C shows a state after the output switching circuits 130 and 140 are turned on / off according to the first relief information held by the interface chip IF. Since the control signals CTRL1 and CTRL2 are at a low level, the output switching circuit 140 is all maintained in the off state, but the output switching circuit 130 is switched on while the switch circuit SW11 is off and SW12 is on. Therefore, the potential of the level keeper connected to the output of the switch circuit SW11 (n + 1) transitions to a low level, and the potential of the level keeper connected to the output of the switch circuit SW11 (n + 2) transitions to a high level.

  FIG. 8D shows a state after the second relief information held by the interface chip IF is set to ON / OFF of the input switching circuits 230 and 240 of the core chip CC via the sub path. Since the control signals CTRL1 and CTRL2 are at a low level, the input switching circuit 240 is all maintained in the OFF state, but the input switching circuit 230 is switched off and the switch circuit SW41 is switched on. For this reason, the receiver input R (n + 1) is in an indefinite state, and the receiver input R (n) transits to a high level.

  FIG. 8E shows a state after the setting of the first and second relief information is completed and the control signals CTRL1 and CTRL2 return to the high level. Since the output switching circuit 140 and the input switching circuit 240 are set to ON / OFF, the switch circuit SW21 is turned off and the SW22 is turned on. Similarly, the switch circuit SW31 is turned off and the SW32 is turned on. For this reason, the potential of the level keeper behind the switch circuit SW31 (n + 1) transitions to a low level, and the potential of the level keeper behind the SW31 (n + 2) transitions to a high level. Further, the receiver input R (n + 1) transitions to a high level and the receiver input R (n) transitions to a low level.

  FIG. 8F is a diagram for explaining the state of the receiver input R of the core chip CC during the above-described relief information transfer period. The receiver input R (n) transitions from the low level of the initial potential to the high level, and then transitions to the low level again. Further, the receiver input R (n + 1) transitions from the high level of the initial potential to an indefinite value, and then transitions to the high level again.

  FIG. 8G shows a state where the receiver input R (n) that should be kept in the initialized state as in the internal node of FIG. 9 is generating a high level hazard.

  The influence of the hazard occurring on the receiver input R (n) in FIG. 8G will be described with reference to FIG.

  FIG. 17 is an example of a test mode setting circuit provided in the core chip CC. The test mode is for setting the core chip CC from the interface chip IF to a state different from the normal state. For example, many types of test modes are installed, such as changing the level of the internal power supply regulator, changing the internal timing, or changing to the burn-in test mode. Code Signal is a test mode entry code, and is a signal input from an address pin or the like. When this Code Signal is decoded and matched, a high level decode signal is output. The signal R (n) is a trigger signal for entering the test mode, and a pulse signal of one shot is input when entering. The output of the NAND gate to which the decode signal of the test code and the trigger signal R (n) are input becomes the set signal of the RS flip-flop. On the other hand, the reset signal of the RS flip-flop is generated when the / RESET signal or the / TEST_EXIT signal is asserted low.

  When the receiver input R (n) of FIG. 8 (g) is connected to the trigger signal R (n) of the test entry of FIG. 17, the test mode that has been completely canceled by the / RESET signal is caused by a hazard that has occurred. There is a risk of entering an unexpected test mode. Depending on the type of test mode, there is a type that interferes with normal operation. In this case, even if an initialization command is input, it may not be set normally and malfunction.

  FIG. 10 is a diagram showing in detail a signal path when two defective through electrodes TSV are replaced with spare through electrodes TSV in the semiconductor memory device 10 according to the present embodiment. In the present embodiment, a switch for connecting not only the switch circuit of the input switching circuit 240 but also the receiver circuits R (n) and R (n + 1) and the test pads T (n) and T (n + 1) according to the operation signal CTRL2. SWT (n) and SWT (n + 1) are also controlled.

  When the operation signal CTRL2 becomes low active, all the switch circuits of the input switching circuit 240 are forcibly turned off. At this time, the core chip CC is forcibly cut off from the interface chip IF and the through silicon via TSV. The operation of the input switching circuit 240 according to the control signal CTRL2 in this embodiment is as described with reference to FIG.

  When the control signal CTRL2 becomes low active, the switches SWT (n), SWT (n + 1), etc. are turned on, and the input signal line and the test ports T (n), T (n + 1) are connected.

  Here, the roles of the test port T and the switch SWT will be described. The core chip CC in the wafer state is normally tested in the probe test process, repairs the defective memory cell, and is shipped to the assembly process. The probe test is usually performed by contacting a bonding pad with a probe card. However, since the chip laminated with the through silicon via TSV does not have a structure for connecting to an external terminal by wire bonding, a contact pad dedicated to the probe test is arranged in the chip. Between the probe test dedicated contact pad and the test port T connected to the surface bump of the through silicon via TSV, an input circuit dedicated to the probe test is arranged. When the probe test is performed, the switch SWT is turned on by the control signal CTRL2, and the test port T is connected to the receiver input R.

  Since the input circuit dedicated to the probe test is used only for the low-speed probe test, it has a simple structure. For example, a simple buffer circuit is sufficient if only an address signal is transmitted. In the case of a control signal originally generated by the interface chip IF, a simplified logic circuit is arranged so as to support only a function necessary for the probe test. These input circuits dedicated to the probe test are also reset by the / RESET signal according to the initialization sequence after power-on shown in FIG. 9, and the initialized initial potential is output to the test port T after the reset is released.

  This initialized state is the precharge standby state of the DDR3-SDRAM, and all the test modes must be reset. It is necessary to maintain the initialized state even after the reset signal returns to the high level and the reset is released. The reset state is maintained until the clock enable signal CKE is set to the high level and the command can be accepted. Thereafter, an initialization command is input from the memory tester to set an appropriate operation mode.

  In the present embodiment, in the stacked and packaged form, the test port T that is the output of the probe test dedicated input circuit is connected to the receiver input R by the switch SWT by the control signal CTRL2. The probe test dedicated input circuit is not affected by the switching of the output switching circuits 130 and 140 of the interface chip IF and the input switching circuits 230 and 240 of the core chip CC accompanying the setting of the relief information of the through silicon via TSV, and thus generates a hazard. There is nothing to do. Therefore, according to the present embodiment, the core chip CC can be kept in the initialized state before and after setting the relief information of the through silicon via TSV, and there is a risk of entering into an unexpected test mode. It can be eliminated.

  FIG. 11 is a circuit diagram of the switch circuit. Here, as a representative example, the connection relationship between the switch circuits SW32 (n-1) and SW31 (n) will be described, but the same applies to other switch circuits. In addition to the core chip CC, the switch circuit on the interface chip IF side has basically the same configuration.

  Switch circuits SW32 (n-1) and SW31 (n) each include a tristate inverter. The switch circuit SW32 (n−1) controls the connection between the through silicon via TSV (n) and the core chip CC, and the switch circuit SW31 (n) controls the connection between the through silicon via TSV (n + 1) and the core chip CC.

  Each tri-state inverter has a PMOS (Positive channel Metal Oxide Semiconductor) FET (Field effect transistor) and a NMOS (Negative Channel Metal Oxide Semiconductor) FET selection transistor connected between the power supply and the ground, respectively. If both the selection transistors are not activated, it does not function as an inverter and its output is in a high impedance state. When the selection transistor is activated, the tri-state inverter is connected to the power supply and the ground and supplied with an operating potential.

  The relief signal Rx selects one of the switch circuits SW32 (n-1) and SW31 (n). When the relief signal Rx is at a high level, the switch circuit SW31 (n) is turned on and the switch circuit SW32 (n-1) is turned off. When the relief signal Rx is at a low level, the switch circuit SW31 (n) is turned off and the switch circuit SW32 (n-1) is turned on.

  A tri-state inverter 400 is further connected to output destinations of the switch circuits SW32 (n-1) and SW31 (n). In the present embodiment, the tri-state inverter 400 is controlled by the operation signal CTRL2. When the operation signal CTRL2 is at a low level, that is, when the power is turned on or during an operation test, the tri-state inverter 400 is turned off. That is, the input signal line of the core chip CC is forcibly turned off regardless of the level of the relief signal Rx.

  FIG. 12 is a circuit diagram of a circuit that generates the operation control signal CTRL2. The rising edge of the reset signal / RESET is detected, and the load signal AFLOAD is generated by the RS flip-flop. During the period when the AFLOAD is at a high level, the first and second relief information of the through silicon via TSV is transferred. With this AFLOAD signal, the oscillator OSC and the counter circuit are activated, and the transfer sequencer is controlled according to the counter value. When counting up to the completion of transfer, the RS flip-flop is reset, and the load signal AFLOAD transitions to a low level.

  The load signal AFLOAD and the test signal TEST for the probe test are input to the 2-input NOR gate, and the output signal becomes the operation control signal CTRL2. The operation control signal CTRL2 is at a low level in either a transfer period in which the load signal AFLOAD is at a high level or a period in which a probe test test signal TEST is performed at a high level.

  The reset signal / RESET becomes a high level at the time of reset and then returns to a low level. The load completion signal AFLOAD becomes a high level at the start of loading of repair information, and becomes a low level after completion of connection replacement. The test signal TEST is at a high level during a test, and is at a low level otherwise.

  FIG. 13 is a time chart of the relief information transfer process in the present embodiment. Since it is not an operation test, the test signal TEST is fixed at a low level. After the reset signal / RESET transitions from the low level to the high level, the load signal AFLOAD becomes the high level.

  The relief information transfer process is executed while the load signal AFLOAD is at a high level. When the transfer of all the relief information is completed, the load signal AFLOAD transitions to a low level. During this time, the operation control signal CTRL2 is held at a low level.

  That is, until the loading of the repair information is completed and the load completion signal AFLOAD becomes low level, the operation signal CTRL2 is maintained at low level, and the connection between each core chip CC and the interface chip IF is cut off. Instead, each test port T is connected to the receiver input R of the core chip CC, and the initial potential of the input circuit dedicated for the probe test is input to the receiver input R.

  Before and after setting the relief information of the through silicon via TSV, the core chip CC can be kept in an initialized state, and it is possible to eliminate a risk of entering into an unexpected test mode.

  Since the connection replacement in the interface chip IF is completed simultaneously with the reading of the antifuse, the connection replacement is always executed before the connection replacement of the core chip CC, and then the relief information is transferred to the core chip CC.

  FIG. 14 is a circuit configuration diagram when only one spare through electrode TSV is provided in the present embodiment. Unlike FIG. 10, since there is only one spare through electrode TSV, a single-stage output switching circuit 120 and a single-stage input switching circuit 220 are installed in both the interface chip IF and the core chip CC. If a defect occurs in two or more through silicon vias TSV, it cannot be repaired. However, since the number of switch circuits is small, there is an advantage that the circuit scale can be reduced.

  FIG. 15 is a circuit configuration diagram in the present embodiment when there is only one spare through electrode TSV and the initial potential initialized from the core chip CC to the interface chip IF is applied. In general, the initial potential may be applied not only from the interface chip IF to the core chip CC but also from the core chip CC to the interface chip IF. In this case, the switch circuit of the input switching circuit 120 may be controlled by the operation signal CTRL1 in the same manner as the operation signal CTRL2. Further, if the operation signal CTRL1 and the operation signal CTRL2 are shared, the number of signal lines can be reduced.

  FIG. 16 is a block diagram showing a circuit configuration of the semiconductor memory device 10.

  As shown in FIG. 16, the external terminals provided in the interposer IP include clock terminals 11a and 11b, a clock enable terminal 11c, command terminals 12a to 12e, an address terminal 13, a data input / output terminal 14, a data strobe terminal 15a, 15b, a calibration terminal 16, and power supply terminals 17a and 17b. These external terminals are all connected to the interface chip IF and are not directly connected to the core chips CC0 to CC7 except for the power supply terminals 17a and 17b.

  First, the connection relationship between these external terminals and the interface chip IF which is a front-end function, and the circuit configuration of the interface chip IF will be described.

  The clock terminals 11a and 11b are terminals to which external clock signals CK and / CK are supplied, respectively, and the clock enable terminal 11c is a terminal to which a clock enable signal CKE is input. The supplied external clock signals CK and / CK and the clock enable signal CKE are supplied to the clock generation circuit 21 provided in the interface chip IF. In this specification, a signal having “/” at the head of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, the external clock signals CK and / CK are complementary signals. The clock generation circuit 21 is a circuit that generates an internal clock signal ICLK. The generated internal clock signal ICLK is supplied to various circuit blocks in the interface chip IF and is also common to the core chips CC0 to CC7 via the TSV. To be supplied.

  The interface chip IF includes a DLL circuit 22, and the input / output clock signal LCLK is generated by the DLL circuit 22. The input / output clock signal LCLK is supplied to the input / output buffer circuit 23 included in the interface chip IF. This is because the DLL function controls the front end with the signal LCLK whose synchronization with the outside is matched when the semiconductor device 10 communicates with the outside. Therefore, the DLL function is not required for the core chips CC0 to CC7 which are back ends.

  The command terminals 12a to 12e are terminals to which a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a chip select signal / CS, and an on-die termination signal ODT are supplied, respectively. These command signals are supplied to a command input buffer 31 provided in the interface chip IF. These command signals supplied to the command input buffer 31 are supplied to the command decoder 32. The command decoder 32 is a circuit that generates various internal commands ICMD by holding, decoding, and counting command signals in synchronization with the internal clock ICLK. The generated internal command ICMD is supplied to various circuit blocks in the interface chip IF, and is also commonly supplied to the core chips CC0 to CC7 via the TSV.

  The address terminal 13 is a terminal to which address signals A0 to A15 and BA0 to BA2 are supplied. The supplied address signals A0 to A15 and BA0 to BA2 are supplied to an address input buffer 41 provided in the interface chip IF. The The output of the address input buffer 41 is commonly supplied to the core chips CC0 to CC7 via the TSV. When the mode register set is entered, the address signals A0 to A15 are supplied to the mode register 42 provided in the interface chip IF. The address signals BA0 to BA2 (bank addresses) are decoded by an address decoder (not shown) provided in the interface chip IF, and the bank selection signal B obtained thereby is supplied to the data latch circuit 25. This is because the bank selection of write data is performed in the interface chip IF.

  The data input / output terminal 14 is a terminal for inputting / outputting read data or write data DQ0 to DQ15. The data strobe terminals 15a and 15b are terminals for inputting / outputting strobe signals DQS and / DQS. The data input / output terminal 14 and the data strobe terminals 15a and 15b are connected to an input / output buffer circuit 23 provided in the interface chip IF. The input / output buffer circuit 23 includes an input buffer IB and an output buffer OB. In synchronization with the input / output clock signal LCLK supplied from the DLL circuit 22, read / write data DQ0 to DQ15 and a strobe signal are provided. Input / output DQS and / DQS. Further, when the internal on-die termination signal IODT is supplied from the command decoder 32, the input / output buffer circuit 23 causes the output buffer OB to function as a termination resistor. Further, the impedance code DRZQ is supplied from the calibration circuit 24 to the input / output buffer circuit 23, thereby designating the impedance of the output buffer OB. The input / output buffer circuit 23 includes a well-known FIFO circuit.

  The calibration circuit 24 includes a replica buffer RB having the same circuit configuration as that of the output buffer OB. When a calibration signal ZQ is supplied from the command decoder 32, an external resistor (connected to the calibration terminal 16 ( The calibration operation is performed by referring to the resistance value (not shown). The calibration operation is an operation for matching the impedance of the replica buffer RB with the resistance value of the external resistor, and the obtained impedance code DRZQ is supplied to the input / output buffer circuit 23. Thereby, the impedance of the output buffer OB is adjusted to a desired value.

  The input / output buffer circuit 23 is connected to the data latch circuit 25. The data latch circuit 25 includes a FIFO circuit (not shown) that realizes a FIFO function that operates by latency control that realizes a well-known DDR function, and a multiplexer MUX (not shown), and is supplied in parallel from the core chips CC0 to CC7. This circuit converts the read data into serial data and converts serial write data supplied from the input / output buffer into parallel data. Therefore, the data latch circuit 25 and the input / output buffer circuit 23 are serially connected, and the data latch circuit 25 and the core chips CC0 to CC7 are parallelly connected. In the present embodiment, the core chips CC0 to CC7 are back end portions of the DDR3 type SDRAM, and the prefetch number is 8 bits. The data latch circuit 25 and the core chips CC0 to CC7 are connected to each bank, and the number of banks included in each core chip CC0 to CC7 is eight banks. Therefore, the connection between the data latch circuit 25 and the core chips CC0 to CC7 is 64 bits (8 bits × 8 banks) per 1DQ.

  Thus, parallel data that has not been serially converted is basically input / output between the data latch circuit 25 and the core chips CC0 to CC7. That is, in a normal SDRAM (that is, a front end and a back end are configured by one chip), data is input / output serially to / from the outside of the chip (that is, the data input / output terminals are per 1DQ). On the other hand, in the core chips CC0 to CC7, data is input / output to / from the interface chip IF in parallel. This is an important difference between the normal SDRAM and the core chips CC0 to CC7. However, it is not essential to input / output all prefetched parallel data using different TSVs, and the number of TSVs required per DQ is reduced by performing partial parallel / serial conversion on the core chips CC0 to CC7 side. It doesn't matter. For example, instead of inputting / outputting 64 bits of data per 1DQ using different TSVs, the number of TSVs required per 1DQ is halved by performing 2-bit parallel / serial conversion on the core chips CC0 to CC7. It may be reduced to (32).

  Further, the data latch circuit 25 is added with a function of enabling a test for each interface chip. The interface chip has no back-end part. For this reason, it cannot be operated as a single unit in principle. However, if the single operation is impossible, the operation test of the interface chip in the wafer state cannot be performed. This indicates that the semiconductor device 10 can only be tested after the assembly process of the interface chip and the plurality of core chips, and means that the interface chip is tested by testing the semiconductor device 10. . If the interface chip has a defect that cannot be recovered, the entire semiconductor device 10 is lost. Considering this point, in the present embodiment, the data latch circuit 25 is provided with a part of a pseudo back-end portion for testing, and a simple storage function is possible at the time of testing.

  The power supply terminals 17a and 17b are terminals to which power supply potentials VDD and VSS are supplied, respectively, and connected to the power-on detection circuit 43 provided in the interface chip IF and also connected to the core chips CC0 to CC7 through the TSV. Has been. The power-on detection circuit 43 is a circuit that detects power-on, and activates the layer address control circuit 45 provided in the interface chip IF when power-on is detected.

  The layer address control circuit 45 is a circuit for changing the layer address in accordance with the I / O configuration of the semiconductor memory device 10 according to the present embodiment. As described above, the semiconductor memory device 10 according to the present embodiment includes the 16 data input / output terminals 14, and the maximum number of I / Os can be set to 16 bits (DQ 0 to DQ 15). The number of I / Os is not fixed to this, and can be set to 8 bits (DQ0 to DQ7) or 4 bits (DQ0 to DQ3). The address allocation is changed according to the number of I / Os, and the layer address is also changed. The layer address control circuit 45 is a circuit that controls a change in address allocation according to the number of I / Os, and is commonly connected to each of the core chips CC0 to CC7 via the TSV.

  The interface chip IF is also provided with a layer address setting circuit 44. The layer address setting circuit 44 is connected to the core chips CC0 to CC7 via the TSV. The layer address setting circuit 44 is cascade-connected to the layer address generation circuit 46 of the core chips CC0 to CC7 using the TSV2 of the type shown in FIG. 2B, and the layers set in the core chips CC0 to CC7 at the time of testing. It plays the role of reading the address.

  Further, a defective chip information holding circuit 33 is provided in the interface chip IF. The defective chip information holding circuit 33 is a circuit that holds a chip number when a defective core chip that does not operate normally is found after assembly. The defective chip information holding circuit 33 is connected to the core chips CC0 to CC7 through the TSV. The defective chip information holding circuit 33 is connected to the core chips CC0 to CC7 while being shifted using the TSV3 of the type shown in FIG.

  Furthermore, a repair information holding circuit 400 is provided in the interface chip IF. The relief information holding circuit 400 is a circuit that stores the above-described relief signal by, for example, an antifuse element, and when a defect is found in the through electrode by an operation test after assembly, the relief signal is written from the tester. The relief signal held in the relief information holding circuit 400 is read out when the power is turned on, transferred to the replacement control circuits 121c to 128c in the interface chip IF, and the core chip using the TSV1 of the type shown in FIG. It is also transferred to the replacement control circuit in CC0 to CC7.

  The above is the outline of the connection relationship between the external terminal and the interface chip IF and the circuit configuration of the interface chip IF. Next, the circuit configuration of the core chips CC0 to CC7 will be described.

  As shown in FIG. 16, the memory cell array 50 included in the core chips CC0 to CC7 which are back-end functions is divided into 8 banks. A bank is a unit that can accept commands individually. In other words, each bank can operate independently by mutually exclusive control. Each bank can be accessed independently from the outside of the semiconductor device 10. For example, the memory cell array 50 of the bank 1 and the memory cell array 50 of the bank 2 are non-exclusive control that can individually control access to the corresponding word line WL, bit line BL, etc. in the same period on the time axis by different commands. It is a relationship. For example, the bank 2 can be controlled to be active while the bank 1 is kept active (the word line and the bit line are active). However, the external terminals (for example, a plurality of control terminals and a plurality of I / O terminals) of the semiconductor device are shared. In the memory cell array 50, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections (in FIG. 16, one word line WL, 1 Only one bit line BL and one memory cell MC are shown). Selection of the word line WL is performed by the row decoder 51. The bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 53. Selection of the sense amplifier SA is performed by the column decoder 52.

  The row decoder 51 is controlled by a row address supplied from the row control circuit 61. The row control circuit 61 includes an address buffer 61 a that receives a row address supplied from the interface chip IF via the TSV, and the row address buffered by the address buffer 61 a is supplied to the row decoder 51. The address signal supplied via the TSV is supplied to the row control circuit 61 and the like via the input buffer B1. The row control circuit 61 also includes a refresh counter 61b. When a refresh signal is issued from the control logic circuit 63, the row address indicated by the refresh counter 61b is supplied to the row decoder 51.

  The column decoder 52 is controlled by a column address supplied from the column control circuit 62. The column control circuit 62 includes an address buffer 62a that receives a column address supplied from the interface chip IF via the TSV, and the column address buffered by the address buffer 62a is supplied to the column decoder 52. The column control circuit 62 also includes a burst counter 62b that counts the burst length.

  The sense amplifier SA selected by the column decoder 52 is further connected to the data control circuit 54 via some amplifiers (such as sub-amplifiers and data amplifiers) not shown. As a result, 8-bit (= prefetch number) read data is output from the data control circuit 54 per I / O (DQ) during the read operation, and 8-bit write data is data during the write operation. Input to the control circuit 54. The data control circuit 54 and the interface chip IF are connected in parallel via the TSV.

  The control logic circuit 63 is a circuit that receives the internal command ICMD supplied from the interface chip IF via the TSV and controls the operations of the row control circuit 61 and the column control circuit 62 based on the internal command ICMD. A layer address comparison circuit (chip information comparison circuit) 47 is connected to the control logic circuit 63. The layer address comparison circuit 47 is a circuit that detects whether or not the core chip is an access target. The detection is performed by a part of the address signal SEL (chip selection information) supplied from the interface chip IF via the TSV. And the layer address LID (chip identification information) set in the layer address generation circuit 46 are compared. When a match is detected, the match signal HIT is activated.

  In the layer address generation circuit 46, a unique layer address is set to each of the core chips CC0 to CC7 at the time of initialization. The layer address setting method is as follows. First, when the semiconductor memory device 10 is initialized, a minimum value (0, 0, 0) is set as an initial value in the layer address generation circuit 46 of each of the core chips CC0 to CC7. The layer address generation circuits 46 of the core chips CC0 to CC7 are cascade-connected using the type of TSV shown in FIG. 2B and have an increment circuit therein. The layer address (0, 0, 0) set in the layer address generation circuit 46 of the uppermost core chip CC0 is sent to the layer address generation circuit 46 of the second core chip CC1 via the TSV and incremented. Thus, different layer addresses (0, 0, 1) are generated. Similarly, the generated layer address is transferred to the lower core chip, and the layer address generation circuit 46 in the transferred core chip increments this. In the layer address generation circuit 46 of the lowermost core chip CC7, the maximum value (1, 1, 1) is set as the layer address. Thereby, a unique layer address is set to each of the core chips CC0 to CC7.

  The layer address generation circuit 46 is supplied with a defective chip signal DEF from the defective chip information holding circuit 33 of the interface chip IF through the TSV. Since the defective chip signal DEF is supplied to each of the core chips CC0 to CC7 using the TSV3 of the type shown in FIG. 2C, an individual defective chip signal DEF can be supplied to each of the core chips CC0 to CC7. The defective chip signal DEF is a signal that is activated when the core chip is a defective chip. When the core chip is activated, the layer address generation circuit 46 uses a layer address that is not incremented instead of an incremented layer address. Transfer to the lower core chip. The defective chip signal DEF is also supplied to the control logic circuit 63. When the defective chip signal DEF is activated, the operation of the control logic circuit 63 is completely stopped. As a result, a defective core chip does not perform a read operation or a write operation even if an address signal or a command signal is input from the interface chip IF.

  The output of the control logic circuit 63 is also supplied to the mode register 64. Thereby, when the output of the control logic circuit 63 indicates the mode register set, the set value of the mode register 64 is overwritten by the address signal. Thereby, the operation mode of the core chips CC0 to CC7 is set.

  Furthermore, an internal voltage generation circuit 70 is provided in the core chips CC0 to CC7. The power supply potentials VDD and VSS are supplied to the internal voltage generation circuit, and the internal voltage generation circuit 70 receives these to generate various internal voltages. The internal voltage generated by the internal voltage generation circuit 70 includes an internal voltage VPERI (≈VDD) used as an operation power supply for various peripheral circuits, an internal voltage VARY (<VDD) used as an array voltage of the memory cell array 50, and the word line WL. An internal voltage VPP (> VDD) or the like which is an activation potential is included. In addition, the core chips CC0 to CC7 are also provided with a power-on detection circuit 71. When the power-on is detected, various internal circuits are reset.

  The peripheral circuits included in the core chips CC0 to CC7 operate in synchronization with the internal clock signal ICLK supplied from the interface chip IF via the TSV. The internal clock signal ICLK supplied via the TSV is supplied to various peripheral circuits via the input buffer B2.

  The above is the basic circuit configuration of the core chips CC0 to CC7. The core chips CC0 to CC7 are not provided with a front-end unit for interfacing with the outside, and therefore cannot be operated alone in principle. However, if the single operation is impossible, it becomes impossible to perform the operation test of the core chip in the wafer state. This indicates that the semiconductor device 10 can only be tested after the assembly process of the interface chip and the plurality of core chips, and means that each core chip is tested by testing the semiconductor device 10. To do. If the core chip has a defect that cannot be recovered, the entire semiconductor device 10 is lost. In consideration of this point, in the present embodiment, the core chips CC0 to CC7 include a plurality of test pads TP and a test front end unit of a test command decoder 65 for a pseudo front end unit for testing. Are provided, and an address signal, test data, and a command signal can be input from the test pad TP. It should be noted that the test front-end unit is a circuit having a function that realizes a simple test in the wafer test, and does not have all the front-end functions in the interface chip. For example, since the operating frequency of the core chip is lower than the operating frequency of the front end, it can be simply realized by a test front end circuit for testing at a low frequency.

  The type of the test pad TP is almost the same as that of the external terminal provided in the interposer IP. Specifically, a test pad TP1 to which a clock signal is input, a test pad TP2 to which an address signal is input, a test pad TP3 to which a command signal is input, a test pad TP4 for inputting / outputting test data, a data strobe A test pad TP5 for inputting and outputting signals, a test pad TP6 for supplying power supply potential, and the like are included.

  At the time of testing, a normal external command that has not been decoded is input, so that a test command decoder 65 is also provided in the core chips CC0 to CC7. Further, since serial test data is input / output during the test, the core chips CC0 to CC7 are also provided with a test input / output circuit 55.

  The above is the overall configuration of the semiconductor memory device 10 according to the present embodiment. As described above, since the semiconductor memory device 10 according to the present embodiment has a configuration in which eight 1 Gb core chips are stacked, the total memory capacity is 8 Gb. Further, since there is one terminal (chip selection terminal) to which the chip selection signal / CS is input, the controller recognizes it as a single DRAM having a memory capacity of 8 Gb.

  In the semiconductor memory device 10 having the above configuration, when the power is turned on, the relief signal held in the relief information holding circuit 400 is read out and transferred to the replacement control circuit in the interface chip IF and each of the core chips CC0 to CC7. As already described, in the interface chip IF and the core chips CC0 to CC7, the defective through electrode is avoided by replacing the defective through electrode with the spare through electrode as it is, but by shifting the connection relation. Therefore, there is almost no difference in wiring length in the signal path before and after the replacement. For this reason, there is almost no skew due to replacement, and signal quality can be improved.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above embodiment, the case where data is supplied from the interface chip IF to the core chips CC0 to CC7 has been described as an example. On the contrary, when data is supplied from the core chips CC0 to CC7 to the interface chip IF. Is the same. That is, a driver circuit may be provided on the core chip CC0 to CC7 side, and a receiver circuit may be provided on the interface chip IF side. The write data supplied from the interface chip IF to the core chips CC0 to CC7 and the read data supplied from the core chips CC0 to CC7 to the interface chip IF are transferred using the same through electrode. On the other hand, both the driver circuit and the receiver circuit are provided in the interface chip IF and the core chips CC0 to CC7.

  For example, in the above embodiment, the chip stacked type DRAM has been described as an example. However, the type of stacked semiconductor chips is not particularly limited, and SRAM, PRAM (registered trademark), MRAM, RRAM (registered trademark), flash It may be another memory device such as a memory, or may be a logic device such as a CPU or DSP.

  3 TSV group, 4, 5, 6 internal circuit, 10 semiconductor memory device, 80 silicon substrate, 81 interlayer insulating film, 82 insulating ring, 83 edge, 84 back bump, 85 surface bump, 91 electrode, 92 through-hole electrode, 93 rewiring layer, 94 NFC, 95 lead frame, 96 underfill, 97 sealing resin, 98 NOR circuit, 100 delay circuit, 101-108 driver circuit, 120, 130, 140 output switching circuit, 201-208 receiver circuit, 220, 230, 240 Input switching circuit, 301-309 through electrode, CC core chip, IF interface chip, IP interposer, TSV through electrode, SB external terminal, L wiring layer, P pad, TH through hole electrode, CTRL operation signal, R1 ~ R8 Relief signal.

Claims (11)

A first semiconductor chip;
A second semiconductor chip stacked on the first semiconductor chip;
A plurality of through-electrodes connecting the first semiconductor chip and the second semiconductor chip,
The second setting circuit included in the second semiconductor chip is:
Before the setting process (Setup) at power-on, the connection between the plurality of input signal lines and the plurality of through electrodes included in the second semiconductor chip is once interrupted,
After setting the second semiconductor chip, each input signal line is connected to one of the plurality of through electrodes according to second relief information indicating connection between the plurality of input signal lines and the plurality of through electrodes. A featured semiconductor device.   2. The semiconductor according to claim 1, wherein the second relief information is supplied from the first semiconductor chip to the second semiconductor chip via a path different from the plurality of through electrodes. apparatus.   The first setting circuit included in the first semiconductor chip includes the plurality of output signal lines and the plurality of through holes included in the first semiconductor chip before the setting process or during the setting process. 2. The semiconductor device according to claim 1, wherein each output signal line is connected to one of the plurality of through electrodes in accordance with first relief information indicating connection of the electrodes.   The first setting circuit included in the first semiconductor chip includes a plurality of outputs included in the first semiconductor chip before or simultaneously with the connection of the plurality of input signal lines and the plurality of through electrodes. 2. The semiconductor device according to claim 1, wherein each output signal line is connected to one of the plurality of through electrodes in accordance with first relief information indicating connection between the signal line and the plurality of through electrodes. A second switch is inserted in the path from the input signal line to the through electrode,
2. The semiconductor device according to claim 1, wherein in the setting process, the connection between the input signal line and the through electrode is cut off by turning off the second switch by a predetermined operation signal.   6. The semiconductor device according to claim 5, wherein the operation signal turns off the second switch at the start of the setting process, and turns on the second switch after a predetermined period has elapsed since the start.   6. The operation signal is a signal supplied to cut off a connection between the second semiconductor chip and the first semiconductor chip during an operation test of the second semiconductor chip. A semiconductor device according to 1. A first switch is interposed in a path from the output signal line included in the first semiconductor chip to the through electrode;
6. In the setting process, the output signal line and the through electrode are shut off by turning off the first switch in addition to the second switch by the operation signal. Semiconductor device. Each of the first semiconductor chips includes n driver circuits assigned numbers 1 to n (n is a natural number),
The second semiconductor chip includes n receiver circuits provided corresponding to the first to n-th driver circuits, respectively, and assigned with numbers 1 to n, respectively.
Numbers 1 to n + m (m is a natural number) are assigned to the plurality of through electrodes,
The first setting circuit connects the output terminals of the i-th driver circuit (i is an integer from 1 to n) to any one of the i-th through i + m-th through electrodes, thereby connecting the n driver circuits. Connect to each through electrode,
The second setting circuit of the second semiconductor chip connects the input terminal of the i-th receiver circuit (i is an integer from 1 to n) to any of the i-th through i + m-th through electrodes. The semiconductor device according to claim 1, wherein the n receiver circuits are connected to different through electrodes.   2. The semiconductor device according to claim 1, wherein among the plurality of through electrodes, a through electrode that is not connected to the first and second semiconductor chips is a defective through electrode.   The semiconductor device according to claim 1, wherein the first semiconductor chip is an interface chip, and the second semiconductor chip is a core chip.

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