JP2012064282A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently replace a defective cell caused after packaging with a redundant cell.SOLUTION: A semiconductor device 10 comprises a plurality of chips 100, a chip 200 for controlling the chips 100, and internal wiring 400 for connecting the chips 100 with the chip 200. Each chip 100 includes an optical fuse 120, a latch circuit 101 for storing information of the optical fuse 120, a latch circuit 102 for storing information of an electric fuse 220 supplied from the chip 200 via the internal wiring 400, and a selection circuit 151 for selecting the information of one of the latch circuits 101 and 102. Based on the selected information, the chip 100 generates a redundancy determination signal HIT. According to the present invention, since the information of the electric fuse is transmitted from the chip 200 to the chip 100 via the internal wiring, the provision of the electric fuse for the chip 100 is not necessary and the transmission does not need an external terminal, so that the startup time will not increase.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of replacing a defective memory cell with a redundant cell.

  A semiconductor memory typified by a DRAM (Dynamic Random Access Memory) includes a large number of memory cells. However, it is inevitable that some memory cells become defective due to the influence of manufacturing conditions and the like. In order to ship such a semiconductor memory as a non-defective product, a redundant repair technique that replaces a defective memory cell with a redundant cell is essential.

  In the redundancy repair technique, first, an operation test is performed on a semiconductor memory in a wafer state, and an address (defective address) of a defective memory cell is detected. Then, the detected address is programmed into an optical fuse provided in the semiconductor memory. An optical fuse is a fuse that can be cut by irradiation with a laser beam, for example, and once cut, it cannot be returned to a conductive state, so that information can be stored in a nonvolatile manner and irreversibly. When an access is requested to the address programmed in the optical fuse, an alternative access is made to a redundant cell (alternative cell) instead of a defective memory cell, thereby relieving the address. It will be.

  Since defects in memory cells mainly occur at the wafer stage (a manufacturing process for forming a plurality of circuits on a wafer, so-called pre-process), most defects are remedied by replacement using an optical fuse. However, after replacement using an optical fuse, it is a post-process including assembly, and a new defect may occur due to, for example, a thermal load during packaging. Such defects can no longer be remedied using optical fuses.

  As a method for solving this problem, Patent Document 1 proposes a semiconductor device capable of using both replacement using an optical fuse and replacement using an electrical fuse. However, the semiconductor device described in Patent Document 1 has a problem that the chip area increases because it is necessary to provide both an optical fuse and an electrical fuse in one chip.

  On the other hand, in Patent Document 2, a defective address of a volatile memory (first semiconductor device) generated after packaging is stored in a non-volatile memory (second semiconductor device) mounted on the same module substrate and activated. Sometimes, a method of loading from the second semiconductor device to the first semiconductor device has been proposed. According to this method, since it is not necessary to provide an electric fuse on the volatile memory side to be repaired such as a DRAM, an increase in chip area can be suppressed.

JP 2002-25289 A JP 2007-328914 A

  However, in the method described in Patent Document 2, since the external terminal of the first semiconductor device is used for loading the defective address, the initialization operation can be performed between the memory controller and the memory module during the loading period. It will disappear. This causes a problem that it takes time to start the memory module.

  In recent years, among the components of semiconductor memory, the back-end part such as the memory core and the front-end part such as the interface circuit are separated into separate chips (core chip and interface chip), and these are stacked and packaged together. A semiconductor device of the above type (a type sealed with resin or the like) has been proposed. In such a type of semiconductor device, if the interface chip in which the front end unit is integrated has the function of an electric fuse and the information on the electric fuse is transferred from the interface chip to the core chip, the core chip in which the back end unit is integrated The load work of the defective address via the external terminal of the semiconductor device becomes unnecessary while preventing the area from increasing. It is possible to prevent an increase in area due to mounting an electric fuse for repairing a defect of a memory cell included in the core chip generated after packaging on the core chip. The present invention has been made based on such technical knowledge.

  A semiconductor device according to the present invention communicates with an external terminal, a plurality of first chips each having a plurality of memory cells, and the outside of the semiconductor device via the external terminals, and controls the plurality of first chips. A second chip, and a plurality of through-electrodes that are provided in each of the plurality of first chips and penetrate the substrate of the first chip, and electrically connect the first chip and the second chip. And the plurality of first chips communicate with each other via the second chip without directly communicating with the outside of the semiconductor device when accessing the plurality of memory cells. Further, the second chip includes an electrical fuse, and each of the plurality of first chips includes an optical fuse and a first latch circuit for holding information on the optical fuse, and the internal wiring. The A second latch circuit for holding the information of the electric fuse supplied in this manner, a selection circuit for selecting one of the information of the first and second latch circuits, and one selected from the selected information. A first control circuit for generating a redundancy judgment signal.

  The semiconductor device according to the present invention includes an external signal terminal, a plurality of memory cells each having a plurality of memory cells, a plurality of core chips not directly connected to the external signal terminal, and an interface connected to the external signal terminal and controlling the plurality of core chips. A chip, the plurality of core chips and the interface chip are stacked, and the plurality of core chips and the interface chip are electrically connected through through electrodes provided in the plurality of core chips, respectively. The interface chip includes an electrical fuse for storing an address of a defective memory cell included in any of the plurality of core chips, and each of the plurality of core chips is defective among the plurality of memory cells. A redundant cell that replaces the memory cell, An optical fuse for storing an address of a memory cell to be stored, a selection circuit for selecting one of an address read from the optical fuse and an address read from the electrical fuse, and a selection circuit selected by the selection circuit And an access control circuit for accessing the redundant cell in place of the defective memory cell in response to a request for access to the address.

  According to the present invention, since the information of the electrical fuse is transferred from the second chip to the first chip via the through electrode, it is not necessary to provide the electrical fuse in the first chip, and the semiconductor is used for the transfer. Since the external terminal of the device is not used, the startup time of the semiconductor device does not increase.

It is a block diagram for demonstrating the principle of this invention. It is typical sectional drawing for demonstrating the structure of the semiconductor device 10 by preferable embodiment of this invention. It is a figure for demonstrating the kind of TSV provided in the core chip. It is sectional drawing which shows the structure of TSV1 of the type shown to Fig.3 (a). 2 is a block diagram showing a circuit configuration of a semiconductor device 10. FIG. It is a flowchart for demonstrating the replacement method of the defective cell contained in core chip CC0-CC7. It is a flowchart for demonstrating in detail the operation | movement of step S15, S16 shown in FIG. 5 is a flowchart for explaining an operation of loading replacement data programmed in an electrical fuse circuit 83. 3 is a block diagram showing the configuration of an electrical fuse circuit 83 in more detail. FIG. 3 is a block diagram showing in more detail the configuration of a defective address latch circuit 56. FIG. FIG. 10 is another block diagram showing the configuration of the defective address latch circuit 56 in more detail. 3 is a block diagram showing in more detail the configurations of an electrical fuse circuit 83 and a defective address latch circuit 56. FIG. 6 is a diagram for explaining the relationship between the selection order of the optical fuse circuit 55 and the selection order of the electrical fuse circuit 83. FIG. It is a circuit diagram showing an example of an address comparison circuit 51a and a selection circuit 56e. It is a circuit diagram which shows the other example of the address comparison circuit 51a and the selection circuit 56e.

  A typical example of a technical idea (concept) for solving the problems of the present invention is shown below. However, it goes without saying that the claimed contents of the present application are not limited to this technical idea, but are the contents described in the claims of the present application.

  That is, in the semiconductor device according to the present invention, a plurality of core chips integrated with a back end part and an interface chip integrated with a front end part are stacked, an optical fuse is provided on the core chip side, and an electric fuse is provided on the interface chip side. The technical idea is to transfer information on the electrical fuse to the core chip via the through electrode when the semiconductor device is activated. This eliminates the need to provide an electrical fuse on the core chip side, thereby preventing an increase in the area of the core chip. In addition, since the information on the electrical fuse is transferred to the core chip via the through electrode, the interface chip performs an initialization operation that needs to be performed with the memory controller outside the semiconductor device via the external terminal of the semiconductor device. There is no hindrance.

  FIG. 1 is a block diagram for explaining the principle of the present invention.

  As shown in FIG. 1, the semiconductor device according to the present invention includes a plurality of first chips 100 and second chips 200. The plurality of first chips 100 are chips having the same circuit configuration, and each includes a memory cell array 110 including a plurality of memory cells. Since the first chip 100 communicates via the second chip 200 without directly communicating with the outside of the semiconductor device, the first chip 100 is not directly connected to the external terminal 300. The plurality of first chips 100 and the second chip 200 are connected to each other through the corresponding internal wiring 400. The internal wiring 400 includes a through electrode that penetrates the substrate of the corresponding first chip 100.

  The second chip 200 is a chip that controls the plurality of first chips 100 and is directly connected to the external terminal 300 in order to communicate with the outside of the semiconductor device. The second chip 200 includes an access control circuit 210, an electric fuse 220, and a flag fuse 230. The flag fuse 230 has the same structure as the electric fuse 220, and stores first flag information FL1 indicating whether or not information is set in the electric fuse 220. The electrical fuse information AF programmed in the electrical fuse 220 and the flag information FL 1 programmed in the flag fuse 230 are supplied to the output circuit 240. The output circuit 240 serves to supply the electrical fuse information AF and flag information FL1 to the first chip 100 via the internal wiring 400.

  The first chip 100 includes an optical fuse 120 and a first latch circuit 101 that holds optical fuse information LF programmed in the optical fuse 120. Further, the first chip 100 has a flag fuse 130. The flag fuse 130 has the same structure as the optical fuse 120, and stores second flag information FL2 indicating whether or not the optical fuse information LF is set in the optical fuse 120. The second flag information FL2 is latched by the fourth latch circuit 104.

  The electrical fuse information AF and the first flag information FL1 transferred from the second chip 200 via the internal wiring 400 are received by the input circuit 140 provided in the first chip 100, and each of them is a second latch circuit. 102 and the third latch circuit 103.

  The optical fuse information LF latched in the first latch circuit and the electrical fuse information AF latched in the second latch circuit are supplied to the selection circuit 151 included in the control circuit 150. The selection circuit 151 is a circuit that selects one of the optical fuse information LF and the electrical fuse information AF. The selection is made by the first and second latches latched by the third and fourth latch circuits 103 and 104. This is performed based on the flag information FL1, FL2. The selected optical fuse information LF or electrical fuse information AF is supplied to an address comparison circuit 152 included in the control circuit 150.

  The address comparison circuit 152 compares the selected optical fuse information LF or electrical fuse information AF with the address ADD requested to be accessed, and activates the redundancy judgment signal HIT when the two match. . When the redundancy judgment signal HIT is activated, access to the memory cell array 110 by the access control circuit 160 is stopped, and instead, access to the redundant array 170 including redundant cells is performed. As a result, the redundant cell is accessed instead of the defective memory cell.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 is a schematic cross-sectional view for explaining the structure of the semiconductor device 10 according to the preferred embodiment of the present invention.

  As shown in FIG. 2, the semiconductor device 10 according to the present embodiment has eight core chips CC0 to CC7 each having the same function and structure and manufactured with the same manufacturing mask, and manufactured with a manufacturing mask different from the core chip. It has a structure in which one interface chip IF and one interposer IP are stacked. The core chips CC0 to CC7 and the interface chip IF are semiconductor chips using a silicon substrate, and all of them are electrically connected to adjacent chips vertically by a large number of through silicon vias TSV (Through Silicon Via) penetrating the silicon substrate. . On the other hand, the interposer IP is a circuit board made of resin, and a plurality of external terminals (solder balls) SB are formed on the back surface IPb thereof.

  The core chips CC0 to CC7 are "known and general itself including both a so-called front-end unit that interfaces with the outside via an external terminal, a plurality of memory cells, and a so-called back-end unit that accesses these memory cells. Although it is a normal memory chip that can operate even with a single chip and can communicate directly with the memory controller, it is not particularly limited. Among the circuit blocks included in the 1 Gb DDR3 (Double Data Rate 3) SDRAM (Synchronous Dynamic Random Access Memory) This is a semiconductor chip from which a so-called front end portion (front end function) for interfacing with is deleted. In other words, in principle, it is a semiconductor chip in which only circuit blocks belonging to the back-end part are integrated. The circuit block included in the front-end unit controls the parallel / serial conversion circuit (data latch circuit) that performs parallel / serial conversion of input / output data between the memory cell array and data input / output terminals, and controls the data input / output timing. For example, a DLL (Delay Locked Loop) circuit may be used. Details will be described later. The interface chip IF is a semiconductor chip in which only the front end portion is integrated. Therefore, the operating frequency of the interface chip is higher than the operating frequency of the core chip. Since the core chips CC0 to CC7 do not include these circuits belonging to the front end unit, the core chips CC0 to CC7 are operated alone in the core chip manufacturing process except during a test operation in which the core chip is performed in a wafer state. It is not possible. An interface chip IF is required to operate the core chips CC0 to CC7. Therefore, the integration degree of the core chip is higher than that of a general single chip. The interface chip IF has a front-end function for communicating with the outside at a first operating frequency, and the plurality of core chips CC0 to CC7 communicate only with the interface chip IF and have a second lower than the first operating frequency. It has a back-end function that communicates at the operating frequency. Therefore, each of the plurality of core chips CC0 to CC7 includes a memory cell array that stores a plurality of information, and a plurality of core chips CC0 to CC7 per I / O (DQ) supplied in parallel from the plurality of core chips CC0 to CC7 to the interface chip IF. The read data is a plurality of bits related to one read command given from the interface chip IF to the core chip. The so-called plurality of bits corresponds to a known number of prefetch data.

  The interface chip IF functions as a common front end unit for the eight core chips CC0 to CC7. Therefore, all external accesses are performed via the interface chip IF, and data input / output is also performed via the interface chip IF. In the present embodiment, the interface chip IF is disposed between the interposer IP and the core chips CC0 to CC7. However, the position of the interface chip IF is not particularly limited, and may be disposed above the core chips CC0 to CC7. Alternatively, it may be arranged on the back surface IPb of the interposer IP. When the interface chip IF is arranged face down on the top of the core chips CC0 to CC7 or face up on the back surface IPb of the interposer IP, there is no need to provide a TSV in the interface chip IF. Further, the interface chip IF may be arranged so as to be sandwiched between two interposers IP.

  The interposer IP functions as a rewiring board for ensuring the mechanical strength of the semiconductor device 10 and increasing the electrode pitch. That is, the electrode 91 formed on the upper surface IPa of the interposer IP is drawn out to the back surface IPb by the through-hole electrode 92, and the pitch of the external terminals SB is expanded by the rewiring layer 93 provided on the back surface IPb. Although only two external terminals SB are illustrated in FIG. 2, a large number of external terminals are actually provided. The layout of the external terminal SB is the same as that in the DDR3-type SDRAM defined by the standard. Therefore, it can be handled as one DDR3-type SDRAM from an external controller.

  As shown in FIG. 2, the upper surface of the uppermost core chip CC0 is covered with an NCF (Non-Conductive Film) 94 and a lead frame 95, and the gaps between the core chips CC0 to CC7 and the interface chip IF are underfilled. 96 and the periphery thereof is covered with a sealing resin 97. Thereby, each chip is physically protected.

  Most of the TSVs provided in the core chips CC0 to CC7 are short-circuited with TSVs of other layers provided at the same position in a plan view seen from the stacking direction, that is, when viewed from the arrow A shown in FIG. Yes. That is, as shown in FIG. 3A, the upper and lower TSV1 provided at the same position in a plan view are short-circuited, and one wiring is configured by these TSV1. These TSV1 provided in each of the core chips CC0 to CC7 are respectively connected to the internal circuit 4 in the core chip. Therefore, input signals (command signal, address signal, etc.) supplied from the interface chip IF to the TSV1 shown in FIG. 3A are commonly input to the internal circuits 4 of the core chips CC0 to CC7. Further, output signals (data and the like) supplied from the core chips CC0 to CC7 to the TSV1 are wired-or and input to the interface chip IF.

  On the other hand, as shown in FIG. 3B, some TSVs are not directly connected to other layers TSV2 provided at the same position in plan view, but are provided in the core chips CC0 to CC7. Connected through the internal circuit 5. That is, these internal circuits 5 provided in the core chips CC0 to CC7 are cascade-connected via the TSV2. This type of TSV2 is used to sequentially transfer predetermined information to the internal circuit 5 provided in each of the core chips CC0 to CC7. Such information includes layer address information described later.

  Furthermore, as shown in FIG. 3C, some other TSV groups are short-circuited with TSVs of other layers provided at different positions in plan view. For this type of TSV group 3, internal circuits 6 of the core chips CC0 to CC7 are connected to a TSV 3a provided at a predetermined position P in plan view. This makes it possible to selectively input information to the internal circuit 6 provided in each core chip. Such information includes defective chip information described later.

  As described above, there are three types (TSV1 to TSV3) of TSVs provided in the core chips CC0 to CC7 shown in FIGS. As described above, most TSVs are of the type shown in FIG. 3A, and address signals, command signals, clock signals, etc. are transferred from the interface chip IF to the core chip CC0 via the TSV1 of the type shown in FIG. To CC7. Also, read data and write data are input / output to / from the interface chip IF via the TSV1 of the type shown in FIG. On the other hand, TSV2 and TSV3 of the types shown in FIGS. 3B and 3C are used to give individual information to the core chips CC0 to CC7 having the same structure.

  FIG. 4 is a cross-sectional view showing the structure of TSV1 of the type shown in FIG.

  As shown in FIG. 4, the TSV1 is provided so as to penetrate the silicon substrate 180 and the interlayer insulating film 181 on the surface thereof. An insulating ring 182 is provided around the TSV1, thereby ensuring insulation between the TSV1 and the transistor region. In the example shown in FIG. 4, the insulating ring 182 is doubled, and the capacitance between the TSV 1 and the silicon substrate 180 is reduced.

  An end 183 of TSV1 on the back surface side of the silicon substrate 180 is covered with a back surface bump 184. The back bump 184 is an electrode in contact with the front bump 185 provided on the lower core chip. The surface bump 185 is connected to the end portion 186 of the TSV1 through pads P0 to P3 provided on the wiring layers L0 to L3 and a plurality of through-hole electrodes TH1 to TH3 connecting the pads. Thereby, the front surface bump 185 and the back surface bump 184 provided at the same position in a plan view are short-circuited. Note that connection to an internal circuit (not shown) is made via internal wiring (not shown) drawn from pads P0 to P3 provided in the wiring layers L0 to L3.

  FIG. 5 is a block diagram showing a circuit configuration of the semiconductor device 10.

  As shown in FIG. 5, the external terminals provided in the interposer IP include clock terminals 11a and 11b, a clock enable terminal 11c, command terminals 12a to 12f, address terminals 13a to 13c, a data input / output terminal 14, and a data strobe terminal. 15a and 15b, a calibration terminal 16, power supply terminals 17a and 17b, and a data mask terminal 18 are included. Of these external terminals, all external signal terminals except for the power supply terminals 17a and 17b are connected to the interface chip IF and are not directly connected to the core chips CC0 to CC7.

  First, the connection relationship between these external terminals and the interface chip IF having the front-end function, and the circuit configuration of the interface chip IF will be described.

  The clock terminals 11a and 11b are terminals to which external clock signals CK and / CK are supplied, respectively, and the clock enable terminal 11c is a terminal to which a clock enable signal CKE is input. The supplied external clock signals CK and / CK and the clock enable signal CKE are supplied to the clock generation circuit 21 provided in the interface chip IF. In this specification, a signal having “/” at the head of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, the external clock signals CK and / CK are complementary signals. The clock generation circuit 21 is a circuit that generates an internal clock signal ICLK. The generated internal clock signal ICLK is supplied to various circuit blocks in the interface chip IF and is also common to the core chips CC0 to CC7 via the TSV. To be supplied.

  The interface chip IF includes a DLL circuit 22, and the input / output clock signal LCLK is generated by the DLL circuit 22. The input / output clock signal LCLK is supplied to the input / output buffer circuit 23 included in the interface chip IF. The DLL function is for controlling the front end with the signal LCLK whose synchronization with the outside is matched when the semiconductor device 10 communicates with the outside. Therefore, the DLL function is not required for the core chips CC0 to CC7 which are back ends.

  The command terminals 12a to 12f are terminals to which a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, an on-die termination signal ODT, and a reset signal / RESET are respectively supplied. is there. These command signals are supplied to a command input buffer 31 provided in the interface chip IF. These command signals supplied to the command input buffer 31 are supplied to the control logic 32. The control logic 32 includes a latency controller 32a and a command decoder 32b, and generates various internal commands ICMD by holding, decoding and counting command signals in synchronization with the internal clock ICLK. The generated internal command ICMD is supplied to various circuit blocks in the interface chip IF, and is also commonly supplied to the core chips CC0 to CC7 via the TSV buffer 34 and the TSV.

  The address terminal 13a is a terminal to which bank addresses BA0 to BA2 are supplied, the address terminal 13b is a terminal to which address signals A0 to A (N-3) are supplied, and the address terminal 13c is an address signal AN to A (N -2) is a terminal to be supplied. The supplied address signals A0-AN and BA0-BA2 are supplied to an address input buffer 41 provided in the interface chip IF. The output of the address input buffer 41 is supplied to the control logic 32 and the layer address buffer 48. The layer address buffer 48 plays a role of commonly supplying a layer address (layer information) EXA to the core chips CC0 to CC7 via the TSV. If the entry is made in the mode register set, the address signals A0 to A15 supplied to the control logic 32 are supplied to the mode register 42 provided in the interface chip IF. The bank addresses BA0 to BA2 are decoded by the control logic 32, and a bank selection signal obtained thereby is supplied to the FIFO circuit 25. This is because the bank selection of write data is performed in the interface chip IF.

  The data input / output terminal 14 is a terminal for inputting / outputting read data or write data DQ0 to DQ7. The data strobe terminals 15a and 15b are terminals for inputting / outputting strobe signals DQS and / DQS. Further, the data mask terminal 18 is a terminal to which a data mask signal DM is supplied. The data input / output terminal 14, data strobe terminals 15a and 15b, and data mask terminal 18 are connected to an input / output buffer circuit 23 provided in the interface chip IF. The input / output buffer circuit 23 includes an input buffer IB and an output buffer OB. In synchronization with the input / output clock signal LCLK supplied from the DLL circuit 22, the read data or write data DQ0 to DQ7 and the strobe signal are provided. Input / output DQS and / DQS. Further, when the internal on-die termination signal IODT is supplied from the control logic 32, the input / output buffer circuit 23 causes the output buffer OB to function as a termination resistor. Further, the impedance code DRZQ is supplied from the calibration circuit 24 to the input / output buffer circuit 23, thereby designating the impedance of the output buffer OB.

  The calibration circuit 24 includes a replica buffer RB having the same circuit configuration as that of the output buffer OB. When a calibration signal ZQC is supplied from the control logic 32, an external resistor (connected to the calibration terminal 16 ( The calibration operation is performed by referring to the resistance value (not shown). The calibration operation is an operation for matching the impedance of the replica buffer RB with the resistance value of the external resistor, and the obtained impedance code DRZQ is supplied to the input / output buffer circuit 23. Thereby, the impedance of the output buffer OB is adjusted to a desired value.

  The input / output buffer circuit 23 is connected to the FIFO circuit 25. The FIFO circuit 25 includes a FIFO circuit unit (not shown) that realizes a FIFO function that operates by latency control that realizes a well-known DDR function, and a multiplexer (not shown), and is a parallel read supplied from the core chips CC0 to CC7. This circuit converts data serially and converts serial write data supplied from an input / output buffer into parallel data. Therefore, the FIFO circuit 25 and the input / output buffer circuit 23 are serially connected, and the FIFO circuit 25 and the core chips CC0 to CC7 are parallelly connected. The parallel write data output from the FIFO circuit 25 is supplied to the core chips CC0 to CC7 via the TSV buffer 26, and the parallel read data output from the core chips CC0 to CC7 is supplied to the FIFO circuit 25 via the TSV buffer 26. Supplied. In the present embodiment, the core chips CC0 to CC7 are back end portions of the DDR3 type SDRAM, and the prefetch number is 8 bits. The FIFO circuit 25 and the core chips CC0 to CC7 are connected to each bank, and the number of banks included in each core chip CC0 to CC7 is eight banks. Accordingly, the connection between the FIFO circuit 25 and the core chips CC0 to CC7 is 64 bits per 1 DQ (8 bits × 8 banks).

  Thus, parallel data that has not been serially converted is basically input / output between the FIFO circuit 25 and the core chips CC0 to CC7. That is, in a normal SDRAM (that is, a front end and a back end are configured by one chip), data is input / output serially to / from the outside of the chip (that is, the data input / output terminals are per 1DQ). On the other hand, in the core chips CC0 to CC7, data is input / output to / from the interface chip IF in parallel. This is an important difference between the normal SDRAM and the core chips CC0 to CC7. However, it is not essential to input / output all prefetched parallel data using different TSVs, and the number of TSVs required per DQ is reduced by performing partial parallel / serial conversion on the core chips CC0 to CC7 side. It doesn't matter. For example, instead of inputting / outputting 64 bits of data per 1DQ using different TSVs, the number of TSVs required per 1DQ is halved by performing 2-bit parallel / serial conversion on the core chips CC0 to CC7. It may be reduced to (32).

  Further, the FIFO circuit 25 is provided with a function capable of testing in units of interface chips. The interface chip has no back-end part. For this reason, it cannot be operated as a single unit in principle. However, if the single operation is impossible, the operation test of the interface chip in the wafer state cannot be performed. This indicates that the semiconductor device 10 can only be tested after the assembly process of the interface chip and the plurality of core chips, and means that the interface chip IF is tested by testing the semiconductor device 10. To do. If the interface chip IF has a defect that cannot be recovered, the entire semiconductor device 10 is lost. In consideration of this point, in the present embodiment, the FIFO circuit 25 is provided with a part of a pseudo back-end unit for testing, so that a simple storage function is possible at the time of testing.

  The power supply terminals 17a and 17b are terminals to which power supply potentials VDD and VSS are supplied, respectively, and connected to the power-on detection circuit 43 provided in the interface chip IF and also connected to the core chips CC0 to CC7 through the TSV. Has been. The power-on detection circuit 43 is a circuit that detects power-on, and activates the layer address control circuit 45 provided in the interface chip IF when power-on is detected.

  The layer address control circuit 45 is a circuit for changing the layer address according to the I / O configuration of the semiconductor device 10 according to the present embodiment. As described above, the semiconductor device 10 according to the present embodiment includes the eight data input / output terminals 14, so that the maximum number of I / Os can be set to 8 bits (DQ0 to DQ7). The number of / O is not fixed to this, and can be set to 4 bits (DQ0 to DQ3), for example. The address allocation is changed according to the number of I / Os, and the layer address is also changed. The layer address control circuit 45 is a circuit that controls a change in address allocation according to the number of I / Os, and is commonly connected to each of the core chips CC0 to CC7 via the TSV.

  The interface chip IF is also provided with a layer address setting circuit 44. The layer address setting circuit 44 is connected to the core chips CC0 to CC7 via the TSV. The layer address setting circuit 44 is cascade-connected to the layer address generation circuit 46 of the core chips CC0 to CC7 using the TSV2 of the type shown in FIG. 3B, and the layer set to the core chips CC0 to CC7 at the time of testing. It plays the role of reading the address.

  Further, a defective chip information holding circuit 33 is provided in the interface chip IF. The defective chip information holding circuit 33 is a circuit that holds a chip number when a defective core chip that does not operate normally is found after assembly. The defective chip information holding circuit 33 is connected to the core chips CC0 to CC7 through the TSV. The defective chip information holding circuit 33 is connected to the core chips CC0 to CC7 while being shifted using the TSV3 of the type shown in FIG.

  Furthermore, an electrical fuse circuit 83 is provided in the interface chip IF. The electrical fuse circuit 83 is a circuit in which information necessary for replacing a defect found after assembly with a redundant circuit is stored. The information stored in the electrical fuse circuit 83 includes at least information related to defects in TSV and information related to defects in memory cells in the core chips CC0 to CC7. TSV defects are remedied by replacing them with other TSVs by the TSV buffers 26 and 34, but since this is not directly related to the gist of the present invention, detailed description thereof is omitted. TSV defects are detected using the DFT circuit 81 and programmed into the electrical fuse circuit 83.

  The electric fuse circuit 83 stores a row address indicating a replacement source word line or a column address indicating a replacement source bit line. The redundant word line or redundant bit line included in the core chips CC0 to CC7 is used as the redundant word line or redundant bit line to be replaced.

  Of the information stored in the electrical fuse circuit 83, information related to the defective address of the memory cell is serial-converted into serial data ALD by the serializer 84 and then transferred to the core chips CC0 to CC7 via the TSV. As shown in FIG. 5, a plurality of TSVs are used in parallel in order to prevent the transfer of a defective address from being disabled due to a defect in the TSV itself. In addition, a plurality of TSVs are used in parallel for signals using TSVs that cannot be replaced, for example, a layer address EXA or a determination signal P / F described later.

  The program for the electrical fuse circuit 83 is performed by the analysis circuit 82. The analysis circuit 82 is activated by the signal FENT which is the output of the DFT circuit 37, and based on the address supplied from the control logic 32 and the determination signal P / F supplied from the core chips CC0 to CC7, the analysis circuit 82 Analyze appearance patterns. The analysis identifies a pattern that can be replaced most efficiently when a defective memory cell is replaced in units of word lines or bit lines. This means that the address stored by the electrical fuse circuit 83 is not an address in units of memory cells but an address in units of word lines or bit lines. Replacement in units of word lines or bit lines is performed in the wafer state when the core chips CC0 to CC7 are manufactured, and the remaining redundant word lines or redundant bit lines not used for replacement in the wafer state are replaced by the electric fuse circuit 83. Will be used by. Therefore, the analysis circuit 82 is a fail memory repair analyzer.

  On the other hand, reading of information programmed in the electric fuse circuit 83 is performed using the load circuit 85. The load circuit 85 reads information programmed in the electric fuse circuit 83 and generates timing signals ALFL and ALCK, thereby synchronizing the serializer 84 and the core chips CC0 to CC7.

  The above is the outline of the connection relationship between the external terminal and the interface chip IF and the circuit configuration of the interface chip IF. Next, the circuit configuration of the core chips CC0 to CC7 will be described.

  As shown in FIG. 5, each of the memory cell arrays 50 included in the core chips CC0 to CC7 having the back-end function is divided into 8 banks. A bank is a unit that can accept commands individually. In other words, each bank can operate independently with non-exclusive control. Each bank can be accessed independently from outside the semiconductor device 10 (an external controller that controls the semiconductor device 10). For example, the memory cell array 50 of the bank 1 and the memory cell array 50 of the bank 2 are non-exclusive control that can individually control access to the corresponding word line WL, bit line BL, etc. in the same period on the time axis by different commands. It is a relationship. For example, the bank 2 can be controlled to be active while the bank 1 is kept active (the word line and the bit line are active). However, the external terminals (for example, a plurality of control terminals and a plurality of I / O terminals) of the semiconductor device 10 are shared. In the memory cell array 50, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections (in FIG. 5, one word line WL, 1 Only one bit line BL and one memory cell MC are shown).

  The memory cell array 50 includes a row redundant array 50a composed of redundant cells RMC connected to a plurality of redundant word lines RWL and a column redundant array 50b composed of redundant cells RMC connected to a plurality of redundant bit lines RBL. Yes. The row redundant array 50a is accessed as a substitute when the memory cell to which access is requested belongs to a defective word line, and the column redundant array 50b is used when the memory cell to which access is requested belongs to a defective bit line. Alternate access. Such alternative access is performed when access is requested to an address stored in the above-described electrical fuse circuit 83 or optical fuse circuits 55 and 57 described later.

  Selection of the word line WL is performed by the row decoder 51. The bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 53. Selection of the sense amplifier SA is performed by the column decoder 52.

  The row decoder 51 is controlled by a row address supplied from the row control circuit 61. The row control circuit 61 includes an address buffer 61 a that receives a row address supplied from the interface chip IF via the TSV, and the row address buffered by the address buffer 61 a is supplied to the row decoder 51. The address signal supplied via the TSV is supplied to the row control circuit 61 and the like via the TSV receiver 35 and the control logic 63. The row control circuit 61 also includes a refresh counter 61b. When an internal refresh command is issued from the control logic circuit 63, the row address indicated by the refresh counter 61b is supplied to the row decoder 51.

  The row decoder 51 includes an address comparison circuit (not shown), and compares the row address supplied from the row control circuit 61 with the address held in the defective address latch circuit 56. The defective address latch circuit 56 is a circuit that latches the defective row address read from the optical fuse circuit 55. The defective address latch circuit 56 includes not only a circuit that latches a defective row address read from the optical fuse circuit 55 but also a circuit that latches a defective row address read from the electrical fuse circuit 83. As a result of comparison by the row decoder 51, when both addresses match, access is made to a redundant word line included in the row redundant array 50a instead of the word line indicated by the row address. On the other hand, if the two addresses do not match, the word line indicated by the row address is accessed as it is.

  The optical fuse circuit 55 includes a plurality of fuse sets, and each fuse set corresponds to a plurality of redundant word lines in the row redundant array 50a. That is, when a row address in a certain fuse set is programmed, when an access to the row address is requested, the redundant word line associated with the fuse set is accessed. Further, some fuse sets included in the optical fuse circuit 55 correspond one-to-one with the fuse sets included in the electric fuse circuit 83. Therefore, a redundant word line designated as a replacement destination by a part of the fuse set included in the optical fuse circuit 55 can also be specified as a replacement destination by a fuse set included in the electrical fuse circuit 83. However, the optical fuse circuit 55 and the electric fuse circuit 83 do not compete with each other, and one redundant word line is replaced by one of the fuse set included in the optical fuse circuit 55 and the fuse set included in the electric fuse circuit 83. Used as a destination.

  The column decoder 52 is controlled by a column address supplied from the column control circuit 62. The column control circuit 62 includes an address buffer 62a that receives a column address supplied from the interface chip IF via the TSV, and the column address buffered by the address buffer 62a is supplied to the column decoder 52. The column control circuit 62 also includes a burst counter 62b that counts the burst length.

  The column decoder 52 includes an address comparison circuit (not shown), and compares the column address supplied from the column control circuit 62 with the address held in the defective address latch circuit 58. The defective address latch circuit 58 is a circuit that latches the defective column address read from the optical fuse circuit 57. The defective address latch circuit 58 includes not only a circuit that latches a defective column address read from the optical fuse circuit 55 but also a circuit that latches a defective column address read from the electrical fuse circuit 83. As a result of comparison by the column decoder 52, if both addresses match, access is made to a redundant bit line included in the column redundant array 50b instead of the bit line indicated by the column address. On the other hand, if the two addresses do not match, the bit line indicated by the column address is accessed as it is. Access to the bit line is performed by selecting the corresponding sense amplifier SA in the sense circuit 53.

  The optical fuse circuit 57 includes a plurality of fuse sets, and each fuse set corresponds to a plurality of redundant bit lines in the column redundant array 50b. That is, when a column address in a certain fuse set is programmed, when access to the column address is requested, the redundant bit line associated with the fuse set is accessed. Further, some fuse sets included in the optical fuse circuit 57 correspond one-to-one with the fuse sets included in the electric fuse circuit 83. Therefore, a redundant bit line designated as a replacement destination by a part of the fuse set included in the optical fuse circuit 55 can also be specified as a replacement destination by a fuse set included in the electric fuse circuit 83. However, the optical fuse circuit 57 and the electric fuse circuit 83 do not compete with each other, and one redundant bit line is replaced by either the fuse set included in the optical fuse circuit 57 or the fuse set included in the electric fuse circuit 83. Used as a destination.

  The sense amplifier SA selected by the column decoder 52 is further connected to the data control circuit 54 via some amplifiers (such as sub-amplifiers and data amplifiers) not shown. As a result, 8-bit (= prefetch number) read data is output from the data control circuit 54 per I / O (DQ) during the read operation, and 8-bit write data is data during the write operation. Input to the control circuit 54. The data control circuit 54 and the interface chip IF are connected in parallel via the TSV buffer 27 and the TSV. Further, the data control circuit 54 includes a test circuit 54a that performs pass / fail judgment during a test operation and outputs the result of the pass / fail judgment as a judgment signal P / F.

  The control logic circuit 63 is a circuit that receives the internal command ICMD supplied from the interface chip IF via the TSV and controls the operations of the row control circuit 61 and the column control circuit 62 based on the internal command ICMD. A layer address comparison circuit (chip information comparison circuit) 47 is connected to the control logic circuit 63. The layer address comparison circuit 47 is a circuit that detects whether or not the core chip is an access target, and the detection is performed using a layer address EXA that is a part of an address signal supplied from the interface chip IF via the TSV. This is done by comparing the layer address LID (chip identification information) set in the layer address generation circuit 46. The layer address EXA supplied from the interface chip IF is input to the core chips CC0 to CC7 via the input receiver 49.

  In the layer address generation circuit 46, a unique layer address is set to each of the core chips CC0 to CC7 at the time of initialization. The layer address setting method is as follows. First, when the semiconductor device 10 is initialized, a minimum value (0, 0, 0) is set as an initial value in the layer address generation circuit 46 of each of the core chips CC0 to CC7. The layer address generation circuits 46 of the core chips CC0 to CC7 are cascade-connected using a TSV of the type shown in FIG. 3B and have an increment circuit therein. The layer address (0, 0, 0) set in the layer address generation circuit 46 of the uppermost core chip CC0 is sent to the layer address generation circuit 46 of the second core chip CC1 via the TSV and incremented. Thus, different layer addresses (0, 0, 1) are generated. Similarly, the generated layer address is transferred to the lower core chip, and the layer address generation circuit 46 in the transferred core chip increments this. In the layer address generation circuit 46 of the lowermost core chip CC7, the maximum value (1, 1, 1) is set as the layer address. Thereby, a unique layer address is set to each of the core chips CC0 to CC7.

  The defective address signal DEF2 is supplied from the inactivation circuit 36 to the layer address generation circuit 46. The inactivation circuit 36 is a circuit that is activated when a defective chip signal DEF1 is supplied from the defective chip information holding circuit 33 of the interface chip IF through the TSV. Since the defective chip signal DEF1 is supplied to each of the core chips CC0 to CC7 using the TSV3 of the type shown in FIG. 3C, an individual defective chip signal DEF can be supplied to each of the core chips CC0 to CC7. The defective chip signal DEF1 is a signal that is activated when the core chip is a defective chip. When the core chip is activated, the layer address generation circuit 46 uses a layer address that is not incremented instead of an incremented layer address. Transfer to the lower core chip. The defective chip signal DEF2 is also supplied to the control logic circuit 63. When the defective chip signal DEF2 is activated, the operation of the control logic circuit 63 is completely stopped. As a result, a defective core chip does not perform a read operation or a write operation even if an address signal or a command signal is input from the interface chip IF.

  The output of the control logic circuit 63 is also supplied to the mode register 64. Thereby, when the output of the control logic circuit 63 indicates the mode register set, the set value of the mode register 64 is overwritten by the address signal. Thereby, the operation mode of the core chips CC0 to CC7 is set.

  Furthermore, an internal voltage generation circuit 72 is provided in the core chips CC0 to CC7. The internal voltage generation circuit 72 is supplied with power supply potentials VDD and VSS, and the internal voltage generation circuit 72 receives these to generate various internal voltages. The internal voltage generated by the internal voltage generation circuit 72 includes an internal voltage VPERI (≈VDD) used as an operation power supply for various peripheral circuits, an internal voltage VARY (<VDD) used as an array voltage of the memory cell array 50, and the word line WL. An internal voltage VPP (> VDD) or the like which is an activation potential is included. In addition, the core chips CC0 to CC7 are also provided with a power-on detection circuit 71. When the power-on is detected, various internal circuits are reset.

  The above is the basic circuit configuration of the core chips CC0 to CC7. The core chips CC0 to CC7 are not provided with a front-end unit for interfacing with the outside, and therefore cannot be operated alone in principle. However, if the single operation is impossible, it becomes impossible to perform the operation test of the core chip in the wafer state. This indicates that the semiconductor device 10 can only be tested after the assembly process of the interface chip and the plurality of core chips, and means that each core chip is tested by testing the semiconductor device 10. To do. If the core chip has a defect that cannot be recovered, the entire semiconductor device 10 is lost. In consideration of this point, in the present embodiment, the core chips CC0 to CC7 include a plurality of test pads TP and a test front end unit of a test command decoder 65 for a pseudo front end unit for testing. Are provided, and an address signal, test data, and a command signal can be input from the test pad TP. It should be noted that the test front-end unit is a circuit having a function that realizes a simple test in the wafer test, and does not have all the front-end functions in the interface chip. For example, since the operating frequency of the core chip is lower than the operating frequency of the front end, it can be simply realized by a test front end circuit for testing at a low frequency.

  The type of the test pad TP is almost the same as that of the external terminal provided in the interposer IP. Specifically, a test pad TP1 to which a clock signal is input, a test pad TP2 to which an address signal is input, a test pad TP3 to which a command signal is input, a test pad TP4 for inputting / outputting test data, a data strobe A test pad TP5 for inputting and outputting signals, a test pad TP6 for supplying power supply potential, and the like are included.

  At the time of testing, a normal external command that has not been decoded is input, so that a test command decoder 65 is also provided in the core chips CC0 to CC7. Further, since serial test data is input and output during the test, the core chips CC0 to CC7 are also provided with a test input / output circuit 29 and a test FIFO circuit 28. In the test, the DFT circuit 66 included in the core chips CC0 to CC7 is used.

  The above is the overall configuration of the semiconductor device 10 according to the present embodiment. Thus, since the semiconductor device 10 according to the present embodiment has a configuration in which, for example, eight 1 Gb core chips are stacked, the memory capacity in this case is 8 Gb in total. Further, since there is one terminal (chip selection terminal) to which the chip selection signal / CS is input, the controller recognizes it as a single DRAM having a memory capacity of 8 Gb. However, the storage capacity of the core chip is not particularly limited in the present invention.

  Next, a method for replacing defective cells included in the core chips CC0 to CC7 will be described.

  The replacement of the defective cell is performed twice in the manufacturing stage of the semiconductor device 10. The first time is performed in the wafer process, and the second time is performed in the assembly process. Replacement in the wafer process is performed using the optical fuses 55 and 57 to repair defects generated in the wafer process, and replacement in the assembly process is performed by using an electric fuse circuit to repair defects generated in the assembly process. 83. That is, in the replacement in the wafer process, the defective address is stored in the core chips CC0 to CC7 itself, whereas in the replacement in the assembly process, the defective address is stored in the interface chip IF.

  FIG. 6 is a flowchart for explaining a method of replacing defective cells included in the core chips CC0 to CC7.

  First, an operation test is performed on the wafer-state core chips CC0 to CC7 to detect a defective address (step S10). The detected defective address is analyzed in a tester outside the semiconductor device 10, and replacement data is specified. The replacement data is information for specifying a replacement source word line or bit line and a replacement destination word line or bit line. The replacement source word line or bit line is specified by the row address or column address, and the replacement destination word line or bit line is specified by the address of the fuse set used in the optical fuse circuits 55 and 57.

  Next, the optical fuse circuits 55 and 57 are programmed based on the replacement data (step S11). Specifically, by irradiating a laser beam using a laser trimmer, a predetermined fuse set included in the optical fuse circuits 55 and 57 has a row address indicating a replacement source word line or a column indicating a replacement source bit line. Program the address. When the replacement operation in the wafer process is completed in this way, the wafer is separated into pieces (step S12). On the other hand, the setting of the electrical fuse circuit 83 included in the interface chip IF is manufactured in a separate process from the core chips CC0 to CC7 (step S13).

  Next, the separated core chips CC0 to CC7 and the interface chip IF are stacked together and packaged as shown in FIG. 2 (step S14). After packaging, a second operation test is performed to detect a defective address (step S15). The core chips CC0 to CC7 to be stacked are guaranteed that all addresses can be normally accessed by the first operation test performed in the wafer state and replacement of defective cells based on the first operation test. There is a possibility that a new defective address is generated due to the load or the load due to the burn-in test. The second operation test is performed in order to detect a new defective address generated after the completion of the first operation test and repair it.

  Next, the electric fuse circuit 83 is programmed based on the detected defective address (step S16). Specifically, by applying a high voltage using an electrical fuse controller (described later) included in the electrical fuse circuit 83, a row address or replacement indicating a replacement source word line in the fuse set included in the electrical fuse circuit 83 Program the column address indicating the original bit line. Thereby, a series of replacement operations are completed, and the semiconductor device 10 is shipped as a non-defective product.

  FIG. 7 is a flowchart for explaining the operations of steps S15 and S16 shown in FIG. 6 in more detail.

  First, one of the core chips CC0 to CC7 is selected (step S20), and an operation test is performed (step S21). The pass / fail judgment in the operation test is performed by the data control circuit 54 (test circuit 54a) in the core chips CC0 to CC7. The determination signal P / F obtained as a result is transferred to the analysis circuit 82 in the interface chip IF via the TSV1 and analyzed by the analysis circuit 82 (step S22). The analysis circuit 82 generates replacement data by analyzing a defective address so that all found defective cells can be replaced by a smaller number of redundant word lines or redundant bit lines. Information regarding the replacement destination word line or bit line included in the replacement data is specified by the address of the fuse set used in the electrical fuse circuit 83.

  As a result of the analysis, when the replacement cannot be performed even if all the fuse sets are used (step S23: NO), the semiconductor device 10 is handled as a defective product (step S27). Further, even if the fuse set in the electric fuse circuit 83 can be used for replacement, the fuse set to be used in the electric fuse circuit 83 is already used in the optical fuse circuits 55 and 57. Even when the fuse set is assigned (step S24: NO), the semiconductor device 10 is handled as a defective product (step S27). If none of these is the case, a row address indicating a replacement source word line or a column address indicating a replacement source bit line is programmed for a predetermined fuse set in the electrical fuse circuit 83 (step S25). Thereby, a defective address newly generated in the core chip is relieved.

  Then, such an operation is sequentially performed for all the core chips CC0 to CC7, and when the above operation is completed for all the core chips CC0 to CC7 (step S26: YES), a series of replacement operations are completed, and the semiconductor The device 10 is shipped as a non-defective product.

  FIG. 8 is a flowchart for explaining the replacement data loading operation programmed in the electrical fuse circuit 83.

  The replacement data loading operation is performed in response to the change of the reset signal / RESET supplied to the command terminal 12f to the high level (step S31). When the reset signal / RESET changes to a high level, the load circuit 85 included in the interface chip IF is activated, and replacement data programmed in the electrical fuse circuit 83 is read (step S32). The replacement data read from the electrical fuse circuit 83 is serial-converted by the serializer 84 and transferred to the core chips CC0 to CC7 via the TSV1 (step S33). When the replacement data is transferred by the serializer 84, the layer address EXA is also transferred by the layer address buffer 48 at the same time. As a result, the replacement data supplied in common to the core chips CC0 to CC7 is valid only for the core chip indicated by the layer address EXA and is latched by the defective address latch circuits 56 and 58 included in the core chip. When all the replacement data has been transferred to the corresponding core chips CC0 to CC7, a series of transfer operations are completed (step S34).

  FIG. 9 is a block diagram showing the configuration of the electrical fuse circuit 83 in more detail.

  As shown in FIG. 9, the electrical fuse circuit 83 is provided for each bank. In this embodiment, since it has an eight-bank configuration, the electric fuse circuit 83 is divided into eight electric fuse circuits 83-0 to 83-7, which correspond to the banks 0 to 7, respectively. Since the electrical fuse circuits 83-0 to 83-7 have the same circuit configuration, only the circuit configuration of the electrical fuse circuit 83-0 is shown in FIG. 9 as a representative.

  The electrical fuse circuit 83-0 includes a plurality of fuse sets 83-00 to 83-07 respectively assigned to the core chips CC0 to CC7. Each of the fuse sets 83-00 to 83-07 includes a plurality of fuse sets for row address and column address. A corresponding control circuit 83a is assigned to each fuse set, and writing to and reading from the fuse set are performed under the control of the electrical fuse controller 83b. Data to be written to the fuse set and data read from the fuse set are transmitted / received via the transfer control circuit 83c.

  Each fuse set includes a plurality of electric fuses. The electric fuse is an electrically writable storage element, and is preferably a nonvolatile and irreversible one-time ROM. As the one-time ROM, an antifuse element that stores data depending on the presence or absence of dielectric breakdown (insulation film breakdown) due to application of a high voltage can be preferably used.

  The data read through the transfer control circuit 83c is serial-converted by the serializer 84 and then transferred to the core chips CC0 to CC7 through the TSV. Data to be written in the electrical fuse circuit 83 is given from the control logic 32 and the analysis circuit 82, and is programmed into a predetermined fuse set under the control of the electrical fuse controller 83b. Therefore, the electrical fuse controller 83b functions as a program circuit that performs a program for the electrical fuse set.

  FIG. 10 is a block diagram showing the configuration of the defective address latch circuit 56 in more detail.

  As shown in FIG. 10, the defective address latch circuit 56 includes a latch circuit 56a that latches replacement data read from the optical fuse circuit 55, and a latch circuit 56b that latches replacement data read from the electrical fuse circuit 83. It has. A data control circuit 56c and a data latch circuit 56d are provided in the previous stage of the latch circuit 56b. Under the control of these circuits 56c and 56d, the replacement data transferred from the interface chip IF via the TSV is supplied to the latch circuit 56b. Latched.

  The output of the latch circuit 56a and the output of the latch circuit 56b are supplied to the selection circuit 56e. The selection circuit 56e is a circuit that selects one of the output of the latch circuit 56a and the output of the latch circuit 56b, and the selected replacement data is supplied to the row decoder 51. The selection by the selection circuit 56e is performed based on flag information described later. The row decoder 51 is provided with an address comparison circuit 51a, and the replacement data selected by the selection circuit 56e is compared with the row address requested to be accessed. As a result, when the two match, the redundant word line included in the row redundant array 50a is accessed instead of the word line indicated by the row address. On the other hand, if the two addresses do not match, the word line indicated by the row address is accessed as it is.

  The column-side defective address latch circuit 58 also has a circuit configuration similar to that of the above-described defective address latch circuit 56, and thus a duplicate description is omitted.

  As described above, since the replacement data transferred from the interface chip IF is commonly supplied to the core chips CC0 to CC7, each of the core chips CC0 to CC7 determines whether or not the transferred replacement data should be taken in. In order to do so, the layer address EXA is required. For this reason, as shown in FIG. 11, when the replacement data is transferred to each of the core chips CC0 to CC7, the layer address EXA is also transferred at the same time. Thereby, the replacement data supplied in common to each of the core chips CC0 to CC7 is valid only for the core chip indicated by the layer address EXA. That is, only when the layer address EXA matches the layer address LID unique to each of the core chips CC0 to CC7, the data control circuit 56c and the data latch circuit 56d are valid, and the process of writing the transferred replacement data to the latch circuit 56b I do. A series of transfer operations are performed in synchronization with the internal clock signal ICLK generated in the interface chip IF.

  FIG. 12 is a block diagram showing the configuration of the electric fuse circuit 83 and the defective address latch circuit 56 in more detail.

  As described above, each bank is divided into electric fuse circuits 83-0 to 83-7, and each electric fuse circuit 83-0 to 83-7 has a plurality of electric fuse sets assigned to the core chips CC0 to CC7, respectively. 83-00 to 83-07 are included. As shown in FIG. 12, the electrical fuse set 83-00 includes X + 1 fuse sets, and thus X + 1 row addresses (or column addresses) can be stored.

  On the other hand, as shown in FIG. 12, the defective address latch circuit 56 is provided with N + 1 latch circuits 56a and X + 1 latch circuits 56b. The N + 1 latch circuits 56a correspond to the 0th to Nth optical fuse sets, respectively. Among these, the latch circuit 56a corresponding to the 0th to (N-1-X) th optical fuse sets does not have the pair of latch circuits 56b, and therefore there is no selection circuit 56e corresponding thereto.

  In contrast, the latch circuit 56a corresponding to the 0th to NXth optical fuse sets includes a pair of latch circuits 56b. Specifically, latch circuits 56b corresponding to the Xth to 0th electrical fuse sets are assigned to the 0th to NXth optical fuse sets, respectively. Therefore, a selection circuit 56e is assigned to these latch circuits 56a and 56b, and one of the outputs is selected. The replacement data transferred from the interface chip IF is latched by the designated latch circuit 56b under the control of the fuse selection circuit 56s.

  The outputs of the latch circuits 56a and 56b are supplied to the address comparison circuit 51a, and when the access matches the requested address, the corresponding redundant word line RWL is accessed.

  FIG. 13 is a diagram for explaining the relationship between the selection order of the optical fuse circuit 55 and the selection order of the electrical fuse circuit 83.

  As already described, the program for the optical fuse circuit 55 is performed in step S11 shown in FIG. 6, and the program for the electric fuse circuit 83 is executed in step S16 shown in FIG. In other words, the optical fuse circuit 55 is programmed first, and the remaining fuse set that was not used in step S11 is used in place of the electric fuse circuit 83. Therefore, the redundant word line selected by the optical fuse circuit 55 and the redundant word line selected by the electric fuse circuit 83 are not allowed to compete. In this embodiment, as shown in FIG. 13, the program for the optical fuse circuit 55 is used to prevent such competition and to efficiently use the remaining fuse set in the electric fuse circuit 83. The 0th optical fuse set is used sequentially (arrow LF), and the program to the electrical fuse circuit 83 is used sequentially from the 0th electrical fuse set paired with the Nth optical fuse set (arrow AF). As a result, the remaining fuse set can be efficiently replaced by the electric fuse circuit 83.

  FIG. 14 is a circuit diagram showing an example of the address comparison circuit 51a and the selection circuit 56e. The circuit example shown in FIG. 14 is preferably applied to the row side.

  In the example shown in FIG. 14, 14 latch circuits 56a and 14 latch circuits 56b corresponding to the respective bits A0 to A13 of the row address are provided, and these outputs are respectively associated with the row address by the EXNOR circuit. It is compared with each bit to be. The outputs of the EXNOR circuit corresponding to the latch circuit 56a are collected by an AND gate circuit and output as an optical fuse hit signal LFHIT. Similarly, the output of the EXNOR circuit corresponding to the latch circuit 56b is also collected by the AND gate circuit and output as the electric fuse hit signal AFHIT.

  The optical fuse hit signal LFHIT and the electrical fuse hit signal AFHIT are supplied to the selection circuit 56e, and one of them is selected by the selection signal SEL. The selected signal is output as a redundancy judgment signal HIT. The selection signal SEL is generated by the AND gate circuit 56f. The AND gate circuit 56f is supplied with the output of the latch circuit 56ae that latches the optical fuse enable signal LFEN and the output of the latch circuit 56be that latches the electrical fuse enable signal AFEN. The electric fuse enable signal AFEN corresponds to the first flag information FL1 shown in FIG. 1, and indicates whether or not the corresponding electric fuse set is valid, that is, whether or not it is being used. The optical fuse enable signal LFEN corresponds to the second flag information FL2 shown in FIG. 1, and indicates whether the corresponding optical fuse set is valid, that is, whether it is used.

  The optical fuse enable signal LFEN is a signal that is high when the optical fuse set is used, and the electric fuse enable signal AFEN is a signal that is high when the electric fuse set is used. Therefore, when the optical fuse set is in use, the selection signal SEL is always at a low level, whereby the selection circuit 56e selects the optical fuse hit signal LFHIT. On the other hand, when the optical fuse set is not used and the electric fuse set is used, the selection signal SEL becomes high level, and the selection circuit 56e selects the electric fuse hit signal AFHIT.

  FIG. 15 is a circuit diagram showing another example of the address comparison circuit 51a and the selection circuit 56e. The circuit example shown in FIG. 15 is preferably applied to the column side.

  In the example shown in FIG. 15, seven latch circuits 56a and seven latch circuits 56b corresponding to the respective bits Y3 to Y9 of the column address are provided, but each bit is input to the selection circuit 56e. This is different from the circuit example shown in FIG. The outputs of the seven selection circuits 56e are respectively compared with the corresponding bits by the EXNOR circuit. The outputs of these EXNOR circuits are collected by an AND gate circuit 56g and output as a redundancy judgment signal HIT.

  The selection signal SEL is commonly supplied to the seven selection circuits 56e. The selection signal SEL is a signal generated by the AND gate circuit 56f. As described with reference to FIG. 14, when the optical fuse set is in use, the selection signal SEL is always at a low level. 56e selects the optical fuse side. On the other hand, when the optical fuse set is not in use and the electrical fuse set is in use, the selection signal SEL becomes high level, and the selection circuit 56e selects the electrical fuse side.

  Further, the output of the latch circuit 56ae that latches the optical fuse enable signal LFEN and the output of the latch circuit 56be that latches the electrical fuse enable signal AFEN are supplied to the OR gate circuit 56h. The output of the OR gate circuit 56h is input to the AND gate circuit 56g. As a result, when both the optical fuse set and the electrical fuse set are not in use, the redundancy determination signal HIT is always fixed to an inactive state.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  The technical idea of the present application can be applied to a semiconductor device having a core chip related to volatile and nonvolatile memory cells and an interface chip for controlling the core chip. Furthermore, the circuit format in each circuit block disclosed in the drawings and other circuits for generating control signals are not limited to the circuit format disclosed in the embodiments.

  The technical idea of the semiconductor device of the present invention can be applied to various semiconductor devices. For example, a semiconductor device having functions such as a central processing unit (CPU), a micro control unit (MCU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), an application specific standard product (ASSP), and a memory In general, the present invention can be applied.

  When a field effect transistor (FET) is used as a transistor, it can be applied to various FETs such as MIS (Metal-Insulator Semiconductor) and TFT (Thin Film Transistor) in addition to MOS (Metal Oxide Semiconductor). . Furthermore, some bipolar transistors may be included in the device.

  Further, the NMOS transistor (N-type channel MOS transistor) is a representative example of the first conductivity type transistor, and the PMOS transistor (P-type channel MOS transistor) is a representative example of the second conductivity type transistor.

  Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

4-6 Internal circuit 10 Semiconductor device 11a, 11b Clock terminal 11c Clock enable terminal 12a-12f Command terminal 13a-13c Address terminal 14 Data input / output terminal 15a, 15b Data strobe terminal 16 Calibration terminal 17a, 17b Power supply terminal 18 Data mask Terminal 21 Clock generation circuit 22 DLL circuit 23 Input / output buffer circuit 24 Calibration circuit 25, 28 FIFO circuit 26, 27, 34 TSV buffer 29 Input / output circuit 31 Command input buffer 32 Control logic 32a Latency controller 32b Command decoder 33 Defective chip information Holding circuit 35 TSV receiver 36 Inactivation circuit 37 DFT circuit 41 Address input buffer 42 Mode register 43 Power-on detection circuit 44 Layer Address setting circuit 45 Layer address control circuit 46 Layer address generation circuit 47 Layer address comparison circuit 48 Layer address buffer 49 Input receiver 50 Memory cell array 50a Row redundancy array 50b Column redundancy array 51 Row decoder 51a Address comparison circuit 52 Column decoder 53 Sense circuit 54 Data control circuit 54a Test circuit 55, 57 Optical fuse circuit 56, 58 Defective address latch circuit 56a, 56b, 56ae, 56be Latch circuit 56c Data control circuit 56d Data latch circuit 56e Select circuit 56f to 56h Gate circuit 56s Fuse select circuit 58 Defective Address latch circuit 61 Row control circuit 61a Address buffer 61b Refresh counter 62 Column control circuit 62a Address buffer 62 Burst counter 63 Control logic 64 Mode register 65 Command decoder 66 DFT circuit 71 Power-on detection circuit 72 Internal voltage generation circuit 81 DFT circuit 82 Analysis circuit 83 Electrical fuse circuit 83-0 to 83-7 Fuse set 83a Control circuit 83b Electrical fuse controller 83c Transfer control circuit 84 Serializer 85 Load circuit 91 Electrode 92 Through-hole electrode 93 Redistribution layer 94 NCF
95 Lead frame 96 Underfill 97 Sealing resin 100 First chip 101 to 104 Latch circuit 110 Memory cell array 120 Optical fuse 130 Flag fuse 140 Input circuit 150 Control circuit 151 Selection circuit 152 Address comparison circuit 160 Access control circuit 170 Redundant array 180 Silicon substrate 181 Interlayer insulating film 182 Insulating ring 183 End 184 Back bump 185 Front bump 186 End 200 Second chip 210 Access control circuit 220 Electric fuse 230 Flag fuse 240 Output circuit 300 External terminal 400 Internal wiring CC0 to CC7 Core chip HIT Redundancy determination signal IF Interface chip IP Interposer RBL Redundant bit line RMC Redundant cell RWL Redundant word line SB External terminal TSV Through electrode

Claims (20)

An external terminal,
A plurality of first chips each having a plurality of memory cells;
A second chip that communicates with the outside of the semiconductor device via the external terminal and controls the plurality of first chips;
A plurality of internal electrodes each provided on each of the plurality of first chips, including a plurality of through electrodes penetrating the substrate of the first chip, and electrically connecting the first chip and the second chip; And wiring,
The plurality of first chips communicate with the outside through the second chip without directly communicating with the outside of the semiconductor device in accessing the plurality of memory cells,
Furthermore, the second chip includes an electrical fuse,
Further, each of the plurality of first chips includes:
An optical fuse and a first latch circuit for holding information on the optical fuse;
A second latch circuit for holding information on the electrical fuse supplied via the internal wiring;
A selection circuit for selecting information of one of the first and second latch circuits;
And a first control circuit that generates one redundancy determination signal from the selected information. Furthermore, the second chip includes a first output circuit that outputs information on the electric fuse to the internal wiring,
2. The semiconductor device according to claim 1, wherein each of the first chips includes a first input circuit that inputs information of the electric fuse from the internal wiring. Further, the second chip includes first flag information indicating whether information is set in the electric fuse,
Further, each of the first chips is
A third latch circuit for holding the first flag information supplied via the internal wiring;
Second flag information indicating whether or not each of the optical fuses has been used,
The first control circuit uses the first flag information and the second flag information held in the third latch circuit to determine one of the first and second latch circuits in the selection circuit. The semiconductor device according to claim 2, wherein Further, the first output circuit of the second chip outputs the first flag information to the internal wiring,
The semiconductor device according to claim 3, wherein the first input circuit of the first chip inputs the first flag information via the internal wiring. Further, each of the first chips has different chip identification information for each of the plurality of first chips allocated to its own chip,
The first output circuit of the second chip is attached to the information of the electric fuse and outputs layer information to the internal wiring,
The first input circuit of the first chip takes in the information of the electrical fuse sent from the second chip into the second latch circuit when the layer information matches the chip identification information. Item 5. The semiconductor device according to any one of Items 2 to 4. Further, the first chip performs a pass / fail judgment related to a plurality of data included in the plurality of memory cells, and transfers a result of the pass / fail judgment to the second chip. Including
Further, the second chip analyzes the plurality of pass / fail judgment results transferred from the plurality of second output circuits included in the plurality of first chips, and the analysis results are analyzed as the plurality of the plurality of second output circuits. The semiconductor device according to claim 1, further comprising an analysis circuit set in the electric fuse as repair information of the memory cell. Further, the second chip includes a fuse for storing the first flag information having the same structure as the electric fuse,
5. The semiconductor device according to claim 3, wherein each of the first chips includes a fuse for storing the second flag information having the same structure as the optical fuse. Each of the plurality of first chips includes a plurality of the redundancy determination signals and a plurality of the optical fuses respectively corresponding to the plurality of redundancy determination signals,
The cutting of the plurality of optical fuses is executed from the optical fuse corresponding to either the upper or lower redundancy judgment signal among the plurality of redundancy judgment signals,
The second chip includes a plurality of the electrical fuses respectively corresponding to the plurality of redundancy determination signals, and a second control circuit,
2. The second control circuit executes the setting of the electric fuse from the electric fuse corresponding to the redundancy determination signal of one of the upper and lower ones among the plurality of redundancy determination signals. 8. The semiconductor device according to claim 7.   The semiconductor device according to claim 1, wherein the electric fuse is a one-time ROM. Further, each of the plurality of first chips has a first output circuit that outputs parallel data that is a plurality of parallel bits related to the plurality of memory cells,
Further, the second chip converts the parallel data supplied from the plurality of first chips into serial data that is a plurality of serial bits, and outputs the serial data to the external terminal of the semiconductor device. The semiconductor device according to claim 1, comprising a circuit. An external signal terminal;
A plurality of core chips each having a plurality of memory cells and not directly connected to the external signal terminals;
An interface chip connected to the external signal terminal and controlling the plurality of core chips,
The plurality of core chips and the interface chip are stacked, and the plurality of core chips and the interface chip are electrically connected via through electrodes provided in the plurality of core chips,
Furthermore, the interface chip includes an electrical fuse for storing an address of a memory cell that is defective in any of the plurality of core chips,
Further, each of the plurality of core chips is
A redundant cell that replaces a defective memory cell among the plurality of memory cells;
An optical fuse for storing an address of the defective memory cell;
A selection circuit for selecting one of the address read from the optical fuse and the address read from the electrical fuse;
A semiconductor device comprising: an access control circuit that accesses the redundant cell instead of the defective memory cell in response to a request for access to the address selected by the selection circuit.   12. The semiconductor device according to claim 11, wherein the address read from the electric fuse is supplied from the interface chip to the plurality of core chips via the through electrode without passing through the external signal terminal. apparatus. Further, each of the plurality of core chips is
A first latch circuit for holding an address read from the optical fuse;
A second latch circuit that reads from the electrical fuse and holds an address supplied from the interface chip via the through electrode,
The semiconductor device according to claim 12, wherein the selection circuit selects one of an address held in the first latch circuit and an address held in the second latch circuit. Further, each of the plurality of core chips includes a test circuit that performs pass / fail judgment related to a plurality of data included in the plurality of memory cells,
The interface chip further includes a program circuit that programs the electrical fuse based on a plurality of pass / fail judgment results by the plurality of test circuits included in the plurality of core chips. The semiconductor device according to any one of 11 to 13.   15. The semiconductor device according to claim 14, wherein the result of the plurality of pass / fail judgments by the plurality of test circuits is supplied from the plurality of core chips to the interface chip via the through electrode. Each of the plurality of core chips includes a plurality of the optical fuses,
The interface chip includes a plurality of the electrical fuses,
The plurality of optical fuses includes a plurality of first optical fuses and a plurality of second optical fuses,
The plurality of first optical fuses are not assigned the plurality of electrical fuses of the corresponding interface chip,
The plurality of second optical fuses are respectively assigned the plurality of electric fuses of the corresponding interface chip,
The selection circuit selects any one of an address read from the plurality of second optical fuses and an address read from the corresponding plurality of electric fuses. The semiconductor device according to any one of 1 to 15.   The semiconductor device according to claim 16, wherein the programming of the plurality of optical fuses is performed preferentially from the plurality of first optical fuses. The optical fuse is programmed before the plurality of core chips are stacked,
The semiconductor device according to claim 11, wherein the electric fuse is programmed after the plurality of core chips and the interface chip are stacked.   The semiconductor device according to claim 18, wherein the electric fuse is a one-time ROM.   The semiconductor device according to claim 19, wherein the electrical fuse is an antifuse element that stores information irreversibly by destruction of an insulating film.

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