JP2012253685A - Variable gain amplifier circuit and receiver circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable gain amplifier circuit and receiver circuit using the same, capable of achieving the amplification or damping of a continuously input signal as well as a wide gain variable range and high linearity.SOLUTION: The variable gain amplifier circuit applies a bias voltage to a first resistor and a second resistor provided in a second variable gain amplification section when a gain of a first variable gain amplification section is minimum, for the purpose of lowering a level of a signal input into a gate of an amplifier transistor (as shown by states (A)-(D) in Figure 1(a)).

Description

  The present invention relates to a variable gain amplifier having a wide gain variable width that is configured by using a semiconductor element, and in particular, a variable gain amplifier and communication effective for realizing a wireless communication device in which an input signal varies greatly depending on reception conditions. It relates to equipment.

  A broadband wireless communication device such as a television broadcast tuner using a cable or radio wave requires a variable gain amplifier circuit (variable gain amplifier circuit with low distortion) having high linearity. This is because when a strong signal (a signal having a high signal strength) is input, the modulation is prevented from being disturbed between channels.

  Such a variable gain amplifier circuit is disclosed in Patent Document 1. As shown in FIG. 15, the variable gain amplifier circuit of Patent Document 1 includes a plurality of transistor differential pairs (M0, M1,..., Mk−1) each including two amplification transistors, and each transistor differential pair. The current is turned on or off.

  As a result, the current value flowing through the variable gain amplifier circuit (current value flowing through the transistor differential pair) remains constant, and the transistor width is changed. In this way, variable gain is realized while achieving high linearity.

  Here, the intensity (level) of the signal input to the communication device greatly changes (fluctuates) depending on the reception status. For this reason, it is necessary to increase the gain variable range (gain variable width) of the variable gain amplifier circuit.

  However, only the variable gain amplifier circuit (referred to as a unit circuit) shown in FIG.

  An example of a method for configuring a variable gain amplifier circuit having a large gain variable range is described in Non-Patent Document 1. According to Non-Patent Document 1, in order to increase the gain variable range as compared with the case where the gain variable is realized by one unit circuit, a plurality of unit circuits that include a plurality of transistor differential pairs and change the gain are provided. At the same time, a capacitance attenuator is connected to each of the plurality of unit circuits.

  By adopting such a configuration, it is possible to realize a gain variable range that cannot be realized by a single unit circuit by making the gain variable range larger (wider). In addition, the capacity attenuator generates less thermal noise than a resistance attenuator realized by a resistor. Therefore, the capacity attenuator is effective for a low noise variable gain amplifier circuit.

JP 2002-330039 A (published on November 15, 2002)

"A digital terrestrial television (ISDB-T) tuner for mobile applications" IEEE ISSCC Dig. Tech. Papers, 2004 pp278-279.

  Assume that a variable gain amplifier circuit with a wide gain variable range is realized while maintaining high linearity by combining the above-described conventional techniques. A case will be considered in which the intensity of the signal input to the variable gain amplifier circuit changes (fluctuates) greatly depending on the reception status.

  In this case, it is necessary to change the gain of the variable gain amplifying circuit in accordance with the signal strength that has changed greatly depending on the reception situation. As an example, an operation in the case where the strength of the input signal increases depending on the reception situation and the gain of the variable gain amplifier circuit is decreased will be described.

  When the gain of the variable gain amplifier circuit is reduced, the gain i [dB] of the transistor differential pair constituting the variable gain amplifier circuit is sequentially reduced. Suppose you need it. For the gain i, i = 0, 1, 2,... K−1 (k is an integer of 1 or more).

  FIG. 16 shows the overall configuration of the conventional variable gain amplifier circuits 101a and 101b. FIG. 16A shows the variable gain amplifier circuit 101a when configured with a single end, and FIG. 16B shows the variable gain amplifier when configured with a differential. It is a block diagram which shows the circuit 101b. Here, as an example, the variable gain amplifier circuit 101b having a differential configuration shown in FIG. 16B will be described.

  First, consider a case where the gain set in accordance with the reception status is large. In this case, a signal input from a terminal IN configured as a differential is amplified through the unit circuit 102 after passing through the capacitor 104 that removes the DC voltage, and is output from the terminal OUT.

  On the other hand, consider a case where the gain set according to the reception status is small. In this case, the signal input from the terminal IN configured as a differential is attenuated by the capacitance attenuator 111 including a plurality of capacitors, then amplified through the unit circuit 103, and output from the terminal OUT.

  The unit circuits 102 and 103 may be the same circuit or different circuits. A circuit configuration example of the unit circuits 102 and 103 is shown in FIG.

  In the unit circuits 102 and 103, k transistor differential pairs configured by connecting the sources of two amplification transistors are prepared (M0 to Mk−1). In each of the transistor differential pairs M0 to Mk−1, a differential signal is input to the differential gate.

  At this time, in the unit circuits 102 and 103, the unit circuits 102 and 103 can set k gains by using the state in which the transistor differential pairs M0 to Mk-1 are conductive (k states). become able to do.

  The conduction or blocking of each of the transistor differential pairs M0 to Mk-1 is realized by providing switch circuits Sw0 to Swk-1. As an example, the transistor differential pair M0 of the unit circuit 102 can be cut off by cutting off the switch circuit Sw0 of the unit circuit 2.

  The connection of the switch circuits Sw0 to Swk-1 will be described. One end of each of the switch circuits Sw0 to Swk-1 is connected to sources connected to each other in the two amplification transistors constituting the transistor differential pair. One end of each of the switch circuits Sw0 to Swk-1 is connected to an input of a constant current source. One constant current source is provided for one unit circuit. All of the outputs of the constant current source are electrically grounded.

  The operation when the gain is gradually reduced in the variable gain amplifier circuit 101b when the strength of the signal input during reception varies greatly depending on the reception situation will be described in order.

  If it is determined that the intensity of the received signal is high, the variable gain amplifier circuit 101b gradually cuts off the switch circuits Swk-1 to Sw0 included in the unit circuit 2 in order to avoid a sudden gain change.

  As a result, the current of the transistor differential pairs Mk-1 to M0 is gradually cut off, so that the total transistor width of the amplification transistors provided in the unit circuit 102 is reduced, and the gain as the unit circuit 102 is reduced. (State (A) in FIG. 18).

  Here, it is assumed that only the switch circuit Sw0 is turned on in the unit circuit 102 and the unit circuit 102 has the minimum gain. In this case, since no current flows through the unit circuit 103, signal amplification by the unit circuit 103 is not performed (state (B) in FIG. 18).

  Next, it is assumed that the gain when only the switch circuit Sw0 of the unit circuit 102 is conductive is also large, and it is necessary to further attenuate the signal input during reception.

  In this case, the switch circuit Sw0 included in the unit circuit 102 is cut off, and the current of the transistor differential pair M0 is cut off. At the same time, all the switch circuits Sw0 to Swk-1 included in the unit circuit 103 are made conductive (state (C) in FIG. 18).

  At this time, simultaneously with the transition from the state (B) to the state (C), a bias voltage is applied to the gate terminals of all the amplification transistors included in the unit circuit 103. As a result, it takes time for the charge to accumulate in the capacitance attenuator 111, and the current is cut off until a desired bias state is reached.

  For this reason, in the conventional variable gain amplifier circuit of FIG. 16, as a result, the received signal is interrupted as shown in the signal cut-off period of FIG. 18, and continuously input signals such as television broadcasting are received. Sometimes the signal is interrupted. For this reason, there has been a problem that the television image is interrupted.

  The state (D) shows a state when the switch circuit is gradually cut off from the state (C).

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to enable amplification or attenuation of a signal that is continuously input, and to realize a wide variable gain range and high linearity. It is an object of the present invention to provide a variable gain amplifying circuit capable of performing the above.

  In order to solve the above problems, the variable gain amplifier circuit of the present invention includes a first variable gain amplifier and a second variable gain amplifier that can change a gain when a signal input from the outside is amplified, The maximum value of the gain of the first variable gain amplifier is higher than the maximum value of the gain of the second variable gain amplifier, and the minimum value of the gain of the first variable gain amplifier is the second variable gain amplifier. A variable gain amplifier circuit having a gain higher than a minimum value of the first and second variable gain amplifying units, wherein each of the first variable gain amplifying unit and the second variable gain amplifying unit includes a transistor group including a plurality of amplifying transistors to which the signal is input to a gate; One end of each transistor group is connected to the gate of the amplification transistor, and the other end is connected to the gate of the other amplification transistor of the other transistor group. And a second resistor to which the bias voltage is applied at the other end, and when the gain of the first variable gain amplifier is minimized, the first resistor included in the second variable gain amplifier and the The bias voltage is applied to the second resistor.

  According to the invention, when the gain of the first variable gain amplifying unit is minimized, the bias voltage is applied to the first resistor and the second resistor included in the second variable gain amplifying unit.

  This eliminates an unstable bias state period until the bias voltage of the amplification transistor reaches a steady state, so that the second variable gain amplification unit is stopped at the moment when the first variable gain amplification unit is stopped. The gain can be reduced by the above-mentioned, and the signal is not interrupted when the two variable gain amplifiers are switched.

  Therefore, even if a continuously input signal such as a television broadcast is input, the TV image is not interrupted.

  Further, since two variable gain amplifying units that can change the gain are provided, a wide variable gain range and high linearity can be realized.

  Therefore, it is possible to provide a variable gain amplifier circuit that can amplify or attenuate continuously input signals and realize a wide variable gain range and high linearity.

  In order to solve the above problems, the variable gain amplifier circuit of the present invention includes a first variable gain amplifier and a second variable gain amplifier that can change a gain when a signal input from the outside is amplified, The maximum value of the gain of the first variable gain amplifier is higher than the maximum value of the gain of the second variable gain amplifier, and the minimum value of the gain of the first variable gain amplifier is the second variable gain amplifier. A variable gain amplifier circuit having a gain higher than a minimum value of the first and second variable gain amplifying units, wherein each of the first variable gain amplifying unit and the second variable gain amplifying unit includes a transistor group including a plurality of amplifying transistors to which the signal is input to a gate One end of each transistor group is connected to the gate of the amplification transistor, and the other end is connected to the gate of the other amplification transistor of the other transistor group. A second resistor to which the bias voltage is applied at the other end, and when the gain of the second variable gain amplifying unit is maximized, the first resistor included in the first variable gain amplifying unit and the second resistor The bias voltage is applied to the second resistor.

  According to the invention, when the gain of the second variable gain amplifying unit becomes maximum, the bias voltage is applied to the first resistor and the second resistor included in the first variable gain amplifying unit.

  As a result, an unstable bias state period until the bias voltage of the amplification transistor reaches a steady state can be eliminated. Therefore, at the moment when the second variable gain amplification unit is stopped, the first variable gain amplification unit is stopped. Thus, the gain can be increased, and the signal is not interrupted when the variable gain amplifier is switched.

  Therefore, even if a continuously input signal such as a television broadcast is input, the TV image is not interrupted.

  Further, since two variable gain amplifying units that can change the gain are provided, a wide variable gain range and high linearity can be realized.

  Therefore, it is possible to provide a variable gain amplifier circuit that can amplify or attenuate continuously input signals and realize a wide variable gain range and high linearity.

In the variable gain amplifier circuit, a comparison circuit that compares a level of the amplified signal amplified by the first variable gain amplifier and the second variable gain amplifier with a predetermined value;
And an automatic gain control circuit for reducing the gain of the second variable gain amplifier when the level of the amplified signal is greater than the predetermined value.

  Thereby, the determination of the signal level after amplification and the control of the gain of the second variable gain amplifier can be performed.

  In the variable gain amplifier circuit, a comparison circuit that compares the level of the amplified signal amplified by the first variable gain amplifier and the second variable gain amplifier with a predetermined value, and the level of the amplified signal is the level described above. An automatic gain control circuit that increases the gain of the first variable gain amplifying unit when the value is smaller than the predetermined value may be provided.

  Thereby, the determination of the signal level after amplification and the control of the gain of the first variable gain amplifier can be performed.

  In the variable gain amplifying circuit, the first variable gain amplifying unit and the second variable gain amplifying unit are switches in which sources of the plurality of amplifying transistors are connected to each other and one end is connected to the source. A circuit may be provided for each transistor group, and a current source may be further provided in which an input is connected to the other end of all the switch circuits and an output is electrically grounded.

  By appropriately turning on or off the switch circuit, an output signal can be output from the drain of the amplification transistor.

  The variable gain amplifier circuit may further include a DC voltage removal capacitor that is a capacitor for removing a DC voltage, and the signal may be input to the first variable gain amplifier through the DC voltage removal capacitor. As a result, a DC voltage can be removed from the signal input to the first variable gain amplifier.

  The variable gain amplifier circuit may further include a capacitance attenuator that attenuates the signal, and the signal may be input to the second variable gain amplifying unit via the capacitance attenuator. As a result, it is possible to realize a gain variable range that cannot be realized by the second variable gain amplifying unit alone.

  In addition, the capacity attenuator generates less thermal noise than a resistance attenuator realized by a resistor. Therefore, the capacity attenuator is effective for a low noise variable gain amplifier circuit.

  In the variable gain amplifier circuit, the capacitance attenuator may include an attenuation capacitor that is a capacitor to which the signal is input at one end and the other end is connected to an input of the second variable gain amplifier. As a result, the input signal can be attenuated and the DC voltage can be removed.

  In the variable gain amplifier circuit, the signal is a differential signal, the second variable gain amplifier has a differential configuration, and has a first input terminal and a second input terminal to which the signal is input, The capacitance attenuator is a variable capacitance attenuator whose amount of attenuation is variable, and the variable capacitance attenuator is connected to a switching transistor whose gate receives a control signal and one end connected to a source of the switching transistor. A first capacitor having the other end connected to the first input terminal, a first capacitor connected to the drain of the switching transistor, and a second capacitor connected to the second input terminal. May be provided.

  By appropriately turning on or off the switching transistor, the combined capacitance of the variable capacitance attenuator can be changed to vary the attenuation amount of the variable capacitance attenuator.

  In the variable gain amplifier circuit, the signal is a differential signal, the second variable gain amplifier has a differential configuration, and has a first input terminal and a second input terminal to which the signal is input, The capacitance attenuator is a variable capacitance attenuator whose amount of attenuation is variable, and the variable capacitance attenuator includes a transistor switch including two switching transistors whose control signals are input to gates connected to each other, and one end Is connected to one source of the transistor switch, the other end is connected to the other source of the transistor switch, and one end is connected to one end of the third capacitor in the previous stage, and the other end Are connected to one end of the third capacitor, one end is connected to the other end of the third capacitor in the previous stage, and the other end is connected to the other end of the third capacitor. Capacity and With obtaining, one of the drain in the transistor switch is coupled to said first input terminal, the other of the drain in the transistor switch may be connected to the second input terminal.

  By appropriately turning on or off the transistor switch, the combined capacitance of the variable capacitance attenuator can be changed to vary the attenuation amount of the variable capacitance attenuator.

  In the variable gain amplifier circuit, the frequency of the signal may be 40 megahertz or more. As a result, the configuration of the variable gain amplifier circuit can be made suitable for receiving continuous signals such as television images.

  Since the receiving circuit of the present invention includes any one of the variable gain amplifier circuits described above, it is possible to amplify or attenuate signals that are continuously input and to achieve high linearity.

  In the variable gain amplifier circuit according to the present invention, as described above, each of the first variable gain amplifier and the second variable gain amplifier includes a transistor group including a plurality of amplifier transistors in which a signal is input to the gate, and each transistor group. A first resistor having one end connected to the gate of one of the amplification transistors and a bias voltage applied to the other end; one end connected to the gate of the other amplification transistor of each transistor group; A second resistor to which a voltage is applied, and when the gain of the first variable gain amplifier is minimized, the bias is applied to the first resistor and the second resistor of the second variable gain amplifier. A voltage is applied.

  Further, in the variable gain amplifier circuit of the present invention, as described above, each of the first variable gain amplifier and the second variable gain amplifier includes a transistor group including a plurality of amplifier transistors each having a signal input to the gate, One end of the transistor group has one end connected to the gate of the amplification transistor and the other end is applied with a bias voltage. The other end of the transistor group has one end connected to the gate of the amplification transistor and the other end is connected to the other end. A second resistor to which the bias voltage is applied, and when the gain of the second variable gain amplifying unit is maximized, the first resistor and the second resistor included in the first variable gain amplifying unit include: The bias voltage is applied.

  Therefore, it is possible to amplify or attenuate a signal input continuously, and to provide a variable gain amplifier circuit capable of realizing a wide variable gain range and high linearity, and a receiving circuit using the variable gain amplifier circuit. Play.

It is explanatory drawing of the signal output level of the terminal OUT in the variable gain amplifier circuit which concerns on embodiment of this invention, (a) is the signal output level of the terminal OUT in the variable gain amplifier circuit which concerns on embodiment of this invention. FIG. 6B is a waveform diagram showing the signal output level of the terminal OUT in the conventional variable gain amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the whole structure of the variable gain amplifier circuit which concerns on embodiment of this invention, (a) is a block diagram of the variable gain amplifier circuit at the time of comprising by a single end, (b) was comprised by the differential. It is a block diagram of the variable gain amplifier circuit in the case. It is a circuit diagram which shows the circuit structural example of the unit circuit which concerns on embodiment of this invention. It is a circuit diagram for demonstrating the state (A) of Fig.1 (a). FIG. 2 is a circuit diagram for explaining a transition from a state (B) to a state (C) in FIG. It is a circuit diagram for demonstrating the state (C) of Fig.1 (a). It is a circuit diagram for demonstrating the state (D) of Fig.1 (a). It is a circuit diagram for demonstrating the state (E) of FIG. FIG. 13 is a circuit diagram for explaining a transition from a state (F) to a state (G) in FIG. 12. It is a circuit diagram for demonstrating the state (G) of FIG. It is a circuit diagram for demonstrating the state (H) of FIG. It is explanatory drawing of the signal output level of the terminal OUT in the variable gain amplifier circuit which concerns on other embodiment of this invention, and shows the signal output level of the terminal OUT in the variable gain amplifier circuit which concerns on other embodiment of this invention. It is a waveform diagram. It is a circuit diagram which shows the capacity | capacitance attenuator which concerns on another embodiment of this invention. It is a circuit diagram which shows the capacity | capacitance attenuator which concerns on another embodiment of this invention. 10 is a circuit diagram showing a variable gain amplifier circuit of Patent Document 1. FIG. FIG. 7 is a block diagram showing an overall configuration of a conventional variable gain amplifier circuit, where (a) is a variable gain amplifier circuit configured with a single end, and (b) is a variable gain amplifier circuit configured with a differential. . It is a circuit diagram which shows the circuit structural example of a unit circuit. It is explanatory drawing of the signal output level of the terminal OUT in the conventional variable gain amplifier circuit, and is a wave form diagram which shows the signal output level of the terminal OUT in the conventional variable gain amplifier circuit.

  An embodiment of the present invention will be described below with reference to FIGS.

Embodiment 1
FIG. 2 is a block diagram showing the overall configuration of the variable gain amplifier circuits 10a and 10b according to the present embodiment. FIG. 2A is a block diagram of the variable gain amplifier circuit 10a configured with a single end, and FIG. 2B is a block diagram of the variable gain amplifier circuit 10b configured with a differential.

  Here, as an example, the variable gain amplifying circuit 10b having the differential configuration shown in FIG. 2B will be described. However, the same explanation can be made for the variable gain amplifying circuit 10a having a single end configuration. Not too long.

  The gains of the variable gain amplifier circuits 10a and 10b according to the present embodiment can be changed. First, consider a case where the gain set according to the reception situation is large. In this case, a signal input from a differential terminal IN is amplified through a unit circuit 2 (first variable gain amplifier) after passing through a capacitor group 4 ′ that removes a DC (Direct Current) voltage. And output from the terminal OUT. The capacitor group 4 'includes capacitors 4a and 4b (DC voltage removal capacitors).

  The frequency of the signal may be 40 MHz (megahertz) or more. Thereby, the configuration of the variable gain amplifier circuits 10a and 10b can be made suitable for receiving a continuous signal such as a television image.

  On the other hand, consider a case where the gain set according to the reception status is small. In this case, the signal input from the terminal IN configured as a differential is attenuated by the capacitance attenuator 11 including the capacitors 11a, 11b, and C0, and then amplified through the unit circuit 3 (second variable gain amplifier). And output from the terminal OUT.

  The unit circuits 2 and 3 may be the same circuit or different circuits. FIG. 3 is a circuit diagram showing a circuit configuration example of the unit circuits 2 and 3 according to the present embodiment.

  In the unit circuits 2 and 3, k transistor differential pairs (transistor groups) configured by connecting the sources of a plurality of (for example, two) amplification transistors are prepared (transistor differential pair M0). ~ Mk-1, multiple transistor differential pairs). In each of the transistor differential pairs M0 to Mk−1, a differential signal is input to the differential gate.

  At this time, the unit circuits 2 and 3 can set k gains for each of the unit circuits 2 and 3 by using the state in which the transistor differential pairs M0 to Mk-1 are conductive (k states). become able to do.

  The conduction or blocking of each of the transistor differential pairs M0 to Mk-1 is realized by providing switch circuits Sw0 to Swk-1. The switch circuits Sw0 to Swk-1 are provided for each transistor differential pair. As an example, the transistor differential pair M0 of the unit circuit 2 can be cut off by cutting off the switch circuit Sw0 of the unit circuit 2.

  The connection of the switch circuits Sw0 to Swk-1 will be described. One end of each of the switch circuits Sw0 to Swk-1 is connected to sources connected to each other in the two amplification transistors constituting the transistor differential pair. One end of each of the switch circuits Sw0 to Swk-1 is connected to an input of a constant current source. One constant current source is provided for one unit circuit, the constant current source corresponding to the unit circuit 2 is a constant current source I31 (current source), and the constant current source corresponding to the unit circuit 3 is a constant current. Source I32 (current source). All of the outputs of the constant current source are electrically grounded.

(Operation of variable gain amplifier circuit)
Here, as an example, the strength (level) of a signal input during reception changes greatly (varies) in the reception state using FIGS. 4 to 7. In this case, the operation when the gain is gradually reduced in the variable gain amplifier circuit 10b will be described.

  First, regarding the variable gain amplifier circuit 10b shown in FIG. 4, the strength (level) of the signal received by the unit circuit 2 is the AGC circuit 50a (automatic gain control circuit) provided in the subsequent stage of the unit circuits 2 and 3. Is being monitored by When the intensity of the signal received by the unit circuit 2 is high (large) as a result of monitoring, the variable gain amplifier circuit 10b gradually cuts off (cuts) the switch circuit included in the unit circuit 2 from Swk-1 to Sw0. To do. The strength comparison will be described later.

  The reason for gradually shutting off each switch circuit is to avoid a sudden change in gain.

  When the currents of the transistor differential pairs Mk-1 to M0 are cut off, the total transistor width of the amplifying transistors that are transistors included in the unit circuit 2 and that constitute the transistor differential pairs Mk-1 to M0 is reduced. Get smaller. Therefore, the gain decreases (state (A) in FIG. 1A).

  Next, in the variable gain amplifier circuit 10b shown in FIG. 5, only the switch circuit Sw0 is conducted in the unit circuit 2, and the gain of the unit circuit 2 is minimized.

  Here, at the same time that the gain of the unit circuit 2 is minimized, the bias voltage V12 is applied to the gate terminals of the transistor differential pairs Mk-1 to M0 included in the unit circuit 3 (state (A in FIG. 1A) ) To state (B)).

  In this case, no current flows through the unit circuit 3. This is because, in the unit circuit 3, only the bias voltage V12 is applied to the gate terminals of the transistor differential pairs Mk-1 to M0, and all the switch circuits Swk-1 to Sw0 are cut off. Because.

  Therefore, signal amplification is not performed in the unit circuit 3 in the variable gain amplifier circuit 10b shown in FIG.

  Next, it is assumed that the gain when only the switch circuit Sw0 of the unit circuit 2 is conductive is large, and the signal received by the unit circuit 2 needs to be further attenuated.

  In this case, as shown in FIG. 6, the switch circuit Sw0 of the unit circuit 2 is shut off, and all the switch circuits of the unit circuit 2 are shut off. In some cases, the constant current source I31 is also turned off. This can contribute to lower power consumption.

  By doing so, the current of the transistor differential pair Mk-1 to M0 including the current of the transistor differential pair 0 is cut off. However, at this time, the bias voltage V11 applied to the gates of the transistor differential pairs Mk-1 to M0 is maintained as it is.

  At the same time as the currents of all the transistor differential pairs Mk-1 to M0 included in the unit circuit 2 are cut off, all the switch circuits Sw0 to Swk-1 included in the unit circuit 3 are turned on (FIG. 1A (C)).

  At this time, before the transition from the state (B) to the state (C), the bias voltage V12 is applied to the gate terminal of the amplification transistor included in the unit circuit 3 in advance.

  For this reason, time until electric charge accumulates in the capacity attenuator 11 can be saved. That is, the charge of the capacitance attenuator 11 can be accumulated before the next unit circuit 3 to be used is used. As a result, it is possible to eliminate an unstable bias period until the bias voltage of the amplification transistor reaches a steady state.

  Therefore, the current of the amplifying transistor is not momentarily interrupted as in the conventional variable gain amplifier circuit whose signal waveform is shown in FIG. Therefore, the signal received by the variable gain amplifier circuit 10b is not interrupted.

  After that, when only the switch circuit Swk-1 is cut off among the switch circuits included in the unit circuit 3, the bias voltage V11 applied to the gates of the transistor differential pairs Mk-1 to M0 is turned off in the unit circuit 2. (State (D) in FIG. 1A).

  The time change of the signal when the state (A) is changed to the state (D) is as shown in FIG. Therefore, as shown in FIG. 1B, which is the same drawing as FIG. 18, there is no signal interruption during the transition from the state (B) to the state (C).

(Unit circuit)
Each of the unit circuits 2 and 3 according to the present embodiment includes the following members.

  That is, the unit circuit 2 or the unit circuit 3 includes two amplification transistors that constitute the transistor differential pair and whose sources are connected to each other.

  One transistor differential pair is provided, and one end is provided with a switch circuit connected to the source in the number of the transistor differential pairs.

  Furthermore, an input is connected to the other end of all the switch circuits, and an output is provided with a current source that is electrically grounded.

  By appropriately turning on or off the switch circuit, an output signal can be output from the drain of the amplification transistor.

(Capacitance attenuator)
In the capacitive attenuator 11 according to this embodiment, a signal input to the transistor differential pair may be input to the unit circuit 3 via the capacitive attenuator 11 that attenuates the signal. As a result, a gain variable range that cannot be realized by the unit circuit 3 alone can be realized.

  In addition, the signal is input to one end of the capacity attenuator 11 according to the present embodiment, and the other end includes capacitors 11a and 11b (attenuation capacitors) that are capacitors connected to the input of the second variable gain amplifying unit. Also good. Thereby, attenuation of the input signal and removal of the DC voltage can be performed.

(Bias voltage V11, V12)
The bias voltage according to the present embodiment is applied as shown below.

  First, one end of a resistor R11 (first resistor) is connected to one of differential inputs (the gate of one of the amplification transistors of each transistor differential pair). Similarly, one end of the resistor R12 (second resistor) is connected to the other of the differential inputs (the gate of the other amplification transistor of each transistor differential pair). A bias voltage is applied to a connection point where the other end of the resistor R11 and the other end of the resistor R12 are connected. In the unit circuit 2, the bias voltage V11 is applied to the connection point, and in the unit circuit 3, the bias voltage V12 is applied to the connection point.

  By providing the resistors R11 and R12, the high frequency signal component is prevented from affecting the unit circuits 2 and 3. The unit circuits 2 and 3 are circuits to which bias voltages V11 and V12 are applied.

(Comparison of signal strength)
The comparison of signal strength is performed by connecting an RSSI circuit 50b (Received Signal Strength Indicator: comparison circuit) and an AGC (Automatic Gain Control circuit) circuit 50a.

  The RSSI circuit 50b compares the level of the amplified signal SA amplified by the unit circuit 2 and the unit circuit 3 with a predetermined value.

  The AGC circuit 50a performs the following gain control in addition to the monitor described above. That is, the AGC circuit 50a reduces the gain of the unit circuit 3 when the level of the amplified signal SA is higher than the predetermined value. The AGC circuit 50a increases the gain of the unit circuit 2 when the level of the amplified signal SA is smaller than the predetermined value.

  In the unit circuits 2 and 3, bias voltages V11 and V12 are applied, but the bias voltages V11 and V12 may be supplied via a K-bit line shown in FIG.

  Further, the K-bit line may be extended from the AGC circuit 50a as shown in FIG. 2, or may be extended from the outside of the variable gain amplifier circuit 10b.

  The criteria for determining the gain are not particularly limited because they differ depending on the system. As an example, in the first embodiment, when shifting from the minimum value of the gain of the unit circuit 2 to the maximum value of the gain of the unit circuit 3, the intensity of the signal received by the unit circuit 2 is the maximum intensity ( 100%) is switched when it reaches 50%. As a result, the variable gain amplifier circuit 10b is provided with hysteresis characteristics to prevent the operation from becoming unstable.

(Minimum / Maximum gain)
The minimum value of the first gain range that is the gain range of the unit circuit 2 is not particularly limited. For example, the minimum value of the first gain range may be slightly above or below the maximum value of the second gain range. Further, the minimum value of the first gain range may be created so as to be slightly higher than the maximum value of the second gain range.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. Configurations other than those described in the second embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 are given the same reference numerals, and explanation thereof is omitted.

  In the second embodiment, with reference to FIGS. 8 to 11, when the strength (level) of a signal input during reception largely changes (fluctuates) in the reception state, the variable gain amplifier circuit 10 b gains. The operation when gradually increasing the value will be described.

  First, for the variable gain amplifier circuit 10b shown in FIG. 8, the strength (level) of the signal received by the unit circuit 3 is monitored by an AGC circuit (automatic gain control circuit, not shown). If the intensity of the signal received by the unit circuit 3 is low (small) as a result of monitoring, the variable gain amplifier circuit 10b gradually turns on the switch circuit included in the unit circuit 3 from Sw0 to Swk-1.

  The reason why each switch circuit is gradually turned on is to avoid a sudden change in gain.

  When the current of the transistor differential pair M0 to Mk-1 flows, the total transistor width of the amplification transistors that are transistors included in the unit circuit 3 and that constitute the transistor differential pair M0 to Mk-1 is increased. . Therefore, the gain increases (state (E) in FIG. 12).

  Next, in the variable gain amplifier circuit 10b shown in FIG. 9, all the switch circuits Swk-1 to Sw0 are conducted in the unit circuit 3, and the gain of the unit circuit 3 is maximized.

  Here, at the same time when the gain of the unit circuit 3 is maximized, the bias voltage V11 is applied to the gate terminals of the transistor differential pairs Mk-1 to M0 included in the unit circuit 2 (from the state (E) in FIG. 12 to the state). (Transition to (F)).

  In this case, no current flows through the unit circuit 2. This is because, in the unit circuit 2, only the bias voltage V11 is applied to the gate terminals of the transistor differential pairs Mk-1 to M0, and all the switch circuits Swk-1 to Sw0 are cut off. Because.

  Therefore, signal amplification is not performed in the unit circuit 2 in the variable gain amplifier circuit 10b shown in FIG.

  Next, it is assumed that the gain when all the switch circuits Swk-1 to Sw0 of the unit circuit 3 are conductive is also small, and the signal received by the unit circuit 3 needs to be further amplified.

  In this case, as shown in FIG. 10, all the switch circuits Swk-1 to Sw0 included in the unit circuit 3 are shut off. In some cases, the constant current source I32 is also turned off. This can contribute to lower power consumption.

  By doing so, the currents of the transistor differential pairs Mk-1 to M0 are cut off. However, at this time, the bias voltage V12 applied to the gates of the transistor differential pairs Mk-1 to M0 is maintained as it is.

  Then, all the switch circuits Swk-1 to Sw0 included in the unit circuit 3 are shut off, and at the same time, the switch circuit Sw0 included in the unit circuit 2 is turned on (state (G) in FIG. 12).

  At this time, before the transition from the state (F) to the state (G), the bias voltage V11 is applied to the gate terminal of the amplification transistor included in the unit circuit 2 in advance.

  For this reason, it is possible to save time until charges are accumulated in the capacitors 4a and 4b of the capacitor group 4 'for removing the DC voltage. Therefore, the current of the amplifying transistor is not momentarily interrupted as in the conventional variable gain amplifier circuit whose signal waveform is shown in FIG. Therefore, the signal received by the variable gain amplifier circuit 10b is not interrupted.

  Thereafter, when the switch circuits Sw0 and Sw1 included in the unit circuit 2 are turned on, the bias voltage V12 of the unit circuit 3 is turned off (state (h) in FIG. 12).

  The time change of the output signal when the state (E) is changed to the state (H) is as shown in FIG. 12, and the signal is not interrupted during the transition from the state (F) to the state (G).

[Embodiment 3]
The following will describe still another embodiment of the present invention with reference to FIG. The configurations other than those described in the third embodiment are the same as those in the first and second embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 and 2 are given the same reference numerals, and descriptions thereof are omitted.

  In the third embodiment, a first configuration example of the capacity attenuator 11 will be described with reference to FIG.

  In the variable capacity attenuator 11_3, which is a first configuration example of the capacity attenuator 11, a capacitor C0 that is always conductive is provided at the input of the unit circuit 3 that is configured differentially.

  In the variable capacitance attenuator 11_3, one capacitance Cm (m = 1, 2 to k), a switching transistor Sm (m = 1, 2 to k) to which a control signal is input to the gate, and the other capacitance Cm ( m = 1, 2 to k) are connected in series. The capacitance switching circuit 5m (m = 1, 2 to k) configured in this way is connected between the inputs of the unit circuit 3 configured differentially.

  Therefore, when the gains after the attenuation by the capacitors 11a, 11b, and C0, which are the capacitors included in the capacitor attenuator 11, are still large and further attenuation is necessary, the switching transistor Sm is turned on in order and the combined capacitance (the combined capacitance Increase the capacitance. Thereby, the amount of attenuation can be increased (varied).

  As described above, in the variable capacitance attenuator 11_3 according to the third embodiment, the signal is a differential signal, the unit circuit 3 has a differential configuration, and the first input terminal and the first input terminal to which the signal is input. It has 2 input terminals. The variable capacity attenuator 11_3 includes a switching transistor Sm whose gate receives a control signal. One end is connected to the source of the switching transistor Sm, and the other end includes one capacitor Cm (first capacitor) connected to the first input. Further, one end is connected to the drain of the switching transistor Sm, and the other end is provided with the other capacitor Cm (second capacitor) connected to the second input.

  By appropriately turning on or off the switching transistor Sm, it is possible to vary the amount of attenuation of the variable capacitance attenuator 11_3 by changing the combined capacitance of the variable capacitance attenuator 11_3.

[Embodiment 4]
The following will describe still another embodiment of the present invention with reference to FIG. Configurations other than those described in the fourth embodiment are the same as those in the first to third embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 3 are given the same reference numerals, and descriptions thereof are omitted.

  In the fourth embodiment, a second configuration example of the capacity attenuator 11 will be described with reference to FIG.

  In the variable capacity attenuator 11_4, which is a second configuration example of the capacity attenuator 11, a capacitor C0 that is always conductive is provided at the input of the unit circuit 3 that is configured differentially.

  Here, the variable capacitor attenuator 11_4 includes a capacitor Cma (third capacitor, m = 1, 2 to k), a capacitor Cmb (fourth capacitor, m = 1, 2 to k), and a capacitor Cmc (fifth capacitor). , M = 1, 2 to k), and the same number of transistor switches Sm ′ as the capacitance Cma. The capacities Cma, Cmb, and Cmc will be described later.

  Here, in the variable capacitance attenuator 11_4 according to the fourth embodiment, the signal is a differential signal, the unit circuit 3 has a differential configuration, and a first input terminal and a second input to which the signal is input. It has a terminal. The variable capacitance attenuator 11_4 includes a transistor switch Sm ′ composed of two switching transistors whose control signals are input to gates connected to each other.

  One end is connected to one source of the transistor switch Sm ′, and the other end is provided with a capacitor Cma connected to the other source of the transistor switch Sm ′. Also good.

  Furthermore, one end is connected to one end of the previous stage capacitor Cma, and the other end is provided with a capacitor Cmb connected to one end of the capacitor Cma.

  Furthermore, one end is connected to the other end of the previous stage capacitor Cma, and the other end is provided with a capacitor Cmc connected to the other end of the capacitor Cma.

  One drain of the transistor switch Sm ′ is connected to the first input, and the other drain of the transistor switch Sm ′ is connected to the second input.

  Therefore, when the gains after the attenuation by the capacitors 11a, 11b, and C0, which are the capacitors included in the capacitor attenuator 11, are still large and further attenuation is necessary, the transistor switch Sm ′ is turned on in order and the combined capacitor (the combined capacitor Increase the capacitance. Thereby, the amount of attenuation can be increased (varied).

(Application example)
Since the receiving circuit of the present invention includes any one of the variable gain amplifier circuits described above, it is possible to amplify or attenuate signals that are continuously input and to achieve high linearity.

  Note that the broadcast frequency of televisions and radios is 45 MHz or higher, and the variable gain amplifier circuits 10a and 10b according to the present embodiment may be used as variable gain amplifiers for tuners used in televisions and radios. In this way, even when the received signal fluctuates greatly according to the reception situation, it is possible to receive the image without interruption.

  As described above, in the variable capacitance attenuator 11_4 according to the fourth embodiment, the composite capacitance of the variable capacitance attenuator 11_4 is changed by appropriately turning on or off the transistor switch Sm ′, thereby changing the variable capacitance attenuation. The attenuation of the device 11_4 can be varied.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The variable gain amplifier circuit of the present invention can be applied to a television that receives a television broadcast. In particular, it can be suitably used for a television that receives a television broadcast using a cable or radio wave.

10a, 10b Variable gain amplifier circuit 2 Unit circuit (first variable gain amplifier section)
3. Unit circuit (second variable gain amplifier)
4 'capacity group 4a, 4b capacity (DC voltage rejection capacity)
5 m capacity switching circuit 11 capacity attenuator 11_3, 11_4 variable capacity attenuator 11a, 11b capacity (attenuation capacity)
50a AGC circuit (automatic gain control circuit)
50b RSSI circuit (comparison circuit)
C0, Cm, Cma, Cmb, Cmc Capacitance I31, I32 Constant current source (current source)
M0 to Mk-1 Transistor differential pair (transistor group)
R11 resistor (first resistor)
R12 resistance (second resistance)
SA Signal after amplification Sm Switching transistor Sm 'Transistor switch Sw0-Swk-1 Switch circuit V11, V12 Bias voltage

Claims (12)

A first variable gain amplifying unit and a second variable gain amplifying unit capable of changing a gain when a signal input from the outside is amplified, and the maximum value of the gain of the first variable gain amplifying unit is the second variable gain. A variable gain amplifying circuit that is higher than the maximum gain of the variable gain amplifying unit, wherein the minimum value of the gain of the first variable gain amplifying unit is higher than the minimum value of the gain of the second variable gain amplifying unit;
The first variable gain amplifying unit and the second variable gain amplifying unit are respectively
A transistor group having a plurality of amplification transistors to which the signal is input to the gate;
A first resistor having one end connected to the gate of one of the amplification transistors of each transistor group and a bias voltage applied to the other end;
A second resistor having one end connected to the gate of the other amplification transistor of each transistor group and the other end to which the bias voltage is applied;
A variable gain amplification characterized by applying the bias voltage to the first resistor and the second resistor included in the second variable gain amplifier when the gain of the first variable gain amplifier is minimized. circuit. A first variable gain amplifying unit and a second variable gain amplifying unit capable of changing a gain when a signal input from the outside is amplified, and the maximum value of the gain of the first variable gain amplifying unit is the second variable gain. A variable gain amplifying circuit that is higher than the maximum gain of the variable gain amplifying unit, wherein the minimum value of the gain of the first variable gain amplifying unit is higher than the minimum value of the gain of the second variable gain amplifying unit;
The first variable gain amplifying unit and the second variable gain amplifying unit are respectively
A transistor group having a plurality of amplification transistors to which the signal is input to the gate;
A first resistor having one end connected to the gate of one of the amplification transistors of each transistor group and a bias voltage applied to the other end;
A second resistor having one end connected to the gate of the other amplification transistor of each transistor group and the other end to which the bias voltage is applied;
A variable gain amplification characterized in that the bias voltage is applied to the first resistor and the second resistor included in the first variable gain amplifier when the gain of the second variable gain amplifier is maximized. circuit. A comparison circuit that compares the level of the amplified signal amplified by the first variable gain amplification unit and the second variable gain amplification unit with a predetermined value;
2. The variable gain amplifier circuit according to claim 1, further comprising an automatic gain control circuit that reduces the gain of the second variable gain amplifier when the level of the amplified signal is greater than the predetermined value. A comparison circuit that compares the level of the amplified signal amplified by the first variable gain amplification unit and the second variable gain amplification unit with a predetermined value;
3. The variable gain amplifier circuit according to claim 2, further comprising an automatic gain control circuit that increases the gain of the first variable gain amplifier when the level of the amplified signal is smaller than the predetermined value. The first variable gain amplifying unit and the second variable gain amplifying unit are respectively
The sources of the plurality of amplification transistors are connected to each other;
A switch circuit having one end connected to the source is provided for each transistor group,
5. The variable according to claim 1, further comprising a current source having an input connected to the other end of all the switch circuits and an output electrically grounded. 6. Gain amplifier circuit. It further includes a direct current voltage removal capacity that is a capacity for removing direct current voltage,
6. The variable gain amplifier circuit according to claim 1, wherein the signal is input to the first variable gain amplifier through the DC voltage removal capacitor. A capacitance attenuator for attenuating the signal;
The variable gain amplifier circuit according to claim 1, wherein the signal is input to the second variable gain amplifying unit via the capacitance attenuator.   8. The variable attenuator according to claim 7, wherein the capacitance attenuator includes an attenuation capacitance that is a capacitance to which the signal is input at one end and the other end is connected to an input of the second variable gain amplifying unit. Gain amplifier circuit. The above signal is a differential signal,
The second variable gain amplifying unit has a differential configuration, and has a first input terminal and a second input terminal to which the signal is input,
The capacity attenuator is a variable capacity attenuator whose amount of attenuation is variable,
The variable capacity attenuator is
A switching transistor in which a control signal is input to the gate;
A first capacitor having one end connected to the source of the switching transistor and the other end connected to the first input terminal;
9. The variable gain amplifier circuit according to claim 8, further comprising: a second capacitor having one end connected to the drain of the switching transistor and the other end connected to the second input terminal. The above signal is a differential signal,
The second variable gain amplifying unit has a differential configuration, and has a first input terminal and a second input terminal to which the signal is input,
The capacity attenuator is a variable capacity attenuator whose amount of attenuation is variable,
The variable capacity attenuator is
A transistor switch composed of two switching transistors whose control signals are input to gates connected to each other;
A third capacitor having one end connected to one source of the transistor switch and the other end connected to the other source of the transistor switch;
A fourth capacitor having one end connected to one end of the third capacitor in the previous stage and the other end connected to one end of the third capacitor;
One end is connected to the other end of the third capacitor in the previous stage, and the other end is provided with a fifth capacitor connected to the other end of the third capacitor,
One drain of the transistor switch is connected to the first input terminal,
9. The variable gain amplifier circuit according to claim 8, wherein the other drain of the transistor switch is connected to the second input terminal.   The variable gain amplifier circuit according to any one of claims 1 to 10, wherein the frequency of the signal is 40 MHz or higher.   A receiving circuit comprising the variable gain amplifier circuit according to claim 1.

Images