JP2007519366A - Integrated variable frequency filter for wideband tuners. - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated TV signal receiving tuner incorporating a variable frequency filter and expanding an input voltage range.
The variable frequency filter circuit includes a first differential transistor pair biased with a first current, a second differential transistor pair biased with a second current, and first and second capacitors. Is provided. The variable frequency filter circuit can be configured as a band pass filter or a band elimination filter by applying an input signal voltage to different input nodes of the variable frequency filter circuit. The variable frequency filter circuit can be tuned by adjusting the first current value and the second current value. In an alternative embodiment, the tuning frequency is varied by switching capacitive loads or by changing the resistive impedance introduced at the emitters of the differential transistor pair to achieve a wider filter input voltage range. The variation of the emitter resistance uses a MOS switch and controls the on-resistance of the MOS switch to achieve high-precision tuning over a wide frequency range.
[Selection] Figure 2

Description

  The present invention relates to a variable tuning system for a television signal receiver, and more particularly, the present invention can be included in a tuning circuit for all VHF channels, all UHF channels having frequencies in the low VHF band, VHF band and UHF band. The present invention relates to a variable frequency filter.

  Television signals are transmitted in the assigned radio frequency (RF) band. In the United States, the low VHF band is in the frequency range of 54 to 88 MHz, the VHF band is 120 to 216 MHz, and the UHF band is further up to 1 GHz. Conventional television receivers use a tuner to tune or select a desired RF signal within a given frequency range (6 MHz) and remove all other signals for reception of the desired channel.

  FIG. 1 is an example of a conventional tuning system that can be used to receive low VHF, VHF and UHF broadcast channels. Referring to FIG. 1, the input RF signal to the input terminal 1 is a signal from a terrestrial broadcast or a cable transmission line. This input RF signal is applied to an RF input circuit including a band pass filter 2, a band elimination filter 3 (also referred to as a trap or notch filter) and an RF amplifier 4 capable of gain control from outside. The output of the amplifier 4 is applied to a tuning circuit 8 which is usually composed of an integrated circuit (IC). The tuning circuit 8 may include one or more mixers 5 and one or more variable frequency local oscillators 6. The tuning frequency control system 7 in the IC tuner 8 is a control signal for tuning the operating frequencies of the bandpass filter 2, the band elimination filter 3 and the variable frequency local oscillator 6 for receiving and selecting a desired channel. Is generated.

  The conventional tuner such as the tuner shown in FIG. 1 usually uses individual components for the configuration of an RF input circuit such as a filter. These individual components include varactors (variable capacitance diodes), inductors, capacitors, switchable diodes, and the like. For example, switchable diodes are used to switch between several assigned frequency bands. The varactor part performs a fine adjustment operation for high-precision frequency selection in the selected frequency band. Tuner components other than the above, such as a mixer and a transmission circuit, are manufactured by being mounted on one integrated circuit separately from the filter in the tuner.

The filter can be integrated with the rest of the tuner circuit using a transistor based circuit. A general method for realizing a high-order active filter is a method of cascading biquadratic filter sections (also referred to as biquad filters). Usually, the biquad filter is configured using a transistor pair and a capacitor pair connected to each other. Frequency tuning is achieved by varying the pair of connected currents. One disadvantage of active biquad filters is that they have a limited dynamic range compared to passive filter configurations. Usually, for bipolar transistor pairs connected to each other, the input voltage range is 2 V _T or less. Here, V _T is about 26 mV at 300 ° K, which is a value independent of technology. Examples of tuning systems for TV receivers are described in US Pat. Nos. 4,363,135 and 5,752,179.

R. L. Geiger et al: “Active Filter Design using Operational TransconductanceAmplifiers: A Tutorial,” IEEE Circuits and Devices Magazine, IEEE Inc. Vol.1, No.2, 1 March 1985, pp.20-32 E. Sanchesz – Sinensio et al: “CMOS Transconductance Amplifiers: Circuits, Devices and Systems,” Institution of Electrical Engineers, Stenvenage, GB, Vol.47, No.1, 4 February 2000, pp.3-12

  There is a need to provide a tuner comprising an integrated circuit filter. There is also a need to provide a filter for use in a tuner that can receive a wider range of input voltages.

  According to one embodiment of the present invention, the variable frequency filter circuit includes a first differential pair and a second differential pair. The first differential pair includes a first input terminal connected to the first node, a second input terminal connected to the second node, and an output terminal connected to the first current source. The first differential pair is biased with a second current source. The second differential pair has a first input terminal connected to the output terminal of the first differential pair, a second input terminal connected to the second node, and a third current source connected to the output. And an output terminal for generating a voltage signal. The second differential pair is biased with a fourth current source. The circuit further includes: a first capacitor connected between a third node and the output terminal of the first differential pair; and the first node and the output terminal of the second differential pair. And a second capacitor connected therebetween.

  The variable frequency filter circuit of the present invention can be configured as a band pass filter by connecting the input voltage signal to the third node and connecting the first node to a first voltage source such as a ground potential point. it can. Also, the variable frequency filter circuit can be configured as a band elimination filter by connecting the input voltage signal to the first node and connecting the third node to a first voltage source such as a ground potential point. .

  In one embodiment, the variable frequency filter circuit of the present invention is tuned by adjusting the current values of the first, second, third and fourth current sources.

  In another embodiment, the first and second differential pairs of the variable frequency filter circuit are embodied as emitter coupled bipolar transistor pairs. In still another embodiment, a variable resistance element is introduced into each bipolar emitter terminal of the first and second differential pairs. These variable resistance elements introduce an emitter resistance into these differential pairs to effectively expand the input voltage range of this variable frequency filter circuit.

  In yet another embodiment of the present invention, the variable frequency filter circuit further comprises a coarse tuning system for selecting different frequency bands. The coarse tuning system includes a first bank of capacitors each connected to a switch in a first switch bank. Each group of capacitors and switches connected in series with each other is connected between the third node and the output terminal of the first differential pair. The coarse tuning system further includes a bank of capacitors, each connected in series to one of the switches of the second switch bank. Each of the group of capacitors and switches connected in series is connected between the first node and the output terminal of the second differential pair. The first and second switch banks are selectively connected in parallel with one or more of the first banks of capacitors in parallel with the first capacitors, and one or more of the second banks of capacitors are connected to the first Control is performed with a corresponding control signal so as to selectively connect the two capacitors in parallel.

  According to another embodiment of the invention, an emitter resistor is introduced into each of the differential pairs via a bank of transistor pairs. Each of the transistor pairs is controlled by a control signal that selectively turns on the transistor pairs. As a result, a stepwise increase or decrease of the resistive load at the emitter terminals of the differential pair is achieved. Further, the voltage value of the control signal can be changed with high accuracy so as to achieve high-precision minute resistance value fluctuation.

  That is, in one embodiment, coarse tuning of the variable frequency filter circuit is achieved by capacitance switching and resistance value switching. Therefore, in order to select a desired frequency band, the first bank and the second bank of capacitors are selectively connected to selectively drive the bank of transistor pairs. On the other hand, fine tuning of the variable frequency filter circuit is achieved by adjusting the voltage value of the control signal for controlling each of the transistor pairs in the transistor pair bank with high accuracy.

  A variable frequency tuning system having a wide operable frequency band and a wide input RF signal voltage range can be provided.

  A variable frequency biquad filter for low VHF, VHF and UHF reception according to the principles of the present invention will be described. The variable frequency biquad filter includes two differential pairs that are respectively biased by first and second current sources. This filter can be tuned by adjusting the value of the current flowing through these first and second current sources. This variable frequency biquad filter can be easily integrated into an integrated circuit, thereby enabling a fully integrated circuit configuration. By eliminating the use of individual components, the tuner of the present invention can minimize dimensions and reduce manufacturing costs. In one embodiment, the variable frequency biquad filter is configured to expand the input voltage range compared to a conventional emitter coupled bipolar transistor pair based filter. When incorporated into a tuning system, the variable frequency biquad filter of the present invention achieves improved tuning performance.

  FIG. 2 is a block diagram of a tuning circuit that can employ the integrated variable frequency filter of the present invention. 1 and 2, the same constituent elements are shown with the same reference numerals. Referring to FIG. 2, the tuner 20 includes an RF input circuit and a tuning circuit 8. The RF input circuit includes a band pass filter 22 and a band elimination filter 23 configured using the variable frequency biquad filter according to the present invention. Therefore, the tuner 20 integrates the band-pass filter 22 and the band elimination filter 23 in the same integrated circuit 8 as the tuning circuit 8, thereby improving the performance of the tuner and reducing the manufacturing cost. The configuration of the tuner 20 shown in FIG. 2 is for illustration, and the variable frequency biquad filter of the present invention can be integrated with a tuner of an arbitrary configuration in order to exhibit the RF filter function. Those skilled in the art will appreciate.

  Another advantage of the variable frequency biquad filter of the present invention is the adaptability of this basic filter circuit. That is, this basic variable frequency biquad filter circuit can be easily configured to have a filter function and a filter shape as a bandpass filter or a band elimination filter. More specifically, this basic variable frequency filter can be reconfigured by feeding the input RF signal to a different input node of the filter circuit, resulting in a filter with a different transfer function. Details of the biquad filter of the present invention will be described later with reference to FIGS.

  FIG. 3 is a circuit diagram of a biquad filter configured as a band-pass filter of a single-ended topology according to one embodiment of the present invention. Referring to FIG. 3, the bandpass biquad filter 100 (bandpass filter 100) includes two emitter coupled transistor pairs. The first emitter-coupled transistor pair is composed of bipolar transistors T1 and T1 ', and the second emitter-coupled transistor pair is composed of bipolar transistors T2 and T2'.

In the first emitter-coupled transistor pair, the collector terminal of the transistor T1 is connected to the supply source of the power supply voltage _VCC of this filter circuit. On the other hand, the collector terminal of the transistor T1 ′ is connected to the supply source Cur1 ′ of the current value I1. The emitter terminals of these transistors T1 and T1 ′ are connected in common and connected to a current source Cur1 that generates a current 2I1. The base terminal of the transistor T1 is connected to the ground potential point.

In the second emitter-coupled transistor pair, the collector terminal of transistor T2 is connected to the source of voltage _VCC . The collector terminal of the transistor T2 ′ is connected to a current source Cur2 ′ that produces a current value I2. The emitter terminals of these transistors T2 and T2 'are connected in common and connected to a current source Cur2 which generates a current value 2I2. The base terminal of the transistor T2 is connected to the collector terminal of the transistor T1 ′ and to the capacitor C1. The other terminal of the capacitor C1 is connected to receive the input RF signal Vin. The base terminals of the transistors T1 ′ and T2 ′ are connected in common. The collector of the transistor T2 ′ is connected to the capacitor C2, and the other terminal of the capacitor C2 is connected to the ground potential point. The capacitances of these capacitors C1 and C2 are generally not the same, and are set to values selected based on the formula described later.

  Finally, a gain 1 amplifier Amp1 is connected between the collector terminal and the base terminal of the transistor T2 '. The output signal Vout obtained at the collector terminal of the transistor T2 'is the same as the signal Vout obtained at the output terminal of the amplifier Amp1. Since the input impedance of the differential pair is high, the amplifier Amp1 can be replaced with a simple wiring. The amplifier Amp1 is not necessary for the operation of the filter circuit, but is preferably provided when the filter circuit is interconnected with other circuit blocks. The amplifier Amp1 acts as a buffer for the output signal Vout and prevents interference from subsequent circuit blocks to the operation of the filter circuit.

で与えられる。ここでＵ_Ｔは３００゜Ｋで２６ｍＶにほぼ等しい熱力学ポテンシャルであり、ｓはラプラス変数であって純正弦波信号の場合はｊωに等しい。 The relationship between the output signal Vout and the input signal Vin, ie, the transfer function of the bandpass filter 100, is given by

Given in. Here, U _T is a thermodynamic potential substantially equal to 26 mV at 300 ° K, and s is a Laplace variable, which is equal to jω in the case of a pure sine wave signal.

で与えられる。 The center frequency (f ₀ ) and 3-dB bandwidth (B) of the bandpass filter 100 are given by

Given in.

  As shown above, the center frequency and 3-dB bandwidth of the bandpass filter 100 can be changed by adjusting the currents I1 and I2 of the filter circuit.

  FIG. 4 is a circuit diagram of a biquad filter configured as a band elimination filter in a single-ended topology according to one embodiment of the present invention. The band elimination filter is also called a “trap or notch filter”. 3 and 4, the same components are indicated with the same reference numerals. As is apparent from the comparison of FIGS. 3 and 4, by using the basic biquad filter circuit of two emitter-coupled transistor pairs in different filter configuration, and by applying the input RF signal to different nodes of the filter circuit, Has a different filter function.

Referring to FIG. 4, the band elimination filter 200 includes two emitter coupled transistor pairs connected in the same manner as the band pass filter 100 of FIG. More specifically, the first emitter-coupled transistor pair consists of bipolar transistors T1 and T1 ′. Connect the collector terminal of the transistor T1 to the supply voltage V _CC supply, connected to the 'current source Cur1 the collector terminal produces a current value I1' of the transistor T1. The emitter terminals of the transistors T1 and T1 ′ are connected in common and connected to a current source Cur1 that generates a current 2I1. In order to configure this basic biquad filter circuit as a band elimination filter, the base terminal of the transistor T1 is connected to receive the input RF signal Vin.

In the second emitter-coupled transistor pair including the bipolar transistors T2 and T2 ′, the collector terminal of the transistor T2 is connected to the power supply voltage _VCC supply source, and the collector terminal of the transistor T2 ′ is used as a current source that generates a current having a current value I2. Connecting. The emitter terminals of these transistors T2 and T2 ′ are connected in common and connected to a current source Cur2 that generates a current value 2I2. The base terminal of the transistor T2 is connected to the collector terminal of the transistor T1 ′ and to the capacitor C1. In the band elimination filter 200, the other terminal of the capacitor C1 is connected to the ground potential point (GND). The base terminals of the transistors T1 ′ and T2 ′ are connected in common. The collector terminal of the transistor T2 ′ is connected to the capacitor C2. In the band elimination filter configuration, the other terminal of the capacitor C2 is connected to receive the input signal Vin. An amplifier Amp1 having a gain of 1 is connected between the collector terminal and the base terminal of the transistor T2 ′. The output signal Vout is obtained at both the collector terminal of the transistor T2 ′ and the output of the amplifier Amp1. As described above, the use of the amplifier Amp1 is optional, but using this amplifier is advantageous in that the impedance of the filter output can be lowered.

で与えられる。ここで、Ｕ_Ｔは３００゜Ｋで２６ｍＶにほぼ等しい熱力学ポテンシャルであり、ｓはラプラス変数であって純粋正弦波についてｊωに等しい。 The relationship between the output signal Vout and the input RF signal Vin of the band elimination filter 200, that is, the transfer function, is expressed by the following equation:

Given in. Here, U _T is a thermodynamic potential approximately equal to 26 mV at 300 ° K, and s is a Laplace variable, which is equal to jω for a pure sine wave.

で与えられる。 The center frequency (f ₀ ) and 3-dB bandwidth of the band elimination filter 200 are given by the following equations:

Given in.

The above equation shows that the center frequency f ₀ and the 3-dB bandwidth of the band elimination filter 200 can be changed by adjusting the current values I1 and I2.

  As described above, in order for the TV tuner to receive input RF signals in the low VHF, VHF and UHF bands, the RF input circuit of the TV tuner must be able to receive input signals in a wide voltage range. FIGS. 5 and 6 illustrate another embodiment of the present invention in which a biquad filter is configured to provide an extended input voltage range for receiving an input RF signal in all relevant frequency bands. When a biquad filter with an expanded input voltage range is incorporated in a TV signal receiving tuner, the tuning performance of the tuner can be greatly improved.

  FIG. 5 is a circuit diagram of a biquad filter configured as a band-pass filter in a single-ended topology according to another embodiment of the present invention. 5 and 3, the same components are indicated with the same reference numerals.

Referring to FIG. 5, the band pass filter 300 includes two emitter coupled transistor pairs connected in the same manner as the emitter coupled transistor pair in the band pass filter 100 of FIG. The first emitter coupled transistor pair includes bipolar transistors T1 and T1 ′. Connect the collector terminal of the transistor T1 to the supply voltage V _CC supply, connected to the transistor T1 'current source Cur1 resulting current of the current value I1 to the collector terminal of'. The base terminal of the transistor T1 is connected to the ground potential point. In this embodiment, the emitter terminals of the transistors T1 and T1 ′ are commonly connected through two MOS transistors M1 and M1 ′ biased in the triode element region. A common node of these transistors M1 and M1 ′ is connected to a current source Cur1 that generates a current having a current value 2I1. The gate terminals of the transistors M1 and M1 ′ are connected to receive the control signal Vg1, and the transistors M1 and M1 ′ are always on by the control signal Vg1.

The second emitter coupled transistor pair consists of bipolar transistors T2 and T2 '. The collector terminal of the transistor T2 is connected to the power supply voltage V _CC supply, transistor T2 'the collector terminal of current source Cur2 causing the current I2' is connected to. The emitter terminals of these transistors T2 and T2 ′ are commonly connected through MOS transistors M2 and M2 ′ biased in the triode element region. A common node of the transistors M2 and M2 ′ is connected to a current source Cur2 that generates a current 2I2. The gate terminals of the transistors M2 and M2 ′ are connected to receive the control signal Vg2, and the transistors M2 and M2 ′ are always on by the control signal Vg2.

  Describing the RF input circuit portion of the band pass filter 300, the base terminal of the transistor 2 is connected to the collector terminal of the transistor T1 'and the capacitor C1. The other terminal of the capacitor C1 is connected to receive the input RF signal Vin. In this embodiment, bandpass filter 300 includes a switching circuit that achieves coarse tuning at discrete frequency steps. A switching circuit including a bank of capacitors is selectively switch-connected in parallel with the capacitor C1. More specifically, in the embodiment shown in FIG. 5, the capacitors C1 ′ and C1 ″ are placed in parallel with the capacitor C1 through the switches sw1 and sw2 between the input signal Vin input point and the base terminal of the transistor T2, respectively. The switch sw1 is controlled by the control signal s1, and the switch sw1 ′ is controlled by the control signal s2.

  In the embodiment shown in FIG. 5, the switching circuit of the bandpass filter 300 includes two capacitors and two switches. This configuration is merely exemplary, and the switching circuit can be configured to produce a desired capacitance value that provides a coarse switching function by a combination of one or more capacitors and one or more corresponding switches. Also, each capacitor in the capacitor bank can have a different capacitance value so as to realize a desired capacitance value, as will be understood from the following formula.

  Moving to the output circuit portion of the bandpass filter 300, the collector terminal of the transistor T2 'is connected to the capacitor C2, and the output signal Vout is obtained from the connection point with the capacitor C2. The other terminal of the capacitor C2 is connected to the ground potential point (GND). In this embodiment, a bank of capacitors is selectively connected in parallel with capacitor C2. Capacitors C2 ′ and C2 ″ are connected between the ground potential point and the supply point of the output voltage Vout through the switches sw2 and sw2 ′. The switch sw2 is the control signal s1 and the switch sw2 ′ is the control. In this embodiment, the bank of capacitors includes two capacitors and two corresponding switches, and in another embodiment, one or more capacitors constitute a capacitor bank, and one or more are controlled by the signal s2. The corresponding switch can also be used.

  Finally, a gain 1 amplifier Amp1 is connected between the collector terminal and the base terminal of the transistor T2 '. The base terminals of the transistors T1 'and T2' are connected in common. As described above, the use of the amplifier Amp1 is optional, and is required only when this filter circuit is interconnected with other circuit blocks.

で与えられる。ここで、ｋ１はトランジスタＭ１およびＭ１’のテクノロジーおよび結合構造で定まる定数であり、ｋ２はトランジスタＭ２およびＭ２’のテクノロジーおよび結合構造で定まる定数であり、Ｖｇ１はトランジスタＭ１およびＭ１’のゲート端子への制御電圧であり、Ｖｇ２はトランジスタＭ２およびＭ２’のゲート端子への制御電圧であり、Ｖ_Ｔはトランジスタの閾値電圧である。 Since MOS transistors M1 and M1 ′ and M2 and M2 ′ are biased in the triode element region, these transistors act like resistors. In this embodiment, transistors M1 and M1 ′ are transistors of the same size, and transistors M2 and M2 ′ are transistors of the same size. Each of the transistors M1 and M1 ′ has a resistance value Re1, and each of the transistors M2 and M2 ′ has a resistance value Re2, which has the following equation:

Given in. Here, k1 is a constant determined by the technology and coupling structure of the transistors M1 and M1 ′, k2 is a constant determined by the technology and coupling structure of the transistors M2 and M2 ′, and Vg1 is connected to the gate terminals of the transistors M1 and M1 ′. a control voltage, Vg2 is the control voltage to the gate terminal of the transistor M2 and M2 ', the V _T is the threshold voltage of the transistor.

  When resistance values Re1 and Re2 (emitter resistance) are introduced into the emitter terminals of the emitter-coupled transistor pair, emitter deterioration occurs, which brings about an effect of expanding the input voltage range of the emitter-coupled transistor pair. In this embodiment, the MOS transistor is used as a variable resistance element for introducing a desired emitter resistance value. In another embodiment, a variable resistance element such as a variable resistor may be used for introducing the resistance values Re1 and Re2.

で与えられる。ここで、Ｃｔ１はトランジスタＴ１’のコレクタ端子における全容量、Ｃｔ２はトランジスタＴ２’のコレクタ端子における全容量、Ｕ_Ｔは３００゜Ｋで２６ｍＶにほぼ等しい熱力学ポテンシャル、ｓはラプラス変数であって純正弦波についてはｊωに等しい。 The relationship between the output signal Vout and the input RF signal Vin, that is, the transfer function, is expressed by the following equation:

Given in. Here, Ct1 the transistor T1 'total capacitance at the collector terminals of, Ct2 transistor T2' approximately equal thermodynamic potential in 26mV at full capacity, _{U T} is 300 ° K at the collector terminal of the, s is a Laplace variable genuine For a string wave, it is equal to jω.

で与えられる。 The center frequency (f ₀ ) and 3-dB bandwidth (B) of the bandpass filter 300 are:

Given in.

  The equations listed above show that the center frequency and 3-dB bandwidth of bandpass filter 300 can be changed by currents I1 and I2 and control signals Vg1 and Vg2. More specifically, control voltages Vg 1 and Vg 2 provide the “fine tuning” function of bandpass filter 300.

The coarse tuning operation in the bandpass filter 300 for frequency band switching is brought about by signals s1 and s2 for the control of the switches associated with the bank of capacitors. More specifically, under the control of these signals s1 and s2, switches sw1, sw1 ′, sw2 and sw2 ′ switch select several frequency bands such as low VHF, medium / high VHF, and UHF. . The total capacitance Ct1 at the collector terminal of the transistor T1 ′ and the total capacitance Ct2 at the collector terminal of the transistor T2 ′ are Ct1 = C1 + sw1 · C1 ′ + sw1 ′ · C1 ″ and Ct2 = C2 + sw2 · C2 ′ + sw2 ′ · C2 ″
Given in. Here, sw1 and sw1 ′ indicate a logical value “0” or “1” of the switches sw1 and sw1 ′, and sw2 and sw2 ′ indicate a logical value “0” or “1” of the switches sw2 and sw2 ′. For example, a logical value “1” represents a closed state of the switch, and a logical value “0” represents an open state. By selecting the desired total capacitances Ct1 and Ct2 through these switches sw1, sw1 ′, sw2 and sw2 ′, “coarse tuning” of the bandpass filter 300 is obtained.

  FIG. 6 is a circuit diagram of a biquad filter configured as a band elimination filter in a single-ended topology according to an alternative embodiment of the present invention. 5 and 6, the same components are indicated with the same reference numerals. Referring to FIG. 6, the band elimination filter 400 uses the biquad circuit of the present invention and is configured to add an input RF signal to another input node of the biquad circuit in order to achieve a desired notch filter function. That is, the band-pass filter 300 and the band elimination filter 400 indicate that the basic biquad filter circuit of the present invention has flexibility in providing a desired filter characteristic.

The band elimination filter 400 of FIG. 6 includes two emitter coupled transistor pairs connected in the same manner as the band filter 300 of FIG. Referring to FIG. 6, the first emitter-coupled transistor pair consists of bipolar transistors T1 and T1 ′. The collector terminal of the transistor T1 is connected to a source of supply voltage V _CC, transistor T1 'the collector terminal of the current value I1 current source Cur1 supplied' to connect to. The emitter terminals of the transistors T1 and T1 ′ are connected to each other through MOS transistors M1 and M1 ′ biased in the triode element region. The common connection point of the transistors M1 and M1 ′ is connected to a current source Cur1 that supplies a current of value 2I1. The gate terminals of the transistors M1 and M1 ′ are connected to receive the control signal Vg1, and the transistors M1 and M1 ′ are always kept on by the control signal Vg1. The input RF signal Vin is connected to the base terminal of the transistor T1.

The second emitter-coupled transistor pair is composed of bipolar transistors T2 and T2 ′. Connect the collector terminal of the transistor T2 to a source of supply voltage V _CC, to connect 'the collector terminal of the current value I2 current source Cur2 supplies' transistor T2. The emitter terminals of the transistors T2 and T2 'are connected to each other through MOS transistors M2 and M2' biased in the triode element region. The common connection point of the transistors M2 and M2 ′ is connected to a current source Cur2 that supplies a current of value 2I2. The gate terminals of MOS transistors M2 and M2 ′ are connected to receive control signal Vg2, and transistors M2 and M2 ′ are always on by this control signal Vg2.

  The base terminal of the transistor T2 is connected to the collector terminal of the transistor T1 'and also to the capacitor C1. The other terminal of the capacitor C1 is connected to the ground potential point (GND). In this embodiment, a bank of capacitors is connected in parallel with the capacitor C1. More specifically, in the embodiment of FIG. 6, the capacitors C1 ′ and C1 ″ are connected between the ground potential point and the base terminal of the transistor T2 via switches sw1 and sw2, respectively. The switch sw1 is a control signal. The switch sw1 ′ is controlled by the control signal s2.

  At the output node of the band elimination filter 400, the collector terminal of the transistor T2 'is connected to the capacitor C2, and the output signal Vout is taken out from the capacitor C2. The other terminal of the capacitor C2 is connected to receive the input signal Vin. In this embodiment, the capacitor banks are connected in parallel with the capacitor C2 in a switchable manner. That is, the capacitors C2 ′ and C2 ″ are connected between the input signal Vin and the output signal Vout via the switches sw2 and sw2 ′. The switch sw2 is controlled by the control signal s1, and the switch sw2 ′ is controlled by the control signal s2. To do.

  An amplifier Amp1 having a gain of 1 is connected between the collector terminal and the base terminal of the transistor T2 '. The base terminals of the transistors T1 'and T2' are connected in common. As described above, the use of the amplifier Amp1 is optional, but the inclusion of this amplifier is advantageous because the filter output has a low impedance.

で与えられる。ここで、ｋ１はトランジスタＭ１およびＭ１’のテクノロジーおよび結合構造で定まる定数であり、ｋ２はトランジスタＭ２およびＭ２’のテクノロジーおよび結合構造で定まる定数であり、Ｖｇ１はトランジスタＭ１およびＭ１’のゲート端子への制御電圧であり、Ｖｇ２はトランジスタＭ２およびＭ２’のゲート端子への制御電圧であり、Ｖ_Ｔはこれらトランジスタの閾値電圧である。 Since MOS transistors M1 and M1 ′ and M2 and M2 ′ are biased in the triode element region, these transistors act as resistors. In this embodiment, transistors M1 and M1 ′ have the same dimensions, and transistors M2 and M2 ′ have the same dimensions. The resistance value Re1 of the transistors M1 and M1 ′ and the resistance value Re2 of the transistors M2 and M2 ′ are respectively expressed by the following equations:

Given in. Here, k1 is a constant determined by the technology and coupling structure of the transistors M1 and M1 ′, k2 is a constant determined by the technology and coupling structure of the transistors M2 and M2 ′, and Vg1 is connected to the gate terminals of the transistors M1 and M1 ′. a control voltage, Vg2 is the control voltage to the gate terminal of the transistor M2 and M2 ', the V _T is the threshold voltage of these transistors.

  By introducing resistance values Re1 and Re2 into the emitter terminals of the emitter coupled transistor pair, emitter degradation occurs, thereby expanding the input voltage range of the emitter coupled transistor pair.

で与えられる。ここで、Ｃｔ１はトランジスタＴ１’のコレクタ端子における総容量、Ｃｔ２はトランジスタＴ２’のコレクタ端子における総容量、Ｕ_Ｔは３００゜Ｋ２６ｍＶにほぼ等しい熱力学ポテンシャル、ｓはラプラス変数であって純正弦波信号についてはｊωに等しい。 The relationship between the output signal Vout of the band elimination filter 400 and the input RF signal Vin, that is, the transfer function is expressed by the following equation:

Given in. Here, Ct1 the transistor T1 total capacity at the collector terminal of the 'total capacitance at the collector terminal of, Ct2 transistors T2', approximately equal thermodynamic potential in _{U T} 300 ° K26mV, s is pure sine wave a Laplace variable For the signal, it is equal to jω.

で与えられる。 The center frequency (f ₀ ) and the 3-dB bandwidth (B) of the band elimination filter 400 are given by

Given in.

  The above equation shows that the center frequency and 3-dB bandwidth of the band elimination filter 400 can be changed by the currents I1 and I2 and the control signals Vg1 and Vg2. More specifically, the control signals Vg 1 and Vg 2 provide a “frequency fine tuning” function to the band elimination filter 400.

Under the control of the signals s1 and s2, the switches sw1, sw1 ′, sw2 and sw2 ′ switch several frequency bands such as low VHF, medium / high VHF and UHF. The total capacitance Ct1 at the collector terminal of the transistor T1 ′ and the total capacitance Ct2 at the collector terminal of the transistor T2 ′ are:
Ct1 = C1 + sw1 · C1 ′ + sw1 ′ · C1 ″ and Ct2 = C2 + sw2 · C2 ′ + sw2 ′ · C2 ″
Is equal to Here, sw1 and sw1 ′ represent logical values “0” or “1” of the switches sw1 and sw1 ′, and sw2 and sw2 ′ represent logical values “0” or “1” of the switches sw2 and sw2 ′. For example, a logical value “1” represents a closed switch, and “0” represents an open switch. By selecting desired total capacitances Ct1 and Ct2 by these switches sw1, sw1 ′, sw2 and sw2 ′, “frequency coarse adjustment” of the band elimination filter 400 can be achieved.

  FIG. 7 shows a circuit diagram of a band-pass biquad filter with a single-ended topology according to a second alternative embodiment of the present invention. The biquad filter 500 of FIG. 7 is configured in the same manner as the bandpass biquad filter 300 of FIG. 5 and 7, the same reference numerals are given to the same components. Referring to FIG. 7, the band pass filter 500 is configured by connecting two emitter-coupled transistor pairs in the same manner as the band pass filter 300 of FIG. However, in this embodiment, the emitter terminals of each pair of these emitter-connected transistor pairs are connected to each other via a bank of FET pairs. More specifically, the emitter terminals of each emitter-coupled transistor pair are connected to each other via two pairs of MOS transistors. The total resistive load on the emitter terminals of the emitter coupled transistor pair is given by the parallel resistance of these MOS transistor pairs.

  For the first emitter-coupled transistor pair, the first pair of MOS transistors M10 and M10 'is connected in series between the emitter terminals of transistors T1 and T1'. A common node of these MOS transistors M10 and M10 'is connected to the current source Cur1. The gate terminals of the transistors M10 and M10 'are commonly connected to the supply source of the control signal Vg1'. A second pair of MOS transistors M11 and M11 'is connected in parallel with the first pair of MOS transistors M10 and M10'. The common node of these transistors M11 and M11 'is also connected to the current source Cur1. A control voltage Vg1 ″ is supplied to the gate terminals of the transistors M11 and M11 ′.

  For the second emitter coupled transistor pair, a first MOS transistor pair consisting of MOS transistors M20 and M20 'is connected in series between the emitter terminals of transistors T2 and T2'. A common node of the transistors M20 and M20 'is connected to the current source Cur2. The gate terminals of transistors M20 and M20 'are connected to the source of control signal Vg2'. A second MOS transistor pair composed of MOS transistors M21 and M21 'is connected in parallel with the first MOS transistor pair. The common node of these transistors M21 and M21 'is also connected to the current source Cur2. The gate terminals of the transistors M21 and M21 'are connected to the supply source of the control signal Vg2 ".

  By including the plurality of MOS transistor pairs in the emitter coupled transistor pair of the band-pass filter 500, a coarse tuning system, that is, a coarse tuning system that can achieve coarse tuning control by switching resistance values in addition to capacitance switching is realized. To do. More specifically, coarse tuning in bandpass filter 500 can be achieved by selectively switching capacitors C1 'and C1 "and C2' and C2" to the input voltage node and the output voltage node, respectively. The coarse tuning can also be achieved by controlling on / off of the MOS transistor pair of the emitter coupled transistor pair to increase or decrease the resistive load at the emitter terminal of the emitter coupled transistor pair stepwise. When the MOS transistor is turned off, the electrical circuit is effectively an open circuit and the impedance is very high. On the other hand, when the MOS transistor is turned off, the on-resistance of the transistor becomes a very small value, which is in contrast to the high-resistance state in the off state.

  That is, the bank of MOS transistor pairs incorporated in the emitter coupled transistor pair of the bandpass filter 500 effectively acts as a switch and as a variable resistor. In order to achieve coarse tuning, the control signals to the gate terminals of these MOS transistors control the on / off of each MOS transistor pair, thereby introducing discrete stepwise resistance variation. Further, in order to achieve fine tuning, the control signal becomes a gate voltage, and the MOS transistor is biased in the triode element region. The gate voltage of each MOS transistor pair is adjusted with high accuracy so that a finite resistance value variation can be obtained with high accuracy. More specifically, for fine tuning, the on-resistance of the MOS transistor is continuously varied by adjusting the gate voltage. As a result, the resistive load at the emitter terminal of the emitter-coupled transistor pair can be adjusted to a desired resistance value so that high-precision control of the frequency characteristics of the bandpass filter can be achieved.

でそれぞれ与えられる。ここでＲｅ１０はトランジスタＭ１０およびＭ１０’の対の抵抗値、Ｒｅ１１はトランジスタＭ１１およびＭ１１’の対の抵抗値、Ｒｅ２０はトランジスタＭ２０およびＭ２０’の対の抵抗値、Ｒｅ２１はトランジスタＭ２１およびＭ２１’の対の抵抗値をそれぞれ表す。また、ｋ１’およびｋ１”はトランジスタ対Ｍ１０／Ｍ１０’およびトランジスタ対Ｍ１１／Ｍ１１’のテクノロジーおよび結合構造で定まる定数であり、ｋ２’およびｋ２”はトランジスタ対Ｍ２０／Ｍ２０’およびトランジスタ対Ｍ２１／Ｍ２１’のテクノロジーおよび結合構造で定まる定数である。Ｖｇ１’およびＶｇ１”はトランジスタ対Ｍ１０／Ｍ１０’およびトランジスタ対Ｍ１１／Ｍ１１’のそれぞれの制御電圧である。Ｖｇ２’およびＶｇ２”はトランジスタ対Ｍ２０／Ｍ２０’およびトランジスタ対Ｍ２１／Ｍ２１’のそれぞれの制御電圧である。また、Ｖ_Ｔは上記トランジスタの閾値電圧である。 In this embodiment, each of the pair of MOS transistors M10 and M10 ′, the pair of M11 and M11 ′, the pair of M20 and M20 ′, and the pair of M21 and M21 ′ is composed of the same transistor. If the gate voltage is higher than the threshold voltage, the resistance value of each of these transistor pairs is:

Are given respectively. Here, Re10 is the resistance value of the pair of transistors M10 and M10 ′, Re11 is the resistance value of the pair of transistors M11 and M11 ′, Re20 is the resistance value of the pair of transistors M20 and M20 ′, and Re21 is the pair of transistors M21 and M21 ′. Represents the resistance value of each. K1 ′ and k1 ″ are constants determined by the technology and coupling structure of the transistor pair M10 / M10 ′ and the transistor pair M11 / M11 ′, and k2 ′ and k2 ″ are the transistor pair M20 / M20 ′ and the transistor pair M21 / M21. It is a constant determined by 'technology and bonding structure. Vg1 ′ and Vg1 ″ are the control voltages of the transistor pair M10 / M10 ′ and the transistor pair M11 / M11 ′, respectively. Vg2 ′ and Vg2 ″ are the control of the transistor pair M20 / M20 ′ and the transistor pair M21 / M21 ′, respectively. Voltage. V _T is the threshold voltage of the transistor.

で与えられる。ここでＲｅ１_ＴＯＴは第１のエミッタ結合トランジスタ対（トランジスタＴ１およびＴ１’）の総等価抵抗値、Ｒｅ２_ＴＯＴは第２のエミッタ結合トランジスタ対（トランジスタＴ２およびＴ２’）の総等価抵抗値である。 The total equivalent resistance value for coarse tuning is the parallel resistance value of the MOS transistor in the on state,

Given in. Here, Re1 _TOT is the total equivalent resistance value of the first emitter-coupled transistor pair (transistors T1 and T1 ′), and Re2 _TOT is the total equivalent resistance value of the second emitter-coupled transistor pair (transistors T2 and T2 ′).

  Each of the emitter-coupled transistor pairs of the bandpass filter 500 of FIG. 7 includes two MOS transistor pairs. However, this configuration is exemplary only, and other embodiments may include more than one MOS transistor pair in each emitter-coupled transistor pair. For example, in one embodiment, each of the emitter coupled transistor pairs of the bandpass filter includes four MOS transistor pairs. Further, when a plurality of MOS transistor pairs are incorporated in the emitter coupled transistor pair, all but one of the MOS transistor pairs are completely turned off to cause stepwise resistance value fluctuations. In that case, one MOS transistor pair is kept on so as to provide a connection between the emitter terminals of the emitter coupled transistor pair.

  FIG. 8 is a circuit diagram of a band-eliminated biquad filter of a single-ended topology according to a second alternative embodiment of the present invention. The band elimination biquad filter of FIG. 8 is configured in the same manner as the band element biquad filter of FIG. 6 and 8, the same components are indicated by the same reference numerals. Referring to FIG. 8, the band elimination filter 600 includes two emitter-coupled transistor pairs that are connected in the same manner as the band elimination filter 400 of FIG. In this embodiment, the emitter terminals of the emitter coupled transistor pair are connected to each other through the MOS transistor pair, similarly to the band-pass filter 500 of FIG. That is, each emitter terminal of the emitter coupled transistor pair is connected to each other through two MOS transistor pairs. The total resistive load on the emitter terminals of this emitter coupled transistor pair is given by the parallel resistance of these MOS transistor pairs.

  Since the configuration and operation of the MOS transistor pair in the emitter coupled transistor pair of the band elimination filter 600 are the same as those of the band pass filter 500 of FIG. 7, no further description will be given here. The advantage of incorporating the MOS transistor pair in the emitter coupled transistor pair of the band elimination filter 600 is the same as that of the filter 500 of FIG. That is, by adopting the MOS transistor pair, both the coarse tuning control and the fine tuning control can be achieved as described with reference to FIG.

  In FIG. 8, each bank of MOS transistor pairs includes two MOS transistor pairs. In another embodiment, each bank of the MOS transistors of the band elimination filter 600 includes two or more MOS transistor pairs, thereby providing a desired resistance value for both coarse tuning control and fine tuning control. Of course you can.

  As described above with reference to FIGS. 3 to 8, the biquad filter circuit of the present invention is configured using transistors and capacitors that can be easily configured in the form of one integrated circuit. Therefore, the biquad filter circuit of the present invention can be integrated with other tuner circuits and manufactured in the form of a fully integrated tuner. When a tuner for a television receiver is configured as an RF input stage using the biquad filter of the present invention, the tuner performance can be remarkably improved in all frequency bands to be studied. Furthermore, the biquad filter circuit of the present invention can be configured to increase the input voltage range, thereby ensuring the reception quality of input signals in all frequency bands. The biquad filter of the present invention can be embodied in a tuner for terrestrial broadcasting or cable TV transmission.

  The descriptions above are intended to be illustrative of specific embodiments of the invention and are not intended to be limiting. Many modifications and variations are possible within the scope of this invention. For example, the differential transistor pair in the biquad filter circuit can be realized using only MOS transistors. Another possible modification of these filter circuits is to combine a MOS transistor in parallel or in series with a linear resistor so as to provide a limitation of the total variable range of the resistive load at the emitter node.

  In the embodiments shown in FIGS. 5 to 8, an emitter resistor is introduced into the filter circuit in order to expand the input voltage range, and a coarse tuning system is introduced in order to switch the frequency band. In other embodiments of the invention, an emitter resistor or coarse tuning system can be introduced to further enhance the performance of the biquad filter circuit. For example, an emitter resistor can be introduced into the bandpass filter of FIG. 3 to expand the input voltage range. Further, in the embodiments shown in FIGS. 5 to 8, MOS transistors are used for introducing the emitter resistance into the differential transistor pair, and these MOS transistors also function as a switch for introducing a step-like resistance value variation. It is comprised so that it may do. In other embodiments, these MOS transistors can be replaced with switching devices having variable on-resistance.

  The biquad filter circuits shown in FIGS. 3-8 are for illustrative purposes only. Those skilled in the art will appreciate that the basic biquad filter circuit shown in these figures can be extended to the realization of higher order filters using the same tuning principle and the combination of continuous and stepped control of the operating frequency. It will be clear. The invention is defined by the appended claims.

  The present invention can be used for a TV signal receiving apparatus in which the operable frequency band is greatly expanded.

1 is an illustration of a conventional tuning system for reception of low VHF, VHF and UHF broadcast channels. The block diagram of the tuning circuit which can utilize the integrated variable frequency filter of this invention. 1 is a circuit diagram of a band-pass biquad filter of a single-ended topology according to one embodiment of the present invention. 1 is a circuit diagram of a band-end biquad filter of a single-ended topology according to one embodiment of the present invention. FIG. 6 is a circuit diagram of a band-pass biquad filter with a single-ended topology according to an alternative embodiment of the present invention. FIG. 6 is a circuit diagram of a band-end biquad filter with a single-ended topology according to an alternative embodiment of the present invention. FIG. 5 is a circuit diagram of a single-ended topology band-pass biquad filter according to a second alternative embodiment of the present invention. FIG. 6 is a circuit diagram of a band-end biquad filter with a single-ended topology according to a second alternative embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input terminal 2, 22 Bandpass filter 3, 23 Band elimination filter 4 Amplifier 5 Mixer 6 Variable frequency oscillator 7 Frequency control voltage generator 8 IC tuning circuit 10, 20 Tuner

Claims (40)

A variable frequency filter circuit,
A first input terminal connected to the first node, a second input terminal connected to the second node, and an output terminal connected to the first current source, biased by the second current source A first differential transistor pair;
A first capacitor connected between a third node and the output terminal of the first differential transistor pair;
A first input terminal connected to the output terminal of the first differential transistor pair, a second input terminal connected to the second node, and a third current source for supplying an output voltage signal. A second differential transistor pair having an output terminal and biased by a fourth current source;
A circuit including a second capacitor connected between the first node and the output terminal of the second differential transistor pair.   2. The circuit according to claim 1, wherein said circuit functions as a band-pass filter when said first node is connected to a first supply voltage source and said third node is connected to an input voltage terminal for receiving an input voltage signal.   3. The circuit of claim 2, wherein the first supply voltage is a ground potential point voltage.   The first current source has a first current value, the second current source has a second current value equal to twice the first current value, and the third current source has A third current value, the fourth current source has a fourth current value equal to twice the third current value, and the output voltage signal includes the first current value and the first current value. 3. The circuit according to claim 2, wherein the circuit is tuned to a selected frequency of the input voltage signal by a change in current value of 3.   2. The circuit according to claim 1, wherein said circuit functions as a band elimination filter when said first node is connected to an input voltage terminal for receiving an input voltage signal and said third node is connected to a first supply voltage supply source.   6. The circuit of claim 5, wherein the first supply voltage is a ground potential point voltage.   The first current source has a first current value, the second current source has a second current value equal to twice the first current value, and the third current source has A third current value, the fourth current source has a fourth current value equal to twice the third current value, and the output voltage signal includes the first current value and the first current value. 6. The circuit according to claim 5, wherein the circuit is tuned to a selected frequency of the input voltage signal by a change in current value of 3. The first differential transistor pair is
A first transistor having a first current handling terminal connected to a second supply voltage supply source, a second current handling terminal connected to the second current source, and a control terminal connected to the first node When,
A second transistor having a first current handling terminal connected to the first current source, a second current handling terminal connected to the second current source, and a control terminal connected to the second node; The circuit of claim 1 comprising:   9. The circuit of claim 8, wherein the first transistor and the second transistor include bipolar NPN transistors.   9. The circuit of claim 8, wherein the second supply voltage is a power supply voltage.   9. The circuit according to claim 8, wherein the second current handling terminal of each of the first transistor and the second transistor is connected to the second current source via a variable resistance element.   The variable resistance element is a MOS transistor, that is, a first current handling terminal connected to the second current handling terminal of each of the first and second transistors, and a second current connected to the second current source. 12. The circuit of claim 11 including a MOS transistor having a handling terminal and a control terminal for receiving a control signal for biasing the MOS transistor to a triode element region. The second current handling terminals of the first and second transistors are connected to the second current handling terminals respectively via a bank of switch pairs connected to the second current handling terminals and controlled by a control signal and having variable on-resistance. The circuit of claim 8 connected to a current source.   The bank of switch pairs having the variable on-resistance is between a plurality of MOS transistor pairs, that is, between the second current handling terminal of the first transistor and the second current handling terminal of the second transistor. 14. The circuit of claim 13, further comprising a plurality of transistor pairs each comprising one or more transistors connected in series to receive the control signal. A first plurality of capacitors each connected in series between the third node and the output terminal of the first differential transistor pair, and a corresponding first plurality of switches connected in series with the capacitors When,
A plurality of second capacitors each connected in series between the first node and the output terminal of the second differential transistor pair, and a corresponding second plurality of switches connected in series with the capacitors Including
The first and second switches are selectively connected to one or more of the first capacitors by a plurality of control signals corresponding to the first and second switches, and the second plurality of capacitors. 15. The circuit of claim 14, wherein the circuit is controlled to selectively connect one or more of the second capacitor and the second capacitor.   Selectively turning on one or more of the plurality of MOS transistor pairs, and setting one or more of the first plurality of capacitors and the second plurality of capacitors to the first capacitor and the second 16. The circuit of claim 15, wherein coarse tuning is achieved by selectively connecting in parallel with each one of the capacitors.   15. The circuit of claim 14, wherein fine tuning is achieved by adjusting a voltage value of the control signal that controls each one of the MOS transistor pairs. The second differential transistor pair is
A first current handling terminal connected to a second supply voltage source; a second current handling terminal connected to the fourth current source; and a control terminal connected to the output terminal of the first differential transistor pair. A first transistor having:
A second transistor having a first current handling terminal connected to the third current source, a second current handling terminal connected to the fourth current source, and a control terminal connected to the second node; The circuit of claim 1 comprising:   The circuit of claim 18, wherein the first transistor and the second transistor comprise bipolar NPN transistors.   The circuit of claim 18, wherein the second supply voltage is a power supply voltage.   19. The circuit according to claim 18, wherein the second current handling terminal of each of the first transistor and the second transistor is connected to the fourth current source via a variable resistance element.   The variable resistance element is a MOS transistor, that is, a first current handling terminal connected to the second current handling terminal of each of the first and second transistors, and a second current connected to the fourth current source. 24. The circuit of claim 21 including a MOS transistor having a handling terminal and a control terminal for receiving a control signal for biasing the MOS transistor to a triode element region.   The fourth current handling terminals of the first and second transistors are connected to the second current handling terminals via a bank of switch pairs each connected to the second current handling terminal and controlled by a control signal and having a variable on-resistance. The circuit of claim 18 connected to a current source.   The bank of switch pairs having the variable on-resistance is between a plurality of MOS transistor pairs, that is, between the second current handling terminal of the first transistor and the second current handling terminal of the second transistor. 24. The circuit of claim 23, comprising a plurality of transistor pairs each comprising one or more transistors connected in series to receive the control signal. A first plurality of capacitors each connected in series between the third node and the output terminal of the first differential transistor pair, and a corresponding first plurality of switches connected in series with the capacitors When,
A plurality of second capacitors each connected in series between the first node and the output terminal of the second differential transistor pair, and a corresponding second plurality of switches connected in series with the capacitors Including
The first and second switches are selectively connected to one or more of the first capacitors by a plurality of control signals corresponding to the first and second switches, and the second plurality of capacitors. 25. The circuit of claim 24, wherein the circuit is controlled to selectively connect one or more of the second capacitor and the second capacitor.   Selectively turning on one or more of the plurality of MOS transistor pairs, and setting one or more of the first plurality of capacitors and the second plurality of capacitors to the first capacitor and the second 26. The circuit of claim 25, wherein coarse tuning is achieved by selectively connecting in parallel with each one of the capacitors.   25. The circuit of claim 24, wherein fine tuning is achieved by adjusting a voltage value of the control signal that controls each one of the MOS transistor pairs. A first plurality of capacitors each connected in series between the third node and the output terminal of the first differential transistor pair, and a corresponding first plurality of switches connected in series with the capacitors When,
A plurality of second capacitors each connected in series between the first node and the output terminal of the second differential transistor pair, and a corresponding second plurality of switches connected in series with the capacitors Including
The first and second switches are selectively connected to one or more of the first capacitors by a plurality of control signals corresponding to the first and second switches, and the second plurality of capacitors. The circuit according to claim 1, wherein one or more of the first and second capacitors are controlled to be selectively connected to the second capacitor. The circuit of claim 1, further comprising a gain of 1 amplifier having an input terminal connected to the output terminal of the second differential transistor pair and an output terminal connected to the second node. A first input terminal connected to the first node; a second input terminal connected to the second node; and an output terminal connected to the first current source, biased by the second current source. 1 pair of differential bipolar transistors, each having a common node with each emitter terminal connected to the second current source to a first plurality of MOS transistor pairs, ie, the second current source. A first differential bipolar transistor pair connected through a first plurality of MOS transistor pairs controlled by a control signal;
A first capacitor connected between a third node and the output terminal of the first differential bipolar transistor pair;
A first input terminal connected to the output terminal of the first differential bipolar transistor pair, a second input terminal connected to the second node, and a third current source for supplying an output voltage signal And a second differential bipolar transistor pair biased by a fourth current source, each emitter terminal being connected to the fourth current source as a second plurality of MOS transistor pairs, that is, the fourth current. A second differential bipolar transistor pair each having a common node connected to the source and connected through a second plurality of MOS transistors each controlled by a control signal;
A variable frequency filter circuit including a second capacitor connected between the first node and the output terminal of the second differential bipolar transistor pair;
A variable frequency filter circuit that achieves coarse tuning by selectively turning on the one or more MOS transistor pairs of the first and second MOS transistor pairs. 31. The circuit of claim 30, wherein the circuit functions as a band pass filter when the first node is connected to a first supply voltage source and the third node is connected to an input voltage terminal for receiving an input voltage signal.   32. The circuit of claim 31, wherein the first supply voltage is a ground potential point voltage.   31. The circuit according to claim 30, wherein the circuit functions as a band elimination filter when the first node is connected to an input voltage terminal for receiving an input voltage signal and the third node is connected to a first supply voltage source.   34. The circuit of claim 33, wherein the first supply voltage is a ground potential point voltage. The first differential transistor pair is
A first current handling terminal connected to a second supply voltage source; a second current handling terminal connected to the second current source through the first plurality of transistor pairs; and a first node connected to the first node. A first bipolar NPN transistor having a control terminal;
A first current handling terminal connected to the first current source; a second current handling terminal connected to the second current source through the first plurality of transistor pairs; and a second node connected to the second current source. 32. The circuit of claim 30, including a second bipolar NPN transistor having a control terminal.   36. The circuit of claim 35, wherein the second supply voltage is a power supply voltage.   The first plurality of transistor pairs includes a plurality of MOS transistor pairs connected in parallel between the second current handling terminals of each of the first bipolar NPN transistor and the second bipolar NPN transistor, and Each of the plurality of MOS transistor pairs includes two or more MOS transistors connected in series and receives a common control signal, and a node between each of the plurality of MOS transistor pairs is connected to the second current source. 36. The circuit of claim 35. The second differential transistor pair is
A first current handling terminal connected to a second supply voltage source; a second current handling terminal connected to the fourth current source through the second plurality of transistor pairs; and the first differential transistor pair. A first bipolar NPN transistor having a control terminal connected to the output terminal of
A first current handling terminal connected to the third current source; a second current handling terminal connected to the fourth current source through the second plurality of transistor pairs; and a second node connected to the second node. 31. The circuit of claim 30, including a control terminal.   39. The circuit of claim 38, wherein the second supply voltage is a power supply voltage.   The second plurality of transistor pairs includes a plurality of MOS transistor pairs connected in parallel between the second current handling terminals of each of the first bipolar NPN transistor and the second bipolar NPN transistor, and Each of the plurality of MOS transistor pairs receives a common control signal including two or more MOS transistors connected in series with each other, and a node between each of the plurality of MOS transistor pairs is connected to the fourth current source. 40. The circuit of claim 38.

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