JP2012253659A - Communication device, information processing device and data transmission method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication device capable of guaranteeing a time of data transmitted to a plurality of peripheral circuits, without performing complicated priority control.SOLUTION: A communication device 100 includes: a transmission register 35 in which transmission data is stored; transmission destination specification means 34 for specifying one transmission destination from a plurality of transmission destinations; transmission control means 33 for serially transmitting the transmission data to the transmission destination; transmission data buffers 36, 39 for storing transmission data waiting for transmission; transmission data control means 40 for overwriting the transmission data stored in the transmission register on the transmission data stored in the transmission data buffers when the transmission destinations of the transmission data stored in the transmission register and the transmission data stored in the transmission data buffers are identical.

Description

  The present invention relates to a communication apparatus that transmits data to a transmission destination, and more particularly to a communication apparatus that switches a transmission destination by chip selection.

  Data may be transmitted and received by serial communication between a chip in the microcomputer or a microcomputer and a peripheral IC. In such serial communication, when the transmission side and the reception side have a one-to-many relationship, a chip selection function is generally mounted on the transmission side (hereinafter simply referred to as a communication device). In addition, since a data transmission request to each peripheral IC is irregularly generated in the microcomputer, a data transmission request to another IC may be generated during data transmission to one IC. A buffer is provided.

  Several methods are known as to how transmission control is performed when a plurality of transmission data is accumulated in the transmission buffer. For example, the transmission order of transmission data can be managed by a FIFO (First In First Out) method. However, in FIFO, when a lot of data is already stored in the transmission buffer, it is difficult to guarantee the time until transmission data newly requested by the microcomputer is transmitted.

  In addition, for example, a method in which a communication device manages priority is known. In this case, the communication device requires priority management such as setting a priority for each IC or dynamically determining the priority by software or the like. However, if priority is set for each IC, it is difficult to guarantee the time of transmission data transmitted to an IC with a low priority. Further, the method of dynamically setting the priority by software or the like has a problem that the processing becomes complicated (see, for example, Patent Document 1). Japanese Patent Application Laid-Open No. 2004-228688 describes a register writing unit that writes data to a plurality of registers, and determines the priority of data writing based on the generated internal clock signal when the timing of writing data to the plurality of registers competes. A writing unit is disclosed.

JP 2007-140215 A

  However, in the technique described in Patent Document 1, since the priority is determined by using the clock frequency or the like, the process is still complicated. In addition, there is a problem that it is not possible to cope with the case where the number of ICs increases.

  In view of the above problems, an object of the present invention is to provide a communication device capable of guaranteeing the time of data transmitted to a plurality of peripheral circuits without performing complicated priority control.

  In view of the above problems, the present invention provides a transmission register to which transmission data is written, a transmission destination designating unit that designates one transmission destination from a plurality of transmission destinations, a transmission control unit that serially transmits transmission data to the transmission destination, If the transmission data buffer for storing transmission data waiting to be transmitted and the transmission data written in the transmission register and the transmission destination of the transmission data stored in the transmission data buffer are the same, the transmission data buffer stores the transmission data. And a transmission data control means for overwriting the transmission data with the transmission data written in the transmission register.

  It is possible to provide a communication apparatus capable of guaranteeing the time of data transmitted to a plurality of peripheral circuits without performing complicated priority control.

It is an example of the figure which illustrates typically the procedure in which the communication apparatus of this embodiment transmits data. It is an example of the schematic block diagram of ECU. It is a figure which shows an example of the block diagram of a conventional communication apparatus, and an example of a register format. It is a figure which shows an example of the block diagram of the communication apparatus of this embodiment. It is a figure which shows an example of the register format of this embodiment. It is an example of the timing chart figure of the conventional communication apparatus. It is an example of the sequence diagram of the conventional communication apparatus. It is an example of the timing chart figure of a communication apparatus. It is an example of the sequence diagram of a communication apparatus. It is an example of the flowchart figure which shows the process sequence of a transmission data control part. It is an example of the figure explaining the example of a transition of a priority. It is an example of the figure explaining the example of a transition of a priority.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
FIG. 1 is an example of a diagram schematically illustrating a procedure in which the communication apparatus according to the present embodiment transmits transmission data.
As shown in FIG. 1A, transmission data 1 to 3 are sequentially written in the transmission data buffer. In the figure, it is assumed that transmission data under the transmission data buffer is written earlier. A priority can be set in the transmission data buffer.

If the next transmission data buffer is empty, the communication device writes the transmission data in the next transmission data buffer. When the priorities are the same, the transmission data to be written is determined by FIFO (First In First Out). For this reason, the transmission data 1 of the next transmission data buffer is written in the register for transmission and transmitted to the transmission destination.
As shown in FIG. 1B, when there is no transmission data 1 in the next transmission data buffer, the communication apparatus writes transmission data 2 that is next to transmission data 1 to the next transmission data buffer. Here, it is assumed that the transmission data 3a is written in the transmission register in a state where the transmission data 2 exists in the next transmission data buffer. Transmission data 3 and transmission data 3a are transmission data having the same transmission destination.
As shown in FIG. 1C, the communication device sets the priority of the transmission data written earlier when the transmission data of the same destination as the transmission data of the transmission register exists in the transmission data buffer or the next transmission data buffer. Read is incremented by 1 to replace the priority of transmission data written later. That is, when the priority of the transmission data 3 is “0”, the priority of the transmission data 3a is “1”. This is because transmission data transmitted to the same transmission destination in a short time is considered to have high priority.
As shown in FIG. 1D, the communication apparatus erases the transmission data 3 from the transmission data buffer and writes the transmission data 3a. Thereby, transmission data transmitted later can be preferentially transmitted.
As shown in FIG. 1E, the communication device compares the priority of the transmission data in the next transmission data buffer and the transmission data in the transmission data buffer. That is, the priority 0 of the transmission data 2 is compared with the priority 1 of the transmission data 3a. In this case, the higher priority should be given priority.
As illustrated in FIG. 1F, when the transmission data in the transmission data buffer has a higher priority, the communication apparatus switches the transmission data in the next transmission data buffer and the transmission data in the transmission data buffer. That is, the transmission data 2 and the transmission data 3a are exchanged.

  In this way, when a transmission request for transmission data of the same transmission destination frequently occurs, the communication device increases the priority of the transmission data. In addition, transmission data having the same transmission destination existing in the transmission data buffer or the next transmission data buffer is overwritten with transmission data written later. As a result, the transmission data of the same transmission destination becomes one, so that it is easy to guarantee time.

  In addition, since the priority of transmission data in the transmission data buffer is adjusted according to the frequency of transmission, even if the transmission data is written later, the transmission data of the transmission destination that is frequently written has a higher priority and is sure. Guaranteed on time.

  In addition, since there is only one transmission data of the same transmission destination in the transmission data buffer, the number of registers in the transmission data buffer may be the number of transmission destinations (the number of chip select). For this reason, the capacity of the transmission data buffer can be reduced. In the conventional technique, since it is common to prepare two or more registers for each transmission destination in consideration of the maximum communication load, in this embodiment, the capacity of the transmission data buffer can be reduced to about half or less. it can.

  In addition, since there is only one transmission data of the same transmission destination, priority management between transmission data becomes easy. For this reason, complicated priority management considering the maximum communication load is not required. Further, since only one register is required for one transmission destination, it is easy to increase the transmission destination even when a large transmission data buffer cannot be provided.

[Configuration example]
FIG. 2 shows an example of a schematic configuration diagram of the ECU. The ECU (electronic control unit) 300 includes a microcomputer 200 and peripheral circuits. The peripheral circuit is, for example, an IC 101 (hereinafter referred to as IC 1 to 4 when distinguished), and provides an additional function to the microcomputer 200. The communication device 100 according to the present embodiment communicates with the ICs 1 to 4.

  The microcomputer 200 includes a CPU 11, a RAM 12, a ROM 13, an INTC 14, a DMAC 15, and a bus controller 16 that are connected to the main bus 19. The microcomputer 200 includes a Timer (hereinafter referred to as Timer 1 and Timer 0 when distinguished) 17, an ADC 18, and a communication device 100 connected to the peripheral bus 20. The CPU 11 is a single core or multi-core CPU. Alternatively, a hardware multi-thread (HMT) type CPU may be used. The CPU 11 executes the program using the RAM 12 as a working memory. The ROM 13 is a non-volatile memory such as a flash memory, and stores programs executed by the CPU 11 and static data. The program is a device driver, an OS, an application unique to the microcomputer 200, and the like. The number of applications is not limited to one. For example, in the ECU 300 with integrated functions, a plurality of applications with different control targets may be stored.

  The DMAC 15 transmits the data in the RAM 12 and the ROM 13 to the Timer 17, the ADC 18, the communication device 100, or a CAN controller (not shown) according to an instruction from the CPU 11. The DMAC 15 receives an instruction from the CPU 11 interrupted via the INTC 14 from these circuits, receives data from the Timer 17, the ADC 18, and the communication device 100, and writes it in the RAM 12.

  The INTC 14 arbitrates an interrupt request input from the Timer 17, the ADC 18, or the communication device 100 via the IRQ or other interrupt terminal based on the priority order of the peripheral devices and notifies the CPU 11 of the arbitration request. As a result, the CPU 11 executes a process determined according to the interrupted peripheral device.

  The bus controller 16 absorbs the difference in the number of buses and the frequency between the main bus 19 and the peripheral bus 20 and transfers data to each other.

  A peripheral circuit having a relatively slow execution speed is connected to the peripheral bus 20, and the Timer 17 notifies the CPU 11 by interrupting the CPU 11 via the INTC 14 when the value set by the CPU 11 is counted, for example. By the notification, the CPU 11 can execute a predetermined program periodically, for example.

  The communication device 100 is connected to each of the ICs 1 to 4. Specifically, they are connected to the ICs 1 to 4 by clock signal lines, data transmission lines, data reception lines, and C / S lines, respectively. The communication apparatus 100 and one multiplexer may be connected, and the ICs 1 to 4 may be connected from the multiplexer.

  IC1-4 are one of the resources which the microcomputer 200 uses. These are arranged in order to provide functions required by the microcomputer 200 when the resources (ADC and Timer) in the microcomputer 200 are insufficient, or functions that the microcomputer 200 does not have. IC1-4 are ADC, DAC, another microcomputer etc., for example. And the communication apparatus 100 enables the microcomputer 200 to communicate with IC1-4 selectively. For example, this is effective when the microcomputer 200 does not have a sufficient number of I / O ports. If IC1 is an ADC, when requesting A / D conversion from IC1, microcomputer 200 designates IC1 as a transmission destination and writes transmission data to be converted into communication device 100. For example, if the IC 2 is another microcomputer, the microcomputer 200 designates the other microcomputer as a transmission destination and writes transmission data to be transmitted to the communication device 100.

  Conversely, transmission data transmitted from the ICs 1 to 4 to the communication device 100 is notified by the communication device 100 interrupting the CPU 11 via the INTC 14. When the CPU 11 controls the DMAC 15, the transmission data of the ICs 1 to 4 is written into the RAM 12.

[Configuration example of communication device]
FIG. 3 shows an example of a configuration diagram (FIG. 3A) and a register format (FIG. 3B) of a conventional communication device 100 for comparison, and FIG. 4 shows a configuration diagram of the communication device 100 of this embodiment. FIG. 5 shows an example of the register format of this embodiment.

  Comparing FIG. 3A and FIG. 4, the communication apparatus 100 of this embodiment is different in that it includes a next transmission data buffer 39 and a transmission data control unit 40. Further, by connecting the transmission data buffer 36 and the transmission data control unit 40, it is possible to control transmission of transmission data with a guaranteed time.

<Register format>
First, the register format will be described.
The register format of the transmission register 35 includes a transmission destination chip select designation bit and transmission data. The register format of the transmission register 35 has not been changed conventionally.
The register format of the reception register 38 includes a reception chip select number bit and reception data. The register format of the reception register 38 has not been changed conventionally.
The register format of the transmission data buffer 36 includes a priority bit, a transmission destination chip select designation bit, and transmission data. A priority bit is added to the register format of the transmission data buffer 36 of the present embodiment.
The register format of the next transmission data buffer 39 is the same as the register format of the transmission data buffer 36.

  Further, for example, the conventional transmission data buffer 36 requires 30 stages even if there are only four transmission destinations, whereas the transmission data buffer 36 of the present embodiment can be provided with a minimum of four stages. This is because in the transmission data having the same transmission destination, the priority of the past transmission data is reflected in the newer transmission data, and the past transmission data is overwritten.

Information set in each register is as follows.
-Destination chip select designation bit: Information for selecting IC1-4-Transmission data: Data transmitted to IC1-4 (data includes command)
Priority bit: Priority information of transmission data (assuming that the higher the value, the higher the priority)
・ Receiving chip select number bit: Identification information of the IC in which transmission data is written to the reception register 38 among the ICs 1 to 4. ・ Reception data: data received from the ICs 1 to 4. Further, a circuit for setting transmission data or the like in each register is as follows. It becomes as follows.
-Transmission register: CPU11
Receive registers: IC1 to IC4 (serial communication control unit)
Transmission data buffer: transmission data control unit 40
Next transmission data buffer: transmission data control unit 40
-Transmission / reception control register: CPU11
<Each block of communication device>
In the clock control register 31, clock control information (for example, a frequency division ratio) for controlling the clock frequency is set. For example, the microcomputer 200 sets the clock control information in the clock control register 31 by initial setting immediately after the power is turned on. The serial clock control unit 32 generates a clock frequency using, for example, a PLL and a frequency divider based on the clock control information. The clock frequency is a signal for synchronizing with the ICs 1 to 4 and is supplied to the ICs 1 to 4 via the clock signal line 41. The serial clock control unit 32 supplies a clock frequency to the serial communication control unit 33 and peripheral devices in the microcomputer 200.

  The serial communication control unit 33 includes a serial output signal line 42 and a serial input signal line 43. The serial output signal line 42 and the serial input signal line 43 are both connected to the ICs 1 to 4. The serial output signal line 42 is a signal line for transmitting transmission data from the communication device 100 to any one of the ICs 1 to 4, and the serial input signal line 43 is transmitted from any one of the ICs 1 to 4 by the communication device 100. Is a signal line for receiving the signal. The serial communication control unit 33 is connected to the next transmission data buffer 39, the transmission / reception control register 37, and the reception register 38.

  The serial communication control unit 33 has a data buffer (not shown) (for transmission and reception), and transmits the transmission data of the next transmission data buffer 39 after moving to the data buffer. The serial communication control unit 33 accumulates the transmission data received from the ICs 1 to 4 in the data buffer, and moves to the reception register 38 when one transmission data is received. The serial communication control unit 33 receives the reception data from the transmission destination ICs 1 to 4 when transmitting the transmission data. The received data is data for echoing transmission data and notifying the reception state.

  The chip select control unit 34 has as many chip select signal lines as the number of channels. That is, each chip select signal line 44 is connected to one of the ICs 1 to 4. The chip select control unit 34 reads the transmission destination chip select designation bit of the next transmission data buffer 39, and asserts the chip selection signal line 44 connected to any one of the ICs 1 to 4 based on the transmission destination chip select designation bit (negative). Any of logical positive logic).

  In the transmission register 35, transmission data to be transmitted is written. When the CPU 11 of the microcomputer 200 executes a command to transmit transmission data to any one of the ICs 1 to 4 by executing a program, the transmission data is written in the transmission register 35. For the program, the destination chip select designation bit and the transmission data are designated by an argument or the like.

  The transmission data control unit 40 is connected to the transmission register 35, the transmission data buffer 36, and the next transmission data buffer 39. The transmission data control unit 40 assigns a priority bit to data for transmission to which no priority bit is assigned in the transmission data buffer 36. The initial value of the priority bit is zero. Further, the transmission data control unit 40 detects transmission data having the same transmission destination in the transmission data buffer 36, rewrites the priority bit, erases old transmission data among transmission data having the same transmission destination, and transmits the next transmission data buffer 39 and the transmission data. The priority bits of the buffer 36 are compared, transmission data is exchanged based on the comparison result, and the like. Detailed control will be described later.

  The transmission data buffer 36 of this embodiment has at least as many registers as the number of transmission destinations. There may be more registers than the number of destinations. By mounting more registers than the number of transmission destinations, when the CPU 11 writes transmission data of the same transmission destination to the transmission register 35 in a short time, a plurality of transmission data can be stored in the transmission data buffer 36. The state can be reduced.

  The transmission data control unit 40 reads from the transmission data buffer 36 preferentially from transmission data having a high priority bit, but reads from old transmission data if the priority bits are the same. In this sense, the transmission data buffer 36 has a FIFO type property.

  Note that the conventional transmission data buffer 36 has a write pointer indicating a write start address and a read pointer indicating a read start address. The write pointer indicates the address of the register next to the register in which the transmission data was last written in the transmission data buffer 36, and the read pointer is the register next to the register in which the transmission data read by the serial communication control unit 33 is stored. Indicates the address. When the transmission data of the transmission data buffer 36 is transmitted by the serial communication control unit 33, the write pointer and the read pointer indicate the same register address. Therefore, when the read pointer indicates an address smaller than the write pointer, the transmission data to be transmitted by the serial communication control unit 33 is stored in the transmission data buffer 36.

  In principle, the next transmission data buffer 39 is a buffer in which transmission data to be transmitted next by the serial communication control unit 33 is stored. The reason for writing in principle is that the data may be moved from the next transmission data buffer 39 to the transmission data buffer 36 depending on the priority before being taken into the serial communication control unit 33. The transmission data once transmitted to the serial communication control unit 33 never returns to the next transmission data buffer 39.

  The transmission / reception control register 37 is a register for the CPU 11 of the microcomputer 200 to set transmission permission or reception permission. For example, the CPU 11 sets transmission permission in the transmission / reception control register 37 when transmission data is completely written in the transmission register 35, and sets reception permission in the transmission / reception control register 37 when a transmission / reception completion interrupt is received.

  The reception register 38 is connected to the serial communication control unit 33 and the chip select control unit 34. In the reception register 38, the reception chip select number and the reception data received by the serial communication control unit 33 are written according to the channel information asserted by the chip select control unit 34. When the serial communication control unit 33 interrupts transmission / reception completion to the CPU 11, the CPU 11 reads received data from the reception register 38.

[About transmission data]
As described with reference to FIG. 1, the communication apparatus 100 according to the present embodiment transmits only subsequent transmission data among transmission data having the same transmission destination. For this reason, transmission data is limited to an absolute value, not a relative value. For example, since the relative value is transmitted for the transmission data requesting the inversion of the state, not the state itself (for example, transmission data for determining opening / closing every time “1” is transmitted), an odd number of transmission data of the same transmission destination If it is missing, the control and state will be reversed.

  On the other hand, since transmission data including the numerical value itself such as High or Low, on or off, open or closed is transmitted as an absolute value, one or more of the transmission data of the same transmission destination is missing. However, since the last absolute value is valid, the control and state as instructed by the CPU 11 can be obtained. Therefore, the CPU 11 of this embodiment is designed to transmit such absolute value transmission data.

[Conventional transmission example]
FIG. 6 shows an example of a timing chart of a conventional communication apparatus 100 described for comparison, and FIG. 7 shows an example of a sequence diagram.
s1: The CPU 11 writes the transmission data 1 to the transmission register 35.
s2: The transmission data buffer 36 detects writing to the transmission register 35 with a flag or the like, and stores the transmission data 1 in the register. The transmission data buffer 36 updates the write pointer to indicate the register next to the newly stored register. As a result, the write pointer and the read pointer do not match.
s3: When the transmission data 1 is written in the transmission register 35, the CPU 11 sets transmission permission in the transmission / reception control register 37.
s4: The serial communication control unit 33 detects a mismatch between the write pointer and the read pointer, and reads the transmission data 1 from the register indicated by the read pointer of the transmission data buffer 36.
s5: Since the transmission permission is set in the transmission / reception control register 37, the serial communication control unit 33 starts transmission of the transmission data 1. The serial communication control unit 33 updates the read pointer to indicate the register next to the read register. As a result, the write pointer matches the read pointer.
s6: While the serial communication control unit 33 is transmitting the transmission data 1, the CPU 11 writes the transmission data 2 in the transmission register 35.
s7: The transmission data buffer 36 detects writing to the transmission register 35 with a flag or the like and stores it in the register.
s8: While the serial communication control unit 33 is transmitting the transmission data 1, the CPU 11 writes the transmission data 3 in the transmission register 35.
s9: The transmission data buffer 36 detects writing to the transmission register 35 with a flag or the like and stores it in the register. The write pointer is also updated in s6 to s7.
s10: When the transmission of the transmission data 1 is completed, the serial communication control unit 33 writes the reception data in the reception register 38.
s11: When the transmission of the transmission data 1 is completed, the serial communication control unit 33 issues a transmission / reception completion interrupt to the CPU 11.
s12: The serial communication control unit 33 detects a mismatch between the write pointer and the read pointer, and reads the transmission data 2 from the register indicated by the read pointer of the transmission data buffer 36.
s13: Since the transmission permission is set in the transmission / reception control register 37, the serial communication control unit 33 starts transmission of the transmission data 2. The serial communication control unit 33 updates the read pointer to indicate the register next to the read register. At this next point, the write pointer and the read pointer remain inconsistent.
s14: When the transmission of the transmission data 2 is completed, the serial communication control unit 33 writes the reception data in the reception register 38.
s15: When the transmission of the transmission data 2 is completed, the serial communication control unit 33 issues a transmission / reception completion interrupt to the CPU 11.
s16: The serial communication control unit 33 detects a mismatch between the write pointer and the read pointer, and reads the transmission data 3 from the register indicated by the read pointer of the transmission data buffer 36.
s17: Since the transmission permission is set in the transmission / reception control register 37, the serial communication control unit 33 starts transmission of the transmission data 3. The serial communication control unit 33 updates the read pointer to indicate the register next to the read register. As a result, the write pointer matches the read pointer.
s18: When the transmission of the transmission data 3 is completed, the serial communication control unit 33 writes the reception data in the reception register 38.
s19: When the transmission of the transmission data 3 is completed, the serial communication control unit 33 issues a transmission / reception completion interrupt to the CPU 11.

[Transmission example of this embodiment]
FIG. 8 shows an example of a timing chart of the communication apparatus 100 of the present embodiment, and FIG. 9 shows an example of a sequence diagram.
s21: The CPU 11 writes the transmission data 1 in the transmission register 35.
s22: The transmission data control unit 40 detects writing to the transmission register 35 with a flag or the like, and reads the transmission data 1 from the transmission register 35.
s23: The transmission data control unit 40 reads the transmission destination chip select designation bit of each transmission data from the transmission data buffer 36. At this time, there is no transmission data in the transmission data buffer 36 yet.
s24: The transmission data control unit 40 reads the transmission destination chip select designation bit of the transmission data stored in the next transmission data buffer 39. At this time, there is no transmission data in the next transmission data buffer 39 yet.
s25: The transmission data control unit 40 determines whether the transmission data 1 read from the transmission register 35 and the transmission data having the same transmission destination chip select designation bit exist in the transmission data buffer 36 or the next transmission data buffer 39.
s26: Here, since transmission data is not stored in the transmission data buffer 36 and the next transmission data buffer 39, the transmission data control unit 40 writes the transmission data 1 in the next transmission data buffer 39.
s27: The CPU 11 writes the transmission data 2 to the transmission register 35.
s28: The CPU 11 writes the transmission data 3 to the transmission register 35.
s29: The transmission data control unit 40 detects writing to the transmission register 35 with a flag or the like, and reads the transmission data 2 from the transmission register 35.
s30: The transmission data control unit 40 reads the transmission destination chip select designation bit of each transmission data from the transmission data buffer 36. There is no transmission data in the transmission data buffer 36 yet.
s31: The transmission data control unit 40 reads the transmission destination chip select designation bit of the transmission data stored in the next transmission data buffer 39. Since the transmission data 1 is stored in the next transmission data buffer 39, the transmission destination chip select designation bit of the transmission data 1 is read.
s32: The transmission data control unit 40 determines whether or not transmission data 2 having the same transmission destination chip select designation bit as the transmission data 2 read from the transmission register 35 exists in the transmission data buffer 36 or the next transmission data buffer 39.
s33: Since transmission data 1 and transmission data 2 do not match the transmission destination chip select designation bit, the transmission data control unit 40 writes transmission data 2 in the transmission data buffer 36.
s34: The transmission data control unit 40 detects writing to the transmission register 35 with a flag or the like, and reads the transmission data 3 from the transmission register 35.
s35: The transmission data control unit 40 reads the transmission destination chip select designation bit of each transmission data from the transmission data buffer 36. The transmission destination chip select designation bit of the transmission data 2 is read from the transmission data buffer 36.
s36: The transmission data control unit 40 reads the transmission destination chip select designation bit of the transmission data stored in the next transmission data buffer 39. Since the transmission data 1 is stored in the next transmission data buffer 39, the transmission destination chip select designation bit of the transmission data 1 is read.
s37: The transmission data control unit 40 determines whether or not transmission data 3 having the same transmission destination chip select designation bit as the transmission data 3 read from the transmission register 35 exists in the transmission data buffer 36 or the next transmission data buffer 39.
s38: Since transmission data 3 and transmission data 1 or transmission data 2 do not match the destination chip select designation bit, transmission data control unit 40 writes transmission data 3 in transmission data buffer 36.
s39: The CPU 11 sets transmission permission in the transmission / reception control register 37.
s40: The serial communication control unit 33 detects that there is transmission data in the next transmission data buffer 39 using a flag or the like, and reads the transmission data 1 from the next transmission data buffer 36. The lower 16 bits of the transmission data in the next transmission data buffer 39 move to the serial communication control unit 33. Further, the upper 4 bits of the transmission data in the next transmission data buffer 39 move to the chip select control unit 34.
s41: Since transmission permission is set in the transmission / reception control register 37, the serial communication control unit 33 starts transmission of the transmission data 1.
s42: The transmission data control unit 40 detects that the transmission data in the next transmission data buffer 39 has moved to the serial communication control unit 33, reads the transmission data 2 from the transmission data buffer 36, and writes it in the next transmission data buffer 39. . The transmission data 2 is erased from the transmission data buffer 36.
s43: While the serial communication control unit 33 is transmitting the transmission data 1, the CPU 11 writes the transmission data 3a in the transmission register 35. Transmission data 3a and transmission data 3 have the same transmission destination.
s44: The transmission data control unit 40 detects writing to the transmission register 35 with a flag or the like, and reads the transmission data 3a from the transmission register 35.
s45: The transmission data control unit 40 reads the transmission destination chip select designation bit of each transmission data from the transmission data buffer 36. Here, the destination chip select designation bit of the transmission data 3 is read.
s46: The transmission data control unit 40 reads the transmission destination chip select designation bit of the transmission data 2 stored in the next transmission data buffer 39. Here, the transmission destination chip select designation bit of transmission data 2 is read.
s47: The transmission data control unit 40 determines whether or not the transmission data 3a read from the transmission register 35 and transmission data having the same transmission destination chip select designation bit exist in the transmission data buffer 36 or the next transmission data buffer 39.
s48: Since the transmission data 3a and the transmission data 3 have the same destination chip select designation bit, the transmission data control unit 40 reads the priority bit of the transmission data 3 in the transmission data buffer 36.
s49: The transmission data control unit 40 increments the read priority bit by 1.
s50: The transmission data control unit 40 sets the priority bit incremented by 1 as the priority bit of the transmission data 3a.
s51: The transmission data control unit 40 replaces the transmission data 3 in the transmission data buffer 36 with the transmission data 3a.
s52: The transmission data control unit 40 reads the priority bit of the transmission data 2 from the next transmission data buffer 39.
s53: The transmission data control unit 40 reads the priority bit of the transmission data 3a from the transmission data buffer 36.
s54: The transmission data control unit 40 compares the priority bits of the transmission data 3a and the transmission data 2.
s55: Since the transmission data 3a has a larger priority bit, the transmission data control unit 40 saves the transmission data 2 of the next transmission data buffer 39 in the transmission data buffer 36.
s56: The transmission data 3a of the transmission data buffer 36 is written into the next transmission data buffer 39 (transmission data 2 and transmission data 3a are interchanged).
s57: When the transmission of the transmission data 1 is completed, the serial communication control unit 33 writes the reception data in the reception register 38.
s58: When the transmission of the transmission data 1 is completed, the serial communication control unit 33 issues a transmission / reception completion interrupt to the CPU 11.
s59: The serial communication control unit 33 detects that there is transmission data in the next transmission data buffer 39 by a flag or the like, and reads transmission data 3a because transmission permission is set in the transmission / reception control register 37.
s60: The serial communication control unit 33 starts transmission of the transmission data 3a. As a result, the lower 16 bits of the transmission data 3 a of the next transmission data buffer 39 are moved to the serial communication control unit 33. Further, the upper 4 bits of the transmission data 3 a in the next transmission data buffer 39 are moved to the chip select control unit 34.

  Thereafter, the transmission data control unit 40 detects that the transmission data 3 a of the next transmission data buffer 39 has moved to the serial communication control unit 33, reads the transmission data 2 from the transmission data buffer 36, and receives the next transmission data buffer 39. Write to. The transmission data 2 is transmitted by the serial communication control unit 33 when the serial communication control unit 33 transmits the transmission data 3a.

  As described above, the communication apparatus 100 according to the present embodiment can sort the transmission order according to the priority of the transmission data and transmit the data in the order of high priority. Moreover, the priority can be made higher as data is transmitted more frequently.

<Processing procedure of transmission data control unit>
FIG. 10 is an example of a flowchart illustrating a processing procedure of the transmission data control unit 40. A part of the processing procedure overlaps with the description of the sequence diagram.

  The transmission data control unit 40 monitors the transmission register 35 and determines whether or not there is a write in the transmission register 35 (S110).

  When there is a write in the transmission register 35 (Yes in S110), the transmission data control unit 40 reads transmission data from the transmission register 35 (S120).

  The transmission data control unit 40 determines whether there is transmission data of the same transmission destination in the next transmission data buffer 39 (S130). If there is no transmission data in the next transmission data buffer 39 in the first place, or if there is transmission data in the next transmission data buffer 39 and the transmission destination chip select designation bits do not match, the determination in S130 is No.

  When there is transmission data of the same transmission destination in the next transmission data buffer 39 (Yes in S130), the transmission data control unit 40 transmits the data portion (lower 16 bits) of the next transmission data buffer 39 read from the transmission register 35. Replace with the data portion of the data (S140). As a result, only data to be transmitted later to the same destination can be transmitted, and time guarantee is facilitated.

  Next, the transmission data control unit 40 increments the priority bit of the next transmission data buffer 39 by 1 (S150). Thereby, the priority of the transmission data transmitted frequently can be enlarged.

  When there is no transmission data of the same transmission destination in the next transmission data buffer 39 (No in S130), the transmission data control unit 40 determines whether there is transmission data of the same transmission destination in the transmission data buffer 36 (S160). . Note that transmission data of the same transmission destination is not stored in the next transmission data buffer 39 and the transmission data buffer 36. In addition, there is no situation where transmission data is written in the transmission data buffer 36 even though transmission data is not written in the next transmission data buffer 39.

  When there is transmission data with the same transmission destination in the transmission data buffer 36 (Yes in S160), the transmission data control unit 40 acquires priority bits from transmission data with the same transmission destination in the transmission data buffer 36 (S170).

  The transmission data control unit 40 increments the acquired priority bit by 1 (S180). Thereby, the priority of the transmission data transmitted frequently can be enlarged.

  The transmission data control unit 40 sets the priority bit incremented by 1 to the priority bit of the transmission data read from the transmission destination register (S190).

  Then, the transmission data control unit 40 overwrites the transmission data having the same transmission destination in the transmission data buffer 36 with the transmission data in which the priority bit is newly set (S200). As a result, only data to be transmitted to the same destination later can be transmitted.

  The transmission data control unit 40 determines whether or not the priority bit of the next transmission data buffer 39 is equal to or higher than the priority bit of the transmission data of the overwritten transmission data buffer 36 (S210). If the priority bits are equal, the transmission data previously written in the next transmission data buffer 39 is given priority. For this reason, when the priority bit of the next transmission data buffer 39 is equal to or higher than the priority bit of the transmission data of the overwritten transmission data buffer 36 (Yes in S210), the process ends.

  When the priority bit of the next transmission data buffer 39 is not equal to or higher than the priority bit of the transmission data of the overwritten transmission data buffer 36 (No in S210), the priority bit of the transmission data of the overwritten transmission data buffer 36 is the largest. Therefore, the transmission data control unit 40 replaces the overwritten transmission data in the transmission data buffer 36 with the transmission data in the next transmission data buffer 39 (S220). Thereby, transmission data that is frequently transmitted can be transmitted with priority.

  On the other hand, in step S160, when there is no transmission data of the same transmission destination in the transmission data buffer 36 (No in S160), the transmission data control unit 40 determines whether or not transmission data is written in the next transmission data buffer 39. (S230). This determination can also be determined in S130.

  When transmission data is written in the next transmission data buffer 39 (Yes in S230), the transmission data cannot be written in the next transmission data buffer 39, so the transmission data control unit 40 transmits the transmission data read from the transmission register 35. Write to the data buffer 36 (S240).

  When the transmission data is not written in the next transmission data buffer 39 (No in S230), the transmission data can be written in the next transmission data buffer 39. Therefore, the transmission data control unit 40 transmits the transmission data read from the transmission register 35 to the next transmission. Write to the data buffer 39 (S250).

[About transition of priority]
FIG. 11 is an example of a diagram illustrating an example of priority transition. As shown in FIG. 11A, when the data 3a is written in the transmission register 35 in a state where the transmission data 3 is written in the next transmission data buffer 39, the priority is set as shown in FIG. The increased transmission data 3a is written into the next transmission data buffer 39 (processing of S140 and S150).

  Assuming a situation where the CPU 11 transmits the transmission data 3b to the same destination one after another, first, as shown in FIGS. 11C and 11D, the priority of the transmission data 3b is higher than the transmission data 3a. The transmission data 3b is written in the next transmission data buffer 39 by one.

  Next, when the transmission data 3c is written in the transmission register 35, similarly, as shown in FIGS. 11E and 11F, the priority of the transmission data 3c is increased by one with respect to the transmission data 3b. Transmission data 3 c is written in the next transmission data buffer 39.

  FIG. 12 is another example of a diagram illustrating an example of priority transition. Assume that a situation occurs in which the CPU 11 sequentially transmits transmission data to the same transmission destination as the transmission data 2 in the transmission data buffer 36. In this case, when the priority bits of the transmission data in the next transmission data buffer 39 and the transmission data in the transmission data buffer 36 are reversed, the transmission data in the next transmission data buffer 39 and the transmission data in the transmission data buffer 36 are switched.

  FIGS. 12A and 12B are in the same state as FIGS. 11A and 11B. For example, in FIG. 12C, when the transmission data 2a is written in the transmission register 35, the priority of the transmission data 2a is increased by one with respect to the transmission data 2, and as shown in FIG. The transmission data 2a is written into the transmission data buffer 36 (processing of S170 to S200). At this next point, the priority bits of the transmission data 3a in the next transmission data buffer 39 and the transmission data 2a in the transmission data buffer 36 are equal.

  Next, in FIG. 12E, when the transmission data 2b is written in the transmission register 35, the priority of the transmission data 2b is increased by one with respect to the transmission data 2a, and as shown in FIG. The transmission data 2b is written in the transmission data buffer 36.

  At this next point, since the priority bits of the transmission data 3a in the next transmission data buffer 39 and the transmission data 2b in the transmission data buffer 36 are reversed, the transmission data 3b in the next transmission data buffer 39 and the transmission data 2b in the transmission data buffer 36 are reversed. Replacement occurs.

[Others]
In the above embodiment, the initial value of the priority bit is set to zero. However, the transmission data control unit 40 may set a priority bit other than zero. For example, the transmission data control unit 40 monitors the transmission frequency for each transmission destination in the past predetermined time (for example, several seconds), increases the priority bit of transmission data with a low transmission frequency, and sets the transmission data buffer 36 as an initial value. Set to. Because the initial value of the priority bit of the transmission data of the transmission destination that is transmitted only occasionally becomes large, the transmission data with high priority bit because of the high-frequency transmission is also time for the transmission destination data that is transmitted only occasionally. It will be easier to guarantee.

  The priority bit is set by the transmission data control unit 40, but the CPU 11 may be settable. In this case, the software executed by the CPU 11 increases or decreases the priority bits for each transmission destination or even for the same transmission destination depending on the type of event. Therefore, since other transmission data is frequently transmitted, even if the priority is high, the CPU 11 can preferentially transmit the transmission data that the CPU 11 desires to transmit.

11 CPU
31 clock control register 32 serial clock control unit 33 serial communication control unit 34 chip select control unit 35 transmission register 36 transmission data buffer 37 transmission / reception control register 38 reception register 39 next transmission data buffer 40 transmission data control unit 100 communication device 101 IC
200 Microcomputer 300 ECU

Claims (9)

A transmission register to which transmission data is written; and
A destination designation means for designating one destination from a plurality of destinations;
A transmission control means for serially transmitting transmission data to a transmission destination;
A transmission data buffer for storing transmission data awaiting transmission;
When the transmission data written in the transmission register and the transmission destination of the transmission data stored in the transmission data buffer are the same, the transmission data stored in the transmission data buffer is the transmission data written in the transmission register. A transmission data control means for overwriting;
A communication device. The transmission data buffer stores transmission data with priority information added thereto,
When the transmission data control means overwrites the transmission data stored in the transmission data buffer with the transmission data written in the transmission register,
Determine priority information according to the frequency of overwriting the transmission data of the same destination, and write to the transmission data buffer,
The communication apparatus according to claim 1. If the priority is higher as the priority information is larger,
When the transmission data control means overwrites the transmission data stored in the transmission data buffer with the transmission data written in the transmission register,
Setting priority information larger than the priority information of transmission data stored in the transmission data buffer to overwrite the priority information of transmission data written in the transmission register;
The communication device according to claim 2. When the transmission data control means overwrites the transmission data stored in the transmission data buffer with the transmission data written in the transmission register,
As the number of times of overwriting increases, a larger priority information is set in the priority information of transmission data written in the transmission register and overwritten.
The communication device according to claim 3. The transmission data buffer includes a next transmission data buffer in which transmission data to be transmitted by the transmission control unit is stored, and a transmission waiting transmission data buffer in which one or more transmission data are accumulated until the transmission data is written in the next transmission data buffer And
When the transmission data written to the transmission register and the transmission destination of the transmission data stored in the next transmission data buffer are the same,
The transmission data control means overwrites the transmission data stored in the next transmission data buffer with the transmission data written in the transmission register;
The communication apparatus according to claim 1, wherein The transmission data buffer includes a next transmission data buffer in which transmission data to be transmitted by the transmission control unit is stored, and a transmission waiting transmission data buffer in which one or more transmission data are accumulated until the transmission data is written in the next transmission data buffer And
By overwriting the transmission data stored in the transmission data buffer waiting for transmission with the transmission data written in the transmission register together with the determined priority information,
When the transmission data of the transmission data buffer waiting for transmission has a higher priority than the transmission data of the next transmission data buffer,
The transmission data control means replaces transmission data with the highest priority of the transmission waiting transmission data buffer and transmission data of the next transmission data buffer.
The communication apparatus according to any one of claims 2 to 4, wherein The initial value of the priority information is set to zero or arbitrarily set when transmission data is written to the transmission register,
The communication apparatus according to claim 2, wherein The communication device according to any one of claims 1 to 7,
Program storage means for storing a program;
A computing means for executing the program;
Data writing means for writing a transmission destination and transmission data to the transmission register according to the calculation result of the calculation means;
An information processing apparatus. A transmission register to which transmission data is written; and
A destination designation means for designating one destination from a plurality of destinations;
A transmission control means for serially transmitting transmission data to a transmission destination;
A transmission data buffer for storing transmission data awaiting transmission, and a data transmission method for a communication apparatus,
When the transmission data written in the transmission register and the transmission destination of the transmission data stored in the transmission data buffer are the same, the transmission data stored in the transmission data buffer is the transmission data written in the transmission register. Overwrite,
A data transmission method characterized by the above.

Images