JP2012253258A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reliably deposit a Cu film by an electrolytic plating.SOLUTION: A semiconductor device manufacturing method comprises immersing a silicon substrate in a plating tank with rotating the silicon substrate at a speed such that a relative speed between a plating liquid to which an inhibitor and an accelerator are added and the silicon substrate becomes 100 m/min and over. Accordingly, molecules of the inhibitor adhere to a surface of a seed layer and seed dissolution is inhibited. The semiconductor device manufacturing method comprises energizing between the silicon substrate and an anode electrode with rotating the silicon substrate at a speed such that a relative speed between the silicon substrate and the plating liquid becomes 30 m/min and under when making a conductive film grow. Accordingly, bottom-up growth is accelerated and formation of a hole in a wiring groove is prevented.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, semiconductor devices such as LSI (Large Scale Integration) have been required to have higher speed and higher integration. Along with this, miniaturization, thinning, low resistance, and high current density of semiconductor circuit wiring have been achieved. For example, as a wiring material used for miniaturization of wiring, a Cu film having low resistance and excellent electric conductivity is used. In forming the wiring using the Cu film, after forming a wiring groove on the insulating film in advance, the Cu film is grown in the wiring groove by, for example, electrolytic plating.

  In the electrolytic plating method, first, a diffusion prevention film (Barrier Metal) for preventing Cu from diffusing into the insulating film is formed to cover the wiring groove. Further, a seed layer is formed so as to cover the diffusion prevention film. The seed layer is formed by, for example, a physical vapor deposition (PVD) method. The diffusion prevention film and the seed layer are continuously formed in a vacuum. Thereafter, the substrate is connected to the cathode electrode and immersed in the plating solution. Furthermore, electricity is applied between the substrate and the anode electrode to reduce Cu ions in the plating solution and to cause Cu to be electrolytically deposited.

  In the electroplating method used for fine wiring, so-called bottom-up growth is known in which the filling of Cu proceeds from the bottom to the top of the opened wiring groove. Bottom-up growth is performed by adding several kinds of organic additives and inorganic additives to the plating solution. For example, in the electrolytic plating of Cu using a copper sulfate aqueous solution as a plating solution, an inhibitor having an effect of suppressing the precipitation of Cu and an accelerator having an effect of promoting the precipitation of Cu are added. In this case, it is considered that the growth rate of Cu at the bottom of the wiring groove becomes significant due to the difference in adsorption concentration between the inhibitor and the promoter at various points on the surface of the wiring groove, and bottom-up growth is realized.

  After the Cu film is formed, the excess Cu film formed on the surface of the insulating film is removed by a chemical mechanical polishing (CMP) method. If the thickness of the Cu film is not uniform, the wiring resistance may vary due to variations in dishing. For this reason, conventionally, the substrate is rotated at a predetermined speed in the electrolytic plating tank during the formation of the Cu film. As the rotation speed of the substrate, for example, when the substrate diameter is D and the rotation speed is N, the speed around the substrate defined by D × N × π is 6000 × π mm in the first step within 10 sec from plating immersion. / Min or less, and in the subsequent second step, it is greater than 6000 × π mm / min.

JP 2009-277772 A JP2009-228078

  Here, in the electrolytic plating of Cu, the seed layer may be dissolved in the plating solution. In general, in the film formation using the PVD method, the coverage of Cu with respect to the inner wall of the wiring groove tends to decrease due to the shadow effect. Furthermore, the Cu film formed by the PVD method has a property of being slightly dissolved in a copper sulfate aqueous solution that is a plating solution. For this reason, there is a possibility that the seed layer dissolves and is lost due to the portion where the coverage is lowered being in contact with the plating solution. When the seed layer is lost, local conduction shortage occurs in that portion. When local conduction shortage due to seed loss occurs, Cu embedding defects are likely to be induced, for example, voids are generated in the wiring grooves during Cu electroplating.

  As a means for alleviating the shadow effect with the seed layer by the PVD method, there is a thick seed layer. However, if the seed layer is thickened, the seed layer tends to protrude into an eaves shape (Overhang) at the opening at the upper end of the wiring trench. As a result, before the Cu film is buried in the bottom of the wiring groove during electrolytic plating, a pinch-off phenomenon in which the opening portion of the wiring groove is first closed with the Cu film is induced, and it becomes easy to generate voids in the wiring. The pinch-off phenomenon is more likely to occur as the wiring becomes finer. If the seed layer is thinned to prevent the pinch-off phenomenon, seed dissolution is likely to occur.

In addition, when the seed layer is formed using a chemical vapor deposition (CVD) method, which has better coverage than the PVD method, the shadow effect is reduced, but the impurity concentration in the film tends to increase. It is difficult to ensure adhesion with other films.
This invention is made | formed in view of such a situation, and it aims at ensuring precipitation of Cu film | membrane by the electroplating method.

  According to one aspect of the embodiment, a step of forming an insulating film above the substrate, a step of forming a groove in the insulating film, a step of forming a conductive seed layer on the inner wall of the groove, a metal A step of immersing the substrate in the electrolytic plating solution while rotating the electrolytic plating solution containing salt and the outer peripheral portion of the substrate at a rotational speed of 100 m / min or more, and the substrate immersed in the electrolytic plating solution And a step of growing a conductive film in the trench by energizing the semiconductor device.

  According to another aspect of the embodiment, a step of forming an insulating film above the substrate, a step of forming a groove in the insulating film, and a step of forming a conductive seed layer on the inner wall of the groove And a step of immersing the substrate in the electrolytic plating solution while rotating the electrolytic plating solution containing the metal salt and the outer peripheral portion of the substrate at a rotational speed that is a first relative speed; While rotating the relative speed of the outer peripheral portion of the substrate at a second relative speed that is slower than the first relative speed, the conductive film is energized to grow a conductive film inside the groove. And a method of manufacturing a semiconductor device including the steps.

  Seed dissolution in the process of immersing the substrate in the plating tank is suppressed. Conduction failure due to seed dissolution is prevented, and a conductive film can be reliably formed in the wiring trench.

FIG. 1A is a cross-sectional view (part 1) illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1B is a cross-sectional view (part 2) illustrating the example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1C is a sectional view (part 3) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1D is a cross-sectional view (No. 4) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1E is a sectional view (No. 5) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 2 is a diagram showing an example of a schematic configuration of a plating apparatus used in the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a sequence diagram of the electroplating process of the semiconductor device according to the first embodiment of the present invention. FIG. 4A is a cross-sectional view (part 1) illustrating an example of an electrolytic plating process of the semiconductor device according to the first embodiment of the present invention. FIG. 4B is a sectional view (No. 2) showing an example of the electrolytic plating step of the semiconductor device according to the first embodiment of the present invention. FIG. 4C is a cross-sectional view (part 3) illustrating the example of the electrolytic plating process of the semiconductor device according to the first embodiment of the present invention. FIG. 4D is a cross-sectional view (part 4) illustrating the example of the electrolytic plating process of the semiconductor device according to the first embodiment of the present invention. FIG. 4E is a sectional view (No. 5) showing an example of the electrolytic plating step of the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a diagram showing the relationship between the seed dissolution area ratio of the sidewall and the inhibitor concentration in the immersion stage of the electrolytic plating process of the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a conceptual diagram of a process in which an inhibitor is adsorbed in the electrolytic plating process of the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a diagram showing the relationship between the seed dissolution area ratio of the sidewall and the relative speed in the bottom growth stage of the electrolytic plating process of the semiconductor device according to the first embodiment of the present invention. FIG. 8 is a diagram showing the relationship between the relative speed of the plating solution and the substrate and the growth rate of the plating film in the electrolytic plating process of the semiconductor device according to the first embodiment of the present invention. FIG. 9 is a sequence diagram of an electrolytic plating process for a semiconductor device according to the second embodiment of the present invention.

The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
The foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

(First embodiment)
The first embodiment will be described in detail with reference to the drawings.
First, steps required until a sectional structure shown in FIG. 1A is obtained will be described. First, a surface which is one surface of an n-type or p-type silicon (semiconductor) substrate 1 is thermally oxidized to form an element isolation insulating film 2 to a depth of, for example, 30 nm. Defining the active region. Such an element isolation structure is called LOCOS (Local Oxidation of Silicon). STI (Shallow Trench Isolation) may be used for the element isolation structure.

  Next, a dopant impurity is introduced into the active region of the silicon substrate 1 by ion implantation to form a well. When a p-type impurity such as boron is introduced as a dopant impurity, a p-well 3 is formed in the silicon substrate 1. After forming the p-well 3, the surface of the active region is thermally oxidized to form the gate insulating film 5. As the gate insulating film 5, for example, a thermal oxide film is formed to a thickness of about 6 nm to 7 nm. In the following, the case where the p-well 3 is formed will be described, but the same process is performed when the n-well is formed in the silicon substrate 1.

  Subsequently, a polysilicon film is formed to a thickness of 200 nm on the entire upper surface of the silicon substrate 1 by using, for example, a CVD method. Thereafter, the polysilicon film is patterned using a photolithography technique and an etching technique to form a gate electrode 6 on the silicon substrate 1. A plurality of gate electrodes 6 are formed in parallel with each other on the p-well 3.

Further, ions are implanted into the p-well 3 using the gate electrode 6 as a mask, and phosphorus is introduced as an n-type impurity into regions on both sides of the gate electrode 6 in the p-well 3. Thereby, the first and second source / drain extensions 8 are formed. The first and second source / drain extensions 8 constitute a shallow region of the extension source / drain region. Thereafter, a silicon oxide film as an insulating film is formed on the entire upper surface of the silicon substrate 1 to a thickness of 300 nm by using, for example, a CVD method. Thereafter, the insulating film is anisotropically etched. The insulating film is etched back, and an insulating sidewall 10 is formed on the side of the gate electrode 6.

  Subsequently, n-type dopant impurities such as arsenic are ion-implanted again into the silicon substrate 1 using the gate electrode 6 and the insulating sidewall 10 as a mask. As a result, source / drain diffusion layers 11 are formed in the p-well 3 on the side of the gate electrode 6. The source / drain diffusion layer 11 forms a deep region of the extension source / drain.

  Further, a refractory metal film such as a cobalt film is formed to a thickness of 10 nm on the entire surface of the silicon substrate 1 by sputtering, for example. Thereafter, the refractory metal film is heated at 500 ° C. for 30 seconds to react with silicon, for example. As a result, a refractory metal silicide layer such as a cobalt silicide layer is formed on the silicon substrate 1 in the source / drain diffusion layer 11, and the resistance of each source / drain diffusion layer 11 is reduced. Thereafter, the refractory metal film remaining unreacted on the element isolation insulating film 2 or the like is removed by wet etching using, for example, a mixed solution of sulfuric acid and hydrogen peroxide. Thereafter, annealing is performed twice in a nitrogen atmosphere at 800 ° C. for 30 seconds. As a result, a source / drain electrode 12A made of, for example, cobalt silicide is formed on the source / drain diffusion layer 11. Further, a silicide layer 12B made of, for example, cobalt silicide is formed on the gate electrode 6.

  Through the steps so far, transistors T1 and T2, which are semiconductor elements composed of the gate insulating film 5, the gate electrode 6, the source / drain electrode 12A, and the like, are formed in the active region of the silicon substrate 1.

  Next, as an oxide film 14, for example, a silicon oxide film (SIO film) is formed on the entire upper surface of the silicon substrate 1 to a thickness of 1000 nm by plasma CVD. Thereafter, the surface of the oxide film 14 is polished and planarized by a CMP method.

  Subsequently, the contact hole 15 is formed by etching the oxide film 14 using a resist film (not shown) as a mask. The diameter of the contact hole 15 is, for example, 0.25 μm, and reaches the source / drain electrode 12A.

Then, a conductive plug 16 that is electrically connected to the source / drain electrode 12A is formed using the contact hole 15. Specifically, for example, a Ti / TiN film is formed on the inner surface of the contact hole 15 by a CVD method using TiCl ₄ gas. Further, a W film is grown on the adhesion film. The W film is formed by, for example, a CVD method using WF ₆ gas and SiH ₄ gas, or WF ₆ gas and H ₂ gas. The W film has a thickness that reaches, for example, 300 nm on the oxide film 14. As a result, the gap of the contact hole 15 is filled with the W film. Thereafter, the excess W film and the adhesion film grown on the upper surface of the oxide film 14 are removed by the CMP method. As a result, one conductive plug 16 is formed in each contact hole 15.

Next, steps required until a sectional structure shown in FIG.
On the oxide film 14, as the liner film 21, for example, an oxide film containing C or N is formed to a thickness of several tens of nm by plasma CVD. Subsequently, an organic or inorganic low dielectric constant film is formed on the liner film 21 as an insulating interlayer film 22 to a thickness of 100 nm to 300 nm. The insulating interlayer film 22 is uniformly applied on the liner film 21 using, for example, a spin coating apparatus, and then cured by heat treatment. A first interlayer insulating film 20 is formed by a laminated film of the liner film 21 and the insulating interlayer film 22.

  Thereafter, a silicon carbide insulating film 23 serving as a hard mask is formed on the interlayer insulating film 20 to a thickness of several tens of nm. Further, a photoresist film is formed to a thickness of 50 nm to 500 nm on the insulating film 23 by spin coating. Subsequently, the resist film is patterned to form a mask 24 having an opening corresponding to the wiring groove.

Next, steps required until a sectional structure shown in FIG.
Further, the insulating film 23 is dry etched using the mask 24 to form a hard mask 23A. Further, the interlayer insulating film 20 and the liner film 21 are sequentially dry-etched to form a wiring groove 26. As the dry etching, for example, reactive plasma etching to which a CF-based gas such as CF ₄ , NH ₃ gas, or N ₂ / H ₂ gas is added is used. The wiring trench 26 is formed to a depth at which the underlying conductive plug 16 is exposed. After the wiring trench 26 is formed, the mask 24 may be removed by washing with an organic cleaning solution. Further, in order to remove moisture adsorbed on the interlayer insulating film 20, heat treatment is performed at 150 ° C. to 300 ° C., for example. The processing time is, for example, 0.5 minutes to 3 minutes. Thereafter, for cleaning, the hard mask 23A and the wiring trench 26 are physically etched in the range of 5 nm to 15 nm using Ar plasma. Alternatively, the heat treatment may be performed at 150 to 350 ° C. for 0.5 to 3 minutes while introducing a reducing gas containing H ₂ gas.

Next, steps required until a sectional structure shown in FIG.
First, a barrier metal film 27 is formed so as to cover the inner surface of the wiring groove 26 and the hard mask 23A. Further, a seed layer (not shown) is formed on the barrier metal film 27. The barrier metal film 27 and the seed layer are formed by, for example, the PVD method in each dedicated chamber attached to the same film forming apparatus. That is, the barrier metal film 27 and the seed layer are continuously formed under vacuum without being exposed to the atmosphere. The barrier metal film 27 is made of a tantalum compound or a titanium compound and is formed on the wiring trench 26 and the hard mask 23A. The thickness of the barrier metal film 27 is 3 nm to 30 nm in the flat portion. For example, copper or a copper alloy is used for the seed layer. The thickness of the seed layer is 10 nm to 100 nm in the flat portion. Next, a conductive film 28 made of Cu is filled in the wiring groove 26 by electrolytic plating. The conductive film 28 is also formed above the hard mask 23A.

  Next, as shown in FIG. 1E, a CMP (Chemical Mechanical Polishing) method is used to remove excess Cu on the wiring trench 26, unpatterned flat portion Cu, barrier metal film 27, and hard mask 23A. Polish with In the CMP method, an organic acid slurry is used. After polishing, surface cleaning using an organic acid cleaning solution may be performed to remove residues on the substrate surface. As a result, a semiconductor device 73 is formed in which the wiring layer 72 in which the wiring 71 is embedded in the interlayer insulating film 20 is formed. The semiconductor device 73 may have two or more wiring layers. In this case, the steps shown in FIGS. 1B to 1E are repeated.

Here, the details of the electrolytic plating process described with reference to FIG. 1D will be described below.
As shown in FIG. 2, a plating apparatus 31 used for electrolytic plating has a rotation unit 32 having a power feeding mechanism in the upper part, and a plating tank 33 is arranged in the lower part. The rotation unit 32 has a substrate holder 35 attached to the lower end of the rotation shaft 34. A plurality of clamps 36 are disposed on the lower surface of the substrate holder 35 and are held so that the silicon substrate 1 faces downward, that is, the opening of the wiring groove 26 is disposed on the lower side. The rotation unit 32 is controlled by a rotation controller 37.

An anode electrode 38 is disposed in the plating tank 33 at a position facing the silicon substrate 1. For the anode electrode 38, for example, pure copper or phosphorous copper I (0 at% to several at%) is used. A diffusion plate 39 is installed between the anode electrode 38 and the cathode electrode (silicon substrate 1) so that the plating solution contacts the silicon substrate 1 uniformly. Anode electrode 38 and diffusion plate 3
9 is immersed in the plating solution. The plating tank 33 is connected to a plating tank 42 via a pipe 41, and the plating solution is circulated between the plating tank 33 and the plating tank 42 by a circulation pump 43 at a speed of 5 l / min to 40 l / min. . The plating tank 42 is provided with an additive supplier 44 that supplies the additive into the plating solution, and the concentration of the additive in the plating solution can be adjusted. For the plating solution, an aqueous copper sulfate solution to which an inhibitor and an accelerator are added is used. As the inhibitor, an organic polymer having a chain structure having a relatively large molecular weight (MW = 1000 to 5000), for example, polyethylene glycol or polypropylene glycol is used. As the promoter, an organic or inorganic compound containing an element (for example, S: sulfur) having a relatively small molecular weight (Mw = 100 to 500) and high affinity for Cu is used.

  Further, the plating apparatus 31 is provided with an external power supply 45 so that electric power can be applied between the anode electrode 38 in the plating tank 33 and the clamp 36 of the rotary unit 32. A current required for Cu growth is supplied to the silicon substrate 1 through the clamp 36. The silicon substrate 1 mounted on the rotating unit 32 corresponds to a cathode electrode, and the surface is coated with Cu by electrolytic deposition. Supply of the plating solution and the additive into the plating tank 33 is performed from the lower part of the plating tank 33, flows to the upper side of the plating tank 33, and then is discharged through the drain 33 </ b> A on the side of the plating tank 33.

  Further, FIG. 3 shows a sequence of the electrolytic plating process. The horizontal axis shows the passage of time. From the top, the vertical axis indicates the substrate immersion rate, the relative speed between the plating solution and the silicon substrate, and the growth amount of the plating film. In the first first step S 1, the silicon substrate 1 is mounted on the rotation unit 32. At this stage, the substrate immersion rate, relative speed, and plating film growth amount are all zero.

  In the subsequent second step S2, the silicon substrate 1 is immersed in the plating solution. At this time, the substrate immersion rate gradually increases. The silicon substrate 1 is mounted on the rotating unit 32 with the plating surface, that is, the surface where the wiring groove 26 is opened, facing downward. The rotation unit 32 moves in the direction approaching the plating tank 33 while rotating the silicon substrate 1 and immerses the silicon substrate 1 in the plating solution. This rotation generates a relative speed between the silicon substrate 1 and the plating solution. The relative speed is maintained at the first speed V1 of 100 m / min or more. Details of the relative speed will be described later. The amount of plating film growth is zero. Even after the substrate immersion rate reaches 100%, the relative speed is maintained at 100 m / min or more, and thereafter, the process proceeds to the bottom-up growth stage which is the third step S3.

  After the third step S3, the substrate immersion rate is maintained at 100% until the plating growth is completed. The relative speed of the substrate and the plating solution is maintained at the second speed V2 of 30 m / min or less. Details of the relative speed will be described later. By energizing the silicon substrate 1, the growth of the plating film is started. In subsequent step S <b> 4, the conductive film 28 is embedded in the wiring trench 26. When the embedding of the conductive film 28 into the wiring groove 26 is completed, the process proceeds to the fourth step S5.

  In the fourth step S5, the conductive film 28 is uniformly grown on the entire upper surface of the silicon substrate 1 including the flat portion. From the viewpoint of stirring the plating solution 40, the relative speed is increased. However, the relative speed may not be changed from the fourth step S4.

Here, the details of the relative speed (first speed V1) between the silicon substrate 1 and the plating solution in the electrolytic plating process will be described.
When the silicon substrate 1 is immersed in the plating solution in step S2, the relative speed between the silicon substrate 1 and the plating solution is controlled to be 100 m / min or more. Since the silicon substrate 1 is rotated, a difference occurs in the relative speed in the surface of the substrate, but the relative speed in a portion where the seed dissolution is likely to occur is set to 100 m / min or more. The location where the seed dissolution is likely to occur is the vicinity of the outer peripheral portion of the silicon substrate 1 and the location where the shadow effect is likely to occur when the seed layer is formed by the PVD method.

  FIG. 4A shows a partially enlarged view of a portion where the shadow effect appears. FIG. 4A is a partially enlarged view in a state where the silicon substrate 1 is held downward by the rotating unit 32 of the plating apparatus 31. A barrier metal film 27 is formed on the silicon substrate 1 disposed downward so as to cover the wiring trench 26 and the hard mask 23A. In the seed layer 28A formed on the surface of the barrier metal film 27, the inner portion of the wiring trench 26 is relatively thin due to the shadow effect.

  Most of the seed dissolution is considered to occur at the timing when the silicon substrate 1 is immersed in the plating solution as shown in FIG. 4B. In order to verify that the inhibitor, which is a plating additive, has an effect of suppressing seed dissolution, a barrier metal film 27 and a seed layer 28A are formed on the silicon substrate 1 on which the wiring trench 26 is formed by the PVD method. The silicon substrate 1 was immersed for several seconds in a plating solution containing 0 ml / l (no addition) of the inhibitor and a plating solution containing 0.1 ml / l of the inhibitor.

  As shown in FIG. 5, compared to the area of seed dissolution on the side wall when no inhibitor is added, in the plating solution with 0.1 ml / l of inhibitor added, the area of seed dissolution on the side wall of the wiring groove 26 is larger. It decreased significantly. This is presumably because the inhibitor coated the surface of the seed layer 28A and the seed layer 28A was protected.

  As shown in the conceptual diagram of FIG. 6, it is considered that a micro area called a diffusion layer 51 is formed at the interface between the surface of the silicon substrate 1 and the plating solution 40. A region away from the surface of the silicon substrate 1 is a fluidized bed 52. The additive molecules 53 in the plating solution 40 are carried to the vicinity of the silicon substrate 1 by liquid circulation, and arrive (adsorb) on the substrate surface through the diffusion layer 51. In general, the inside of the diffusion layer 51 is regarded as a stationary system without limit. In addition, the inhibitor molecule 53 has a relatively large molecular weight, and the movement speed in the diffusion layer 51 is expected to be slow. Therefore, it is considered that the rate at which the inhibitor molecules 53 are adsorbed on the substrate surface is limited by the process in which the inhibitor molecules 53 pass through the diffusion layer 51.

Here, the thickness of the diffusion layer 51 generated at the interface between the fluid liquid and the solid changes depending on the flow speed of the liquid, and the thickness of the diffusion layer 51 decreases as the flow speed increases. As an example, according to YG Levich (Physicochemical Hydrodynamics, Prentice-Hall, Englewood Cliffs, NJ, 1962), the thickness of the diffusion layer 51 generated on the surface of the rotating electrode immersed in the solution is: 1.61 × D ^1/3 ν ^1/6 ω ^−1/2 . Where D: diffusion coefficient (dm ² / s), ν: kinematic viscosity (dm ² / s), ω: angular velocity (s-1) or 2πN / 60 (N is the number of revolutions; rpm), The angular velocity in the middle corresponds to the flow velocity.

  In this embodiment, the flow velocity corresponds to the relative velocity between the silicon substrate 1 and the plating solution 40. That is, if the relative speed between the silicon substrate 1 and the plating solution 40 is increased to reduce the thickness of the diffusion layer 51, the adsorption speed of the inhibitor molecules 53 on the silicon substrate 1 is increased.

Here, the result of investigating the relationship between the relative speed between the silicon substrate 1 and the plating solution 40 and the seed dissolution is shown in FIG. 1 ml / l of an inhibitor was added to the plating solution 40, and the relative speed was 14 m / min and 120 m / min. From FIG. 7, it can be seen that seed dissolution is reduced at a relative speed of 120 m / min compared to a relative speed of 14 m / min. This is because the adsorption rate of the inhibitor increases as the relative speed increases. Further, as a result of electrolytic plating while changing the relative speed, it was found that the conductive film 28 can be formed in the wiring groove 26 without a gap if the relative speed between the silicon substrate 1 and the plating solution is 100 m / min or more. Here, the relative speed is a relative speed between the silicon substrate 1 and the plating solution in a portion where the seed dissolution is likely to occur, that is, the outer peripheral portion of the silicon substrate 1.

  The rotation speed of the silicon substrate 1 is controlled by a rotation controller 37 of the plating apparatus 31. Further, the moving speed of the plating solution is determined by the performance of the circulation pump 43 and the like, and can be set to a substantially constant value. Therefore, the relative speed between the silicon substrate 1 and the plating solution can be easily controlled by the plating apparatus 31.

Next, the relative speed (second speed V2) between the silicon substrate 1 and the plating solution in step S3 in FIG. 3 will be described.
In step S3, as shown in FIG. 4C, after the silicon substrate 1 is immersed in the plating solution 40, a current is passed through the silicon substrate 1 to form a plating film. At this time, the rotation speed is controlled by the rotation controller 37 so that the relative speed between the silicon substrate 1 and the plating solution 40 is 30 m / min or less. Here, the relative velocity between the silicon substrate 1 and the plating solution in the portion where the seed dissolution is likely to occur, that is, the outer peripheral portion of the silicon substrate 1 is set to 30 m / min or less. In the process in which the conductive film 28 is filled in the wiring trench 26, bottom-up growth proceeds predominantly due to the effect of the additive.

  Here, seed dissolution may occur during bottom-up growth. For example, a hole may be generated along the side wall of the wiring groove 26 in the opening portion of the wiring groove 26. This is believed to occur due to seed dissolution. Since a hole is likely to be generated in the vicinity of the opening of the wiring groove 26 where the additive is relatively easily adsorbed, a mechanism in which the inhibitor once adsorbed is desorbed from the surface of the seed layer 28A by an action such as electrolysis is considered. It is done. Therefore, the bottom-up growth needs to be completed before the inhibitor is desorbed from the seed layer 28A on the sidewall of the wiring trench 26.

  In order to increase the bottom-up growth rate, the adsorption concentration (adsorption rate) of the promoter at the bottom portion 26A of the wiring groove 26 may be increased, or the adsorption concentration of the inhibitor may be decreased. Here, the accelerator having a relatively small molecular weight has a high adsorption speed to the silicon substrate 1 and a short time for passing through the diffusion layer 51. Furthermore, it is difficult to increase the adsorption rate of the accelerator. On the other hand, since the adsorption rate of the inhibitor depends on the thickness of the diffusion layer 51, the adsorption rate can be reduced by increasing the thickness of the diffusion layer 51.

  The degree of adsorption of the inhibitor can be grasped from a comparison between the bottom-up growth rate and the plating growth rate in a flat region other than the wiring groove 26. When the inhibitor is sufficiently adsorbed inside and outside the wiring groove 26, the bottom-up growth rate. And the plating growth rate in the flat region becomes equal. On the other hand, when the supply of the inhibitor is not sufficient and the adsorption of the inhibitor inside the wiring groove 26 is poor, the difference between the bottom-up growth rate and the plating growth rate in the flat region becomes large.

  FIG. 8 shows the relationship between the relative speed between the plating solution 40 and the silicon substrate 1 and the plating growth rate. The horizontal axis represents the relative speed, and the vertical axis represents the plating growth rate. Line L1 indicates the bottom-up growth rate, and line L2 indicates the plating growth rate of the flat portion. The bottom-up growth rate was calculated using a wiring groove 26 having a width of 70 nm, and 1 ml / l inhibitor was added to the plating solution 40. When the relative speed is 30 m / min or less, the difference between the bottom-up growth rate and the plating growth rate in the flat region is large. This is because in this region, the adsorption of the inhibitor inside the wiring groove 26 is small. On the other hand, when the relative speed is 100 m / min or more, the bottom-up growth rate is substantially equal to the plating growth rate at the flat portion. In this region, the adsorption of the inhibitor inside the wiring groove 26 is sufficiently advanced, suggesting that the adsorption rate is fast.

Therefore, as shown in FIG. 4D, the conductive film 28 is grown at a relative speed at which the bottom-up growth rate becomes remarkable as compared with the flat portion until the wiring groove 26 is filled with the conductive film 28 by bottom-up growth. Thereafter, as shown in FIG. 4E, 200 nm˜
A conductive film 28 is formed to a thickness of 3000 nm. This is to ensure a polishing margin in the subsequent CMP process. The growth of the conductive film 28 in FIGS. 4C to 4E is performed at a current density of 7 to 30 A / cm ² , for example. After plating film formation, heat treatment may be performed at 100 ° C. to 350 ° C. for 1 minute to 10 minutes in order to relieve residual stress of the conductive film 28.

  As described above, in this embodiment, when the silicon substrate 1 is immersed in the plating solution, the relative speed between the silicon substrate 1 and the plating solution is set to 100 m / min or more. Thereby, the adsorption of the inhibitor to the surface of the seed layer 28A is promoted, and the seed dissolution is reduced. Thereby, generation | occurrence | production of the space | gap in the wiring groove | channel 26 can be suppressed. In addition, when the conductive film 28 is grown after the silicon substrate 1 is immersed in the plating solution, the relative speed between the silicon substrate 1 and the plating solution is set to 30 m / min or less, so that the inhibitor in the wiring groove 26 is adsorbed. Less and promotes bottom-up growth. As a result, the conductive film 28 in the wiring trench 26 can be buried more quickly than the seed dissolution proceeds. As a result, the generation of voids in the wiring groove 26 can be suppressed.

  Here, when seed dissolution does not occur during the bottom-up growth in step S3, the relative speed may be controlled only when the silicon substrate 1 is immersed in step S2. In addition, when it is not necessary to consider the seed dissolution during the immersion of the silicon substrate 1 in step S3, the relative speed may be controlled only during the bottom-up growth in step S3.

(Second Embodiment)
A second embodiment will be described with reference to the drawings. The same components as those in the first embodiment are denoted by the same reference numerals. Moreover, the description which overlaps with 1st Embodiment is abbreviate | omitted.
In this embodiment, in order to prevent seed dissolution, the silicon substrate 1 is immersed in a plating solution while applying a bias voltage.

  FIG. 9 shows a sequence of the electrolytic plating process. The horizontal axis shows the passage of time. From the top, the vertical axis shows the substrate immersion rate, the relative speed between the plating solution and the silicon substrate, the bias voltage, and the growth amount of the plating film. In the first step S 1, the silicon substrate 1 is mounted on the rotation unit 32. At this stage, the substrate immersion rate, relative speed, bias voltage, and plating film growth amount are all zero.

  In the subsequent second step S <b> 2, the silicon substrate 1 is immersed in the plating solution 40. At this time, the substrate immersion rate gradually increases. The relative speed is maintained at the first speed V1 of 100 m / min or more. The bias voltage is a value equal to or lower than the voltage during plating growth, and a voltage adjusted to such an extent that the conductive film 28 is not deposited between the silicon substrate 1 and the anode electrode 38 is applied. The magnitude of the bias voltage is smaller than that during the growth of the conductive film 28, and a different value is used depending on the size and pattern of the silicon substrate 1 and the plating apparatus 31. The growth amount of the plating film at this stage is zero. Even after the substrate immersion rate reaches 100%, the relative speed is maintained at 100 m / min or more, and thereafter, the process proceeds to the bottom-up growth stage which is the third step S3.

  After the third step S3, the substrate immersion rate is maintained at 100% until the plating growth is completed. The relative speed is maintained at the second speed V2 of 30 m / min or less. The bias voltage is set to zero, and a predetermined current is supplied to the silicon substrate 1 instead. Thereby, the growth of the plating film is started. In subsequent step S <b> 4, the conductive film 28 is embedded in the wiring trench 26.

  In the fourth step S5, the conductive film 28 is uniformly grown on the entire upper surface of the silicon substrate 1 including the flat portion. From the viewpoint of stirring the plating solution 40, the relative speed is increased. However, the relative speed may not be changed from the fourth step S4.

  Thereafter, when the excess conductive film 28 is polished by the CMP method, a semiconductor device 73 as shown in FIG. 1E is formed. In this embodiment, the seed dissolution is further suppressed by applying a bias voltage when the silicon substrate 1 is immersed in the plating solution. As a result, the generation of voids in the wiring groove 26 can be further suppressed. Other effects are the same as those of the first embodiment.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is to be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

1 Silicon substrate 20 Interlayer insulating film 26 Wiring groove (pattern)
28 conductive film 28A seed layer 40 plating solution V1 first speed V2 second speed

Claims (4)

Forming an insulating film above the substrate;
Forming a groove in the insulating film;
Forming a conductive seed layer on the inner wall of the groove;
A step of immersing the substrate in the electrolytic plating solution while rotating the electrolytic plating solution containing a metal salt at a rotational speed at which the relative speed of the outer peripheral portion of the substrate is 100 m / min or more;
Energizing the substrate immersed in an electrolytic plating solution to grow a conductive film inside the groove;
A method of manufacturing a semiconductor device including:   While rotating the substrate at a rotation speed at which the relative speed between the electrolytic plating solution and the outer peripheral portion of the substrate is 30 m / min or less, the conductive film is formed in the groove by energizing the substrate immersed in the electrolytic plating solution. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is grown.   3. The semiconductor according to claim 1, wherein in the step of immersing the substrate in an electrolytic plating solution, a voltage lower than a voltage applied to the substrate is applied to the substrate when a conductive film is grown in the groove. Device manufacturing method. Forming an insulating film above the substrate;
Forming a groove in the insulating film;
Forming a conductive seed layer on the inner wall of the groove;
A step of immersing the substrate in the electrolytic plating solution while rotating at a rotational speed at which the relative speed between the electrolytic plating solution containing the metal salt and the outer peripheral portion of the substrate is the first relative speed;
While rotating the relative speed between the electrolytic plating solution and the outer peripheral portion of the substrate at a second relative speed that is slower than the first relative speed, the substrate immersed in the electrolytic plating solution is energized to enter the inside of the groove. Growing a conductive film;
A method of manufacturing a semiconductor device including:

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