JP2001053150A - Method for producing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase production yield, while reducing continuity faults by filling the interconnection plane including interconnection trenches formed on a semiconductor substrate or contact holes made in the interconnection trenches with liquid thereby preventing generation of void in the interconnection plane of a wafer. SOLUTION: Trenches in an insulation film can be filled with pure water 102, and bubbles can be removed by spraying pure water to the interconnection plane prior to a plating process, and plating liquid 108 can be spread sufficiently in the trench in the following process. After filling a cell 107, the plating liquid 108 is jetted uniformly from the central part of a semiconductor substrate 1a toward the end part thereof. After the plating liquid 108 touches the semiconductor substrate 1a, electrolysis is started, and a field plating layer of 0.7 μm thickness is formed on the interconnection plane of the semiconductor substrate 1a. After the semiconductor substrate is cleaned by spraying pure water from a nozzle 101 which is reciprocated, a rotor 104 is rotated and the semiconductor substrate 1a is dried. According to this method, a good conductor film can be formed in a fine trench without generating voids.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly, to a semiconductor integrated circuit device formed by embedding a wiring conductor film in a groove or a connection hole formed in an insulating film on a semiconductor substrate. The present invention relates to a technology effective when applied to an embedded wiring technology.

[0002]

2. Description of the Related Art As a method of forming wiring of a semiconductor integrated circuit,
There is a process called the Damascene method.
In this method, after forming a wiring groove in an insulating film, a conductive film for forming a wiring is deposited on the main surface of the semiconductor substrate, and the conductive film in a region other than the groove is subjected to chemical mechanical polishing (CMP). ;
This is a method of forming a buried wiring in a groove for forming a wiring by removing it by chemical mechanical polishing. This method is particularly suitable as a method for forming an embedded wiring made of a copper-based conductor material (copper or copper alloy), which is difficult to perform fine etching.

[0003] As an application of the damascene method, there is a dual-damascene method. According to this method, after forming a groove for forming a wiring and a connection hole for making a connection with a lower layer wiring in an insulating film, a conductor film for forming a wiring is deposited on the main surface of the semiconductor substrate, and further, other than the groove. In this method, the conductive film in the region is removed by CMP to form a buried wiring in the groove for forming the wiring and to form a plug in the connection hole. In the case of this method, particularly in a semiconductor integrated circuit having a multilayer wiring structure, the number of steps can be reduced, and the wiring cost can be reduced.

[0004] The wiring formation technology using such a damascene method is described in, for example, (1) K. Abe et.al, in Extended Abstracts 1994 SSD.
M, pp937-940 (2) Valery M. Dubin et.al, in Proceedings 1997 VM
IC, pp69-74.

[0005] The above-mentioned document (1) discloses a technique of forming a groove in an insulating film, depositing copper by a sputtering method, and further performing a heat treatment to satisfactorily fill the groove for forming a wiring. Further, the above-mentioned document (2) discloses a method in which copper is deposited in a groove and a connection hole formed in an insulating film by a sputtering method, and then copper is buried by a plating method.

[0006]

In the buried wiring technology, the following problems occur with the miniaturization of wiring grooves and connection holes and the increase in aspect ratio.

That is, it is difficult to embed the wiring conductor film in the wiring groove or the connection hole by the sputtering method alone, and the groove or the connection hole cannot be sufficiently buried, and the buried wiring (the wiring portion and the connection hole) cannot be buried. Good electrical characteristics cannot be secured.

When the plating method is used, the embedding capability is high, but the underlying metal is required, and the embedding limit is determined by the coverage of the underlying metal. There is a problem to solve the problem of hindering the miniaturization of holes (including holes). Further, when the conductor film is formed by plating, gas accumulated in the wiring groove and the connection hole may be taken into the conductor film, which may lead to the generation of voids.

An object of the present invention is to provide a technique for preventing the occurrence of voids on a wiring surface of a wafer, improving the yield, and reducing conduction defects in the process of forming an electrolytic / electroless plating film.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) a step of filling a liquid on a wiring surface including a wiring groove formed in an insulating film on a semiconductor substrate or a connection hole formed in the wiring groove, and (b) a step of filling a wiring surface of the semiconductor substrate with a liquid. (C) chemically and mechanically polishing the conductive film outside the wiring groove to leave the conductive film in the wiring groove portion, by performing plating and forming a conductive film on the wiring surface; Forming a buried wiring.

According to the above-described manufacturing method, the liquid is filled in the wiring groove and the connection hole formed on the wiring surface, whereby the gas in the wiring groove and the connection hole is removed. In the groove where the conductor film is embedded
Voids that occurred with a probability of 0.5% can be reduced to 0%,
A good conductor film that sufficiently fills the inside of the groove can be formed.

In addition, since the occurrence of voids in the trenches in which the conductor film is buried is prevented by the plating method, conduction defects can be reduced, and the yield and reliability of the semiconductor integrated circuit device can be improved.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) FIG. 1 is a cross-sectional view showing an example of a semiconductor integrated circuit device manufactured according to the present invention.

The semiconductor integrated circuit device according to the first embodiment is
An MISFET (Metal) is formed in the p-well 1b of the semiconductor substrate 1a.
Insulator Semiconductor Field Effect Transistor)
Qn is formed.

The n-channel MISFET Qn includes a gate electrode 4 formed on a main surface of a semiconductor substrate 1a via a gate insulating film 5a, and a semiconductor substrate 1 on both sides of the gate electrode 4.
The semiconductor device has a semiconductor region 3 formed on the main surface of the gate electrode 4a, and a sidewall spacer 5b and a cap insulating film 5c are formed on the side surface and the upper surface of the gate electrode 4, respectively.

The gate insulating film 5a is made of a silicon oxide film having a thickness of several nm, and can be formed by, for example, a thermal CVD method or a thermal oxidation method.

The gate electrode 4 is made of, for example, a low-resistance polycrystalline silicon film, and a lower layer may be formed by forming a silicide layer or a metal layer such as tungsten thereon.

The semiconductor region 3 is an n-channel MISFE
It functions as a source / drain region of TQn, and an n-type impurity such as phosphorus (P) or arsenic (As) is implanted at a high concentration.

[0023] On top of the gate electrode 4 and the semiconductor region _{3, WSi x, MoSi x,} TiSi x, may attempt to lower the resistance by forming a silicide film formed by laminating a refractory metal silicide film such as TaSi _x .

The sidewall spacer 5b and the cap insulating film 5c can be, for example, a silicon oxide film or a silicon nitride film.

An insulating film 7 is formed above the n-channel MISFET Qn. BPSG as the insulating film 7
(Boron-doped Phospho Silicate Glass) membrane or PS
A reflow film such as a G (Phospho Silicate Glass) film can be used.
A stacked film with a silicon oxide film formed by the D method or the sputtering method can also be used. After being deposited, the insulating film 7 is polished by, for example, a CMP method, and its surface is planarized.

A contact hole 8 is formed in the insulating film 7 on the semiconductor region 3.
As will be described later with reference to FIG. 2, the connection hole 8 is formed by a barrier conductor film 9a such as titanium nitride formed by a sputtering method, and formed by a blanket CVD method or a selective CVD method, for example. A conductor film 9b made of tungsten or the like is formed.
The plug 9 includes the barrier conductor film 9a and the conductor film 9b.

An insulating film 10 is formed on the insulating film 7, and a buried wiring 12 is formed in the wiring groove 11 formed in the insulating film 10.
Is formed within.

The insulating film 10 is composed of, for example, a silicon oxide film formed by a CVD method.

As will be described later with reference to FIG. 3, the buried wiring 12 includes a barrier conductor film 12a such as titanium nitride, a seed film 12b made of copper or the like, and a conductor film 12c. Conductive film 12c is made of, for example, copper. By using a material having a low resistivity as the main conductive layer, such as copper, an increase in wiring resistance due to miniaturization of the embedded wiring 12 can be suppressed. This makes it possible to achieve higher performance of the semiconductor integrated circuit device. The barrier conductor film 12a is
It can function as a barrier film for preventing copper, which is a material constituting c, from diffusing into the insulating film 7 and the insulating film 10, and also improves the adhesion with copper deposited in the wiring groove 11. In addition to the titanium nitride film, the barrier conductor film 12a may be, for example, a tantalum film, a tantalum nitride film, a tungsten nitride film, a tungsten film, or a compound of these and silicon.

An insulating film 13 is formed on the buried wiring 12 and the insulating film 10. The insulating film 13 includes a barrier insulating film 13a and an insulating film 13b formed in contact with the buried wiring 12 and the insulating film 10.

The barrier insulating film 13a can be, for example, a silicon nitride film formed by a plasma CVD method, and has a function of suppressing the diffusion of copper forming the conductor film 12c of the embedded wiring 12. Thereby, the barrier conductor film 12
It is possible to prevent the diffusion of copper into the insulating films 7, 10 and 13 together with a, to maintain their insulating properties, and to enhance the reliability of the semiconductor integrated circuit device.

The insulating film 13b can be, for example, a silicon oxide film formed by a CVD method,
It is for ensuring the depth of the.

The groove 15 is formed in the insulating film 13, and a buried wiring 16 as a second metal wiring is formed in the groove 15. Note that a part of the groove 15 also includes a connection hole for connecting to the embedded wiring 12 formed thereunder. That is, a groove and a connection hole are formed, a conductive film is deposited on an insulating film including the inside of the groove and the connection hole, and the conductive film in a region other than the groove is removed by, for example, a CMP method to form a connection wiring and The wiring is formed by a so-called dual damascene method in which wiring is integrally formed.

Like the buried wiring 12, the buried wiring 16 comprises a barrier conductor film 16a such as titanium nitride, a seed film 16b made of copper or the like, and a conductor film 16c. Conductive film 16
c is, for example, copper, and by using a material having a low resistivity as a main conductive layer, it is possible to suppress an increase in wiring resistance due to miniaturization of the embedded wiring 16. This makes it possible to achieve higher performance of the semiconductor integrated circuit device. The barrier conductor film 16a can prevent the material of the conductor film 16c, for example, copper, from diffusing into the insulating film 13 and can prevent the groove 1
5 also improves the adhesion to the copper deposited. Barrier conductor film 1
6a may be, for example, a tantalum film, a tantalum nitride film, a tungsten nitride film, a tungsten film, or a compound thereof with silicon, in addition to the titanium nitride film.

It should be noted that an insulating film and an embedded wiring similar to the insulating film 13 and the embedded wiring 16 may be formed on the embedded wiring 16 to form a multilayer structure.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

First, as shown in FIG. 2, p ^- providing a semiconductor substrate 1a made of single crystal silicon in the form, impurities for the conductivity type of p-type, for example, boron (B) doped by ion implantation or the like Thus, a p-well 1b is formed.

Next, a silicon oxide film serving as a gate insulating film 5a, a polycrystalline silicon film serving as a gate electrode 4, and a silicon oxide film serving as a cap insulating film 5c are sequentially deposited on the main surface of the semiconductor substrate 1a to form a laminated film. Is formed, and the laminated film is etched using a resist patterned by photolithography as a mask to form a gate electrode 4 and a cap insulating film 5c. The gate insulating film 5a can be formed by, for example, a thermal CVD method, and the gate electrode 4
Can be formed by a CVD method, but is doped with an n-type impurity (for example, phosphorus (P)) in order to reduce the resistance value. Incidentally, the upper portion of the polycrystalline silicon _{4 WSi x, MoSi x, TiSi} x,
A refractory metal silicide film such as TaSi _x may be laminated. The cap insulating film 5c can be deposited by, for example, a CVD method.

Next, after a silicon oxide film is deposited on the semiconductor substrate 1a by the CVD method, reactive ion etching (R
This silicon oxide film is anisotropically etched by the IE) method to form sidewall spacers 5b on the side walls of the gate electrode 4, and ion-implant n-type impurities (phosphorus) to form p-wells on both sides of the gate electrode 4. 1b has n-channel MI
The semiconductor region 3 forming the source and drain regions of the SFET Qn is formed. The side wall spacer 5b
A low-concentration impurity semiconductor region may be formed before the formation of the semiconductor layer, and a high-concentration impurity semiconductor region may be formed after the formation of the sidewall spacer 5b.

Next, after depositing a silicon oxide film on the semiconductor substrate 1a by the CVD method, for example,
The insulating film 7 whose surface is flattened is formed by polishing by the MP method. Further, a connection hole 8 is formed in the insulating film 7 on the semiconductor region 3 on the main surface of the semiconductor substrate 1a by using a known photolithography technique.

Next, a barrier conductor film 9a of, for example, titanium nitride is deposited by sputtering, and a conductor film 9b of, for example, tungsten is deposited by blanket CVD.

Next, the plug 9 is formed by removing the barrier conductor film 9a and the conductor film 9b on the insulating film 7 other than the connection holes 8 by, for example, an etch-back method.

Next, as shown in FIG. 3, a silicon oxide film is deposited by a CVD method to form an insulating film 10.

Next, the insulating film 10 is processed by using a known photolithography technique and an etching technique to form a wiring groove 11.

Next, the embedded wiring 1 is formed on the entire surface of the semiconductor substrate 1a.
For example, a titanium nitride film to be the second barrier conductor film 12a is deposited. The titanium nitride film can be deposited by, for example, a CVD method or a sputtering method. The titanium nitride film is deposited to improve the adhesion of the copper film and prevent the diffusion of copper, which will be described later, and has a thickness of about 500 °. In the first embodiment, a titanium nitride film is exemplified. However, a metal film such as tantalum or a tantalum nitride film may be used. In the case where the barrier film is tantalum or tantalum nitride, the titanium nitride film is more suitable than when titanium nitride is used. Good adhesion to copper film. It is also possible to sputter-etch the surface of the titanium nitride film immediately before the next step of depositing the conductor film 12c. By such sputter etching, water, oxygen molecules, and the like adsorbed on the surface of the titanium nitride film can be removed, and the adhesiveness of the conductor film 12c can be improved. In particular, after the deposition of the titanium nitride film, the effect is great when vacuum breaking is performed to expose the surface to the atmosphere and deposit the conductor film 12c.

Next, a thin film of copper, which is a metal to become the conductor film 12c, is deposited, fluidized by heat treatment, and
Embedded well without gaps. For the deposition of the copper film, an ordinary sputtering method can be used, but a physical vapor deposition method such as a vapor deposition method or a plating method may be used. When the plating method is used, the seed film 12b needs to be deposited before depositing the copper thin film, and is deposited by the sputtering method. The condition of the heat treatment requires a temperature and a time at which copper constituting the conductive film 12c is fluidized.
４５０450 ° C., 3 minutes to 5 minutes.

Next, the excess barrier conductor film 12a, seed film 12b and the copper film on the insulating film 10 are removed, and the conductor film 12c, the seed film 12b and the barrier film forming the buried wiring 12 in the wiring groove 11 are formed. The conductor film 12a is formed. The removal of the barrier conductor film 12a, the seed film 12b, and the conductor film 12c is performed by polishing using a CMP method.

Next, a silicon nitride film is deposited on the buried wiring 12 and the insulating film 10 to form a barrier insulating film 13a. For depositing a silicon nitride film, for example, plasma CV
The D method can be used, and the film thickness is about 100 nm.

Next, as shown in FIG. 4, an insulating film 13b is deposited to complete the insulating film 13. The insulating film 13b can be, for example, a silicon oxide film formed by a CVD method.

Next, a groove 15 is formed. The groove 15 also includes a connection hole for connecting to the buried wiring 12 which is a lower wiring. The groove 15 is formed by first forming a photoresist film having the same shape as the connection hole pattern for connecting to the embedded wiring 12 on the insulating film 13 by a photolithography process, and using the photoresist film as a mask to form a connection hole pattern by a dry etching process. Form. Subsequently, the photoresist film is removed, a photoresist film having the same shape as the groove 15 is formed on the insulating film 13 by a photolithography process on the insulating film 13, and the wiring groove pattern is formed by a dry etching process using the mask as a mask. To form

Next, after removing the photoresist film, a barrier conductor film 16a made of titanium nitride or the like, which becomes a part of the buried wiring 16, as in the case of the buried wiring 12.
Is deposited, and then a seed film 16b is deposited.

Next, after the semiconductor substrate 1a is set on the spinning device as shown in FIG. 5, the rotor 104 is rotated at a speed of 300 rpm, and the shaft 100 is moved from the central portion of the semiconductor substrate 1a to the end surface of the wiring by the nozzle 101. To and from pure water 1
Spray 02 for 10 seconds. As the nozzle, for example, an ultrasonic nozzle is used. By spraying pure water 102 on the wiring surface before a plating step described later, the trench 15 can be filled with the pure water 102 and bubbles can be removed. 15 are sufficiently diffused.

Next, after the wiring surface of the semiconductor substrate 1a is placed in a jet device as shown in FIG.
5, the semiconductor substrate 1a is fixed. Subsequently, the pump 110
With the operation described above, the plating solution 108 flows from the plating solution tank 111 into the cell 107. The plating solution 108 is, for example, a copper sulfate plating solution. When the plating solution 108 is filled in the cell 107, it flows uniformly from the center to the end of the semiconductor substrate 1a. In the electrolysis, the plating solution 108 is applied to the semiconductor substrate 1.
Starting after contact with a, an electroplating layer having a thickness of 0.7 μm is formed on the wiring surface of the semiconductor substrate 1a.

Next, after the semiconductor substrate 1a is set in the spin device shown in FIG. 5, the rotor 104 is rotated at a speed of 300 rpm, and the shaft 100 moves the nozzle 101 from the center to the end of the wiring surface of the semiconductor substrate 1a. Reciprocate and spray with pure water for 10 seconds to wash. Subsequently, the rotor 104 is
The semiconductor substrate 1 is rotated at a speed of 000 rpm for 30 seconds.
Dry a.

In an experiment conducted by the inventor, voids 112 as shown in FIG. 7A in which the vicinity of the groove 15 was enlarged in the conventional plating method with a probability of 0.5% as shown in FIG. In the plating method of the present invention described with reference to FIG.
Was reduced to 0%, and a good conductor film 16c sufficiently filling the groove 15 as shown in FIG. 7B was formed.

Finally, the conductor film 16c, the seed film 16b and the barrier conductor film 16a on the insulating film 13 are removed to form the buried wiring 16, whereby the semiconductor integrated circuit device shown in FIG. 1 is almost completed. The CMP method is used to remove the conductor film 16c, the seed film 16b, and the barrier conductor film 16a.

In the present embodiment, the occurrence of voids in the trench 15 in which the conductive film 16c is buried is prevented by plating, so that conduction failure is reduced, and the yield and reliability of the semiconductor integrated circuit device are improved. Can be planned.

(Embodiment 2) In a method of manufacturing a semiconductor integrated circuit device according to Embodiment 2, pure water is applied onto a wiring surface of a semiconductor substrate 1a by using a spin device before a plating step in Embodiment 1 described above. The spraying step is replaced with a step of jetting a copper sulfate plating solution onto the wiring surface of the semiconductor substrate 1a using a jet type apparatus, and the other members and steps are the same as in the first embodiment. Therefore, description of those similar members and steps will be omitted.

The method of manufacturing the semiconductor integrated circuit device according to the second embodiment is the same as that of the first embodiment up to the steps shown in FIGS.

Then, after the semiconductor substrate 1a is installed in a jet device as shown in FIG.
At 05, the semiconductor substrate 1a is fixed. Subsequently, the pump 11
By the operation 0, the plating solution 108 flows from the plating solution tank 111 into the cell 107. The plating solution 108 is a copper sulfate plating solution, except sulfuric acid or hydrochloric acid for etching the seed film. When the plating solution 108 is filled in the cell 107, it flows uniformly from the center to the end of the semiconductor substrate 1a.

The subsequent steps are the same as the steps of the first embodiment shown in FIGS.

According to the second embodiment, the same effects as those of the first embodiment can be obtained.

(Third Embodiment) In a method of manufacturing a semiconductor integrated circuit device according to a third embodiment, pure water is sprayed onto a wiring surface of a semiconductor substrate 1a using a spin device before a plating step in the first embodiment. The step is replaced with a step of filling the groove 15 of the semiconductor substrate 1a with pure water using a bubble removing device, and other members and steps are the same as those in the first embodiment.
Is the same as Therefore, description of those similar members and steps will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIG.

The method of manufacturing the semiconductor integrated circuit device of the third embodiment is the same as that of the first embodiment up to the steps shown in FIGS.

After that, the semiconductor substrate 1a is fixed to the bubble removing device as shown in FIG. Subsequently, after the pressure in the cell 116 is reduced to the atmospheric pressure or less by the pump 115, the pump 115 is stopped.

Next, the cell 116 is filled with pure water, and the trench 15 of the semiconductor substrate 1a is filled with pure water. Cell 116
Since the inside is previously depressurized, the gas in the groove 15 escapes, and the pure water fills the groove 15 without gaps.

Subsequent steps are the same as those shown in FIGS. 6 and 7 in the first embodiment.

According to the third embodiment, since the pressure in the cell 116 is reduced, pure water easily penetrates into the groove 15 and air bubbles in the groove 15 are removed at normal pressure. The bubbles in the groove 15 can be more reliably removed than in the first embodiment.

(Fourth Embodiment) In the method of manufacturing a semiconductor integrated circuit device according to the fourth embodiment, pure water is sprayed on the wiring surface of the semiconductor substrate 1a using a spin device before the plating step in the first embodiment. The step is replaced with a step of filling the groove 15 of the semiconductor substrate 1a with pure water using a bubble removing device, and other members and steps are the same as those in the first embodiment.
Is the same as Therefore, description of those similar members and steps will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIG.

The method of manufacturing the semiconductor integrated circuit device of the fourth embodiment is the same as that of the first embodiment up to the steps shown in FIGS.

Thereafter, the cell 119 of the bubble removing device as shown in FIG. 9 is filled with pure water. Subsequently, after the wiring surface of the semiconductor substrate 1a is placed downward in the bubble removing device, the semiconductor substrate 1a is fixed with the holding jig 117.

Next, the pure water in the cell 119 is heated by the heater 120 for one minute, for example, to raise the temperature of the pure water to the boiling point. Thereafter, pure water is newly introduced into the cell 119, and cooled for two minutes, for example. By lowering the temperature of the pure water to 80 ° C. or lower, the groove 15 of the semiconductor substrate 1a is filled with the pure water.
By raising the temperature of the pure water to the boiling point, the pure water that has become water vapor fills the groove 15 instead of the gas, and the gas escapes from the groove 15. Then, fresh water was added to cell 11
9 and is cooled to form steam.
The pure water that has filled the inside returns to the liquid, and the gap formed in the groove 15 due to the return of the water vapor to the liquid is filled with the pure water that has been newly added.

The subsequent steps are the same as the steps in FIGS. 6 and 7 in the first embodiment.

According to the fourth embodiment, in order to make the pure water permeate into the groove 15 by utilizing the pressure difference between the water vapor and the liquid, air bubbles in the groove 15 are removed at normal pressure. The bubbles in the groove 15 can be more reliably removed than in the first embodiment.

(Fifth Embodiment) In the method of manufacturing a semiconductor integrated circuit device according to the fifth embodiment, pure water is sprayed onto the wiring surface of the semiconductor substrate 1a using a spin device before the plating step in the first embodiment. The step is replaced with a step of filling the groove 15 of the semiconductor substrate 1a with pure water using a bubble removing device, and other members and steps are the same as those in the first embodiment.
Is the same as Therefore, description of those similar members and steps will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIG.

The method of manufacturing the semiconductor integrated circuit device of the fifth embodiment is the same as that of the first embodiment up to the steps shown in FIGS.

Thereafter, the semiconductor substrate 1a is set in a bubble removing device as shown in FIG. 10 with the wiring surface of the semiconductor substrate 1a facing downward, and the semiconductor substrate 1a is fixed by the holding jig 121. Next, pure water 124 flows from the pure water tank 127 to the pipe 126 by the operation of the pump 128. Subsequently, the pure water 124 is sprayed onto the wiring surface of the semiconductor substrate 1a through the nozzle 125, and the cells 1
It flows into 23. When the pure water 124 is filled in the cell 123, it flows uniformly from the center to the end of the semiconductor substrate 1a, filling the groove 15 of the semiconductor substrate 1a.

Subsequent steps are the same as those shown in FIGS. 6 and 7 in the first embodiment.

According to the fifth embodiment, the same effects as in the first embodiment can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the fourth embodiment, it has been described that pure water in a cell is cooled down to 80 ° C. or less by newly introducing pure water into the cell of the bubble removing device. May use a cooling pipe.

Further, in the fifth embodiment, the case where the bubble removing device having the pipe with the nozzle is used is exemplified, but a slit type (with a groove) pipe may be used.

[0086]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.

(1) By a plating method, a good conductor film can be formed without generating voids in fine grooves.

(2) Since the occurrence of voids in the trenches in which the conductor film is buried is prevented by the plating method, conduction defects can be reduced, and the yield and reliability of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1 in the order of steps.

FIG. 3 is a cross-sectional view showing an example of a method for manufacturing the semiconductor integrated circuit device of Embodiment 1 in the order of steps.

FIG. 4 is a cross-sectional view showing one example of a method for manufacturing the semiconductor integrated circuit device of Embodiment 1 in the order of steps;

FIG. 5 is an explanatory view of a spin device for removing air bubbles in the method for manufacturing a semiconductor integrated circuit device according to the first embodiment;

FIG. 6 is an explanatory diagram of a jet type device that performs a bubble removing and plating step in the method for manufacturing a semiconductor integrated circuit device of the first embodiment.

FIGS. 7A and 7B are explanatory views of a groove where a void has occurred and a groove where no void has occurred.

FIG. 8 is an explanatory diagram of an air bubble removing device for removing bubbles in a method of manufacturing a semiconductor integrated circuit device according to a third embodiment.

FIG. 9 is an explanatory view of a bubble removing device for removing bubbles in a method of manufacturing a semiconductor integrated circuit device according to a fourth embodiment.

FIG. 10 is an explanatory diagram of a bubble removing device for removing bubbles in a method of manufacturing a semiconductor integrated circuit device according to a fifth embodiment.

[Explanation of symbols]

 Reference Signs List 1a semiconductor substrate 1b p-well 2 field insulating film 3 semiconductor region 4 gate electrode 5a gate insulating film 5b sidewall spacer 5c cap insulating film 7 insulating film 8 connection hole 9 plug 9a barrier insulating film 9b conductor film 10 insulating film 11 wiring groove 12 Embedded wiring 12a Barrier conductive film 12b Seed film 12c Conductive film 13 Insulating film 13a Barrier insulating film 13b Insulating film 15 Groove 16 Embedded wiring 16a Barrier conductive film 16b Seed film 16c Conductive film 100 Shaft 101 Nozzle 102 Pure water 104 Rotor 105 Holder Jig 106 Cathode 107 Cell 108 Plating solution 109 Anode 110 Pump 111 Plating solution tank 112 Void 113 Holding jig 115 Pump 116 Cell 117 Holding jig 119 Cell 120 Heater 121 Holding jig 23 cell 124 Pure water 125 nozzles 126 piping 127 pure water tank 128 pump Qn n-channel type MISFET

Continued on the front page F-term (reference) 4M104 BB18 BB30 BB32 BB33 CC01 DD08 DD16 DD17 DD19 DD37 DD52 FF18 FF22 HH13 5F033 HH04 HH11 HH19 HH27 HH28 HH29 HH30 HH32 HH33 HH34 JJ19 JJ21 KK32 MM33 NN06 NN07 PP06 PP07 PP15 PP27 QQ09 QQ10 QQ11 QQ37 QQ48 RR04 RR06 RR14 RR15 SS08 SS11 SS15 TT02 TT08 XX02

Claims (7)

[Claims] 1. A step of filling a liquid on a wiring surface including a wiring groove formed in an insulating film on a semiconductor substrate or a connection hole formed in the wiring groove, and (b) wiring on the semiconductor substrate. Forming a conductive film on the wiring surface by plating the surface, and (c) chemically and mechanically polishing the conductive film outside the wiring groove to form the conductive film in the wiring groove portion. Forming a buried wiring by leaving it. A method for manufacturing a semiconductor integrated circuit device, comprising: 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said liquid is pure water, at least one component of an electrolytic plating solution, or at least one component of an electroless plating solution. A method for manufacturing a circuit device. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said liquid discharged from a nozzle is sprayed and permeated onto said wiring surface using a spin device. A method for manufacturing an integrated circuit device. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the liquid surface is evacuated, and then the liquid is allowed to permeate the wiring surface. A method for manufacturing a circuit device. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the boiling liquid is permeated into the wiring surface, and then the cooled liquid is permeated. Of manufacturing a semiconductor integrated circuit device. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a nozzle or a pipe with a slit is provided at a tip of the pump pipe, and a liquid discharged from the nozzle or the pipe with a slit is provided. A semiconductor integrated circuit device. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said conductor film is a copper film.