JP2012246216A - Method for forming nanostructure on substrate and use of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon substrate which exhibits reduced reflectivity.SOLUTION: The disclosure is directed to a method for forming nanostructures on a substrate including silicon comprising the steps of: (a) depositing a layer of transition metal on the surface of the substrate; (b) annealing the layer of the transition metal to form a patterned transition metal layer; and (c) etching the substrate to form the nanostructures on the substrate surface.

Description

  The present invention relates to a method for producing nanostructures on a silicon-containing substrate and the use thereof.

  Silicon (Si) with various structural forms and crystal orientations is widely used in optoelectronic devices and solar cell applications. However, flat silicon has an inherently high reflectivity that exhibits a strong spectral dependence. Therefore, efficient suppression of reflections over a wide spectral range has been studied, and numerous solutions have been proposed to overcome this technical problem.

  In one known approach, deep surface texturing has been proposed with the aim of reducing the surface reflectivity of the silicon substrate. For example, a smooth silicon substrate surface can be subjected to etching to obtain a Si rough surface (ie, “texturing”). With such texturing, the roughened Si surface can exhibit reduced reflectivity. However, one limitation of such a “texturing” method is that it is applicable only to silicon having a specific type of surface orientation, ie silicon <100>. It has also been found that Si substrates with deep surface texturing tend to exhibit reflectivity that increases rapidly with the angle of incident light.

Thus, in another known approach, anti-reflective coatings such as SiO _x coatings, Si ₃ N ₄ coatings, TiO _x coatings, and the like are provided on the silicon substrate surface. One limitation of such an approach is that each type of anti-reflective coating is typically only useful for reduced reflectivity in a limited spectral range and only for a specific angle of incidence. In the point. Thus, the use of anti-reflective coatings is not suitable for reducing reflectivity when the Si substrate is subjected to a broad spectrum of radiation, for example solar radiation over a wide range of wavelengths.

  To overcome this drawback, it has also been proposed to provide a two-layer anti-reflective coating. Such double layer coatings can improve the reduction of reflectivity, but the production of these coatings is difficult, expensive to apply and may lack effectiveness when used in photovoltaic modules. Are known.

  Yet another approach to solving the above technical problem is catalytic etching. However, this technique has the following disadvantages. First, catalytic etching is not suitable for producing complex three-dimensional (3D) nanostructures on a silicon substrate. Furthermore, with this technique, it is difficult to provide high aspect ratio structures with varying degrees of complexity, especially when the structures are smaller to the nanosize range.

Another proposed technique involves irradiation of the Si substrate with a laser pulse in the presence of a halogen gas. In this technique, spike formation is strongly dependent on the characteristics of the laser pulse. The laser pulse must be very fast and very strong, and the irradiation must be carried out in the presence of a halogen, for example SF ₆ . However, the drawback of this technique is the low controllability of the Si substrate etch depth and etch uniformity, which results in large variations in etch depth across the Si wafer.

  Accordingly, there is a need to provide a method for manufacturing a silicon substrate exhibiting reduced reflectivity that overcomes or at least ameliorates the above technical problems.

  In one aspect, a method for providing nanostructures on a silicon-containing substrate comprising: (a) depositing a transition metal layer on a surface of the substrate; and (b) annealing the transition metal layer. Providing a patterned transition metal layer; and (c) etching the substrate to form nanostructures on the substrate surface.

  Advantageously, the present disclosure provides a simple and effective method for producing a silicon substrate with low reflectivity, the patterned silicon substrate being suitable for use in making photovoltaic devices and as an anode. In addition, it functions as a starting template for the fabrication of optoelectronic devices. Specifically, the method can provide a silicon substrate that exhibits low reflectivity over a broad radiation spectrum (“black silicon”) and does not require the application of one or more layers of antireflective coatings.

  More advantageously, the method reduces the reflectivity of any surface orientation (eg, <100>, <111>, <010>, <001>, <110>, <011>, <101>). It is effective for producing a patterned silicon substrate.

  More advantageously, surprisingly, the patterned silicon substrate made according to the above method has a band gap such as gallium nitride (GaN) with a greatly reduced density of surface defects (such as cracks and etch pits). It has been found that it can be used to grow a wide layer of semiconductor material. Advantageously, this allows the surface-modified silicon substrate produced by the above method to function as a starting template for optoelectronic devices.

  In another aspect, there is provided a patterned silicon substrate comprising nanostructures on exposed surfaces produced by the above method.

  In another aspect, there is provided the use of a patterned silicon substrate as defined above for the deposition and growth of a gallium nitride (GaN) layer.

  In yet another aspect, the use of a patterned silicon substrate as defined above for the manufacture of photovoltaic (PV) devices is provided.

  In yet another aspect, the use of a patterned silicon substrate as defined above as an anode is defined.

In another aspect, a method for depositing an aluminum nitride (AlN) layer on a silicon substrate having a patterned surface, comprising: (a) providing a patterned silicon substrate as defined above; ) Passing trimethylaluminum (TMA) over the patterned surface to deposit an Al layer on the surface; and (c) depositing a layer of Al on the patterned surface at a predetermined V / III ratio and temperature. Passing TMA and ammonia (NH ₃ ) to effect deposition of AlN on the patterned surface; and (d) adjusting the temperature and V / III ratio in step (c) to achieve two-dimensional AlN growth. A method is provided.

  In one embodiment, the adjusting step includes an initial decrease in temperature and V / III ratio during step (b).

  In another embodiment, the adjusting step further comprises, during step (b), after the initial decrease in temperature, increasing the temperature again to the initially determined temperature while maintaining the V / III ratio.

  In another embodiment, the adjusting step further comprises reducing the V / III ratio by at least 50%.

  In yet another embodiment, the initial decrease in temperature during step (b) is a decrease of 150 ° C. or higher.

  Advantageously, effective two-dimensional growth of the AlN buffer layer can be achieved by adjusting the temperature and / or V / III ratio during step (b) as defined above. The AlN buffer layer grown according to the above-described method can function as a template for growing the GaN layer. Advantageously, it has been found that a GaN layer grown on the above-described patterned silicon substrate with an AlN buffer layer reduces the strain that occurs in the crystal lattice. The reduction in strain can be demonstrated by the lower density of pit defects found in the surface morphology of the grown GaN layer.

  Accordingly, in yet another aspect, a method for providing indium gallium nitride (InGaN) / GaN multiple quantum wells (MQWs) on a silicon substrate, the patterning defined above (i) Providing a silicon substrate; (ii) depositing an AlN layer on the patterned silicon substrate according to the method defined above; and (iii) further depositing alternating layers of GaN and AlN layers thereon. Achieving a desired thickness is provided.

  The accompanying drawings illustrate the disclosed embodiments and serve to explain the principles of the disclosed embodiments. However, it should be understood that the drawings have been prepared for purposes of illustration only and are not intended to define the limitations of the present invention.

FIG. 6 is a schematic diagram illustrating steps for generating nanostructures on a substrate comprising silicon. FIG. 6 is a schematic diagram illustrating steps for generating nanostructures on a substrate comprising silicon and silicon oxide. It is an atomic force microscope (AFM, atomic force microscope) image of the nanodot formed by the rapid annealing step. FIG. 3b is a graph showing a temperature profile of annealing to form the nanodots in FIG. 3a. It is a top view of the AFM image of the formed nanodot. 3c is a cross-sectional analysis plot across the line width shown in FIG. 3c, showing that the size distribution of the nanodots is about 40-80 nm wide and 20-30 nm high. It is a scanning electron microscope (SEM) image of the nanostructure formed on the substrate surface after etching, and the thickness of the deposited layer of transition metal (Au) was 3 nm. It is the SEM image of the nanostructure formed on the substrate surface after the etching, and the thickness of the deposited layer of transition metal (Au) was 6 nm. It is the SEM image of the nanostructure formed on the substrate surface after the etching, and the thickness of the deposited layer of transition metal (Au) was 9 nm. It is the SEM image of the nanostructure formed on the substrate surface after the etching, and the thickness of the deposited layer of transition metal (Au) was 12 nm. 4B is an SEM image showing the substrate of FIG. 4a after cleaning with a buffered oxide etch (BOE) solution. 4b is a SEM image showing the substrate of FIG. 4b after cleaning with BOE solution. 5 is an SEM image showing the substrate of FIG. 4c after cleaning with a BOE solution. 5 is an SEM image showing the substrate of FIG. 4d after cleaning with a BOE solution. 6 is a three-dimensional AFM image and line scan profile for each substrate sample in FIGS. It is the contact angle measurement result performed with respect to Si nano pillar (left) and the conventional silicon (111) wafer (right). 5 is a reflectance plot of exposed silicon versus substrate after etching of FIGS. It is a cross-sectional SEM image of a silicon nano pillar. Cross-sectional SEM image showing growth of gallium nitride (GaN) using low temperature aluminum nitride (LT-AlN, low temperature aluminum nitride) interlayer on Si nanostructure surface template, inset shows high temperature AlN nanostructure growth The interface of the Si (111) made to show is shown. It is a SEM image which shows the defect observed in GaN grown on the conventional Si (111). FIG. 6 shows GaN using multiple AlN buffer layers grown on Si nanopillars at different temperatures and V / III ratios. FIG. 4 shows GaN using a plurality of AlN buffer layers grown on conventional Si (111) at different temperatures and V / III ratios. It is a graph plot which shows the photoluminescence (PL, photoluminescence) measurement result in various temperatures performed with respect to the conventional indium gallium nitride (InGaN) / GaN multiple quantum well (MQW) on Si (111). It is a graph plot which shows the photoluminescence (PL) measurement result in various temperature performed with respect to the indium gallium nitride (InGaN) / GaN multiple quantum well (MQW) on Si nano pillar. It is a SEM image which shows the form of the InGaN / GaN sample on the conventional Si (111) [left] and Si nano pillar [right]. 2 is an SEM image of Si nanoneedles having a diameter of about 20 nm and a length greater than 1 μm suitable for use in photovoltaic (PV) applications. 2 is a PL spectrum in different regions of GaN on a Si wafer. It is a photograph which shows the comparison of the black Si wafer (left) which has the conventional bright Si wafer (right) versus a nano pillar. It is a transmission electron microscope (TEM) image which shows reduction of a threading dislocation (bright distortion line) and a double stack AlN buffer layer. It is a SEM image which shows the growth of a HT-AlN buffer layer. FIG. 5 is an SEM image showing the growth of double / multiple stack AlN buffer layers on Si nanopillars (growth at various temperatures and V / III ratios). FIG. 15b is an SEM image of a GaN layer grown on the conventional AlN layer of FIG. 15a. FIG. 15b is an SEM image of a GaN layer grown on the conventional AlN layer of FIG. 15b. FIG. 3 is a schematic diagram showing the steps of growing a double / multiple stack AlN buffer layer on Si nanopillars by adjusting temperature and V / III ratio. FIG. 3 is a schematic diagram showing steps for growing a single HT-AlN layer on Si nanopillars. It is a SEM image of the surface form of Au nanodot patterned GaN anode.

Definitions As used herein, the following words and terms shall have the meanings set forth below.

In the context of this specification, the term “V / III ratio” refers to a group V element that is passed across a wafer surface to grow a microcrystalline structure (eg, AlN, GaN, AlGaN, etc.) on the wafer surface ( For example, it should be construed to refer to the molar ratio of N) and Group III elements (eg, Al, Ga, etc.). The V / III ratio depends on the molar precursor ratio at a particular temperature and pressure. The V / III ratio can be changed / adjusted by changing the flow rate of the molar precursor (eg, TMA, NH ₃ ) that is passed over the wafer surface for reaction.

  The term “nanosize structure” or “nanostructure” as used herein shall be construed to refer to a structure having a width and / or height dimension of 10 nm to 1,500 nm.

  The term “substantially” does not exclude “completely”; for example, a composition that is “substantially free” of Y may not be completely free of Y. If desired, the word “substantially” may be excluded from the definition of the present invention.

  Unless otherwise specified, "includes" and "includes", and grammatical variations thereof, are intended to represent "unrestricted" or "inclusive" languages, which are listed elements Including the additional elements not listed.

  As used herein, the term “about” typically refers to +/− 5% of the indicated value, more typically, relative to the concentration of the ingredients of the formulation. +/− 4% of the value, more typically +/− 3% of the indicated value, more typically +/− 2% of the indicated value, even more typically the indicated value Means +/- 1%, even more typically +/- 0.5% of the indicated value.

  Throughout this disclosure, certain specific embodiments may be disclosed in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the disclosed ranges. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges and individual numerical values within that range. For example, the description of ranges such as 1 to 6 includes subranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, and individual numbers within the range, 1, 2, 3, 4, 5, 6 and the like should be considered as specifically disclosed. This applies regardless of the width of the range.

Disclosure of Optional Embodiments An exemplary non-limiting embodiment of a method for providing nanostructures on a silicon-containing substrate is now disclosed.

  The substrate can essentially comprise crystalline Si. The substrate may further include one or more layers of oxidized Si. In one embodiment, the substrate is selected to be substantially pure Si. The Si substrate can have any surface orientation selected from the group consisting of <100>, <111>, <010>, <001>, <110>, <011>, <101>. In one embodiment, the Si substrate has a surface orientation <111>.

In another embodiment, the Si substrate includes an additional layer of SiO ₂ on its surface for receiving a deposited layer of transition metal.

  The depositing step (a) of the disclosed method may include a physical vapor deposition (PVD) step. PVD may be selected from the group consisting of sputter deposition, vapor deposition, cathodic arc deposition, electron beam (e-beam) physical vapor deposition, pulsed laser deposition, and combinations thereof. In one embodiment, the depositing step (a) comprises sputtering the transition metal layer on the substrate surface. In yet another embodiment, an e-beam PVD process is used to deposit a layer of transition metal on the substrate.

  Transition metals deposited on the substrate are Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Hf, Ta, W , Re, Os, Ir, Pt, and Au. In one embodiment, the transition metal is selected to be Au.

  The transition metal layer can be deposited at a thickness of 2-20 nm, 2-4 nm, 2-6 nm, 2-8 nm, 2-10 nm, 2-12 nm, 2-14 nm, 2-16 m or 2-18 nm. In specific embodiments, the transition metal layer is deposited at a thickness of about 3 nm, about 6 nm, about 9 nm, about 12 nm, about 15 nm, and about 18 mm.

  The annealing step (b) may be performed at a temperature below 1000 ° C. In one embodiment, the annealing step (b) is performed at a temperature below 800 ° C. In yet another embodiment, the annealing temperature is from about 400 ° C to about 750 ° C. In yet another embodiment, the annealing temperature is between about 400 ° C and about 500 ° C. Furthermore, the step of annealing may be performed for a period of 10 seconds to 120 seconds. The duration of annealing may depend on the temperature at which the annealing step is performed. In another embodiment, the annealing step may be performed for a period of 30 to 90 seconds, and the annealing temperature is 400 ° C to 500 ° C.

  After the step of annealing, a patterned transition metal layer may be formed on the Si substrate. The patterned transition metal layer may include discrete transition metal nanoparticles.

  In one embodiment, after annealing, the patterned transition metal layer may have a configuration of a plurality of discrete ball-shaped nanoparticles or nanodots dispersed throughout substantially the entire surface area of the substrate. The nanodot may be a sphere, an ellipse, or an ellipse.

The etching step (c) may be performed using a gas etchant containing at least one halogen gas and an inert gas. The halogen gas may be a reactive species selected to isotropically etch the substrate layer. The halogen gas can be selected from Cl ₂ , Br ₂ , or F ₂ . In one embodiment, the halogen gas is Cl _2. The inert gas species may be any suitable non-active species selected to provide a physical impact for breaking the Si-Si bond. In one embodiment, the inert gas is argon. The gas flow ratio of halogen gas to inert gas in the etchant can be selected from the group consisting of 9: 1, 8: 1, 7: 1, 6: 1, 5: 1, 4: 1 and 3: 1. In one embodiment, the etchant may have a flow rate ratio of halogen to inert gas of 6: 1. Advantageously, the ratio of halogen gas to inert gas can be suitably controlled to affect the etching rate.

  In one embodiment, the etching step (c) includes an inductive coupled plasma (ICP) etch. In another embodiment, the etching step (c) may include reactive ion etching (RIE). The etching step may be performed for about 5 seconds to about 60 seconds, about 5 seconds to 120 seconds, about 5 seconds to about 180 seconds, about 5 seconds to about 240 seconds, or about 5 seconds to about 300 seconds. In one embodiment, the etching step may be performed for a period of 5 seconds to 60 seconds.

  During the initial etch phase, for example 10-30 seconds of etching, the etchant may etch the substrate anisotropically, i.e. only in regions of the substrate not covered by the transition metal layer / nanodots. . As the etching step proceeds, the etchant may also partially etch the transition metal nanodots to reduce the size of the nanodots.

  After the etching step, the substrate may exhibit a patterned surface. The patterned substrate layer may include discrete or interconnected island nanostructures. Discrete nanostructures can be cylindrical structures, columnar structures (“nanopillars”), pyramid structures, conical structures (“nanocones”), domed structures (“nanodomes”), acicular structures (“nanoneedles”), tapered structures or these May be included. It has been found that shallow ICP etching can result in the formation of nanopillars, nanocones, nanodomes, and interconnected island nanostructures. Alternatively, a nanoneedle structure can be obtained by deep RIE etching.

  The nanostructures may include a width dimension of about 55 nm to about 250 nm and a height dimension of about 50 nm to about 1200 nm. One nanostructure may be separated from adjacent nanostructures by a minute spacing. The spacing may be from about 25 nm to about 100 nm.

  Advantageously, the disclosed method is flexible in that it can provide a variety of nanostructures. In addition, the annealing period can be increased and / or the annealing temperature can be increased to form finer nanodots in the transition metal layer, thereby allowing the formation of finer nanostructures. It becomes.

  Furthermore, it has been found that if the etching step results in partial etching of the transition metal nanodots, pyramidal or conical nanostructures are formed on the patterned substrate.

  In another embodiment, the patterned substrate may include discrete dome-shaped nanostructures. In yet another embodiment, the patterned substrate may include domed nanostructures that form a network of island-like features that overlap and interconnect with one or more adjacent nanostructures.

In another embodiment of the disclosed method, SiO ₂ layer may be provided on the Si substrate. The transition metal layer can be deposited on the SiO ₂ layer rather than directly on the substrate layer. In order to improve the adhesion between the metal layer and the SiO ₂ layer, one or more transition metal layers may be provided continuously. In one embodiment, a Cr or Ni layer may be deposited on the SiO ₂ layer prior to the deposition of the Au layer. In one embodiment, the SiO ₂ layer, if present, may be provided with a thickness of about 10 nm to about 400 nm.

Advantageously, the high selectivity of SiO ₂ over metal allows anisotropic etching, thereby contrasting with tapered sidewalls (eg cone or pyramid structures) when no SiO ₂ layer is provided. In addition, a patterned Si substrate having substantially vertical sidewalls is obtained.

  An exemplary non-limiting embodiment of a method for depositing an AlN layer on a silicon substrate having a patterned surface is now disclosed.

In one embodiment, a method for depositing an AlN layer on a silicon substrate having a patterned surface, comprising: (a) providing a patterned silicon substrate manufactured by the method described above; Passing trimethylaluminum (TMA) over the patterned surface to deposit a layer of Al on the surface; and (c) TMA and ammonia (NH) on the patterned surface at a predetermined V / III ratio and temperature. ₃ ) passing through to cause deposition of AlN on the patterned surface; and (d) adjusting the temperature and V / III ratio in step (c) to provide two-dimensional AlN growth. A method is provided.

Advantageously, first depositing a layer of Al on the patterned Si substrate prevents unwanted reactions between NH ₃ and Si during step (c) in which AlN crystallites are formed. It has been found that Specifically, the formation of SiN _x crystals is prevented by having an Al protective layer.

  The passing step (c) may be performed at a temperature of 1000 ° C. to about 1100 ° C. Passing step (c) may also be performed at a V / III ratio of 100-1500 as determined by the chamber design. V / III ratio is 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700, 750, 800, 850, 900, 950, 1000, 1050, 1100, 1150, It may be selected from the group consisting of 1200, 1250, 1300, 1350, 1400, 1450, and 1500. In one embodiment, the passing step (C) may be performed at a temperature of 1050 ° C. and a high V / III ratio of 411. During this step, AlN crystallites can form in the nanostructured grooves.

During the adjusting step (d), the V / III ratio can be reduced by 40%, 50%, 60% or 70%. In one embodiment, the adjusting step (d) comprises a reduction of at least 50% or more of the V / III ratio. In one embodiment, the V / III ratio can be reduced by increasing the flow rate of TMA relative to NH ₃ . The adjusting step (d) may further include a step of reducing the temperature by 150 ° C. or more. Advantageously, lowering the temperature and V / III ratio results in more Al atom injection and lowers the diffusion probability of Al adatoms. This nucleates and forms AlN microcrystals on the sidewalls and tips of the nanostructures.

  The adjusting step (d) may further include a step (d2) of raising the temperature to the temperature of step (c) again. In one embodiment, the adjusting step (d) may comprise increasing the temperature to 1050 ° C. while maintaining the V / III ratio. Advantageously, this promotes coalescence of AlN crystallites with high energy Al adatoms, resulting in effective 2D growth of the AlN layer. Also, pores can be formed on the planarized AlN layer under conditions that result in the formation of planarized porous AlN.

  In an alternative embodiment of the method for depositing an AlN layer on a patterned silicon substrate, the adjusting step may optionally be omitted. In this embodiment, AlN crystallites are grown at a constant high temperature and V / III ratio. By doing so, larger AlN crystallites and platelets can be formed compared to AlN crystallites grown at lower temperatures and V / III ratios. In this embodiment, the AlN layer is 3D crystal grown. During the process, several voids can be formed in the AlN crystallites, which can lead to a meltback effect.

  The above method results in the formation of a patterned Si substrate layer that includes a high temperature AlN (HT-AlN) buffer layer deposited on the Si substrate nanostructure. Advantageously, this Si substrate with an HT-AlN buffer layer can subsequently be used to grow a GaN layer thereon.

  Accordingly, another aspect of the present disclosure is a method for providing an InGaN / GaN multiple quantum well (MQW) on a patterned silicon substrate, comprising: (i) providing a patterned silicon substrate as defined above And (ii) depositing an HT-AlN layer on the patterned silicon substrate according to the method described above; and (iii) further depositing alternating layers of GaN and AlN layers thereon to obtain a desired thickness. And achieving the method.

In one embodiment, an HT-AlN buffer layer is formed on a Si substrate, and then trimethylgallium (Ga (CH ₃ ) ₃ ) or “TMGa”, trimethyl gallium) and TMA are flowed over the substrate to produce HT- An AlGaN buffer layer is grown on the AlN layer. The TMGa to TMA flow rate may be a ratio of about 1: 7, 1: 7.5, or 1: 8. The AlGaN layer may be grown at a temperature of 1025 ° C. The AlGaN layer may have a thickness of about 200 nm.

After the AlGaN layer is grown, the GaN layer is grown at the same temperature and pressure while maintaining a low NH ₃ flow rate to prevent meltback. In one embodiment, the TMGa flow rate may be about 15-30 sccm (cubic centimeter per minute). The flow rate of TMA may be about 80-150 sccm, and the flow rate of NH ₃ is about 5-20 slm (liter per minute). The grown GaN layer may have a thickness of about 250 nm.

  Thereafter, an AlN intermediate layer (LT-AlN) may be grown on the GaN layer at a low temperature of about 600 to 700 ° C. The LT-AlN intermediate layer may have a thickness of 2 to 3 nm or less. Advantageously, the AlN intermediate layer functions to reduce stress and strain in the crystal structure and improves the n-GaN layer on the Si substrate.

  An additional GaN layer may be grown on the LT-AlN intermediate layer, followed by another LT-AlN intermediate layer and another GaN layer. This process may be repeated until the desired GaN thickness is obtained.

  The resulting GaN template grown on a patterned Si substrate can be used to grow InGaN / GaN multiple quantum wells and pGaN to form a light emitting diode.

[Example]
Reference will now be made in more detail to non-limiting examples of the present invention by reference to specific examples, which should in no way be construed as limiting the scope of the invention.

Fabrication of patterned Si substrate First, the Si (111) wafer substrate is cleaned in a piranha solution, which is a mixture of sulfuric acid H ₂ SO ₄ and hydrogen peroxide (H ₂ O ₂ ) in a volume ratio of 4: 1. . The purpose of this cleaning step is to remove organic contaminants from the wafer surface.

The Si substrate is then cleaned in hydrofluoric acid (HF) diluted with ammonia fluoride (NH 4 F) and deionized (DI) water (also known as buffered oxide etching, “BOE”). BOE wets the surface of the Si substrate uniformly and the HF component removes any SiO ₂ present on the substrate surface. The pure Si surface is blown dry and used immediately in the next step.

  A thin layer of Au is deposited on the Si substrate layer by a sputtering step in which Au plasma is generated using a gold (Au) target source.

After the Au layer is sputtered on the Si surface, the Si substrate is annealed in the presence of N ₂ at 400 to 500 ° C. for 30 seconds to 90 seconds by a rapid thermal annealing system.

In the presence of N ₂ , the Au particles aggregate due to the surface tension effect to form a ball-like structure or a nanodot structure. Also, some of the Au particles diffuse into the Si substrate during the annealing process. Due to partial diffusion, self-assembled Au nanodots (which later function as etching masks) can be obtained by wet chemical etching, particularly using silver nitrate (AgNO ₃ ) / HF or HF / nitric acid (HNO ₃ ) / acetyl acid (H-Ac) etchants. If done, it is ensured that it is not easily removed during the etching step. In some cases, SiO ₂ is used as a sacrificial layer prior to metal nanodot deposition in order to improve adhesion between the metal nanodots and the oxide layer.

Subsequent etching is performed at a flow ratio of 6: 1 using inductively coupled plasma etching (ICP) in a chlorine (Cl ₂ ) gas and argon (Ar) atmosphere. A typical Cl ₂ gas flow rate may be about 18-50 sccm. While the Cl ₂ gas enables isotropic etching, the neutral gas Ar gives a physical impact and breaks the bonds between Si atoms.

  Referring to FIG. 1, the schematic diagram illustrates one embodiment of the disclosed method for preparing a patterned substrate. A pure Si substrate 2 is provided by cleaning with BOE to remove residual surface oxide. Thereafter, the Au layer 4 is deposited on the Si substrate 2 by a sputtering process. Next, rapid thermal annealing of the Au layer 4 is performed, whereby Au nanodots 6 dispersed on the surface of the Si substrate 2 are formed. Next, ICP or RIE etching is performed.

  During the initial etching step of 10 seconds to 30 seconds, anisotropic etching proceeds in a region of the Si substrate that does not have Au nanodots functioning as a mask, and trenches 8 are formed. At this time, the masked substrate region 10 is not etched.

  However, as etching progresses, the Ar gas etchant also gradually etches Au atoms, reducing the size of Au nanodots over time. Partially etched Au nanodots 14 have a lower masking effect, and the etched Si surface will exhibit nanopyramid or nanoconical structures 12.

In some embodiments, a layer of SiO ₂ (thickness 10 to 400 nm) is provided prior to deposition of the transition metal. Referring to FIG. 2, a schematic diagram of an exemplary method according to the present invention for preparing a patterned Si substrate is shown, where the nanostructure has substantially vertical sidewalls (“nano pillars”).

In FIG. 2, like numerals indicate like features according to FIG. A pure Si substrate 2 ′ is obtained by cleaning with an H ₂ SO ₄ / H ₂ O ₂ solution. Next, a SiO ₂ layer 16 is deposited on the Si substrate 2 ′. Subsequently, one or more metals (Cr, Ni, Au) can be sputtered onto the SiO ₂ layer 16 to form the metal layer 4 ′. Next, rapid thermal annealing is performed to form a plurality of metal nanodots 6 ′ dispersed on the surface of the substrate 2 ′. Next, when ICP / RIE etching is performed, a trench 8 ′ is formed in the SiO ₂ layer 16. In this regard, it should be noted that due to the difference in selectivity, the SiO ₂ layer 16 is etched preferentially over the metal nanodots 6 ′.

Next, the metal nanodots 6 ′ are removed from the SiO ₂ layer 16 by ultrasonic irradiation. As can be seen, the etched SiO ₂ layer now functions as a mask for the Si substrate 2 ′. When ICP / RIE etching is further performed, a trench 18 is formed in the Si substrate 2 ′. Finally, the residual SiO 2 layer is removed by cleaning in a BOE solution to form a patterned Si substrate 20 having a nanostructure with substantially vertical sidewalls.

Fabrication of patterned Si substrates with various thicknesses of Au layers Based on the above protocol, four patterned Si substrates with various thicknesses of Au (samples A to D), namely sample A (3.0 nm), Sample B (6.0 nm), Sample C (9.0 nm), and Sample D (12.0 nm) were prepared. These samples were made using the protocol described in Example 1. The etching step was performed at about 20 ° C.

  4a-4d (corresponding to samples AD) show SEM images of the patterned Si substrate after the etching step. As can be seen from the SEM image, sample A includes a nanopillar structure. As the Au layer becomes thicker, domed nanostructures begin to form (as observed in FIG. 4b). When the Au layer was even thicker, the domed nanostructures (nanodomes) eventually fused (as observed in FIGS. 4c and 4d) to form interconnected island structures.

  The sample was then cleaned in BOE for 5 minutes at 60 ° C. to remove any residual oxide that may have formed during the etching process. As can be seen from FIGS. 5 (a) to 5 (d) corresponding to samples A to D, respectively, the nanostructure becomes clearer after the cleaning step.

Characterization of Nanostructures on Si Substrate Atomic Force Microscope The nanostructures (from Example 2) formed on each of samples AD were investigated under an atomic force microscope (AFM) and their characterization results (Nanostructure dimensions, surface roughness) are shown below and in FIG.

  From FIG. 6, it can be seen that for the same etching conditions but with larger Au nanodots, not only is the size of the Si nanostructure formed larger, but the depth of etching also increases. Furthermore, if the Au nanodot mask is larger, the surface roughness of the sample will also increase. This is probably due to differences in the diffusion rate of plasma radicals into the nanopatterned Au dots during the etching process.

  From the AFM line scan, it can be seen that the sidewalls of the Si nanostructure are tapered and not vertical. This is considered due to physical etching of Au nanodots by Ar gas. Thus, from the above, it is shown that the disclosed method can produce different types of nanostructures on a Si substrate surface, including but not limited to nanopillars, nanodomes, and / or interconnected islands. Can be done.

Contact angle measurement Contact angle measurement was performed on the Si substrate of sample A as compared to a conventional exposed Si wafer of the same orientation (111). The result of this measurement is shown in FIG. Specifically, the contact angle of the nanopillar of sample A is about 101 °, while the contact angle of the smooth exposed Si substrate is about 79 °.

  This result can indicate that a patterned Si substrate with nanopillars is more hydrophobic than a conventional Si wafer. Importantly, it should be noted that the nature of the wafer surface can affect subsequent layers of deposited material that can be grown thereon. For example, in the case of GaN growth on Si, the hydrophobicity of the wafer surface can facilitate the three-dimensional growth and nucleation of AlN islands, which can facilitate the production of good quality AlN buffer layers.

Sample reflectance The reflectance of each of Samples A to D was investigated and compared to exposed Si. The results are shown in FIG.

  As can be seen from FIG. 8, the reflectance of the Au nanodot etched sample is close to 10% compared to 40% of the exposed Si for the visible wavelength (400 to 650 nm). This result suggests that the surface of the Si (111) substrate does not reflect light from the sample surface. Pictures of black Si generated according to the above protocol are also shown in FIGS. 14 (a) and (b).

Cross-sectional analysis A cross-sectional SEM of Si (111) is as shown in FIG. Sharp Si (111) nanopillars are different or scatter light in different directions, reducing the reflectivity of Si and increasing its availability to solar cells. The nanostructure also minimizes the probability of internal reflection of light emission from the GaN (light emitting diode) LED due to the high refractive index η _GaN = 2.33 compared to air. This will extract only about 4% of the light from the LED.

Growth of GaN templates on Si (111) nanostructures with high temperature (HT) -AlN and low temperature (LT) -AlN interlayers In this example, Applicants are using patterned Si substrates with nanostructures (nanopillars). It is used for GaN growth and compared with a GaN layer grown on a conventional Si substrate. The comparison results are shown in FIG.

  Specifically, this example demonstrates that a patterned Si substrate according to the present invention can be used as a template to produce a crack-free GaN layer with an LT-AlN intermediate layer applied.

  A microscope image of a conventional GaN surface on Si is shown in FIG. 10a, where crack lines and etch pits can be clearly observed. In contrast, GaN grown on a patterned Si substrate (as shown in FIG. 10b) is substantially free of defects.

For the growth of the AlN interlayer, we have selected conditions that result in double / multiple AlN layer growth. The method will be described more clearly with reference to FIG. First, an Al layer 24 is deposited as a protective layer on a patterned Si substrate 22 having a plurality of nanostructures 26. The purpose of the Al layer 24 is to prevent the interaction between Si and NH ₃ gas (passed later). This prevents the formation of SiNx harmful to the growth of GaN.

  Since the Si nanostructure 26 is non-planar, a longer TMA flow is used during the formation of the seed layer 24 to ensure that the entire surface is coated with the Al seed layer 24. The temperature for depositing the seed Al layer is 1000 to 1035 ° C.

Next, TMA and NH ₃ are allowed to flow over the surface of the Si substrate 22 to form AlN microcrystals 28. The temperature at this point is set at 1050 ° C. and a high V / III ratio is used. An exemplary flow rate to achieve the desired V / III is shown below.

Subsequently, for further AlN growth, the temperature is reduced to 800-900 ° C. to allow diffusion of Al adatoms so that additional AlN crystallites 32 can be deposited on the vertical / tapered sidewalls of nanostructure 26. Reduce. At this point, the V / III ratio can be increased by increasing the TMA flow rate relative to the NH ₃ flow rate.

Growth at this reduced temperature and reduced V / III ratio shortens the diffusion distance of the adsorbed atoms by reducing its kinetic energy, thus facilitating the reaction with the collision NH ₃ forming AlN. . Thereby, the AlN microcrystal 32 can be nucleated from the side wall and the tip of the nanostructure 26.

  Then, while maintaining the V / III ratio, the temperature is raised again stepwise to 1050 ° C. in multiple steps to promote coalescence of the AlN microcrystals 28 and 32 and achieve good two-dimensional growth. Under this condition, pores can be formed on the planarized AlN layer.

  Another embodiment of the growth of the AlN buffer layer is shown in FIG. Similar numbers (but distinguished by “′” sign) indicate similar features according to FIG.

  The method of FIG. 17 differs from the method described in FIG. 16 in that the temperature is kept constant at a high temperature of 1050 ° C. for a longer period of time. A crystal structure 32 'is formed. The fusion of the microcrystals 32 'results in a three-dimensional growth of the AlN layer, and the AlN microcrystals formed on the tips of the nanostructures 26' fuse with the AlN microcrystals formed on the sidewalls of the nanostructures 26 '. Thus, a larger 3D AlN crystal 34 can be formed. During the process, several voids 36 can be formed, which can provide a meltback effect.

Characterization of InGaN / GaN MQW grown on patterned Si substrate versus conventional InGaN / GaN MQW grown on Si As described above, patterned Si substrate and HT-AlN template for growing GaN layers Followed by growth of InGaN / GaN MQW. In this regard, FIG. 11 shows that PL emission from MQW grown on a conventional Si template (left graph) shows multiple satellite peaks due to the Fresnel reflection effect of Si, while on a patterned Si substrate. PL emission from InGan / GaN MQW grown on the right (graph on the right) shows a characteristic evaluation result indicating that the sum of wide peak emission is shown by eliminating Fresnel reflection. Further, the intensity of PL emission from MQW grown on the patterned Si substrate is also stronger (about twice) than that of conventional MQW on Si. This may be due to increased scattering of light emission from the nanopillar patterned substrate that forms the buried air hole inner layer. With a multi-stack AlN buffer layer, the internal Fresnel reflection can be limited within the escape cone.

  FIG. 12 shows SEM images taken for MQW grown on both types of GaN templates (GaN templates grown on patterned Si substrates and GaN templates grown on conventional Si substrates). . 20 nm size pores or pits that could be joined to form a chain were observed on both samples. Smaller pits are probably generated during coalescence of GaN islands from the AlN buffer layer. Another type of pit, a larger hexagonal V pit with a size of about 100 nm, is notable only in GaN grown on conventional Si (left image). These pits are generated when InGaN / GaN MQW is grown on a strained GaN layer. The reduction in the number of hexagonal V pits in the MQW sample grown on the patterned Si substrate (right image) compared to GaN grown on the patterned Si substrate compared to conventional GaN grown on Si. This suggests that it is more relaxed (less stress and strain).

  The disclosed method for making patterned Si substrates (also called “black Si”) finds utility in photovoltaic applications. Black Si produced by the disclosed method is technically advantageous in PV applications because of its low reflectivity, and also eliminates the need for black Si to apply an anti-reflective coating on the Si substrate. . Specifically, black Si reduces the reflection of incident light to about 5%. This is believed to be due to the formation of a so-called stepwise effective refractive medium due to the nanostructures present on the black Si. In this medium, there is no sharp interface, but there is a continuous change in refractive index, which reduces Fresnel reflection. An exemplary SEM image of the nanostructure can be observed in FIG. 13 (a). FIG. 13B shows a PL spectrum of a GaN template on a conventional Si wafer. As can be seen, the multiple peaks are due to internal reflection from the Si wafer.

  Furthermore, the disclosed patterned Si substrate can serve as a starting template for the production of optoelectronic devices such as LEDs. As described above, for example, a GaN layer grown on a patterned Si substrate exhibits a reduced density of surface defects (eg, cracks) with reduced stress and strain. As a result, InGaN / GaN MQW grown on such a template also exhibits reduced defects (less hexagonal V pits), eliminates Fresnel reflections, and increases PL intensity.

Furthermore, patterned Si substrates are also promising for use as anodes because they can incorporate large amounts of lithium (Li), resulting in a higher nominal capacity of 4000 mAh / g, about 11 times greater than state-of-the-art graphite anodes. Material. Conventionally, incorporation of Li into Si (as a phase of Li ₁₂ Si ₇ , Li ₇ Si _3, etc.) results in a volume expansion of Si (about 4 times). This creates a lot of stress in the Si, which can lead to fracture of the anode layer. A solution to prevent fracture of the Si anode is to produce Si nanowires that exhibit excellent Li incorporation and allow large volume expansion. The disclosed method does so because of the flexibility of the method in shaping Si nanostructures of various shapes and sizes by performing control over the Au mask deposition thickness, annealing conditions and etching conditions. It is suitable for providing a simple Si nanowire.

  The disclosed method can also be applied to anodes for water splitting reactions in hydrogen generation processes. The larger surface area of the anode due to nanostructure formation aids light absorption and accelerates the reaction rate.

  After reading the foregoing disclosure, it will be apparent to those skilled in the art that various other modifications and adaptations of the invention can be made without departing from the spirit and scope of the invention, and all such modifications and adaptations Are intended to be within the scope of the claims appended hereto.

Claims (23)

A method for providing nanostructures on a substrate comprising silicon, comprising:
(A) depositing a layer of transition metal on the surface of the substrate;
(B) annealing the transition metal layer to form a patterned transition metal layer;
(C) etching the substrate to form nanostructures on the substrate surface.   The method of claim 1, wherein the depositing (a) comprises sputtering a layer of transition metal on the substrate surface.   Transition metals are Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Os, The method according to claim 1 or 2, wherein the method is selected from the group consisting of Ir, Pt, and Au.   The method according to claim 3, wherein the transition metal is Au.   The method in any one of Claims 1-4 whose transition metal layer is 2-20 nm.   6. The method of claim 5, wherein the transition metal has a thickness of 3, 6, 9, 12, 15, or 18 nm.   The method according to claim 1, wherein the annealing is performed at a temperature of 400 to 750 ° C.   The method according to claim 1, wherein the annealing is performed for 30 to 90 seconds.   The method according to claim 1, wherein the patterned transition metal layer comprises nanodots.   The method according to claim 9, wherein the nanodot is in the shape of a sphere, an ellipse, or an ellipse.   The method according to claim 1, wherein the nanostructure may be a discrete structure or an interconnect structure.   11. The method of claim 10, wherein the discrete structure comprises a cylindrical structure, a columnar structure, a pyramid structure, a conical structure, a dome-shaped structure, a needle-shaped structure, a tapered structure, or a mixture thereof. The method according to claim 1, wherein the substrate further comprises a SiO ₂ layer.   A patterned silicon substrate comprising nanostructures produced by the method according to claim 1.   Use of a patterned silicon substrate according to claim 14 for the deposition and growth of gallium nitride (GaN) layers.   Use of a patterned silicon substrate according to claim 14 for the manufacture of photovoltaic (PV) devices.   Use of a patterned silicon substrate according to claim 14 as anode. A method for depositing an aluminum nitride (AlN) layer on a silicon substrate having a patterned surface comprising:
(A) providing a patterned silicon substrate according to claim 14;
(B) passing trimethylaluminum (TMA) over the patterned surface to deposit a layer of Al on the surface;
(C) passing TMA and ammonia (NH ₃ ) over the patterned surface at a predetermined V / III ratio and temperature, resulting in the deposition of AlN on the patterned surface;
(D) adjusting the temperature and V / III ratio in step (c) to provide two-dimensional AlN growth.   19. The method of claim 18, wherein adjusting (d) comprises reducing the V / III ratio by more than 50%.   20. The method of claim 19, wherein adjusting (d) further comprises reducing the temperature of step (c).   The method according to any one of claims 18 to 20, wherein the V / III ratio of step c is 100 to 1500.   The method according to any one of claims 18 to 21, wherein step (c) is performed at 1000 to 1100 ° C. A method for providing an InGaN / GaN multiple quantum well (MQW) on a silicon substrate, comprising:
(I) providing a patterned silicon substrate according to claim 14;
(Ii) depositing an AlN layer on the patterned silicon substrate according to any of claims 18-22;
(Iii) further depositing alternating layers of GaN and AlN layers thereon to achieve a desired thickness.