JP2012245039A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine for executing authentication between control devices and determining correctness, the game machine being restored to a state before power failure even if the power interruption occurs during the authentication.SOLUTION: A game play microcomputer includes an encrypted communication unit, a proper connection determining unit, and a determination result storing unit. The microcomputer is configured to perform: power interruption processing for storing a power interruption flag in a memory and waiting until power interruption, with a power interruption detecting signal as a performance starting condition; and power-on processing for keeping on holding game information when the power interruption flag has a predetermined value, and initializing the memory when the power interruption flag has a value other than the predetermined value. Based on turning on the power, power-on processing is performed; direction for starting mutual authentication is set on the proper connection determining unit, after starting the mutual authentication, the determination result storing unit is made to repeat determination until a predetermined determination result is stored; and determination as to whether the power interruption detecting signal as the condition for starting the power interruption processing is detected or not is repeatedly performed.

Description

  The present invention relates to a gaming machine including a game control device that controls the game in an integrated manner, an award value imparting control device that performs control for imparting an award value to a player, and a power supply device that supplies these power sources. .

  Conventionally, there is a pachinko machine as a representative example of a gaming machine. In such a conventional gaming machine, there are a game control device that comprehensively controls the game, and a prize value giving control device that performs control for giving a prize value to the player by a prize value giving command from the game control device. A game microcomputer and an encryption transmission / reception circuit are provided on both sides, and a mutual authentication is performed between the two based on whether or not the other party randomly selects from a plurality of identification information possessed by the game microcomputer. There is one that determines the legitimacy of the other party's control device (Patent Document 1).

JP 2010-148616 A

However, since the mutual authentication procedure described above requires a relatively long time, in the gaming machine described in Patent Document 1, if a power failure occurs during the authentication, the power failure occurs until the authentication is completed. There was a problem that processing could not be performed, and it was not possible to return to the state before the power failure normally when the power failure was restored.
Therefore, the object of the present invention is to correctly authenticate between control devices even if a power failure occurs during authentication in a gaming machine that authenticates between the control devices and determines the validity of each control device. The object is to provide a gaming machine that can be restored to the state before the power failure.

According to the first aspect of the present invention, there is provided a game control device that controls the game in an integrated manner, and a control that is connected to the game control device and that gives a player a prize value by a prize value giving command from the game control device. In a gaming machine comprising: a prize value giving control device; and a power supply device for supplying power to the game control device and the prize value giving control device.
The game control device includes:
Memory that can hold game information even in the event of a power failure with a backup power supply,
A gaming microcomputer for controlling the progress of the game,
The gaming microcomputer is:
Encrypted communication means capable of transmitting / receiving encrypted encrypted data to / from the prize value giving control device;
Mutual authentication is performed with the connected prize value assignment control device via the encryption communication means, and the connected prize value assignment control device is authorized based on the result of the mutual authentication. Regular connection determination means for determining whether or not the grant control device;
A determination result storage means for storing a result of mutual authentication when mutual authentication by the normal connection determination means is completed,
When the supply voltage supplied from the power supply device is reduced to a predetermined voltage, the power failure detection signal output from the power supply device is used as an execution start condition, and power failure confirmation information indicating that a power failure has occurred is stored in the memory. Power off processing to save and wait until power off,
The power failure confirmation information stored in the memory is referred to. When the power failure confirmation information has a predetermined value, the game information held in the memory is held as it is, while the power failure confirmation information is a predetermined value. Is a power-on process for initializing the memory, and is configured to be executable,
Performing the power-on process based on power-on, and setting to instruct the regular connection determination means to start execution of the mutual authentication,
After the execution of the mutual authentication is started, a predetermined result is stored in the determination result storage unit until a predetermined determination result is stored in the determination result storage unit in order to specify whether or not the mutual authentication is completed. It is characterized in that the determination as to whether or not the determination result has been stored is repeatedly performed, and the determination as to whether or not the power failure detection signal, which is an execution start condition of the power-off process, has been detected is repeatedly performed.

Here, the prize value refers to a profit given to the player for winning the player. Specifically, for example, it means that a predetermined number of game balls are paid out.
The award value giving control device is, for example, a payout control device that controls payout of game balls.
The power supply device not only supplies DC32V, DC15V, DC12V, DC5V, etc. to each part (device, circuit, etc.) of gaming machines including game control devices and prize value control devices, but also performs power failure detection and power failure. This device is equipped with a power failure detection circuit that sends detection signals to each part, and supplies the backup power necessary to perform normal power failure processing in the event of a power failure and to retain the information stored in the memory until the time of power failure recovery .
Power outages include not only those caused by changes in power supply conditions such as lightning strikes, fires, and earthquakes, but also human artifacts such as unplugging power cords from outlets.
The power failure confirmation information includes not only when the power failure flag is set, but also when information is written to the table, including information related to power failure (for example, power failure detection results) stored in memory in a state where the information can be referenced. Say.
The power-off refers to stopping the gaming machine by cutting off the power supply from a state where power is supplied to the game control device of the gaming machine.
The power-on means that the game control device of the gaming machine is energized and the CPU constituting the gaming microcomputer performs a boot process and starts operation. Rebooting (restarting) by system reset is also included in the power-on here.
The gaming microcomputer is designed as a one-chip microcomputer, for example, and includes a CPU core, ROM, RAM, and several peripheral circuits (random number generation circuit, clock generator, reset interrupt control circuit, serial connection to the internal bus) A transmission / reception circuit).
The encryption communication means can use an encrypted transmission / reception circuit provided as a peripheral circuit connected to the internal bus of the gaming microcomputer, but may be provided as an external circuit of the gaming microcomputer (amuse chip). Absent.
The regular connection determination means can use a transmission / reception control unit provided in the encryption communication means (encrypted transmission / reception circuit). After the CPU core starts the mutual authentication process, the normal connection determination unit (transmission / reception control unit) manages the mutual authentication process, and writes the determination result storage unit when obtaining the mutual authentication result.
As the determination result storage means, a status REG (register) provided in the encryption communication means (encrypted transmission / reception circuit) can be used.
Mutual authentication refers to a procedure for authenticating each other's validity between two devices. For example, mutual authentication is performed to determine the legitimacy of the connected partner's control device depending on whether or not the other party has randomly selected from a plurality of identification information possessed by its own gaming microcomputer.

  According to the first aspect of the present invention, after instructing the normal connection determination means to start the mutual authentication, the identification of whether or not the mutual authentication is completed is repeatedly performed, and the determination of the power failure detection signal is repeatedly performed. As a result, even if a power failure occurs during the execution of mutual authentication, the state before the power failure can be restored normally when the power failure is restored.

The invention according to claim 2 is the gaming machine according to claim 1,
The processing executed by the gaming microcomputer for controlling the gaming machine includes main processing including loop processing that is repeatedly executed, and timer interrupt processing that is executed every time the interrupt timer expires for the main processing. Have
The gaming microcomputer is:
The power-on process is executed in the main process,
Prior to the execution of the power-on process, a setting for instructing the regular connection determination means to start execution of the mutual authentication is performed,
The power-on process and the mutual authentication are executed in parallel.

  According to the second aspect of the present invention, the power-on process and the mutual authentication process are performed in parallel after the setting for instructing the normal connection determination means to start executing the mutual authentication before the power-on process is executed. Since it is executed, the time from power-on to the start of game control can be shortened.

A third aspect of the present invention is the gaming machine according to the second aspect,
A display device that displays an effect image corresponding to the progress of the game;
An effect control device that controls display on the display device based on a control command from the gaming microcomputer,
The gaming microcomputer is:
In the power-on process executed when the power is turned on, a process for instructing the display control device to display a power-on image indicating that the display device is turned on is executed.
The determination result storage means until a predetermined determination result is stored in the determination result storage means after instructing the display device to display a power-on image indicating that the power is turned on by executing the power-on process. It is characterized in that the determination as to whether or not a predetermined determination result is stored is repeatedly performed.

  According to the third aspect of the present invention, in the power-on process, the process for instructing the effect control device to display the power-on image is executed. Since it can be confirmed by visual recognition of the display device that the gaming machine has been activated before the mutual authentication is completed, the inspection can be made more efficient.

The invention according to claim 4 is the gaming machine according to claim 3,
A launcher that launches a game ball onto the game board; and
A firing control device for controlling the operation of the firing device,
The gaming microcomputer is:
The launch control device is configured to control the launch device by outputting a launch permission signal for allowing the launch control device to launch a game ball and a launch prohibiting signal for prohibiting the launch of the game ball,
In the power-off process executed based on the power failure detection signal output from the power supply device, including a process of outputting the firing prohibition signal,
The execution of the power-off process prohibits the launching of game balls by the launching device.

  According to the fourth aspect of the present invention, since the firing prohibition signal is output in the power-off process, the game ball is launched during the power-off process and the winning ball is performed even though the winning ball is won. This prevents the player from suffering a disadvantage.

The invention according to claim 5 is the gaming machine according to claim 4,
The supply voltage supplied from the power supply device is monitored, and when the supply voltage supplied from the power supply device drops to a predetermined voltage lower than the detection voltage of the power failure detection signal, a reset signal is sent to the game First reset signal output means for outputting to the microcomputer for use;
A second reset signal output means for starting timing by a predetermined reset timer and outputting a reset signal to the gaming microcomputer based on the time-up of the reset timer;
The gaming microcomputer is:
The power-off process executed based on a power failure detection signal output from the power supply device includes a process of starting time measurement of the reset timer,
The time of the reset timer is started by executing the power-off process.

  According to the fifth aspect of the present invention, since the process of starting the reset timer of the second reset signal output means is included in the power-off process, the power failure detection signal is output during the execution of the mutual authentication. Regardless, even if the reset signal by the first reset signal output means is not output, it is possible to reliably return.

  According to the present invention, in a gaming machine that includes a plurality of control devices and performs authentication between the control devices, even when a power failure occurs during the execution of mutual authentication, the state before the power failure can be normally restored at the time of power failure recovery. Can do.

It is the perspective view which looked at the gaming machine of one embodiment of the present invention from the front side (embodiment 1). It is a front view which shows the structure of the game board provided in the game machine of one Embodiment to which this invention is applied (Embodiment 1). It is a block diagram for demonstrating the control system of the game machine of one Embodiment to which this invention is applied (Embodiment 1). FIG. 3 is a block diagram showing a more specific configuration of a gaming microcomputer (game microcomputer: amuse chip: gaming arithmetic processing device) that constitutes a game control device (or payout control device) (Embodiment 1); It is a block diagram which shows the connection of the game control apparatus and payout control apparatus in one Embodiment of this invention (Embodiment 1). It is a block diagram which shows the connection of a plaintext type game control apparatus and a payout control apparatus. This is the first of three flowcharts showing the main process of the game control device (Embodiment 1). This is the second of the three flowcharts showing the main process of the game control device (Embodiment 1). This is the third of the three flowcharts showing the main process of the game control device (Embodiment 1). 7 is a flowchart showing timer interrupt processing of the game control device (Embodiment 1). 7 is a flowchart showing an encrypted communication process in the timer interrupt process of the game control device (first embodiment). 12 is a flowchart illustrating details of an encrypted communication reception process in the encrypted communication process illustrated in FIG. 11 (first embodiment). 12 is a flowchart showing details of an encrypted communication transmission process in the encrypted communication process shown in FIG. 11 (first embodiment). It is the 1st sheet of the 2 sheets of the flowchart which shows the main process of the payout control apparatus (embodiment 1). This is the second of the two flowcharts showing the main process of the payout control device (Embodiment 1). It is a flowchart which shows the detail of the encryption communication process among the main processes of a payout control apparatus (embodiment 1). It is a sequence diagram showing a procedure when data is transmitted and received between the game control device 100 and the payout control device 210. FIG. 17A is a sequence diagram when data is transmitted from the game control device 100, and FIG. 17B is a sequence diagram when the game control device 100 receives data (Embodiment 1). It is the 2nd sheet of the 3 sheets of the flowchart which shows the main process of the game control apparatus in Embodiment 2 (Embodiment 2). It is a flowchart which shows the special figure game process among the timer interruption processes in Embodiment 2 (Embodiment 2). It is time chart 1 explaining Example 1 of invention 3 (Example 1 of invention 3). It is time chart 2 explaining Example 1 of invention 3 (Example 1 of invention 3). It is the 2nd sheet among the 3 sheets of the flowchart which shows the main process of the game control apparatus in Example 1 of invention 3 (Example 1 of invention 3). It is a flowchart which shows the timer interruption process of the game control apparatus in Example 1 of invention 3 (Example 1 of invention 3). It is the 3rd sheet of the 3 sheets of the flowchart which shows the main process of the game control apparatus in Example 2 of invention 3 (Example 2 of invention 3). It is a time chart explaining Example 2 of invention 3 (Example 2 of invention 3).

(Embodiment 1) A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view of a gaming machine according to an embodiment of the present invention as viewed from the front side.
The gaming machine 10 of the present embodiment includes a front frame 12, and the front frame 12 is assembled to a main body frame (outer frame) 11 via a hinge 13 so as to be openable and closable. The game board 30 (see FIG. 2) is stored in a storage portion (not shown) formed on the front side of the front frame 12. A transparent member holding frame 15 that holds a transparent member such as a cover glass that covers the front surface of the game board 30 is attached to the front frame 12.

  In addition, an illuminating device (moving light) 16 having a built-in lamp or the like and a discharge abnormality notification lamp (LED) 17 are provided on the upper part of the transparent member holding frame 15. On the left and right sides of the transparent member holding frame 15 are speakers 19a, 19a, 19b that emit sound (for example, sound effects), and decoration devices 18, 18 that have built-in lamps or the like and emit light for decoration or the like. Is provided.

  The lower part of the front frame 12 is paid from an upper plate 21 for supplying a game ball to a launching device 171 (see FIG. 3) for launching a game ball on the game board, and a ball payout device provided on the back side of the gaming machine 10. There are provided an upper tray ball outlet 22 through which the released game balls flow out, a lower tray 23 for storing game balls dispensed in a state where the upper plate 21 is full, an operation unit 24 of the launching device, and the like. Further, an effect button 25 having a built-in operation switch for receiving an operation input from the player is provided on the upper edge of the upper plate 21. Further, a key 26 for opening and locking the front frame 12 is provided on the lower right side of the front frame 12.

  In the gaming apparatus of this embodiment, the launching device launches the game ball supplied from the upper plate 21 toward the game area 40 when the player rotates the operation unit 24. In addition, when the player operates the effect button 25, it is possible to perform an effect or the like in which the player's operation is intervened in the variable display game on the display device (see FIG. 2). Furthermore, on the front surface of the transparent member holding frame 15 above the upper plate 21, a ball rental button 27 that is operated when a player receives a ball rental from an adjacent ball rental machine, and a prepaid card is discharged from the card unit of the ball rental machine. A discharge button 28, etc., which are operated for the purpose, are provided.

FIG. 2 is a front view showing a configuration of a gaming board provided in a gaming machine according to an embodiment to which the present invention is applied.
A game board 30 provided with a game area 40 on the front surface in which a game ball flows down in a storage portion (not shown) formed on the front side of the front frame 12 (see FIG. 1) of the gaming machine 10 (see FIG. 1) of the present embodiment. Is stored. Further, a transparent member holding frame 15 that holds a transparent cover glass that covers the front surface of the game board 30 is attached to the front frame 12.

  A game area 40 surrounded by guide rails 31 for guiding upward a game ball (hit ball; game medium) launched by a launching device (not shown) is formed on the front surface of the game board 30. At the center, a center case 41 having a variable display device (not shown) capable of executing a special figure variation display game for variably displaying a plurality of identification information (identification symbols) is attached. This variable display device is configured by a color liquid crystal display, for example, but may be configured by a display such as an organic EL or CRT.

  Below the center case 41 is arranged a first start winning opening 36 for giving a start condition for the variable display game (special figure 1 game) in the variable display device. A normal variation winning device 37b having a second start winning opening 37 that can be opened and closed to the left and right has a second start winning opening 37 that is closed and cannot accept a game ball and gives a starting condition for a variable display game (game of FIG. 2). Is arranged. Further, below the normal variation winning device 37b, a state in which the game ball is not accepted and a state in which the game ball is not accepted by opening and closing according to the results of the first special figure fluctuation display game and the second special figure fluctuation display game in the variable display device are easy to accept. An attacker-type big prize opening device (hereinafter, simply referred to as a big prize opening) 38 having an openable / closable door that can be converted into an open / close door is disposed.

  In addition, on the left side of the variable display device in the game area 40, there is a general figure start gate 34 for giving a start condition of the general figure change display game (normal figure game), and a plurality of general prizes are provided below the general figure start gate 34. A mouth 35 is provided, and an out hole 39 for collecting a game ball that has not won a prize opening is disposed below the game area 40. Further, although not shown, in the game area 40, a windmill as a hitting direction changing member, a number of obstacle nails, and the like are provided. Further, in the lower right corner of the game board 30 on the outside of the game area 40, a prize is given to the variable display game corresponding to the first special figure variable display game and the second special figure display game in the variable display device and to the general figure start gate 34. A collective display device 50 is provided for executing a universal map display game with a trigger at one location.

  The collective display device 50 includes a first special figure fluctuation display section (special figure 1 display) 52 and a second special figure fluctuation display section (special figure 2 display) for a variable display game configured by segment type liquid crystal displays and the like. ) 51, a general variation display section (standard diagram display) 53 for a general variation display game composed of two upper and lower LED lamps, and a big hit and a short time state composed of two upper and lower LED lamps. A game state display unit (not shown) for notifying the occurrence of the game. In addition, although not shown, the collective display device 50 is also provided with a storage display unit for informing the start memory number of each variable display game composed of two upper and lower LED lamps.

  In the above general start gate 34, there is a general start SW 34a (see FIG. 3) which is a gate switch (gate SW) including a non-contact sensor for detecting a game ball that has passed through the general start gate 34. When the game ball that is provided and is thrown into the game area 40 passes through the normal map start gate 34, it is detected by the general map start SW 34 a, and the general map change display unit 53 plays the normal map change display game. . In addition, the game ball passes through the usual figure start gate 34 when the usual figure change display game is already being played, or when the usual figure change display game is hit and the normal variation winning device 37b is converted to the open state. Then, if it is less than the upper limit of the usual figure start memory number, the ordinary figure start memory number is incremented by 1 and stored. In the normal chart start memory, a random number value for hit determination for determining a hit error of the normal figure change display game is stored, and when the random number value for hit determination coincides with the determination value, A specific result mode (specific result) is derived by hitting the normal map display game.

  The usual map change display game is executed by a change display unit (common figure display) 53 provided in the collective display device 50. The universal map display 53 is composed of an LED indicating a hit as normal identification information (general map, normal symbol) and an LED indicating a deviation as the normal identification information, and alternately blinking and displaying the two LEDs. Ordinary identification information is displayed in a variable manner, and after a predetermined fluctuation display time has elapsed, one of the LEDs is turned on to display the result. Note that, for example, numbers, symbols, character designs, and the like may be used as the normal identification information, which is displayed by variably displaying for a predetermined time and then stopped. If the stop display of the ordinary map change display game is a specific result, the opening / closing member is opened by a solenoid (general power SOL) 90 (see FIG. 3) as a driving means of the ordinary variation winning device 37b. It will be in the open state opened for predetermined time (for example, 0.5 second). This makes it easier for the game ball to win the second start winning port 37 of the normal variation winning device 37b, and the number of executions of the second special figure variable display game within a predetermined time increases.

  A first start opening switch (Special Figure 1 start opening SW) 36a is provided inside the first start winning opening 36, and based on the detection of the game ball by the special Figure 1 start opening SW 36a, the first special view The start right to start the variable display game is generated. Further, a second start opening switch (Special Figure 2 start opening SW) 37a is provided inside the normal variation winning device 37b. Based on the fact that a game ball is detected by the Special Figure 2 start opening SW 37a, the second special opening prize switch 37b is provided. The start right to start the figure variation display game is generated.

  Further, the right to start the first special figure variation display game is stored as a first start memory (a special figure 1 start memory, a special figure 1 hold number) within a predetermined upper limit number (for example, 4). . The number of the first start memories is displayed on the special figure 1 memory display. The right to start the second special figure variation display game is also stored as a second start memory (special figure 2 start memory, special figure 2 holding number) within a predetermined upper limit number (for example, 4). The number of the second starting memories is displayed on the special figure 2 memory display. In the following description, when the first special figure fluctuation display game and the second special figure fluctuation display game are not distinguished, they are simply referred to as a special figure fluctuation display game.

  The first special figure fluctuation display game and the second special figure fluctuation display game are executed by special figure indicators 52 and 51 provided in the collective display device 50, and a plurality of special identification information (special figures). , Special symbols) are variably displayed, and then a predetermined result mode is stopped and displayed. In addition, a decorative special figure fluctuation display game that displays a plurality of types of identification information (for example, numbers, symbols, character designs, etc.) in a variable display device corresponding to each special figure fluctuation display game is executed. It has become. Therefore, the special figure indicators 52 and 51 and the variable display device constitute a variable display device for displaying the variable display game.

  As a result of the special figure change display game, when the display form of the special figure indicators 52 and 51 becomes a special result form, a special game state (so-called so-called big wins 38 are formed as a big hit). , Jackpot gaming state) occurs. Further, the display mode of the variable display device is also a special result mode corresponding to the display mode of the special figure display 52 or 51. Note that the variable display device may use different display devices and different display areas for the first special figure fluctuation display game and the second special figure fluctuation display game. Further, the special-figure display game may be executed by using only the variable display device without providing the special-figure indicators 52 and 51 in the gaming machine. The second start memory is preferentially digested over the first start memory. If there is a second start memory, the second special figure variation display game may be executed even if the first start memory is present. .

  In addition, when the result mode of the special figure variation display game becomes a special result mode and a special game state occurs, the open / close panel of the big prize opening 38 is a big prize opening by a solenoid (large prize opening SOL) 38 as a driving device. Is closed (a state disadvantageous for the player) to an open state (a state advantageous for the player). A switch (count SW) 38a for detecting a winning ball is arranged inside the big winning opening. Then, the game ball driven into the game area 40 by starting the game is placed in any one of the winning openings such as the first start winning opening 36, the normal variable winning apparatus 37b, the big winning opening 38, the general winning opening 35 and the like. When a prize is won, a predetermined number of prize balls corresponding to each prize opening are paid out by the payout control device 210 (shown in FIG. 3).

FIG. 3 is a block diagram for explaining a control system of a gaming machine according to an embodiment to which the present invention is applied. The gaming machine 10 includes a game control device 100. The game control device 100 includes a game microcomputer 101 (game microcomputer), an input I / F (Interface) 105, an output I / F (Interface) 106, and a reset circuit 108. Prepare. The gaming microcomputer 101 includes a CPU 102, a ROM (Read Only Memory) 103, and a RAM (Random Access Memory) 104.
The CPU 102 is a main control device that controls the game in an integrated manner, and controls the game. The ROM 103 stores invariant information (program, fixed data, etc.) for game control. The RAM 104 is used as a work area that provides a work area for the CPU during game control.

The game control device 100 is provided with a reset circuit 109 (first reset signal output means) as an external circuit of the game microcomputer 101. The reset circuit 109 monitors DC5V of the power supplied from the power supply device. Then, when it is detected that the DC5V power supply voltage has become a predetermined value or less, a reset signal is output to the RST terminal of the gaming microcomputer 101. The reset signal is a kind of forced interrupt signal and resets the entire control system.
Although not shown in FIG. 3, the gaming microcomputer 101 includes a serial transmission / reception circuit, an encryption transmission / reception circuit (encryption communication means), and a random number generation circuit as peripheral circuits connected to the internal bus (see FIG. 4). Communication for mutual authentication is performed between the game microcomputer 101 of the game control device 100 and the game microcomputer 211 of the payout control device 210 (see FIG. 5).
Further, the game control device 100 is connected to an external information terminal 108, and information related to the gaming machine 10 is sent via the external information terminal 108 to an information collection terminal or a game hall internal management device (not shown) installed in the game store. ).

  The game control device 100 includes various detection devices (special drawing start switches 36a and 37b, ordinary drawing start switch 34a, count switch 38a, general prize opening switches 32a to 32n, an overflow switch 109, a frame opening switch 111, and a ball break switch 110. ) Is input. The overflow switch 109 detects that a predetermined number or more of game balls are stored in the lower plate 23. The frame opening switch 111 detects that the front frame 12 is opened. The ball break switch 110 is disposed in a ball storage unit (not shown), and detects that the number of game balls stored in the ball storage unit is less than or equal to a predetermined number. There is provided an interface chip (proximity I / F) that receives a negative logic signal such as a high level of 11V and a low level of 7V supplied from these switches and converts it to a positive logic signal of 0V-5V. . Proximity I / F has an input range of 7V-11V, so that the lead wire of the proximity switch is improperly shorted, the switch is disconnected from the connector, or the lead wire is disconnected and becomes floating An abnormal state can be detected, and an abnormality detection signal is output. Due to the necessity of this proximity I / F circuit, the game control device is supplied with 12V power in addition to 5V power.

  Detection signals from the various detection devices input to the game control device 100 are input to the CPU 102 via the input I / F 105, and the CPU 102 performs various processes such as a big hit lottery based on these signals. In addition, the CPU 102, via the output I / F 106, displays a general-purpose display 53, special-purpose displays 52 and 51, a general electric power SOL (solenoid) 90, a special winning opening SOL (solenoid) 38, a payout control device 210, and an effect. A command signal is transmitted to the control device 150 to control the game in an integrated manner.

Further, the game microcomputer 101 (see FIG. 3) of the game control device 100 transmits a payout command signal to the payout control device 210 that controls the payout motor 220 of the ball payout unit (not shown), and the effect control device 150. A change start command, a customer waiting demo command, a fanfare command, a probability information command, an error designation command, and the like are transmitted as an effect control command signal. Further, the game microcomputer 101 (CPU 102) of the game control device 100 outputs a launch permission signal to the launch control device 170 via the output I / F 106.
Here, the launch permission signal is a signal for permitting the launch of the game ball. The launch prohibition signal is a signal that prohibits the launch of the game ball. In the present embodiment, it means launch permission when the launch permission signal is on, and prohibit fire when the launch permission signal is off. The launch control device 170 controls the operation of the launch device 171. Therefore, the game microcomputer 101 of the game control device 100 is configured to be able to control the launch device by this launch permission signal.

  Next, the production control device 150 and the payout control device 210 will be described.

  The effect control device 150 controls the error notification LED 17, the speaker 30, and the display device 8 on which the effect image is displayed in accordance with the progress of the game, based on various signals input from the game control device 100. The effect control device 150 includes a main control microcomputer (1st CPU) composed of an amusement chip (IC) in the same manner as the game microcomputers 101 and 211, and a video control microcomputer (2nd CPU) that performs video control exclusively under the control of the 1st CPU. The VDP (Video Display Processor) as a graphic processor that performs image processing for video display on the display device 8 according to commands and data from the 2nd CPU 412 and various melody and sound effects are reproduced from the speakers 19a and 19b. Therefore, a sound source LSI for controlling the output of sound is provided, and display on the display device is controlled based on a control command from a game microcomputer (game microcomputer) of the game control device 100.

  In addition, the effect control device 150 is provided with an interface chip (command I / F) that receives a command transmitted from the game control device 100. The variation start command, the customer waiting demo command, the fanfare command, the probability information command, the error designation command, and the like transmitted from the game control device 100 to the effect control device 150 via this command I / F are used as the effect control command signal. Receive. Since the game microcomputer 101 of the game control device 100 operates at DC 5V and the main control microcomputer (1st CPU) of the effect control device 150 operates at DC 3.3V, the command I / F has a signal level conversion function. It has been.

  The payout control device (prize value imparting control device) 210 performs control for driving out the payout motor 220 of the payout unit in accordance with the prize ball payout command signal from the game control device 100 to pay out the prize ball. Further, the payout control device 210 drives the payout motor 220 of the payout unit in accordance with the payout command signal transmitted from the game control device 100 based on the loan request signal from the card unit 70 so as to pay out the rental money. Control.

  The payout control device 210 includes a game microcomputer 211, an input I / F (Interface) 215, an output I / F (Interface) 216, and a reset circuit 219, and a prize ball payout command (command or data) from the game control device 100. Accordingly, the payout motor of the payout unit is driven to perform control for paying out the prize balls. In addition, the payout control device 210 controls the payout unit to drive out a payout motor based on a ball rental request signal from the card unit 70 to pay out a rental ball. The gaming microcomputer 211 includes a CPU 212, a ROM 213, and a RAM 214. The reset circuit 219 functions in the same manner as the reset circuit 109. The reset circuit 219 monitors the DC5V of the power supplied from the power supply device 160 and detects that the DC5V power supply voltage has become a predetermined value or less. Output to the RST terminal of the microcomputer 212.

  The CPU 212 is a control device that comprehensively controls the payout and controls the payout control. The ROM 213 stores invariant information (program, data, etc.) for payout control. The RAM 214 is used as a work area during payout control.

  The CPU 212 receives signals from the payout ball detection switch 112, the overflow switch 109, the ball break switch 110, the error release switch 223, the tax rate setting switch 226, and the lending charge setting switch 227 in the payout unit via the input I / F 215. Is done. Further, the CPU 211 outputs drive signals to the payout motor 220, the error number indicator, the tax rate indicator 224, and the rental fee indicator 225 in the payout unit via the output I / F 216. Further, the CPU 212 of the payout control device 210 outputs a firing permission signal to the firing control device 170 via the output I / F 216. When both the launch permission signal from the game control device and the launch permission signal from the payout control device 210 are signals indicating launch permission, the launch control device 170 causes the launch device 171 to place the game ball in the game area 40. Control to fire.

  The error release switch 223 is operated by the store clerk of the amusement store to cancel the error state when the cause of the error generated by the store clerk of the amusement store is resolved when an error occurs in the payout control device 210. It is a switch. The error number display 222 is disposed on the back side of the payout control device 210 and displays the type of error that has occurred in the payout control device 210 so that it can be specified.

  The game control device 100, the effect control device 150, and the payout control device 210 are connected to a power supply device (power supply device) 160. The power supply device 160 includes an AC-DC converter that generates the DC 32V DC voltage from a 24V AC power source, a DC-DC converter that generates a lower level DC voltage such as DC 12V and DC 5V from the DC 32V voltage, and the like. The power of DC32V, DC15V, DC12V, and DC5V is supplied to the game control device 100, the effect control device 150, and the payout control device 210. The power supply device 160 includes a backup power supply 161, a RAM clear switch 162, and a power failure detection circuit 169. The backup power supply 161 supplies power to the game control device 100, the effect control device 150, and the payout control device 210 (to the internal RAM) even in the event of a power failure (even if not supplied to the effect control device 150). Good).

  The RAM clear switch 162 is a switch that forcibly initializes information stored in the RAM in the game control device 100 and the RAM in the payout control device 200. The initialization switch signal is a signal generated when the RAM clear switch 162 is turned on, and the information stored in the RAM 104 in the gaming microcomputer 101 and the RAM 214 in the gaming microcomputer 211 is forcibly initialized. To do. Although not particularly limited, the initialization switch signal is read when the power is turned on, and the power failure detection signal is repeatedly read in the main loop of the main program executed by the gaming microcomputer 101.

  The power failure detection circuit 169 monitors the voltage of DC32V generated by the power supply device, detects that the voltage drops to a predetermined voltage (for example, 17V) or less, and changes the power failure detection signal. The data is output to the device 150 and the payout control device 210. In this embodiment, when the voltage is normal, an ON signal is continuously output. When it is detected that a power failure has occurred, the signal is changed to an OFF signal, and when the power is restored from the power failure, an ON signal is output (FIGS. 20 and 21). , 25).

  The backup power supply 161 can be composed of one large-capacity capacitor such as an electrolytic capacitor. The backup power is supplied to the RAM 104 of the game microcomputer 101 of the game control device 100 and the RAM 214 of the game microcomputer 211 of the payout control device, and the data stored in the RAM is retained even during a power failure or after the power is shut off. ing.

  When the ball lending button 27 provided in the gaming machine 10 is operated, the card unit 70 subtracts the valuable value for the gaming ball to be lent from the valuable value stored in the card such as the prepaid card or the membership card. The value of the subtracted valuable value is displayed on the balance display unit 29 of the gaming machine 10. Further, when the discharge button 28 provided in the gaming machine 10 is operated, the card unit 70 discharges the card inserted into the card insertion slot.

  FIG. 4 is a block diagram showing a more specific configuration of the game microcomputer (game microcomputer: amuse chip: game operation processing device) 101 (211) constituting the game control device 100 (payout control device 210). It is. The gaming microcomputer 600 includes a CPU core 601, ROM 602, RAM 604, etc., a random number generation circuit 608, a serial transmission / reception circuit 631, an encryption transmission / reception circuit 632, a reset interrupt control circuit (including a watchdog timer WDT) 610. A one-chip microcomputer incorporating a clock generator (including a counter clock timer CTC) 609 and the like as a peripheral circuit connected to its internal bus (CPU bus).

  The gaming microcomputer 600 of this embodiment is divided into a gaming block 600A for performing gaming control and a management block 600B for managing information, and one element constituting each circuit block described below is a semiconductor on a semiconductor substrate. It is formed as an integrated circuit (amusement chip, amusement chip).

  The game block 600A includes a CPU core 601, a user program ROM 602, a user work RAM 604, an external bus interface 606, a bus switching circuit 607, a decryption / ROM writing circuit 614, a mirrored RAM 605, a boot block 613, a reset interrupt control circuit 610, and an address decoder. 611, an output control circuit 612, a clock generator 609, a random number generation circuit 608, and a functional block such as a HW parameter ROM 603. These functional blocks and the management block 110B are connected by a CPU bus 615.

  The CPU core 601 includes various register groups, an arithmetic / logic unit (ALU), an instruction register (IR), a decoder, a program counter (PC), a stack pointer (SP), a data bus connecting them, an address bus, and various control units. In the core, for example, configured with Z80 architecture. The CPU core 601 loads and executes a game control program stored in the user program ROM 602, thereby realizing various functions necessary for controlling the gaming machine 10 in software.

  The user work RAM 604 corresponds to the main memory of the CPU core 601 and is composed of, for example, a high-speed semiconductor device such as an S-RAM. The user work RAM 604 is used as a work area (work area) when executing processing based on the game program in the game block 600A. Note that the user work RAM 604 can be given a battery backup function using a dedicated terminal assigned to one of the terminal groups of the gaming microcomputer 600, and the memory is stored even after the gaming machine 10 is powered off. Keep the contents. In addition, the user work RAM 604 is controlled so that the prohibition and permission of the chip enable are controlled by a protection circuit (not shown). When the chip enable is prohibited (when power is not supplied to the gaming machine 10), Neither writing can be performed.

  The external bus interface 606 is a circuit for performing input / output control of various signals such as a memory request signal, an input / output request signal, a memory write signal, a memory read signal, and a mode signal with an external device. The bus switching circuit 607 is a circuit that performs bus switching to enable input / output of address signals and data signals between an external bus (not shown) and the CPU bus 615 in the chip. For example, when the memory write signal WR is activated while the memory request signal MREQ or the input / output request signal IORQ is activated, an external data signal can be written to a predetermined external I / O, and the memory read signal RD is activated. Then, an external data signal can be taken in from a predetermined external I / O.

  The decryption / ROM writing circuit 614 generates the voltage necessary for decrypting the data sent encrypted and sending it to the user program ROM 602 and the HW parameter ROM 603 which can be electrically written, and controls the timing. Circuit. For example, when an external data signal is given from the outside while sequentially incrementing the external address signal while the mode signal MODE is active, a writing mode to the user program ROM 602 is entered, and the manufacturer or third party of the gaming machine It becomes possible to write a game program. However, if the write end code is recorded in a predetermined area of the HW parameter ROM 603 described later after the game program has been written to the user program ROM 602, the game program cannot be written to the user program ROM 602 thereafter. While the mode signal MODE is at the [H] level, the address signals A0 to A15 and the data signals D0 to D7 are fetched via the bus switching circuit 607, and the information (encrypted) included in the data signals D0 to D7 is fetched. After decrypting the program and the encrypted unique ID), it is output (written) to the user program ROM 602 and the HW parameter ROM 603 via the bus 615.

  The bus 615 includes a data bus, an address bus, and a control bus, and a management block 600B is also connected to the bus 615.

  The mirrored RAM 605 stores information obtained by copying information stored in the user work area when the clock falls (if the CPU core is Z80, the mirrored RAM 605 executes processing when the clock rises, and thus can move synchronously. Not so).

  The reset interrupt control circuit 610 makes an interrupt request to the CPU core 601 in response to an interrupt request signal from the outside, sends a control signal to a circuit (for example, a random number generation circuit) inside the chip, The CPU core 601 is system-reset in response to a reset signal input from, and generates a signal for setting various resources inside the gaming microcomputer 600 to an initial state. The reset interrupt control circuit 610 includes a watchdog timer (WDT). The reset interrupt control circuit 610 has an RST terminal that receives signals from the reset circuits 109 and 219 in FIG. 3 (see FIG. 4).

  The boot block 613 includes a ROM for storing a boot program. When the system of the gaming microcomputer 600 is reset, the boot program starts up and performs a predetermined simple check. If the boot ROM is normal, the protection setting process is executed, and then the process is passed to a predetermined address of the game program (a predetermined address in the address space of the CPU 601 (generally, the first address 0000h in the address space)).

  The address decoder 611 decodes the address information on the CPU bus 615 and controls the output control circuit 612 according to the decoding result. The location of the built-in device and the built-in control / status register group is decoded by the memory mapped I / O method and the I / O mapped I / O method.

  The output control circuit 612 performs signal control from the address decoder 611 and outputs an 8-bit chip select signal (CS0 to CS7) from the external terminal.

  The clock generator 609 generates an operation clock and a counter clock to be supplied to each block in the gaming microcomputer 600 including the CPU core 601 based on the system clock MCLK and the random number clock EXCLK supplied from the outside. . The clock generator 609 includes a counter timer circuit (CTC).

  The random number generation circuit 608 is a circuit that generates a random number used for jackpot determination and the like. In addition to generating a uniform random number using a mathematical method (for example, a congruence method or an M-sequence method), a counter It has a function to generate random numbers by the method. In this embodiment, the peripheral circuit connected to the internal bus 615 of the CPU core 601 is provided in the amuse chip without being configured as an external circuit. The random number generated by the random number generation circuit 608 is used for, for example, a big hit lottery. Further, when the encrypted transmission / reception circuit 632 needs a random number for encrypted communication, the random number generation circuit 608 can supply the random number. Note that the gaming microcomputer 211 provided in the payout control device 210 may not include the random number generation circuit 608.

  The HW parameter ROM 603 is used to record the write end code for prohibiting program writing to the user program ROM 602 and to set parameters specific to the user system (hardware). It is configured by a writable memory (for example, EPROM, EEPROM, flash memory, etc.).

  The serial transmission / reception circuit 631 and the encrypted transmission / reception circuit 632 are circuits for transmission / reception between the game control device 100 and the payout control device 210. When an unencrypted signal is exchanged by SIO connection, a serial transmission / reception circuit 631 having an asynchronous serial communication function (UART function) for realizing serial communication is used. When an encrypted signal is exchanged by encrypted connection, encryption is performed. A transmission / reception circuit 632 is used. Details will be described later with reference to FIGS. 5 and 6.

  A management block 600B for managing information in the gaming microcomputer (amuse chip) 600 includes a management program ROM (HPG program ROM) 616, a management work RAM (HPG work RAM) 619, a bus monitor circuit 618, an ID property memory 617, A management control circuit (HPG) 620, an external communication control circuit 621, and a local bus 622 connecting these circuit blocks are included, and a bus monitor circuit 618 is connected to both the local bus 622 and the CPU bus 615 of the game block 600A. As a result, data can be transmitted / received to / from the CPU core 601 via the CPU bus 615.

  The management work RAM 619 is used as a storage area for temporarily storing information of the game block 600A read via the bus monitor circuit 618. The bus monitor circuit 618 monitors the state of the CPU bus 615, and when the CPU bus 615 is not used by the CPU core 601, the user program ROM 602 and the user work of the game block 600A via the CPU bus 615 as necessary. The RAM 604 and the like are accessed, and necessary data (game program, contents of the user work RAM 604, etc.) are taken into the management block 600B.

  In the ID property memory 617, a unique ID (unique information) used for identification of the gaming microcomputer 600 and determination of the legitimacy is written. This unique ID is stored in the bus 622 and the external communication control circuit 621. Via a management device (hall computer) outside the gaming machine. This allows the management device to monitor the unique ID of the gaming machine. Specifically, if the unique ID set in advance in the gaming machine does not match the unique ID read by the management device, the management device disables input / output of various signals. Then, it becomes impossible to input / output signals between various devices connected to the game control device 100 (for example, the big prize opening solenoid 38 and the normal variable prize opening solenoid 90) and the subordinate control device and the CPU core 102. However, it becomes clear that an abnormality has occurred in the gaming machine due to the fact that the player cannot operate or the decorative lamp does not light.

  In addition to the unique ID, information such as a game type code, a rank code, a manufacturer number, a model code, and an inspection number is written in the ID property memory 134. The game type code is information for distinguishing pachinko gaming machines, throttle machines, and the like, and is represented by, for example, “P” for pachinko gaming machines and “G” for throttle machines. The rank code is a model rank code of the gaming machine 1 (a code for distinguishing between the first type and the second type), a manufacturer number, or a manufacturer ID (or manufacturer code) for identifying the manufacturer of the gaming machine 1. is there. The model code is a product code of the gaming machine 1 set by the manufacturer. The inspection number (or verification code) is a number given to the gaming machine 1 that has passed the inspection by the third party organization.

  Further, the ID property memory 617 includes a ROM and a RAM, and the contents of the ROM are copied to the RAM. That is, the unique ID, game type code, rank code, manufacturer number, model code, and inspection number are stored in the ROM, and are copied to the RAM. The copy timing is performed when the gaming machine is turned on or when the gaming microcomputer 600 is reset, for example, in an initialization process executed in the management block 600B immediately after the system reset.

  The control circuit 620 controls the operation of the management block 600B and has a buffer memory. For example, the control circuit 620 monitors the operation of the CPU core 601 via the bus monitor circuit 618, and copies the contents stored in the user work RAM 604 of the game block 600A to the mirrored RAM 605 during non-operation. Further, the contents of the ID property memory 617 of the management block 600B are transferred to the outside in response to a request from the inspection apparatus, and the program in the user program ROM 602 is transferred to the outside via the bus monitor circuit 618 in response to a program request. Or transfer. The buffer memory is used for timing adjustment at the time of transfer.

  The external communication control circuit 621 communicates with an information collection terminal device and an ID inspection device provided outside the gaming machine. For example, when an information collection terminal device is connected, in response to a request from the information collection terminal device, the storage contents of the management work RAM 619 and the ID property memory 617 are transferred to the requesting information collection terminal device. If an ID inspection device is connected, at least information on the unique ID stored in the ID property memory 617 is transferred to the requesting ID inspection device in response to a request from the ID inspection device.

  FIG. 5 is a block diagram showing the connection between the game control device 100 (game control device) and the payout control device 210 (prize value assignment control device) in one embodiment of the present invention. The game arithmetic processing device (amuse chip) 600 included in the game control device 100 and the game arithmetic processing device 600 (amuse chip) included in the payout control device 210 have the same configuration, both of which are shown in FIG. It has the structure shown. 5, the configuration of the serial transmission / reception circuit 631 and the encrypted transmission / reception circuit 632 will be described in detail. The same reference numerals are assigned to the same circuits on the game control device side and the payout control device side. In any of the game processing device 600 on the game control device side and the game operation processing device 600 on the payout control device side, the CPU core 601, the serial transmission / reception circuit 631, and the encrypted transmission / reception circuit 632 are linked to each other. , Mutual serial transmission / reception and encryption transmission / reception between the payout control devices 210 are realized. Hereinafter, the operation of each circuit will be described mainly as viewed from the game control device 100 side. The operation on the payout control device 210 side is the same.

The serial transmission / reception circuit 631 included in the game processing device 600 on the game control device 100 side includes an input BUF (buffer) 6311, a first output BUF (buffer) 6312, a second output BUF (buffer) 6313, a receiving circuit 6314, and A transmission circuit 6315 is provided.
The input BUF 6311 is a buffer that temporarily stores data received by the receiving circuit 6314. The first output BUF 6312 and the second output BUF 6313 are buffers that temporarily store data transmitted from the transmission circuit 6315 to the reception circuit 6314 of the transmission destination (payout control apparatus 210).
The reception circuit 6314 on the game control device 100 side is a circuit for receiving data transmitted from the transmission circuit 6315 of the transmission source (payout control device 210). In the receiving circuit 6314, the data output via the SIOTX1 terminal (see FIG. 4) provided in the game arithmetic processing device 600 of the payout control device 210 is the SIORX terminal provided in the game arithmetic processing device 600 of the game control device 100. (See FIG. 4).
The transmission circuit 6315 is a circuit for transmitting data stored in the first output BUF 6312 and the second output BUF 6313. The transmission circuit 6315 transmits data to the receiving circuit 6314 on the payout control device 210 side via the SIOTX1 terminal provided on the game processing device 600 on the game control device side and the SIORX terminal provided on the game operation processing device 600 of the payout control device 210. Is output.

The encrypted transmission / reception circuit 632 includes a transmission / reception BUF (buffer) 6321, a control REG (register) 6322, a status REG (register) 6323, a transmission / reception control unit 6324, an encryption unit 6325, a transmission BUF (buffer) 6326, a decryption unit 6167, A reception BUF (buffer) 6328 and a transmission / reception unit 6329 are provided.
The transmission / reception BUF 6321 is a buffer that temporarily stores data exchanged between the CPU core 601 and the transmission / reception control unit 6324. The encryption unit 6325 has a transmission BUF 6326, receives data stored in the transmission / reception BUF 6321 via the transmission / reception control unit 6324, encrypts it, and stores it in the transmission BUF 6326. The transmission BUF 6326 is a buffer that temporarily stores the data encrypted by the encryption unit 6325.

The transmission / reception unit 6329 transmits the encrypted data stored in the transmission BUF 6326 to the payout control device 219 side. Further, the transmission / reception unit 6329 receives the encrypted data transmitted by the transmission / reception unit 6329 of the encryption transmission / reception circuit 632 of the game processing unit 600 of the payout control device 210.
The decryption unit 6327 includes a reception BUF 6328, decrypts the encrypted data received by the transmission / reception unit 6329, and stores the decrypted data in the reception BUF 6328. The reception BUF 6328 is a buffer that temporarily stores the data decoded by the decoding unit 6327.
The transmission / reception control unit 6324 (regular connection determination means) includes a game arithmetic processing device 600 (hereinafter referred to as a game control side chip) of the game control device 100 and a game arithmetic processing device 600 (hereinafter referred to as a payout control side) of the payout control device 210. It is a circuit that controls encrypted transmission / reception in order to realize mutual authentication by a chip). As will be described later, the mutual authentication result is stored in the status REG 6323. The means for executing the storage is the transmission / reception control unit 6324, and the transmission / reception control unit 6324 takes most of the mutual authentication procedure. Therefore, the transmission / reception control unit 6324 performs mutual authentication with the payout control device (prize value giving control device) via the cryptographic communication means, and the payout control device connected based on the result of the mutual authentication is authorized. It can be said that it is a normal connection determination means for determining whether or not the payout control device is a correct one.

  The control REG 6322 is a register used for setting or resetting a request flag for requesting transmission / reception, mutual authentication, initialization of an encrypted transmission / reception circuit, and the like. Various requests are made by writing a predetermined value in a predetermined bit of the control REG 6322. The status REG 6323 (determination result storage means) is a register that stores the statuses of the presence / absence of received data, data communication abnormality (reply data is not returned, etc.), and mutual authentication results (whether they match). The status REG 6323 is a determination result storage unit that stores the result of mutual authentication.

  The procedure of data transmission / reception between the game control device 100 and the payout control device 210 will be described with reference to FIG. FIG. 17 is a sequence diagram showing a procedure when data is transmitted / received between the game control device 100 and the payout control device 210. FIG. 17A is a sequence diagram when data is transmitted from the game control device 100, and FIG. 17B is a sequence diagram when the game control device 100 receives data. In FIG. 17, what is surrounded by a solid rectangle indicates a procedure related to transmission / reception between the game control device 100 and the payout control device 210. In FIG. 17, what is surrounded by a broken-line rectangle indicates a procedure by internal control. The internal control means that the control REG 6322 or the status REG 6323 is operated by the operation of the transmission / reception control unit 6324 in the encrypted transmission / reception circuit 632 itself.

  As shown in FIG. 17A, when data is transmitted from the game control device 100 to the payout control device 210, first, transmission data is set in the transmission / reception buffer 6321 by the game control side chip (1701). Then, a transmission request TX = 1 is sent to the payout control side chip (1702). When the payout control side chip receives a transmission request from the game control side chip, it internally sets a flag of the reception request RX = 1 accordingly (1711). Then, the reception data is acquired from the transmission / reception buffer (1712), and the reception request RX = 0 is sent to the game control side chip (1713). When the game control side chip receives it, it knows that the payout control side chip has received it, internally resets the transmission request TX = 0 and the transmission request flag (1703), and reflects the transmission result in the status REG ( 1704).

  As shown in FIG. 17B, when the game control device 100 receives data from the payout control device 210, the game control side chip first sends a reception request RX = 1 (1751). In response to this, the payout control side chip internally sets the transmission request flag TX = 1 (1761). Then, transmission data is set in the transmission / reception buffer (1762), and a transmission request TX = 0 is sent to the game control side chip (1763). When receiving it, the game control side chip internally resets the reception request flag to RX = 0 (1752), and reflects the reception result in the status REG (1753). Furthermore, “reception data present” is reflected internally in the status REG (1754). Then, the received data is obtained from the transmission / reception buffer (1755), and then “no received data” is reflected internally in the status REG.

  In addition, the game control apparatus 100 side has the initiative in data transmission / reception between the game control apparatus 100 and the payout control apparatus 210 shown in FIG. Both the transmission request and the reception request can be made from the game control device side, and neither the transmission request nor the reception request can be made from the payout control device side.

Next, a mutual authentication method between the game control device 100 and the payout control device 210 will be described.
A plurality of identifiers are stored in the game arithmetic processing device 600 (amuse chip) on both the game control side and the payout control side. The game control side chip randomly selects one identifier from the plurality of identifiers, and transmits the selected identifier to the payout control side chip.
When the payout control side chip receives the identifier transmitted from the game control side chip, it determines whether or not there is an identifier that matches the received identifier among the plurality of identifiers stored in the payout control side chip.
When determining that there is an identifier that matches the received identifier among the plurality of identifiers stored in the payout control side chip, the payout control side chip selects one of the plurality of identifiers stored in the payout control side chip. One identifier is selected at random, and the selected identifier is transmitted to the game control side chip.
When the game control side chip receives the identifier transmitted from the payout control side chip, it determines whether or not there is an identifier that matches the received identifier among the plurality of identifiers stored in the game control side chip.
When the game control side chip determines that there is an identifier that matches the received identifier among the plurality of identifiers stored in the game control side chip, mutual authentication is performed.
The configuration of the payout control side chip is the same as that of the game control side chip and functions in the same manner.

  FIG. 6 is a block diagram showing a connection between the game control device 400 and the payout control device 210 by providing a game control device 400 functioning as a plaintext type game control device instead of the game control device 100 of the embodiment of the present invention. FIG. According to the phrase that the game control device 400 shown in FIG. 6 is a plaintext type, it can be said that the game control device 100 shown in FIG. 5 is an encryption type game control device. Plain text refers to the exchange of data that is not encrypted.

The game control device 400 includes a game arithmetic processing device 700 including a general-purpose microcomputer 702, a serial transmission / reception circuit 701, and a pull-up circuit 703 instead of the amuse chip 600 provided in the game control device 100. The gaming arithmetic processing device 700 does not include the encrypted transmission / reception circuit 632 (see FIG. 5) provided in the gaming arithmetic processing device 600, but the other configurations are the same as those of the gaming microcomputer 101. ing.
Further, the general-purpose serial transmission / reception circuit 701 provided in the game arithmetic processing device 700 of the game control device 400 may be provided externally to the general-purpose microcomputer 702. The general-purpose serial transmission / reception circuit 701 has a function equivalent to that of the serial transmission / reception circuit 631 and is a circuit that is connected to the serial transmission / reception circuit 631 of the payout control device 210 and transmits / receives plain text data. The game processing unit 700 of the game control device 400 includes a pull-up circuit 703, but other configurations (input I / F 105, output I / F 106, etc .: see FIG. 3) are for the game control device 100. This is the same as the arithmetic processing unit 600.

The general-purpose serial transmission / reception circuit 701 includes an input BUF (buffer) 7011, a reception circuit 7012, a first output BUF (buffer) 7013, a second output BUF 7014, and a transmission circuit 7014.
The input BUF 7011 is a buffer that temporarily stores data received by the receiving circuit 7012. The reception circuit 7012 is a circuit for receiving data transmitted from the transmission circuit 6315. Data output via the SIOTX1 terminal of the transmission circuit 6315 included in the game arithmetic processing device 600 of the payout control device 210 is input to the reception circuit 7012.
The first output BUF 7013 and the second output BUF 7014 are buffers that temporarily store data transmitted from the transmission circuit 7014. The transmission circuit 7014 is a circuit for transmitting data stored in the transmission BUF 7013. The transmission circuit 7014 outputs data via the SIOTX1 terminal, and sends the data to the reception circuit 6154 included in the game arithmetic processing device 600 of the payout control device 210.

The general-purpose microcomputer 702 is a processor (CPU) that executes arithmetic processing and controls the game control device 400, a ROM that stores a program and data for controlling the game control device 400, and a work area when the CPU operates. RAM is provided.
The pull-up circuit 703 is a circuit for applying a constant voltage of 5 volts to the transmission / reception unit 6329 of the encryption transmission / reception circuit 632 of the payout control apparatus 210. When exchanging gaming machines in the game hall, the payout control device remains fixed in the hall, and it is normal to exchange only the game control device side. By having this pull-up circuit 703, the payout control device can be used regardless of whether the game control device is an encryption type or a plaintext type while supporting the encryption type. Details will be described later with reference to FIGS. 14, 15, and 16, but the CPU 212 of the payout control device 210 performs processing by distinguishing whether the game control device 100 is an encryption type or a plain text type (step of FIG. 14). S1416-1418, see steps S1512-1514 of FIG. 15).

  Next, processing on the game control device 100 side, that is, processing executed by the CPU 102 of the gaming microcomputer 101 (the CPU core 601 in FIGS. 4 and 5) will be described with reference to FIGS.

[Main processing]
First, the main process will be described. The main process loads and executes the boot program stored in the boot block 613 when the power is turned on (including when the system is reset from a power failure and when the system is reset). After each peripheral circuit enters the control of the CPU core 601, the game program stored in the user program ROM 602 is read and the CPU core 601 starts the program. This main process includes a loop process that is repeatedly executed. This is because the timer interrupt process can be executed in any one of the loop processes, and the player plays a game in the timer interrupt process.

  In the main process, as shown in FIG. 7, first, an interrupt prohibition process (step S1) is performed, and then an interrupt vector setting process (step S2) for setting a jump destination vector address to be executed when an interrupt occurs. ), A stack pointer setting process (step S3) for setting a stack pointer that is the start address of an area in which a value of a register or the like is saved when an interrupt occurs, and an interrupt mode setting process (step S4) for setting an interrupt processing mode I do.

  Next, in order to wait for the program of the payout control device (payout board) 210 (prize value assignment control device) to start up normally, a time of, for example, 4 msec is waited (step S5). As a result, when the power is turned on, the game control device 100 rises first and sends the command to the payout control device 210 before the payout control device 210 starts up, thereby preventing the payout control device 210 from losing the command. be able to.

  Subsequently, mutual authentication is executed (S6). Execution of mutual authentication here means setting necessary for mutual authentication (setting a flag of mutual authentication execution request to a predetermined bit of control REG 6322) and setting for instructing execution of mutual authentication. means. The mutual authentication procedure is performed by exchanging encrypted transmission / reception circuits as described above (see FIG. 5), and is executed by the sequence shown in FIG. 17, and includes a game control side chip and a payout control side chip. It is made by exchanging several times between. The execution of mutual authentication in S6 of FIG. 7 means the start of these series of processes. Therefore, when the mutual authentication is started in S6 of FIG. 7, most of the mutual authentication procedures are thereafter performed between the encrypted transmission / reception circuit 632 of the game control side chip and the encryption transmission / reception circuit 632 of the payout control side chip. When the mutual authentication is completed, the result is written in the status REG 6323. As will be described later, the CPU core 601 of the game control side chip checks that the mutual authentication is completed in S33 of FIG. 8, and proceeds to S34 and thereafter.

  After S6 in FIG. 7, access to a read / write RWM (read / write memory: RAM 104, 604) such as RAM or EEPROM is permitted, and all output ports are set to off (no output) (step S7, S8). In addition, a process for setting the serial port not to be used is performed (step S9). The serial port is a port that is preinstalled in the amuse chip 600. In this embodiment, encrypted communication is performed with the payout control device 210 and parallel communication with the effect control device 150 is not used.

Subsequently, it is determined whether or not the RAM clear SW (initialization switch) in the power supply device 160 is turned on (step S10). Here, if it is determined that the initialization switch is off (step S10; No), it is checked whether the value of the power failure inspection area 1 in the RWM is the normal power failure inspection area check data 1 (step S11). If determined to be normal (step S12; Yes), it is checked whether the value of the power failure inspection area 2 in the RWM is normal power failure inspection area check data (step S13). If the value of the power failure inspection area 2 is normal (step S14; Yes), the checksum of the predetermined area in the RWM is calculated (step S15), and the calculated checksum is compared with the checksum at the time of power interruption. (Step S16), it is determined whether they match (Step S17). And when it corresponds (step S17; Yes), it transfers to step S18 of FIG. 8, and performs the process at the time of recovering normally from a power failure.
Here, the RAM 104 of the RWM stores a power failure flag (power failure confirmation information) (for example, in the power failure inspection area 1). This flag is stored in the RAM 104 in step S48 or step S49 of the power-off process when it is determined in step S31 or step S44 described later that a power failure has occurred. In the check of step S11 or step S12, if this power failure flag is checked and it means that this power-on is to recover from the power failure, it is assumed that it is normal, and after the check sum calculation processing of step S15 Proceed to As a result of checking the power failure flag, if this power-on is not recovered from the power failure, it is determined that it is not normal in step S12 or step 14, and the process proceeds to step S25 in FIG.

  If it is determined that the initialization switch is on (step S10; Yes), the power failure confirmation information is not a predetermined value that means power failure recovery (step S12; No). If it is determined that the data is not normal data (step S14; No), if it is determined that the checksum is not normal (step S17; No), the process proceeds to step S25 in FIG. 8 to perform initialization processing. .

  In step S18 of FIG. 8, all the power outage inspection areas are cleared, the checksum area is cleared (step S19), and the areas related to errors and fraud monitoring are reset (step S20). Next, an area for storing the gaming state in the RWM is examined to determine whether or not the gaming state is a high probability state (step S21). If it is determined that the probability is not high (step S21; No), steps S22 and S23 are skipped and the process proceeds to step S24.

  If it is determined in step S21 that the probability is high (step S21; Yes), the ON information is saved in the high probability notification flag area (step S22), for example, the high provided in the display device 8 (see FIG. 3). The ON (lighting) data of the probability notification LED (error indicator) is saved in the segment area (step S23). And the process (step S24) which transmits the command at the time of the power recovery corresponding to the process number (refer FIG. 19) prepared in order to rationally perform the below-mentioned special figure game process is performed (step S24). Then, the process proceeds to step S30. The command at the time of power recovery is a command for instructing the effect control device 150 to display a power-on image indicating that the power has been turned on and has returned to normal from a power failure. Upon receiving this command, the effect control device 150 displays a predetermined image on the display device 8.

On the other hand, when jumping from step S10, S12, S14, S17 to step S25, all work areas before the access-prohibited area are cleared (step S25), and all stack areas after the access-prohibited area are cleared. (Step S26), the initial value at power-on is saved in the area to be initialized (Step S27). And the time value of the period which outputs the external information regarding RWM clear is set (step S28), the command at the time of power-on is transmitted to the effect control device 150 (step S29), and the process proceeds to step S30. The command at power-on is the power-on image display and RAM initialization indicating that the memory that was holding the previous game content was restored and was initialized without being restored. This is a command for instructing the effect control device 150 to output an initialization notification sound indicating this.
It should be noted that the power-on image sent in step S24 and the power-on image sent in step S29 have similar screens, so that the player does not notice the difference between them, and the inspector in the factory and the store clerk at the amusement store differ. It may be something that you notice.

  The flow from step S7 in FIG. 7 to step S24 in FIG. 8, and the flow from step S25 in FIG. 8 to step S29 in FIG. If this power-on process is grasped from the viewpoint of the power failure flag (power failure confirmation information) stored in the memory (RWM: RAM 104), the power failure confirmation information is a predetermined value with reference to the power failure confirmation information stored in the memory. While the game information held in the memory is held as it is (from step S7 to step S24), if the power failure confirmation information is other than a predetermined value (step S12; No), the memory is initialized. It can be said that this is a power-on process (from step S25 to step S29). Then, these power-on processes are executed based on the power-on, and settings are made to instruct the encrypted transmission / reception circuit 632 (particularly, the transmission / reception control unit 6324: normal connection determination means) to start executing mutual authentication. (Step S6). Since the power-on process and the mutual authentication are executed in parallel, the time from power-on to the start of game control can be shortened.

  Further, in step S24 and step S29, a command transmission process for instructing display of a power-on image indicating that power is turned on to the effect control device 150 is executed, and then a predetermined determination result is stored in the determination result storage means. Since the determination whether or not the predetermined determination result is stored in the determination result storage means is repeatedly performed until it is stored, mutual authentication is performed when checking the start-up of the gaming machine when shipping from the factory. Since it is possible to confirm that the gaming machine has been started before the completion of the inspection, the inspection can be made more efficient.

  In the power failure detection process (step S30), the power failure detection signal input from the power failure detection circuit 169 of the power supply device 160 is read and checked at least twice via the input port (step S30). It is determined that a power failure has occurred when the signal indicates (step S31). If a power failure has occurred (step S31; Yes), the process proceeds to a shutdown process (power-off process) after step S45 in FIG. 9, and a power failure occurrence flag (power failure confirmation information) is displayed in the power failure inspection area of the RAM in step S48 or S49. ) And save. If no power failure has occurred (step S31; No), the process proceeds to step S32.

In step S32, it is determined whether or not a timeout has occurred. This timing can be measured by a timer from the execution of mutual authentication (step S6). Further, it is possible to set a timeout by counting the number of times the processing loop from step S30 to step S33 has been repeated and repeating the loop a predetermined number of times instead of counting by the timer. At this time, it is possible to save RAM by using a register for counting the number of loops.
In the case of time-out (step S32; Yes), a time-out error occurrence command is output to the effect control device 150, and the process proceeds to the shutdown process after step S45. When it is not time-out (step S32; No), it progresses to step 33.

  In step S33, it is checked whether or not mutual authentication has been completed. Specifically, a predetermined bit of the status REG 6323 is checked to check whether or not a flag indicating that mutual authentication has been performed is set. If a flag indicating that mutual authentication has been performed is set (step S33; Yes), the process proceeds to step S34. If the flag indicating that the mutual authentication has been made is not set (step S33; No), the process returns to step S30.

  In step S34, it is checked whether a communication error has occurred during the mutual authentication procedure. Specifically, a predetermined bit of the status REG 6323 is checked to check whether or not a flag for notifying abnormality of data communication is set. An abnormality in data communication is, for example, that no communication result is returned. If a communication error occurs during the mutual authentication procedure (step S34; Yes), a communication error occurrence command is transmitted to the effect control device 150, and the process proceeds to the shutdown process after step S45. If no communication error has occurred (step S34; No), the process proceeds to step S35.

  In step S35, permission to fire is set. Specifically, a firing permission signal is turned ON for the firing control device 170. The launch control device 170 receives both the launch permission signal from the game control device and the launch permission signal from the payout control device, and controls so that the launch device 171 can launch only when both are ON signals. (See FIG. 3). After confirming that the mutual authentication is completed (step S33; Yes) and confirming that there is no communication error (step S34; No), the emission permission signal is turned on (step S35). This is because after the mutual authentication is completed and the game controller 100 and the payout controller 210 have determined that the other party is authorized by the regular connection judging means, the game ball is inserted into the game board. Means you ca n’t fire.

A characteristic part of this embodiment is that a power failure is detected in a series of mutual authentication check processes from step S30 to step S35.
That is, whether or not a predetermined determination result is stored in the determination result storage unit until a predetermined determination result is stored in the status REG 6323 (determination result storage unit) in order to specify whether or not mutual authentication has been completed. (Step S33; if NO, return to step S30) and repeatedly determine whether or not a power failure detection signal, which is a condition for starting the power-off process, has been detected (step S30) (step S30). To the step S33).
As a result, even if a power failure occurs during the execution of mutual authentication, the power failure processing after step S45 is executed and then the shutdown is performed. Therefore, the state before the power failure can be normally restored when the power failure is recovered.

  In step S36, a process of starting a CTC (Counter / Timer Circuit) circuit that generates a timer interrupt signal and a random number update trigger signal (CTC) in the gaming microcomputer 600 (clock generator 609) is performed. The CTC circuit is provided in the clock generator 609 in the amuse chip (game microcomputer) 600. The clock generator divides the oscillation signal (original clock signal) from the crystal oscillator and the timer interrupt with a predetermined period (for example, 4 milliseconds) to the CPU core 601 based on the divided signal. And a CTC circuit that generates a random number update trigger signal CTC that gives a trigger for updating a random number supplied to the signal and random number generation circuit 608.

  After the CTC activation process in step S36, a process for setting the activation of the random number generation circuit is performed (step S37). Specifically, the CPU core 601 sets a code (designated value) for starting the random number generation circuit in a predetermined register (CTC update permission register) in the random number generation circuit 608. Then, the values of the predetermined registers (soft random number registers 1 to n) in the random number generation circuit at the time of power-on are changed to various initial value random numbers (random numbers for determining the big hit symbol (big hit symbol random number 1, big hit symbol random number 2) After saving the initial value (start value) of a random number for determining the normal hit (per random number) in a predetermined area of the RWM (step S38), the interruption is permitted (step S41). The random number generation circuit 608 in the CPU 600 used in the present embodiment is configured such that the initial value of the soft random number register changes every time the power is turned on, and thus this value is used as the initial value (start value) of various initial value random numbers. By doing so, it is possible to break the regularity of random numbers generated by software, making it difficult for a player to obtain illegal random numbers.

  Subsequently, an initial value random number update process (step S42) is performed to update the values of various initial value random numbers to break the regularity of the random numbers. In the present embodiment, although not particularly limited, the big hit random number is configured to be generated using a random number (big hit random number) generated in a random number generation circuit. That is, the big hit random number is a hard random number generated by hardware, and the big hit symbol random number is a soft random number generated by software.

  After the initial value random number update process in step S42, the number of times (two or more) that the power failure detection signal input from the power supply device 160 is read and checked via the input port is set (step S43). Is determined to be ON (step S44). If no power failure has occurred (step S44; No), the process returns to the initial value random number update process (step S42). That is, when no power failure has occurred, the initial value random number update processing and the power failure detection signal check (loop processing) are repeated. By permitting an interrupt before the initial value random number update process (step S42) (step S41), if a timer interrupt occurs during the initial value random number update process, the interrupt process is executed with priority. Can be prevented from being interrupted by waiting for the initial value random number update process.

  Note that the initial value random number update process in step S42 includes a method of performing an initial value random number update process in the timer interrupt process in addition to the main process. In order to avoid execution of the value random number update process, when performing the initial value random number update process in the main process, it is necessary to disable the interrupt and then update to cancel the interrupt. If the initial value random number update process in the timer interrupt process is not performed in the main process and only the main process is performed, there is no problem even if the interrupt is canceled before the initial value random number update process. There is an advantage that it is simplified.

When a power failure detection signal is generated (step S44; Yes), a process for temporarily prohibiting interruption (step S45) is performed, and a process for setting a firing stop (turning off the firing permission signal) is performed (step S46). ), Processing for outputting OFF data to all output ports (step S47).
Thereafter, a power failure occurrence flag is set in the power failure inspection area of the RAM based on the determination result in step S44, the power failure recovery inspection area check data 1 is saved in the power failure recovery inspection area 1 (step S48), and the power failure recovery inspection area 2 is saved. The power failure recovery inspection area check data 2 is saved (step S49). Further, after performing the process of calculating the checksum when the RWM is turned off (step S50) and the process of saving the checksum (step S51), the process of prohibiting access to the RWM (step S52) is performed. Wait until the gaming machine is powered off. In this way, the check data is saved in the power failure recovery inspection area and the checksum at the time of power shutdown is calculated, so that whether or not the information stored in the RWM before the power shutdown is correctly backed up can be checked. This can be determined when the power is turned on again.
A series of processing from step S45 to step S52 is performed when a power failure detection signal output from the power supply device is used as an execution start condition when the supply voltage supplied from the power supply device decreases to a predetermined voltage. This corresponds to a power-off process in which a power failure flag (power failure confirmation information) indicating that the operation has been performed is stored in the memory and waits until power is turned off.

  Here, in step S46, the process of setting the firing stop, that is, the process of turning off the firing permission signal (the process of outputting the firing prohibition signal), the process in which the power-off process outputs the firing prohibition signal. It can be said that it contains. Therefore, the launch of the game ball by the launching device is prohibited by executing the power-off process. According to this, a game ball is fired during execution of the power-off process and a state in which a prize ball is not performed does not occur even though the game ball is won, and the player suffers a disadvantage. This can be prevented.

[Timer interrupt processing]
Next, timer interrupt processing will be described with reference to the flowchart of FIG. The timer interrupt process interrupts the main process and is executed every time the interrupt timer expires. In this specification, it may be simply referred to as interrupt processing. The timer interrupt process shown in FIG. 10 is started when a periodic timer interrupt signal generated by the CTC circuit in the clock generator is input to the CPU core 601 (see FIG. 4).

  When the timer interrupt process is started, first, a register saving process (step S61) is performed in which a value held in a predetermined register is transferred to the RWM. In the Z80 microcomputer used as the gaming microcomputer in this embodiment, the processing can be replaced by saving the value held in the front register to the back register. Next, input processing (step S62) is performed in which inputs from various sensors (special drawing start switch 36a, general diagram start switch 34a, count switch 38a, etc.) are taken, that is, the state of each input port is read. Then, based on the output data set in various processes, an output process (step S63) for performing drive control of an actuator such as a solenoid (large winning opening SOL38, ordinary power SOL90) or the like is performed.

  Next, command transmission processing (step S64), random number update processing 1 (step S65), random number update processing 2 (step) (step S64) for outputting commands set in the transmission buffer in various processes to the production control device 150, the payout control device 210, and the like. S66) is performed. After that, it is monitored whether there is a normal signal input from the special figure start switch 36a, the ordinary figure start switch 34a, the count switch 38a, the winning opening switch 32a. A winning opening switch / error monitoring process (step S67) is performed. Also, a special figure game process (step S68) for performing a process related to the special figure variation display game and a general figure game process (step S69) for performing a process related to the common figure variation display game are performed.

  Next, a segment LED editing process (step S70), which is provided in the gaming machine 10 and drives a segment LED that displays special information variation game and various information related to the game to display desired contents, a magnetic sensor switch, A magnet fraud monitoring process (step S71) is performed in which a detection signal from a vibration sensor switch (not shown) is checked to determine whether there is any abnormality. Then, external information editing processing (step S72) is performed in which signals to be output to various external devices are set in the output buffer.

  Next, encrypted communication processing (step S73) is performed. This is a process for performing award ball data and a payout instruction by encrypted communication with the payout control device. Specifically, this will be described later with reference to FIGS.

  Following the encrypted communication process (step S73), a process of clearing the interrupt request and declaring the end of the interrupt (step S74) is performed, and a process of restoring the register data saved in step S61 (step S75) is performed. After that, a process for permitting an interrupt (step S76) is performed, and the timer interrupt process is terminated.

[Encrypted communication processing]
FIG. 11 is a flowchart showing details of the encrypted communication process (step S73 in FIG. 10) in the timer interrupt process of the game control device according to the first embodiment. In the encrypted communication process, first, the mutual authentication result stored in the status REG 6323 indicates whether or not the mutual authentication between the game control device and the payout control device has been completed, that is, whether or not a mutual connection has been obtained. This is checked by checking (step S731). If mutual authentication has not been completed (step S731; No), a mutual authentication error occurrence command is set (step S736) and the process returns. Here, the mutual authentication error occurrence command is a command sent from the game control device 100 to the effect control device 150 and emits an error notification LED 17 to emit a warning sound to the speakers 19a and 19b. This means that any one or a combination of effects such as displaying a mutual authentication error occurrence is performed.

If mutual authentication has been completed (step S731; Yes), whether a communication error has occurred next is checked by checking a predetermined bit of the status REG 6323 to determine whether a flag indicating an abnormality in data communication is set (step). S732). If a communication error has occurred (step S732; Yes), a communication error occurrence command is transmitted and returned (step S734). The communication error occurrence command is a command transmitted by the game control device 100 to cause the effect control device 150 to execute a predetermined effect.
If no communication error has occurred (step S732; No), an encrypted communication reception process (see FIG. 12) (step S735) and an encrypted communication transmission process (see FIG. 13) (step S737) are executed and the process returns. Note that “RET” in the flowchart of FIG. 11 means that the process returns to the position where step S73 of FIG. 10 is executed, that is, the process proceeds to step S74 (clears the interrupt request) of FIG.

[Encrypted communication reception processing]
FIG. 12 is a flowchart showing details of the encrypted communication reception process in the encrypted communication process shown in FIG. First, whether or not there is received data is checked by checking a predetermined bit of the status REG 6323 to determine whether or not a flag indicating that there is received data is set (step S7351). If there is no received data (step S7351; No), the encrypted communication reception process is terminated. If there is received data (step S7351; Yes), data of the transmission / reception BUF 6321 is acquired (step S7352). Then, it is determined whether or not the received data is a prize ball completion command (command indicating that the prize ball has been paid out) (step S7353). If the command is not a winning ball completion command (step S7353; No), the encrypted communication reception process ends. If it is a winning ball completion command (step S7353; Yes), the encrypted reception flag stored in the status REG 6323 is cleared (step S7354), and the winning ball payout counter stored in the user work RAM 604 is displayed. It updates (step S7355), and this encrypted communication reception process ends.

[Encrypted communication transmission processing]
FIG. 13 is a flowchart showing details of the encrypted communication transmission process in the encrypted communication process shown in FIG. First, it is determined whether or not encrypted reception is being performed by checking a flag (step S7371). If encrypted reception is in progress (step S7371; Yes), this encrypted communication transmission process ends (means that the process proceeds to step S74 in FIG. 10, the same applies hereinafter).
If encrypted reception is not being performed (step S7371; No), a flag is checked to determine whether encrypted transmission is being performed (step S7372). If encrypted transmission is in progress (step S7372; Yes), whether or not payout reception is completed is checked based on whether or not the transmission request flag is 0 (step S7373). If the payout reception has not been completed (step S7373; No), the encrypted communication transmission process ends.
When the payout reception is completed (step S7373; Yes), the reception request flag is set (step S7374), the encrypted reception flag is set (step S7375), and the encrypted transmission flag is cleared (step S7375). Step 7376), the encrypted communication transmission process is terminated.
If encrypted transmission is not in progress at step 7372 (step 7372; No), it is determined by checking a predetermined address in the user work RAM 604 whether there is a transmission waiting ball command (step 7377).

If there is no awaiting transmission ball command (step S7377; No), dummy data (substantially meaningless data to be sent to the payout control device, for example, a command for instructing to pay out zero game balls) is sent to the transmission / reception buffer. It is set (step S7378), a transmission request flag is set (step S7379), and the encrypted communication transmission process is terminated.
If there is a prize ball command waiting for transmission (step S7377; Yes), the prize ball command is set in the transmission / reception buffer (step S7380), a transmission request flag is set (step 7381), and an encrypted transmission flag is set. (Step S 7382), this encrypted communication transmission process ends.

The processes related to the encrypted communication performed by the CPU core 601 by executing the program are only the encrypted communication reception process and the encrypted communication transmission process, and the remaining part of the encrypted communication is the above-described encrypted transmission / reception circuit. 632 is provided on each of the game control device 100 side and the payout control device 210 side, and is realized by communication between the two encrypted transmission / reception circuits 632. The purpose of setting the dummy data in the transmission / reception buffer in step S7378 described above and setting the transmission request flag in step S7379 is to detect unauthorized replacement of the board. Even if there is an act of illegally exchanging the board aiming at a time when there is no data exchange between the game control device and the payout control device, the transmission and reception of dummy data will cause abnormal data communication. Since the status REG 6323 stands as a flag, fraud can be detected.
The transmission / reception request flag is stored in the control REG 6322, and the flags relating to the presence / absence of received data and abnormal data communication are stored in the status REG 6323.
From FIG. 12 and FIG. 13, the next prize ball command is not transmitted from the game control device to the payout control device unless the prize ball completion command indicating that the payout for one prize ball command is completed is received. Yes.

[Processing on the payout control device side]
Processing executed by the gaming microcomputer 211 (the CPU 212 in FIG. 3 and the CPU 601 in FIGS. 4 and 5) of the payout control device 210 (prize value giving control device) will be described with reference to FIGS.

  First, based on the flowcharts of FIGS. 14 and 15, when the gaming machine 10 is turned on (including when it recovers from a power failure and when it is restarted by a system reset), the payout control device 210 starts executing. Processing will be described. In the main process, the CPU core 601 loads and executes the boot program stored in the boot block 613. After each peripheral circuit enters the control of the CPU core 601, the payout control program stored in the user program ROM 602 The processing is started when the CPU core 601 is read and the program is executed.

  FIG. 14 is the first of the two flowcharts showing the main process of the payout control apparatus. In the main processing, first, prohibition of timer interruption performed at a predetermined time period (for example, 1 millisecond period) (step S1401), and an interrupt vector for setting a jump destination vector address to be executed when an interruption occurs. Setting (step S1402), setting of each interrupt mode (step S1403), permission to access the RAM of the payout control device 210 (step S1404), initial setting of CPU peripheral devices (circuits connected to the CPU bus) of the payout control device 210 Setting is performed (step S1405), and a stack pointer is set (step S1406) for setting a stack pointer that is the start address of an area for saving a value of a register or the like when an interrupt occurs.

  Further, it is determined whether or not the RAM clear SW (switch) 162 (see FIG. 3) provided in the power supply device 160 is turned on and an operation for initializing the RAM of the payout control device 210 has been performed (step S1407). When it is determined that the RAM clear SW 162 is not ON, the power is turned on at the time of power failure recovery by determining whether or not the power failure recovery information indicating the recovery from the power failure is set in the RAM. It is determined whether or not (step S1408). If it is determined that the power is turned on when the power failure is restored, it is checked whether the checksum is normal in order to determine whether the data stored in the RAM is corrupted (step S1409). , S1410). Specifically, it is determined whether or not the checksum of the data stored in the RAM when a power failure occurs matches the checksum of the data currently stored in the RAM. When it is determined that the checksum is normal, that is, when it is determined that the data stored in the RAM is normal, the power failure recovery process is executed and the initial value at the time of power failure recovery is stored in the RAM. Setting is performed (step S1411).

  On the other hand, if it is determined in step S1407 that the RAM clear SW 162 is ON, or if it is determined in step S1408 that the power is not turned on when the power failure is restored, or if the checksum is abnormal in step S1410. If it is, the data stored in all the RAMs to be used is cleared (step S1412), the initial value at power-on is set in the RAM (step S1413), and the tax rate corresponding to the tax rate setting SW is set. It is set (step S1414), the lending amount per game ball set by the lending fee setting switch 227 is set (step S1415), and the RAM 214 of the payout control device 210 is initialized.

  If the initialization of the RAM or the initial value at the time of power failure recovery is set in the RAM, then whether the connection with the game control device 100 is an encrypted connection, an unencrypted connection, an encryption It is determined whether the connection is established (step S1416). Specifically, it is checked whether or not there is data in the input BUF (buffer) 6311 of the serial transmission / reception circuit 631 on the payout control device side shown in FIGS. The process waits in step S 1416 until data indicating that the connection type is non-encrypted connection or encrypted connection is stored in the input BUF (buffer) 6311. In the case of non-encrypted connection, information related to the connection type is transmitted from the game control device 100 side by non-encrypted connection (asynchronous serial communication, UART function). If it is determined that the connection is an encrypted connection (step S1416; Yes), it is set that the connection type is an encrypted connection in an area for storing the connection type information in the RAM 214 on the payout control device side (step S1417). If it is determined that the connection is not an encrypted connection (step S1416; No), the fact that the connection type is a non-encrypted connection is set in the area for storing the connection type information in the RAM 214 on the payout control device side (step S1418).

  Next, the PRDY signal for notifying the card unit 70 of whether or not the game ball can be rented is set to ON (step S1419). Then, a CTC (Counter / Timer Circuit) that is a timer for measuring time and generating a timer interrupt signal or the like is set (S1420), and the timer interrupt prohibited in step S1401 is set to be permitted (S1421).

  FIG. 15 is the second of the two flowcharts showing the main process of the payout control apparatus.

  After setting the timer interrupt permission, it is determined whether or not the card unit 70 is connected to the payout control device 210 (step S1501). If it is determined that the card unit 70 is connected, the launch control device 170 receives a game ball. A launch permission signal for permitting firing is set to ON (launch permitted state) (step S1502). If it is determined that the connection is not established (step S1501; No), the firing control device 170 is set to a state where the launching of the game ball is not permitted (a firing permission signal OFF state) (step S1503). The launch control device 170 is a device that controls the launch device 171. When the launch permission signal from the game control device 100 is ON and the launch permission signal from the payout control device is ON, the launch device 171 is a game. Control to launch a sphere.

  Next, information on which of the payout control modes is acquired (step S1504). Then, the process is branched depending on the acquired payout control mode (mode 0, mode 1, mode 2) (step S1505). In the case of mode 0, an excessive payout error monitoring process for monitoring whether or not game balls are excessively paid out is executed (step S1506). Then, a payout device control start determination process is executed in order to start the process of actually paying out the game ball (step S1509).

  In mode 1, a prize ball control process for setting the number of game balls to be paid out as a prize ball is executed (step S1507), a payout control process for controlling the payout motor 220 is executed, and a game ball is awarded as a prize ball. (Step S1510).

  In the case of mode 2, a ball lending control process for setting the number of game balls to be paid out as a lending ball is executed (step S1508), a payout control process for controlling the payout motor 220 is executed, and a game ball is lended. (Step S1510).

  If the processing corresponding to each mode is executed, error notification editing processing (step S1511) for editing notification of an error that has occurred during the game ball payout operation is executed. The error notification is performed by outputting to the error number display 222.

  Next, communication processing with the game control apparatus 100 is performed. First, it is determined with reference to the connection type information written in advance in the RAM 214 whether or not the connection type is an encrypted connection (step S1512). If the connection type is encrypted connection (step S1512; Yes), an encrypted communication process (step S1513, more specifically, see steps S1601 to S1609 in FIG. 16) is executed. If the connection type is not encrypted connection (step S1512; No), unencrypted communication processing (step S1514) is executed. Since the non-encryption process is a method that has been frequently performed in the past, detailed explanation is omitted here, but one of the game control device side sends prize ball data and payout instruction information to the payout control device. Communication.

  After the communication with the game control device, whether or not the power failure detection signal input to the gaming microcomputer 211 from the power failure detection circuit 169 of the power supply device 160 is read twice from the port and indicates whether or not the power failure has occurred twice. Thus, it is determined whether or not a power failure has occurred (step S1515). If it is determined that a power failure has occurred (step S1515; Yes), a series of power-off processing, that is, interrupt prohibition setting (step S1516), all output ports (Step S1517), a power failure flag is set in the power failure inspection area of the RAM 214 of the payout control device 210 and the power failure recovery information is stored in the RAM (step S1518), and the checksum of the data in the RAM before the power supply to the RAM is cut off Calculation and storage (step S1519), access to RAM prohibited (step S1520) Look, wait until the power of the gaming machine 10 is turned off.

  If it is determined in step S1515 that no power failure has occurred (step S1515; No), the process returns to step S1501, and the processes from step 1501 to step S1515 are repeated.

  FIG. 16 is a flowchart showing details of the encrypted communication process (step S1513 in FIG. 15) in the main process of the payout control apparatus. First, it is determined whether mutual authentication has been completed (step S1601). Under the initiative of the game control device, mutual authentication between the game control device and the payout control device is executed in the main process (step S6 in FIG. 7) on the game control device side. As described above with reference to the block diagram of FIG. 5 and the sequence diagram of FIG. 17, most of the mutual authentication procedure is performed by the encryption transmission / reception circuit 632 on the game control device 100 side and the encryption transmission / reception circuit 632 on the payout control device 210 side. The mutual authentication result is stored not only in the status REG 6323 of the encrypted transmission / reception circuit 632 on the game control device side but also in the status REG 6323 of the encryption transmission / reception circuit 632 on the payout control device 210 side. Has been. Whether or not the mutual authentication in step S1601 in FIG. 16 has been completed is determined by the CPU 212 of the game microcomputer 211 of the payout control device 210 (the CPU core 601 of the amuse chip 600) in the encrypted transmission / reception circuit 632 in the amuse chip. This is done by confirming the mutual authentication result stored in a predetermined bit of a certain status REG 6323.

  If mutual authentication has not been completed (step S1601; No), the process returns (proceeds to step S1515 in FIG. 15 and returns to step S1501 if no power failure has occurred. The same applies to the description of FIG. 16 below). Thereby, when the mutual authentication is not completed, a prize ball payout instruction is not sent from the game control device to the payout control device.

  If mutual authentication has been completed (step S1601; Yes), it is checked whether there is a reception request (step S1602). This determination is executed depending on whether or not a reception request flag is set in a predetermined bit of the control REG 6322 on the payout control apparatus side. If it is determined that there is a reception request (step S1602; Yes), it is further determined whether or not the number of prize balls of the received prize ball command has reached a specified number (for example, 16) (step S1603). When the number of winning balls of the received command reaches the specified number (step S1603; Yes), the reception request flag stored in a predetermined bit of the control REG 6322 on the payout control device side is cleared (step S1607). Return. This is to avoid receiving commands that cannot be processed. If the prize ball command indicates 16 or more prize balls, it is discarded as an abnormal command due to noise or the like.

  If the number of winning balls of the received command has not reached the specified number in step S1603 (step S1603; No), the number is added to the remaining number of acquired gaming balls stored in a predetermined area of the payout control device side RAM 214 (step S1603). S1605), the reception request flag of the control REG 6322 is cleared (step S1607), and the process returns.

  If it is determined in step S1602 that there is no reception request (step S1602; No), it is determined whether there is a transmission request (step S1604). This determination is executed depending on whether or not a transmission request flag is set in a predetermined bit of the control REG 6322 on the payout control apparatus side. If it is determined that there is a transmission request (step S1604; Yes), it is checked whether the remaining number of acquired game balls stored in a predetermined area of the payout control device side RAM 214 has become zero (step S1606). If the remaining number of game balls acquired becomes zero (step S1606; Yes), a prize ball completion command (a command for notifying that all prize balls for which a payout instruction has been paid out has been paid out) is transmitted to the game control device side. (Step S1608). Then, the transmission request flag of the control REG 6322 on the payout control device side is cleared (step S1609), and the process returns.

  If it is determined in step S1604 that there is no transmission request, or if it is determined in step S1606 that the remaining number of game balls is not zero, the process returns.

  Note that when the encrypted communication transmission process on the game control device side is described with reference to FIG. 13, if there is no transmission-pending ball command (step S7377), dummy data is set in the transmission / reception buffer (step S7378), and a transmission request is issued. It has been proposed that a series of processing of setting a flag (step S7379) realizes continuous transmission / reception between the game control device side and the payout control device side to prevent unauthorized exchange of boards. The dummy data is a prize ball command for instructing to pay out zero game balls, so that the process of step S1603, step S1605, step S1607 is passed, or the received command has reached the specified number in step 1603. As described above, it is possible to pass any one of the processes exiting to step S1607.

  The encrypted communication process shown in FIG. 16 is performed at the initiative of the gaming device side as in the encrypted communication in the mutual authentication, and is executed according to the sequence shown in FIG. That is, based on a transmission / reception request from the game control device, a prize ball command (a command for instructing a predetermined number of prize ball payouts) is received and a prize ball completion command is transmitted. Therefore, the game control device can confirm that the prize ball has been paid out and send the next command. On the game control device side, the winning ball command accepted by the payout control device and the winning ball command that has not been accepted can be identified, so that the winning ball command that has not been accepted can be transmitted again. Unlike a conventional case where a payout instruction is sent unilaterally (in a running state) in unencrypted (plaintext type) communication, a payout instruction with high reliability is made.

  Further, according to FIG. 16 described above, since the payout control device does not transmit the prize ball completion command unless the payout for one prize ball command is completed, the next prize ball command is not transmitted from the game control device to the payout control device. become. As a result, for example, the number of game balls to be paid out due to the occurrence of a power failure is not properly backed up, and damage to the player is minimized even in the event of a power failure recovery.

  More specifically, each award ball command is specifically described: a 3 award ball command for instructing to award 3 game balls, a 5 award ball command for instructing to award 5 game balls, 10 By reducing the number of payouts in each award ball command to 10 or less, such as 10 award ball commands for instructing the payout of individual game balls, it is possible to minimize the damage in the above-mentioned emergency case It becomes. In the case where the transmission of the dummy data described above is treated as a zero prize ball command, the game control device side returns a response indicating that the payout control device side has received it when the zero prize ball command is transmitted to the payout control device side. Will not be retransmitted even if it is returned, but for the original prize ball command of the three prize ball command, five prize ball command, and ten prize ball command, a reply indicating that it has been received from the payout control device side is returned. If not, it can be retransmitted.

[Invention 1]
From the first embodiment described above, it is monitored whether or not a power failure has occurred until the execution of mutual authentication is completed. If a power failure occurs, a power failure process is performed in which a power failure flag is stored in the RAM. The invention to be extracted is extracted and proposed as Invention 1.

That is, the gaming machine in the invention 1 is
A game control device for overall control of a game, a prize value giving control device that is connected to the game control device and performs control for giving a player a prize value in accordance with a prize value giving command from the game control device, and the game In a gaming machine comprising a power supply device for supplying power to a control device and a prize value giving control device,
The game control device includes:
Memory that can hold game information even in the event of a power failure with a backup power supply,
A gaming microcomputer for controlling the progress of the game,
The gaming microcomputer is:
Encrypted communication means capable of transmitting / receiving encrypted encrypted data to / from the prize value giving control device;
Mutual authentication is performed with the connected prize value assignment control device via the encryption communication means, and the connected prize value assignment control device is authorized based on the result of the mutual authentication. Regular connection determination means for determining whether or not the grant control device;
A determination result storage means for storing a result of mutual authentication when mutual authentication by the normal connection determination means is completed,
When the supply voltage supplied from the power supply device is reduced to a predetermined voltage, the power failure detection signal output from the power supply device is used as an execution start condition, and power failure confirmation information indicating that a power failure has occurred is stored in the memory. Power off processing to save and wait until power off,
The power failure confirmation information stored in the memory is referred to. When the power failure confirmation information has a predetermined value, the game information held in the memory is held as it is, while the power failure confirmation information is a predetermined value. Is a power-on process for initializing the memory, and is configured to be executable,
Performing the power-on process based on power-on, and setting to instruct the regular connection determination means to start execution of the mutual authentication,
After the execution of the mutual authentication is started, a predetermined result is stored in the determination result storage unit until a predetermined determination result is stored in the determination result storage unit in order to specify whether or not the mutual authentication is completed. It is characterized in that the determination as to whether or not the determination result has been stored is repeatedly performed, and the determination as to whether or not the power failure detection signal, which is an execution start condition of the power-off process, has been detected is repeatedly performed.

Here, the prize value refers to a profit given to the player for winning the player. Specifically, for example, it means that a predetermined number of game balls are paid out.
The award value giving control device is, for example, a payout control device that controls payout of game balls.
The power supply device not only supplies DC32V, DC15V, DC12V, DC5V, etc. to each part (device, circuit, etc.) of gaming machines including game control devices and prize value control devices, but also performs power failure detection and power failure. This device is equipped with a power failure detection circuit that sends detection signals to each part, and supplies the backup power necessary to perform normal power failure processing in the event of a power failure and to retain the information stored in the memory until the time of power failure recovery .
Power outages include not only those caused by changes in power supply conditions such as lightning strikes, fires, and earthquakes, but also human artifacts such as unplugging power cords from outlets.
The power failure confirmation information includes not only when the power failure flag is set, but also when information is written to the table, including information related to power failure (for example, power failure detection results) stored in memory in a state where the information can be referenced. Say.
The power-off refers to stopping the gaming machine by cutting off the power supply from a state where power is supplied to the game control device of the gaming machine.
The power-on means that the game control device of the gaming machine is energized and the CPU constituting the gaming microcomputer performs a boot process and starts operation. Rebooting (restarting) by system reset is also included in the power-on here.
The gaming microcomputer is designed as a one-chip microcomputer, for example, and includes a CPU core, ROM, RAM, and several peripheral circuits (random number generation circuit, clock generator, reset interrupt control circuit, serial connection to the internal bus) A transmission / reception circuit).
The encryption communication means can use an encrypted transmission / reception circuit provided as a peripheral circuit connected to the internal bus of the gaming microcomputer, but may be provided as an external circuit of the gaming microcomputer (amuse chip). Absent.
The regular connection determination means can use a transmission / reception control unit provided in the encryption communication means (encrypted transmission / reception circuit). After the CPU core starts the mutual authentication process, the normal connection determination unit (transmission / reception control unit) manages the mutual authentication process, and writes the determination result storage unit when obtaining the mutual authentication result.
As the determination result storage means, a status REG (register) provided in the encryption communication means (encrypted transmission / reception circuit) can be used.
Mutual authentication refers to a procedure for authenticating each other's validity between two devices. For example, mutual authentication is performed to determine the legitimacy of the connected partner's control device depending on whether or not the other party has randomly selected from a plurality of identification information possessed by its own gaming microcomputer.

  According to this, since it was decided to instruct the normal connection determination means to start the mutual authentication, it was possible to repeatedly determine whether or not the mutual authentication was completed and to repeatedly determine the power failure detection signal. Therefore, even if a power failure occurs during the execution of mutual authentication, it is possible to restore to the state before the power failure normally when the power failure is restored.

Also, the above gaming machine,
The processing executed by the gaming microcomputer for controlling the gaming machine includes main processing including loop processing that is repeatedly executed, and timer interrupt processing that is executed every time the interrupt timer expires for the main processing. Have
The gaming microcomputer is:
The power-on process is executed in the main process,
Prior to the execution of the power-on process, a setting for instructing the regular connection determination means to start execution of the mutual authentication is performed,
A gaming machine can be provided in which the power-on process and the mutual authentication are executed in parallel.

  According to this, the power-on process and the mutual authentication process are executed in parallel after the setting for instructing the normal connection determination means to start the mutual authentication before the power-on process is executed. The time from game start to game control start can be shortened.

In the above gaming machine,
A display device that displays an effect image corresponding to the progress of the game;
An effect control device that controls display on the display device based on a control command from the gaming microcomputer,
The gaming microcomputer is:
In the power-on process executed when the power is turned on, a process for instructing the display control device to display a power-on image indicating that the display device is turned on is executed.
The determination result storage means until a predetermined determination result is stored in the determination result storage means after instructing the display device to display a power-on image indicating that the power is turned on by executing the power-on process. It is possible to provide a gaming machine characterized by repeatedly determining whether or not a predetermined determination result is stored.

  According to this, in the power-on process, a process for instructing the effect control device to display the power-on image is executed. Therefore, the mutual authentication is completed when the start-up check is performed at the time of shipment of the gaming machine from the factory. Since it can be confirmed by visual recognition of the display device that the gaming machine has been activated before, the inspection can be made more efficient.

In the above gaming machine,
A launcher that launches a game ball onto the game board; and
A firing control device for controlling the operation of the firing device,
The gaming microcomputer is:
The launch control device is configured to control the launch device by outputting a launch permission signal for allowing the launch control device to launch a game ball and a launch prohibiting signal for prohibiting the launch of the game ball,
In the power-off process executed based on the power failure detection signal output from the power supply device, including a process of outputting the firing prohibition signal,
According to the present invention, it is possible to provide a gaming machine in which the launching of the game ball by the launching device is prohibited by executing the power-off process.

  According to this, since a firing prohibition signal is output in the power-off process, a game ball is launched during execution of the power-off process, and a state in which a prize ball is not performed occurs despite winning a winning opening. Therefore, the player can be prevented from suffering a disadvantage.

In the above gaming machine,
The supply voltage supplied from the power supply device is monitored, and when the supply voltage supplied from the power supply device drops to a predetermined voltage lower than the detection voltage of the power failure detection signal, a reset signal is sent to the game First reset signal output means for outputting to the microcomputer for use;
A second reset signal output means for starting timing by a predetermined reset timer and outputting a reset signal to the gaming microcomputer based on the time-up of the reset timer;
The gaming microcomputer is:
The power-off process executed based on a power failure detection signal output from the power supply device includes a process of starting time measurement of the reset timer,
It is possible to provide a gaming machine characterized in that the reset timer is started by executing the power-off process.
The power-off process using the second reset signal output means will be described later with reference to FIG.

  According to this, since the process of starting the timing of the reset timer of the second reset signal output means is included in the power-off process, the first reset is performed even though the power failure detection signal is output during the execution of the mutual authentication. Even when the reset signal from the signal output means is not output, it is possible to reliably return.

[Invention 2]
From the first embodiment described above, it is monitored whether or not a power failure has occurred until the execution of mutual authentication is completed. If a power failure occurs, a power failure process is performed in which a power failure flag is stored in the RAM. The invention to be extracted was extracted and proposed as Invention 1. As a second aspect of the invention, there is further proposed a gaming machine that outputs a launch permission signal for permitting the launch control device to launch when the validity of the payout control device is recognized by executing mutual authentication.

That is, the gaming machine in the invention 2 is
A game control device for overall control of the game;
An award value giving control device which is connected to the gaming control device and performs a control for giving an award value to a player by an award value giving command from the gaming control device;
A power supply device for supplying power to the game control device and the prize value giving control device;
In a gaming machine comprising a launch control device that controls the operation of a launch device that launches a game ball on a game board,
The game control device includes:
Memory that can hold game information even in the event of a power failure with a backup power supply,
A gaming microcomputer for controlling the progress of the game,
The gaming microcomputer is:
Encrypted communication means capable of transmitting / receiving encrypted encrypted data to / from the prize value giving control device;
Mutual authentication is performed with the connected prize value assignment control device via the encryption communication means, and the connected prize value assignment control device is authorized based on the result of the mutual authentication. Regular connection determination means for determining whether or not the grant control device;
A determination result storage means for storing a result of mutual authentication when mutual authentication by the normal connection determination means is completed,
When the supply voltage supplied from the power supply device is reduced to a predetermined voltage, the power failure detection signal output from the power supply device is used as an execution start condition, and power failure confirmation information indicating that a power failure has occurred is stored in the memory. Power off processing to save and wait until power off,
With reference to the power failure confirmation information stored in the memory, when the power failure confirmation information has a predetermined value, the game information held in the memory is retained as it is, while the power failure confirmation information is other than the predetermined value. In some cases, a power-on process for initializing the memory is configured to be executable,
Performing the power-on process based on power-on, and setting to instruct the regular connection determination means to start execution of the mutual authentication,
After the execution of mutual authentication is started, a predetermined determination is made in the determination result storage means until a predetermined determination result is stored in the determination result storage means in order to specify whether or not the mutual authentication has been completed. Repeatedly determining whether or not the result is stored, and repeatedly determining whether or not the power failure detection signal, which is an execution start condition of the power-off processing, is detected,
If it is determined by the determination that the determination result storage means stores a determination result indicating that the apparatus is a regular prize value giving control device, the launch control device is permitted to launch a game ball. A firing permission signal is output.

  According to this gaming machine, since the normal connection determination means is instructed to start the mutual authentication, it is possible to repeatedly determine whether or not the mutual authentication is completed and to repeatedly execute the determination of the power failure detection signal. As a result, even when a power failure occurs during the execution of mutual authentication, the state before the power failure can be restored normally when the power failure is restored. In addition, it is possible to prevent a state in which a game ball is launched and a prize ball is not performed during the mutual authentication, and it is possible to prevent a player from being disadvantaged.

Also, the above gaming machine,
The processing executed by the gaming microcomputer for controlling the gaming machine includes main processing including loop processing that is repeatedly executed, and timer interrupt processing that is executed every time the interrupt timer expires for the main processing. Have
The gaming microcomputer is:
The power-on process is executed in the main process,
Prior to the execution of the power-on process, a setting for instructing the regular connection determination means to start execution of the mutual authentication is performed,
A gaming machine can be provided in which the power-on process and the mutual authentication are executed in parallel.

  According to this, the power-on process and the mutual authentication process are executed in parallel after the setting for instructing the normal connection determination means to start the mutual authentication before the power-on process is executed. The time from game start to game control start can be shortened.

Furthermore, in the above gaming machine,
A display device that displays an effect image corresponding to the progress of the game;
An effect control device that controls display on the display device based on a control command from the gaming microcomputer,
The gaming microcomputer is:
In the power-on process executed when the power is turned on, a process for instructing the display control device to display a power-on image indicating that the display device is turned on is executed.
The determination result storage means until a predetermined determination result is stored in the determination result storage means after instructing the display device to display a power-on image indicating that the power is turned on by executing the power-on process. It is possible to provide a gaming machine characterized by repeatedly determining whether or not a predetermined determination result is stored.

  According to this, in the power-on process, a process for instructing the effect control device to display the power-on image is executed. Therefore, before the mutual authentication is completed in the case of checking the start-up of the gaming machine at the time of shipment. Since it is possible to confirm that the gaming machine has been activated, it is possible to improve the efficiency of the inspection.

Furthermore, in the above gaming machine,
A launcher that launches a game ball onto the game board; and
A firing control device for controlling the operation of the firing device,
The gaming microcomputer is:
The launch control device is configured to control the launch device by outputting a launch permission signal for allowing the launch control device to launch a game ball and a launch prohibiting signal for prohibiting the launch of the game ball,
In the power-off process executed based on the power failure detection signal output from the power supply device, including a process of outputting the firing prohibition signal,
According to the present invention, it is possible to provide a gaming machine in which the launching of the game ball by the launching device is prohibited by executing the power-off process.

  According to this, since a firing prohibition signal is output in the power-off process, a game ball is launched during execution of the power-off process, and a state in which a prize ball is not performed occurs despite winning a winning opening. Therefore, the player can be prevented from suffering a disadvantage.

In the above gaming machine,
The supply voltage supplied from the power supply device is monitored, and when the supply voltage supplied from the power supply device drops to a predetermined voltage lower than the detection voltage of the power failure detection signal, a reset signal is sent to the game First reset signal output means for outputting to the microcomputer for use;
A second reset signal output means for starting timing by a predetermined reset timer and outputting a reset signal to the gaming microcomputer based on the time-up of the reset timer;
The gaming microcomputer is:
The power-off process executed based on a power failure detection signal output from the power supply device includes a process of starting time measurement of the reset timer,
It is possible to provide a device characterized in that the reset timer starts counting by executing the power-off process.
The power-off process using the second reset signal output means will be described later with reference to FIG.

  According to this, since the process of starting the timing of the reset timer of the second reset signal output means is included in the power-off process, the first reset is performed even though the power failure detection signal is output during the execution of the mutual authentication. Even when the reset signal from the signal output means is not output, it is possible to reliably return.

[Embodiment 2]
Embodiment 2 common to Invention 1 and Invention 2 will be described with reference to FIGS. 18 and 19. Most of the second embodiment is common to the first embodiment. In the first embodiment, the start screen command is sent to the effect control device so that it can be visually confirmed that the gaming machine has been started before the mutual authentication is completed (steps S24 and S29 in FIG. 8). In the second embodiment, this is advanced one step, and before the mutual authentication is completed, a command for further performing a variable display game is sent to the display device.
FIG. 18 is the second of the three flowcharts showing the main process of the game control device according to the second embodiment. In the second embodiment, the first and third of the three flowcharts showing the main process of the game control device are the same, and only a part of the second is different. The difference is that in FIG. 8 of the first embodiment, the processing of S36 “Activate CTC” that was between Step S35 “Set launch permission” and Step S37 “Start setting of random number circuit” is different from Step 24 and Step 30. It is the point which moved between (step S29 and step S30). The step numbers of “Start CTC” after the movement are renumbered in Step 291 and FIG.

  As a result, the timer interrupt process (FIG. 10) can be performed without waiting for the mutual authentication completion determination (step S33), and the game can be started, in particular, the special game process (S68). This helps to prevent the player from getting irritated when waiting for mutual authentication for a long time. However, when the mutual authentication is not completed, the prize ball cannot be paid out. Accordingly, there is a limit to the contents that can be processed in the special figure game process.

  FIG. 19 is a flowchart showing the special game process in the timer interrupt process in the second embodiment. Among the processes depicted in FIG. 19, 20 processes from step A1 to step A20 indicate the special figure game process in the first embodiment. In the second embodiment, steps A21 and A22 are added. There are only two determination processes.

Here, the flow of the special figure game process in the first embodiment will be first described. In the special figure game process of the first embodiment, the start port switch monitoring process is executed (step A1), the count switch monitoring process is executed (step A2), the special figure game process timer is updated by minus 1, and the time is up. When checked (step A3) and time is up (step A4; Yes), the special figure game sequence branch table is set in the register (step A5), and the branch destination address of the process corresponding to the special figure game process number is acquired (step A5). Step A6), the return address after the branch process is completed is saved in the stack area (Step A7), and the process number is branched (Step A8). Here, the process number 0 is a special figure normal process (step A9), the process number 1 is a special figure changing process (step A10), the process number 2 is a special figure display process (step A11), and the process number is 3 is a fanfare / interval process (step A12), process number 4 is a big prize opening release process (step A13), process number 5 is a big prize mouth remaining ball process (step A14), and process number 6 is a big hit. Processing (step A15). Then, after branching to these processes, when the process is finished, each data of the table prepared by the branch process is saved in the work area (step A16), and a table is prepared for controlling the special figure 1 (step A17). The symbol fluctuation control process is executed (step A18), a table for controlling the special figure 2 is prepared (step A19), the symbol fluctuation control process is executed (step A20), and the process returns to the timer interrupt process of FIG. Then, the process proceeds to the general game process (step S69) next to the special figure game process (step S68).
If the time is not up in step A4 (step A4; No), the process from step A17 to step A20 is performed, and then the process returns to the timer interrupt process in FIG.

  Such special figure game processing in the first embodiment cannot be started unless mutual authentication is completed, as shown in FIG. In the second embodiment, the timing at which the CTC is activated is changed so that the interrupt process and thus the special game process can be started before it is determined that the mutual authentication is completed. Of the seven process numbers of the special figure game process, the process numbers 0, 1, and 2 are processes in which no prize ball is paid out, and the process numbers are 3, 4, 5, 6, 7 Focusing on the fact that the process is related to the prize ball payout, whether or not mutual authentication has been completed between step A2 and step A3 (step A21) and the process number is 2 or less. If the mutual authentication has been completed (step A21; Yes), the process proceeds to step A3 to enable processing for all process numbers, and the mutual authentication has not been completed. In the case (step A21; No), a determination is made as to whether the process number is 2 or less (step A22), and only when the process number is 0, 1, or 2, the execution is enabled. Process number is 3, 4, 5 If 6 is any one of, after the processing in step A17-A20, it is obtained by a return to the timer interrupt processing of FIG. 10.

  As can be seen from step A3 and step A4, the special figure game has a special figure game processing timer, and the process can proceed to step A5 and subsequent steps when the time is up. Therefore, for the player, the first short time must be consumed. In view of such circumstances, it is in the interest of the player to enter the game without waiting for the completion of mutual authentication.

[Invention 3-Example 1]
Next, Embodiment 1 of Invention 3 will be described with reference to FIGS. FIG. 20 is a time chart 1 for explaining the first embodiment of the third invention. As described above, the power supply device 160 includes an AC-DC converter and a DC-DC converter, and generates DC32V (FIG. 20B) from AC24V (FIG. 20A), Furthermore, based on DC32V, DC15V (FIG. 20 (c)), DC12V (FIG. 20 (d)), and DC5V (FIG. 20 (e)) are generated, and these several types of DC power supplies are used for the game control device 100. , The payout control device 210, the production control device 150, and the like.

Furthermore, the power supply device 160 is provided with a power failure detection circuit 169, which monitors DC 32V and generates a power failure detection signal ((f) in FIG. 20) when the voltage drops to a predetermined voltage (power failure detection voltage). It is sent to each device (game control device 100, payout control device 210, production control device 150). Specifically, the power failure detection signal ((f) in FIG. 20) is an ON signal until a power failure is detected, and DC32V ((b) in FIG. 20) is between 17.2V and 19.5V. When the voltage drops to the power failure detection voltage (time t ₂ ), a power failure is detected and an OFF signal is output, and then an OFF signal is continuously output until the DC32V voltage recovers from 17.2 V to 19.5 V (FIG. 20). (F)). A predetermined delay corresponding to the characteristics of the AC-DC converter occurs from time t _{1 when} power is cut off at AC 24 V input to time t ₂ when power failure is detected.

As shown in FIG. 20 (c), DC15V power begins to drop near the time _{t 2, the} zero gently drops. Similarly DC12V, voltage DC5V is a relationship between the input voltage range of the switching regulator, the time t ₃ is delayed than, respectively begins to drop at time t _4, to zero gently lowered (FIG. 20 (d (E)). The allowable range of DC5V voltage is 4.75-5.25V. The reset circuits 109 and 219 (see FIG. 3) provided on the boards of the game control device 100 and the payout control device 210 as external circuits of the amuse chip 600 monitor the voltage of the DC5V power source. The detection voltage is 4.5 to 4.65V. Therefore, a reset signal is output at time t ₅ in FIG. 20 (FIG. 20 (g)). This reset signal outputs an OFF signal when the 5V voltage drops to the reset detection voltage, and is an ON signal otherwise. As described above, the reset signal is input to the RST terminal provided in the reset interrupt control circuit 610 of the amuse chip. The CPU core 601 system resets the CPU and its peripheral circuits (the entire game control device if the game control device 100, the entire payout control device if the payout control device).

  Here, the relationship between power failure detection and reset is organized from the viewpoint of power supply. In the case of the game control device 100, if a power failure occurs (step S31 in FIG. 8; Yes or Yes in step S44 in FIG. 9), the power is turned off by executing the power-off process (steps S45-S52). Wait for. In the case of the payout control device 210, if a power failure occurs (step S1515 in FIG. 15; Yes), a power-off process (steps S1516-1520) is executed to wait for the power to be cut off. The power necessary for executing these power-off processes is supplied to each device by a backup power supply 161. When the power failure detection circuit 169 detects a power failure, the power supply device 160 switches the power supply to each device to the supply from the backup power supply 161. As described above, the backup power supply 161 is composed of a large-capacity electrolytic capacitor. Each power supply supplies power that allows each device to perform power-off processing, and stores the contents stored in the RAM in each device during a power failure. It is designed to be able to supply power for holding. However, after completing the power-off process for backing up the data required for the RAM, the time until waiting for the power to be turned off remains maintained for each device. It consumes more power than the power required to hold it.

Therefore, it is desirable to generate the reset signal without delay after a sufficient time has elapsed to complete the power-off process. In the time chart shown in FIG. 20, a power failure detection signal is generated at time t ₂ , and using it as a start condition, power-off processing is performed in each device (game control device 100 and payout control device 210), and is stored in each RAM. A reset signal is generated at time t ₅ shortly after the data holding process is completed, and the CPU core 601 is reset. The reset (system reset) means that the CPU core 601 and its peripheral circuits are forcibly turned off and then turned on (returned on). Therefore, the CPU core 601 stops the power supply to the circuits in its own chip and substrate, and tries to start up the system again. At this time, the boot process is executed in accordance with the boot program stored in the boot block 613. However, the power is not supplied from the backup power supply 161 of the power supply device 160, but from the original AC24V through the AC-DC converter and the DC-DC converter. Power supply to be supplied. Without the power supply, the CPU core 601 does not start because the boot process cannot be completed. At this timing, the target to which the backup power supply 161 supplies power is switched to the RAM only.
If the power supply is cut off due to an earthquake, lightning, fire, etc., the data in the RAM will be held normally by the backup power supply until the situation is restored, and the next power-on. Is restored to normal power supply after a normal power failure recovery.

FIG. 21 is a time chart 2 for explaining the first embodiment of the third invention. This figure, the power failure detection signal at time t ₇ to a power failure occurs at time t ₆ (in FIG. 21 (f)) but is generated, the reset signal (FIG. 20 because of a power failure recovery time t ₉ immediately thereafter The case where (g)) does not occur is shown. In this case, the power-off process described above is performed with the detection of a power failure detection signal as a starting condition, and the game control device 100 and the payout control device 210 enter a state of waiting for the power to be cut off. In this state, it is impossible to return to the original state unless the store clerk notices the situation and turns on the power again.

  In the invention 3, when this problem is solved, the power interruption processing is performed based on the power failure detection signal output from the power supply device, and the supply voltage is lowered to a predetermined voltage lower than the detection voltage of the power failure detection signal In addition, in a gaming machine equipped with a game control device that outputs a reset signal to the microcomputer, even if an instantaneous power failure occurs and only the power failure detection signal is output, the state before the power failure is restored normally when the power failure is restored It is an object to provide a gaming machine that can be used.

And the gaming machine which becomes the solution in that case,
In a gaming machine comprising: a game control device that controls the game in an integrated manner; and a power supply device that supplies power to the game control device.
The game control device includes:
Memory that can hold game information even in the event of a power failure with a backup power supply,
A gaming microcomputer for controlling the progress of the game;
The supply voltage supplied from the power supply device is monitored, and when the supply voltage supplied from the power supply device drops to a predetermined voltage lower than the detection voltage of the power failure detection signal, a reset signal is sent to the game A first reset signal output means for outputting to the microcomputer for use,
The gaming microcomputer is:
A second reset signal output means for starting timing by a predetermined reset timer and outputting a reset signal to the gaming microcomputer based on the time-up of the reset timer;
When the supply voltage supplied from the power supply device drops to a predetermined voltage, the power failure confirmation information indicating that a power failure has occurred is stored in the memory based on a power failure detection signal output from the power supply device. Power-off processing to wait until power-off,
With reference to the power failure confirmation information stored in the memory, when the power failure confirmation information has a predetermined value, the game information held in the memory is retained as it is, while the power failure confirmation information is other than the predetermined value. In some cases, a power-on process for initializing the memory is configured to be executable,
The gaming microcomputer is:
The power cut-off process is executed based on the power failure detection signal, and a process for starting the time measurement of the reset timer is executed.
The power-off process using the second reset signal output means will be described later with reference to FIG.

  According to this gaming machine, even when a power failure detection signal is output and a reset signal is not output, it can be reliably restored without turning on the power again.

Also, the gaming machine,
A launcher that launches a game ball onto the game board; and
A firing control device for controlling the operation of the firing device,
The gaming microcomputer is:
The launch control device is configured to control the launch device by outputting a launch permission signal for allowing the launch control device to launch a game ball and a launch prohibiting signal for prohibiting the launch of the game ball,
In the power-off process executed based on the power failure detection signal output from the power supply device, including a process of outputting the firing prohibition signal,
It is also possible to provide a game ball that is prohibited from being launched by the launching device by executing the power-off process.

  According to this, since the firing prohibition signal is output in the power-off process that is executed when the power failure detection signal is detected, the game ball is launched during the power-stage process and the winning opening is won. Nevertheless, since a state where no prize ball is played does not occur, it is possible to prevent the player from suffering a disadvantage.

  In the first embodiment of the invention 3, in order to achieve this object, the main process and the timer interrupt process of the game control device are changed and the system reset is forcibly applied using the watch dog timer (WDT). Is. FIG. 22 is the second of three flowcharts showing the main process of the game control device according to the first embodiment of the third embodiment (first embodiment of the third embodiment). Most of the flowcharts (FIGS. 7, 8, and 9) showing the main process of the game control device in the first embodiment described above are the same, and the difference is that “launch permission setting” in step S35 and step S36 in FIG. That is, “WDT activation” in step S351 is inserted between “CTC activation”. That is, mutual authentication is completed (step S33; Yes), no communication error occurs (step S34; No), launch permission is set (step S35), and the main process is ready to start the game. By the way, the watchdog timer (WDT) is activated (step S351), and then the CTC is activated (step S36). The watchdog timer (WDT) counts the passage of a predetermined time, and forcibly stops and restarts the CPU when the time passes. The watchdog timer (WDT) is a circuit provided in the reset interrupt control circuit 610 in the gaming microcomputer (amuse chip) 600 as described above.

  FIG. 23 is a flowchart showing the timer interrupt process of the game control apparatus according to the first embodiment of the present invention. Since the CTC is activated in step S36 of the main process, the timer interrupt process is subsequently executed at a predetermined cycle. Most of the timer interrupt processing (FIG. 10) in the first embodiment is the same as that of FIG. 10, except that “WDT” in step S611 is “WDT” between “save register” in step S61 and “input processing” in step S62. It is that "clear" was inserted. This WDT clear means that the above-mentioned watchdog timer is initialized, that is, reset. If the WDT is not cleared, for example, the system is reset during the game, and the player's profit is lost. On the other hand, since interruption is prohibited when a power failure occurs and the power-off process is started (step S45 in FIG. 9), the WDT clear does not work after that, and the CPU is stopped and restarted after a predetermined time has elapsed. Is made. Therefore, the time setting of WDT is set in consideration of the time required to complete the execution of the backup process to the RAM in the power-off process.

[Embodiment 2 of Invention 3]
FIG. 24 is the third of the three flowcharts showing the main process of the game control device according to the second embodiment of the invention 3 (second embodiment of the invention 3). Similar to the first embodiment, the same problem is solved by using a watchdog timer (WDT). Most of the flowcharts (FIGS. 7, 8, and 9) showing the main process of the game control device in the first embodiment described above are the same, and the difference is that “interrupt is prohibited” in step S45 in FIG. This is in that “WDT activation” is inserted between “Launching stop”. In the second embodiment, a watchdog timer (WDT) is activated in the middle of the power-off process, and the CPU is stopped by determining the timing at which a series of RAM storage processes are completed. .

The power-off process using the watchdog timer (WDT) shown in FIG. 24 can also be executed in combination with the first embodiment or the second embodiment described above. It is also possible to combine with Invention 1 or Invention 2 described above.
If it is determined that a power failure has occurred (step S44 in FIG. 24; Yes or step S31 in FIG. 8; Yes), interruption is prohibited (step S45). As a result, timer interrupt processing such as special figure game processing is not performed. At this timing, the watchdog timer (WDT) is started (step S451). The watchdog timer (WDT) is a circuit provided in a reset interrupt control circuit 610 that is one of peripheral circuits connected to the internal bus of the amuse chip 600 shown in FIG. This corresponds to a second reset signal output means for starting timing and outputting a reset signal to the gaming microcomputer based on the time-up of the reset timer.

  As described above with reference to FIG. 3, the game control device 100 and the payout control device 210 are provided with reset circuits 109 and 219, respectively, which are circuits on the board and external to the amuse chip, This reset circuit monitors the supply voltage supplied from the power supply device, and when the supply voltage supplied from the power supply device drops to a predetermined voltage lower than the detection voltage of the power failure detection signal, the reset signal is This corresponds to first reset signal output means for outputting to the gaming microcomputer.

  In the present embodiment, even when the first reset signal output means does not output a reset signal, the next timing after the interruption of the power-off process (step S45) is performed in order to surely perform the reset. To start WDT. The length of time that the watchdog timer (WDT) counts is a relatively short time because it is a time for reliably executing the remaining steps of the power-off process from step S46 to step S52. For example, an appropriate length of time can be selected and set from the variation time values defining the variation display of the special figure variation display game.

FIG. 25 is a time chart for explaining Example 2 of Invention 3 (Example 2 of Invention 3). A power failure occurs at time t _11, a power outage is restored at time t _14. In this case the power failure detection signal (FIG. 25 (f)) is generated at time t _12, continues to output a signal indicating a power failure to the time t _15. DC15V, voltage of DC12V, once the voltage drops, begin to return from near the time t ₁₄ to its original state. Reset circuits 109 and 219 (when the supply voltage supplied from the power supply device is monitored and the supply voltage supplied from the power supply device drops to a predetermined voltage lower than the detection voltage of the power failure detection signal, the reset signal Since the reset signal (FIG. 25 (g)) output from the first reset signal output means for outputting the signal to the gaming microcomputer remains in the ON (High) state, the CPU receives the reset signal from the reset circuit. Does not stop. On the other hand, a watchdog timer (WDT: second reset signal output means for starting timing by a predetermined reset timer and outputting a reset signal to the gaming microcomputer based on the time-up of the reset timer) detection signal and starts counting immediately after the (FIG. 25 (f)) is generated, to generate a WDT reset at time t _16. This stops and restarts the system. With this processing, normal data is stored in the RAM, and the power supply from the backup power supply can be switched normally to the original power supply to restore the state before the power failure.

As described above, in the second embodiment of the present invention 3, the second reset signal output means (from step S45 to step S52) is executed in the power cut-off process (from step S45 to step S52) executed based on the power failure detection signal output from the power supply device. Including a process (step S451) for starting the timing of the reset timer (WDT) and starting the timing of the reset timer of the WDT by executing the power-off process, so that a power failure detection signal is output during the execution of mutual authentication Even if the reset signal is not output, it can be surely restored.
Since the time value set in the reset timer of the WDT only needs to be longer than the time required from t ₂ to t _{5 in} FIG. 20, for example, the variable display of the special figure variable display game stored in the ROM 103 is specified. it may be set to (longer than the time required until t ₅ from t ₂₎ the shortest time value of the variation time value.
As a result, it is possible to return to the state before the power failure without giving the player a sense of incongruity, and it is not necessary to newly provide a time value set in the reset timer of the WDT in the ROM 103, thereby saving the capacity of the ROM. it can.

In the above description, the power failure flag (power failure confirmation information) is stored in the power failure inspection area in the RAM 104, but may be stored in another area in the RAM 104. The power failure flag (power failure confirmation information) can function in the same manner as long as it is stored as information that can be referred to, such as writing a value in a predetermined table, as well as setting or resetting as a flag.
Further, in the above description, the timing for storing the power failure flag is set to step S48 or S49 of the shutdown processing (power shutdown processing), but the power failure flag is set in a predetermined area of the RAM in the power failure detection determination processing (step S31 or step S44). As a stand-up, the power failure flag storing process can be omitted in the power-off process.

  Note that the gaming machine 10 of the present invention is not limited to a pachinko gaming machine as shown in the above embodiment as a gaming machine, and for example, other pachinko gaming machines, arrange ball gaming machines, sparrow ball gaming machines. This is applicable to all gaming machines that use game balls such as.

  In addition, it should be considered that the embodiment disclosed this time is illustrative and not restrictive in all respects. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

8. Display device (display device)
10 gaming machine 100 game control device (game control device)
101, 211, 600 Microcomputer for game (microcomputer for game)
102, 601 CPU, CPU core 104 RAM (memory)
109, 219 Reset circuit (first reset signal output means)
150 Production Control Device 160 Power Supply Device (Power Supply Device)
161 Backup power supply 162 RAM clear SW
169 Power failure detection circuit 170 Launch control device 171 Launch device 210 Discharge control device (award value giving control device)
604 User work RAM (memory)
609 Clock generator (CTC)
610 Reset interrupt control circuit (WDT: second reset signal output means)
631 Serial transmission / reception circuit 632 Encryption transmission / reception circuit (encryption communication means)
6323 Status REG (judgment result storage means)
6324 Transmission / reception control unit (regular connection determination means)

Claims (5)

A game control device for overall control of a game, a prize value giving control device that is connected to the game control device and performs control for giving a player a prize value in accordance with a prize value giving command from the game control device, and the game In a gaming machine comprising a power supply device for supplying power to a control device and a prize value giving control device,
The game control device includes:
Memory that can hold game information even in the event of a power failure with a backup power supply,
A gaming microcomputer for controlling the progress of the game,
The gaming microcomputer is:
Encrypted communication means capable of transmitting / receiving encrypted encrypted data to / from the prize value giving control device;
Mutual authentication is performed with the connected prize value assignment control device via the encryption communication means, and the connected prize value assignment control device is authorized based on the result of the mutual authentication. Regular connection determination means for determining whether or not the grant control device;
A determination result storage means for storing a result of mutual authentication when mutual authentication by the normal connection determination means is completed,
When the supply voltage supplied from the power supply device is reduced to a predetermined voltage, the power failure detection signal output from the power supply device is used as an execution start condition, and power failure confirmation information indicating that a power failure has occurred is stored in the memory. Power off processing to save and wait until power off,
The power failure confirmation information stored in the memory is referred to. When the power failure confirmation information has a predetermined value, the game information held in the memory is held as it is, while the power failure confirmation information is a predetermined value. Is a power-on process for initializing the memory, and is configured to be executable,
Performing the power-on process based on power-on, and setting to instruct the regular connection determination means to start execution of the mutual authentication,
After the execution of the mutual authentication is started, a predetermined result is stored in the determination result storage unit until a predetermined determination result is stored in the determination result storage unit in order to specify whether or not the mutual authentication is completed. A game characterized by repeatedly determining whether or not a determination result has been stored and repeatedly determining whether or not the power failure detection signal, which is an execution start condition of the power-off processing, has been detected. Machine. The processing executed by the gaming microcomputer for controlling the gaming machine includes main processing including loop processing that is repeatedly executed, and interrupt processing that is executed every time the interrupt timer expires for the main processing. And
The gaming microcomputer is:
The power-on process is executed in the main process,
Prior to the execution of the power-on process, a setting for instructing the regular connection determination means to start execution of the mutual authentication is performed,
The gaming machine according to claim 1, wherein the power-on process and the mutual authentication are executed in parallel. A display device that displays an effect image corresponding to the progress of the game;
An effect control device that controls display on the display device based on a control command from the gaming microcomputer,
The gaming microcomputer is:
In the power-on process executed when the power is turned on, a process for instructing the display control device to display a power-on image indicating that the display device is turned on is executed.
The determination result storage means until a predetermined determination result is stored in the determination result storage means after instructing the display device to display a power-on image indicating that the power is turned on by executing the power-on process. The gaming machine according to claim 2, wherein the determination as to whether or not a predetermined determination result is stored is repeatedly performed. A launcher that launches a game ball onto the game board; and
A firing control device for controlling the operation of the firing device,
The gaming microcomputer is:
The launch control device is configured to control the launch device by outputting a launch permission signal for allowing the launch control device to launch a game ball and a launch prohibiting signal for prohibiting the launch of the game ball,
In the power-off process executed based on the power failure detection signal output from the power supply device, including a process of outputting the firing prohibition signal,
4. The gaming machine according to claim 3, wherein launching of a game ball by the launching device is prohibited by executing the power-off process. The supply voltage supplied from the power supply device is monitored, and when the supply voltage supplied from the power supply device drops to a predetermined voltage lower than the detection voltage of the power failure detection signal, a reset signal is sent to the game First reset signal output means for outputting to the microcomputer for use;
A second reset signal output means for starting timing by a predetermined reset timer and outputting a reset signal to the gaming microcomputer based on the time-up of the reset timer;
The gaming microcomputer is:
The power-off process executed based on a power failure detection signal output from the power supply device includes a process of starting time measurement of the reset timer,
5. The gaming machine according to claim 4, wherein the reset timer is started by executing the power-off process.

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