JP2012221524A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of reducing the amount of delay variation and excellently tracking delay on a bit line.SOLUTION: An SRAM comprises: a plurality of replica bit lines rplbt [0] to [p], which are arranged in a column direction; a plurality of replica memory cells RPLCELL which are respectively connected to the replica bit lines; and a plurality of inverters INV [0] to [p] which are respectively connected to the replica bit lines. The replica bit lines are mutually connected in common, the input terminals of the inverters are respectively connected to the replica bit lines, and the output terminals of the inverters are mutually connected in common, so that a sense amplifier enable signal is generated. The sense amplifier enable signal is supplied to sense amplifiers and thereby read signals of bit lines are amplified by the sense amplifiers, so that read data is generated from the output terminals of the sense amplifiers.

Description

  The present invention relates to a technology of a semiconductor memory device, and more particularly to a technology effective when applied to a semiconductor memory device that uses a delay of a replica bit line for generation timing of a sense amplifier enable signal.

  In recent years, in the technology of a semiconductor memory device, it is common to use a replica bit line delay for the generation timing of a sense amplifier enable signal. In this technique, there is a circuit that uses a single replica bit line and has a function of well tracking the delay of the bit line. In such a technique, there is a problem that when the memory capacity is increased, the delay fluctuation amount of the replica bit line is large. As a technique considering the reduction of the fluctuation amount, for example, a technique described in Patent Document 1 is cited.

  The technique of the above-mentioned patent document 1 divides one replica bit line in the row direction (word line direction) and reduces the delay amount of each divided replica bit line, thereby dividing each replica bit line. This is intended to reduce the delay fluctuation amount of the line. Therefore, it is a technology that can reduce the variation in the timing of generating the sense amplifier enable signal due to the reduced delay variation of each replica bit line and the local variation of the logic threshold value of the inverter that receives the delay of the replica bit line. is there.

JP 2010-165415 A

  By the way, in the technique of using the replica bit line delay for the generation timing of the sense amplifier enable signal as described above, in order to track the bit line delay well, only the replica bit line delay is used. Is good. However, in the technique of Patent Document 1 in which one replica bit line is divided and connected by an inverter, the required inverter bit delay is mixed with the required replica bit line delay. It is conceivable that the ability to track the delay well is impaired. In addition, since the number that can be divided is limited, the effect of reducing the delay fluctuation amount is also limited.

  Accordingly, the present invention has been made in view of the above-described problems, and a typical object thereof is to provide a semiconductor memory device capable of reducing the amount of delay variation and tracking the bit line delay satisfactorily. There is to do.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a typical semiconductor memory device is connected to a plurality of word lines arranged in the row direction, a plurality of bit lines arranged in the column direction, and the plurality of word lines and the plurality of bit lines, respectively. A plurality of normal memory cells; an access control circuit capable of selecting any one word line of the plurality of word lines in response to an address signal; and a plurality connected to the plurality of bit lines, respectively. And a sense storage amplifier having the following components.

  In the first semiconductor memory device, a plurality of replica bit lines arranged in a column direction, a plurality of replica memory cells respectively connected to the plurality of replica bit lines, and the plurality of replica bit lines And a plurality of inverters connected to each other. Further, the plurality of replica bit lines are connected in common, the input terminals of the plurality of inverters are connected to the plurality of replica bit lines, respectively, and the output terminals of the plurality of inverters are connected in common. A sense amplifier enable signal is generated. The sense amplifier enable signal is supplied to the plurality of sense amplifiers, so that the plurality of read signals of the plurality of bit lines are amplified by the plurality of sense amplifiers, and the plurality of output terminals of the plurality of sense amplifiers A plurality of read data is generated from the data.

  In the second semiconductor memory device, a plurality of replica bit lines arranged in a column direction, a plurality of replica memory cells respectively connected to the plurality of replica bit lines, and the plurality of replica bit lines And one inverter connected in common. Further, the plurality of replica bit lines are connected in common, the input terminal of the one inverter is connected to the plurality of replica bit lines, and a sense amplifier enable signal is generated from the output terminal of the one inverter. Is done. The sense amplifier enable signal is supplied to the plurality of sense amplifiers, so that the plurality of read signals of the plurality of bit lines are amplified by the plurality of sense amplifiers, and the plurality of output terminals of the plurality of sense amplifiers A plurality of read data is generated from the data.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, a typical effect is that it is possible to provide a semiconductor memory device that can reduce the amount of delay variation and can well track the delay of the bit line.

It is a figure which shows an example of a structure of SRAM using one replica bit line of a prior art. 1 is a diagram showing an example of a configuration of an SRAM using a plurality of replica bit lines according to an embodiment of the present invention. FIG. FIG. 3 is a diagram illustrating an example of a waveform of each part of the SRAM illustrated in FIG. 2. (A) is the SRAM shown in FIG. 1, and (b) is the SRAM shown in FIG. 2, the variation in the generation timing of the sense amplifier enable signal due to the delay variation of each replica bit line and the local variation of the logic threshold value of the inverter. FIG. It is a figure which shows the modification of the structure of SRAM which utilized multiple replica bit lines of embodiment of this invention.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of embodiments or sections. However, unless otherwise specified, they are not irrelevant and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently indispensable in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same members are denoted by the same reference numerals as, the repetitive description thereof will be omitted.

<Outline of Embodiment of the Present Invention>
A semiconductor memory device according to an embodiment of the present invention includes a plurality of word lines (wl) arranged in a row direction, a plurality of bit lines (bt, bb) arranged in a column direction, and the plurality of word lines. A plurality of normal memory cells (MEMCELL) respectively connected to the plurality of bit lines, and an access control circuit capable of selecting any one word line of the plurality of word lines in response to an address signal A semiconductor memory device having (WD, CTRL) and a plurality of sense amplifiers (SA) respectively connected to the plurality of bit lines, further comprising the following components.

  In the first semiconductor memory device, a plurality of replica bit lines (rplbt) arranged in a column direction, a plurality of replica memory cells (RPLCELL) respectively connected to the plurality of replica bit lines, And a plurality of inverters (INV) respectively connected to the plurality of replica bit lines. Further, the plurality of replica bit lines are connected in common, the input terminals of the plurality of inverters are connected to the plurality of replica bit lines, respectively, and the output terminals of the plurality of inverters are connected in common. A sense amplifier enable signal is generated. The sense amplifier enable signal is supplied to the plurality of sense amplifiers, so that the plurality of read signals of the plurality of bit lines are amplified by the plurality of sense amplifiers, and the plurality of output terminals of the plurality of sense amplifiers A plurality of read data is generated from the data. More preferably, it has a plurality of precharge transistors (PCH) respectively connected to the plurality of replica bit lines and a plurality of dummy memory cells (DMYCELL) respectively connected to the plurality of replica bit lines. It is characterized by. The first semiconductor memory device corresponds to an SRAM described with reference to FIG.

  In the second semiconductor memory device, a plurality of replica bit lines (rplbt) arranged in a column direction, a plurality of replica memory cells (RPLCELL) respectively connected to the plurality of replica bit lines, And an inverter (INV) commonly connected to a plurality of replica bit lines. Further, the plurality of replica bit lines are connected in common, the input terminal of the one inverter is connected to the plurality of replica bit lines, and a sense amplifier enable signal is generated from the output terminal of the one inverter. Is done. The sense amplifier enable signal is supplied to the plurality of sense amplifiers, so that the plurality of read signals of the plurality of bit lines are amplified by the plurality of sense amplifiers, and the plurality of output terminals of the plurality of sense amplifiers A plurality of read data is generated from the data. More preferably, it has a plurality of precharge transistors (PCH) respectively connected to the plurality of replica bit lines and a plurality of dummy memory cells (DMYCELL) respectively connected to the plurality of replica bit lines. It is characterized by. The second semiconductor memory device corresponds to an SRAM described with reference to FIG.

  The embodiment based on the outline of the embodiment of the present invention described above will be specifically described below. The embodiment described below is an example using the present invention, and the present invention is not limited to the following embodiment.

  In the following, in order to make the features of the embodiments of the present invention easier to understand, the description will be made in comparison with the prior art.

<Example of using one conventional replica bit line>
An example in which one conventional replica bit line is used will be described with reference to FIGS.

<< Configuration of SRAM >>
FIG. 1 is a diagram showing an example of the configuration of an SRAM using one conventional replica bit line.

  The SRAM shown in FIG. 1 includes a word driver WD, a decode control circuit CTRL, a replica word line rplwl, a plurality (j) of replica memory cells RPLCELL, a replica bit line rplbt, and a plurality (k). ) Dummy memory cell DMYCELL, a precharge transistor PCH, an inverter INV, and a buffer BUF.

  Further, the SRAM shown in FIG. 1 includes a plurality of word lines wl [0] to [n] and a plurality of bit line / inverted bit line pairs bt [0], bb [0] to bt [m], bb [ m], a plurality ((n + 1) × (m + 1)) SRAM / memory cells MEMCELL, and a plurality (m + 1) sense amplifiers SA.

  In the SRAM shown in FIG. 1, each circuit constituting the replica bit line rplbt and the inverter INV receiving the replica bit line rplbt are regarded as one replica circuit block RPLBLK.

  By supplying the clock signal CLK and the address signals a [0] to [h] to the decode control circuit CTRL, the decoder signals dec [0] to [i] are supplied from the decode control circuit CTRL to the word driver WD. The signal of the replica word line rplwl is supplied from the decode control circuit CTRL to the precharge transistor PCH and the plurality of replica memory cells RPLCELL.

  The source of the P channel MOS transistor as the precharge transistor PCH is connected to the power supply voltage VDD, while the drain of the P channel MOS transistor is connected to the replica bit line rplbt. The replica bit line rplbt is connected to a plurality of dummy memory cells DMYCELL, a plurality of replica memory cells RPLCELL, and an input terminal of the inverter INV.

  The signal of the inverted replica bit line rplbtn generated from the output terminal of the inverter INV is supplied to the decode control circuit CTRL and the input terminal of the buffer BUF, and the sense amplifier enable signal sae is generated from the output terminal of the buffer BUF. Supplied to the sense amplifier SA.

  SRAM cell read signals from a plurality of bit line / inverted bit line pairs bt [0], bb [0] to bt [m], bb [m] are supplied to differential input terminals of the plurality of sense amplifiers SA. Thus, read data q [0] to [m] are generated from the output terminals of the plurality of sense amplifiers SA.

  In this SRAM, by increasing or decreasing the number (j) of replica memory cells RPLCELL, the discharge rate of the precharge charge of the replica bit line rplbt to the ground potential GND is increased or decreased, and the potential of the sense amplifier enable signal sae rises. The timing can be adjusted.

  Therefore, in the SRAM using one replica bit line rplbt in FIG. 1, by adopting a self-timing setting technique of the sense amplifier enable signal sae using this replica bit line rplbt, It is possible to realize the delay tracking of the bit line of the built-in SRAM by the local delay variation.

<< Delay Variation of Conventional Replica Circuit Block >>
However, it has been clarified that the technology for setting the self-timing of the sense amplifier enable signal sae in the SRAM using one replica bit line rplbt of the prior art described in FIG. 1 has the following problems. .

  The problem arises when the delay of the replica bit line rplbt becomes large due to the increase in the number of words due to the increase in the storage capacity of the built-in memory built in the SoC (system on chip). That is, when the delay of the replica bit line rplbt increases due to an increase in the number of words due to an increase in storage capacity, a plurality (j) of replica memories that discharge the precharge charge of the replica bit line rplbt to the ground potential GND. The delay variation of the replica bit line rplbt increases due to the variation of the cell current due to the local variation of the cell RPLCELL. Furthermore, as the storage capacity increases, the local variation of the logic threshold value of the inverter INV to which the signal of the replica bit line rplbt is supplied increases. As a result, it has been clarified that the variation of the generation timing (rise timing) of the sense amplifier enable signal sae increases due to the delay variation of the replica bit line rplbt and the local variation of the logic threshold value of the inverter INV. This variation causes a failure in reading data at the output terminal of the sense amplifier SA.

  FIG. 4A shows a sense amplifier based on the delay variation of the SRAM replica bit line rplbt and the local variation of the logic threshold value of the inverter INV using one replica bit line rplbt of the prior art described in FIG. It is a figure which shows the mode of the fluctuation | variation of the production | generation timing (rise timing) of the enable signal sae.

  In the example of FIG. 4A, it is assumed that the signal of the replica bit line rplbt causes an amplitude change of xV in the elapsed time of t_sae. Even when the amplitude of the replica bit line rplbt changes, there are cases where the delay of the replica bit line rplbt is small and becomes the high-speed amplitude change characteristic rplbt_ft, and where the delay of the replica bit line rplbt is large and becomes the low-speed amplitude change characteristic rplbt_sl. . On the other hand, the logic threshold value of the inverter INV to which the signal of the replica bit line rplbt is supplied may be the high logic threshold voltage Vth_high or the low logic threshold voltage Vth_low.

  Therefore, the generation timing of the small delay sae_ft of the sense amplifier enable signal sae is determined by the crossover between the high-speed amplitude change characteristic rplbt_ft and the high logic threshold voltage Vth_high. Also, the generation timing of the large delay sae_sl of the sense amplifier enable signal sae is determined by the crossover between the slow amplitude change characteristic rplbt_sl and the slow amplitude change characteristic rplbt_sl. As a result, the variation width Δt_sae of the generation timing of the sense amplifier enable signal sae becomes Δt_sae = the delay fluctuation amount of the replica circuit block RPLBLK, which is large (compared to FIG. 4B described later). .

  As a technique considering the reduction of the fluctuation range, the technique described in Patent Document 1 described above can be cited. Although this technology divides one replica bit line and connects it with an inverter, the delay of the connecting inverter is mixed with the required replica bit line delay. It is conceivable that the ability to track the delay well is impaired. In addition, since the number that can be divided is limited, the effect of reducing the delay fluctuation amount is also limited.

  Therefore, the present embodiment has been made in view of the problems of the SRAM using one replica bit line rplbt of the prior art as described above, and the problems of the technique described in Patent Document 1 described above. Its typical purpose is to reduce fluctuations in the generation timing of the sense amplifier enable signal even when the storage capacity of the SRAM is increased. Hereinafter, the present embodiment will be specifically described.

<Example using a plurality of replica bit lines of this embodiment>
An example in which a plurality of replica bit lines according to the present embodiment are used will be described with reference to FIGS. 2, 3, 4B, and 5. FIG.

<< Configuration of SRAM >>
FIG. 2 is a diagram showing an example of the configuration of an SRAM using a plurality of replica bit lines according to the present embodiment.

  The SRAM shown in FIG. 2 is basically different from the SRAM shown in FIG. 1 in that the SRAM shown in FIG. 1 is an example using one replica bit line, whereas the SRAM shown in FIG. In this example, a plurality of replica bit lines are used, which reduces the amount of delay in the replica bit lines.

  Furthermore, in contrast to the technique described in Patent Document 1 described above, the replica bit lines are not divided in the row direction (word line direction) but are increased by the number required in the column direction. At that time, the inverter receiving the delay of the replica bit line is arranged independently for each replica bit line. Each circuit constituting each replica bit line and each inverter receiving each replica bit line are regarded as one independent replica circuit block.

  Further, the replica bit lines are connected to each other, and the outputs of the inverters that receive the replica bit lines are also connected to each other. By connecting independent replica circuit blocks, it is possible to reduce the delay fluctuation amount of the replica bit line due to the local fluctuation of the replica memory cell and the delay fluctuation quantity due to the logical threshold fluctuation of the inverter due to the local fluctuation. This effect makes it possible to configure most of the delay with replica bit lines while reducing the amount of delay variation of the entire replica circuit block. According to the above, it is possible to realize a circuit that has a function of well tracking the delay of the bit line with a reduced amount of delay variation.

  Hereinafter, the configuration of the SRAM will be described with reference to FIG. As in the SRAM shown in FIG. 1, the SRAM shown in FIG. 2 also includes a word driver WD, a decode control circuit CTRL, a plurality of word lines wl [0] to [n], and a plurality of bit lines / inverted bit lines. Pairs bt [0], bb [0] to bt [m], bb [m], a plurality ((n + 1) × (m + 1)) of SRAM memory cells MEMCELL, and a plurality (m + 1) of sense amplifiers SA Including.

  The SRAM shown in FIG. 2 differs from the SRAM shown in FIG. 1 in that a plurality of replica word lines rplwl [0] to [p] and a plurality of replica bit lines rplbt [0] to [p] , A plurality of precharge transistors PCH [0] to [p] (P channel MOS transistors), a plurality of inverters INV [0] to [p], and a plurality (j × (p + 1)) of replica memory cells RPLCELL And a plurality of (k × (p + 1)) dummy memory cells DMYCELL.

  Multiple ((n + 1) × (m + 1)) SRAM memory cells MEMCELL, multiple (j × (p + 1)) replica memory cells RPLCELL, and multiple (k × (p + 1)) dummy memory cells For example, there is a relationship of (n + 1) = j + k with DMYCELL.

  In particular, in the SRAM shown in FIG. 2, the number of replica bit lines rplbt [0] to [p] is increased by a necessary number ([0] to [p]: (p + 1)) in the column direction, and a plurality of replica bits The bit lines rplbt [0] to [p] are connected by a short-circuited replica bit line rplbtp, and outputs of a plurality of inverters INV [0] to [p] receiving the replica bit lines rplbt [0] to [p]. They are also connected by an inverted replica bit line rplbtn. Each circuit constituting each replica bit line rplbt [0] to [p] and each inverter INV [0] to [p] receiving each replica bit line rplbt [0] to [p] are independent of each other. One replica circuit block RPLBLK [0] to [p] is considered.

  By supplying the clock signal CLK and the address signals a [0] to [h] to the decode control circuit CTRL, the decoder signals dec [0] to [i] are supplied from the decode control circuit CTRL to the word driver WD. The signals of the plurality of replica word lines rplwl [0] to [p] are supplied from the decode control circuit CTRL to the plurality of precharge transistors PCH [0] to [p] and the plurality of replica memory cells RPLCELL.

  The sources of the P channel MOS transistors as the plurality of precharge transistors PCH [0] to [p] are connected to the power supply voltage VDD, while the drains of the P channel MOS transistors are connected to the plurality of replica bit lines rplbt [0] to Connected to [p]. The plurality of replica bit lines rplbt [0] to [p] are connected to the plurality of replica memory cells RPLCELL, the plurality of dummy memory cells DMYCELL, and the input terminals of the plurality of inverters INV [0] to [p]. Is done.

  The signal of the inverted replica bit line rplbtn generated from the output terminals of the plurality of inverters INV [0] to [p] is supplied to the decode control circuit CTRL and the input terminal of the buffer BUF, and sensed from the output terminal of the buffer BUF. An amplifier enable signal sae is generated and supplied to the plurality of sense amplifiers SA.

  SRAM cell read signals from a plurality of bit line / inverted bit line pairs bt [0], bb [0] to bt [m], bb [m] are supplied to differential input terminals of the plurality of sense amplifiers SA. Thus, read data q [0] to [m] are generated from the output terminals of the plurality of sense amplifiers SA.

<< SRAM Operation >>
FIG. 3 is a diagram for explaining the operation of the SRAM shown in FIG. 2, and shows an example of the waveform of each part of the SRAM shown in FIG.

  As shown in FIG. 3, one selected signal of decoder signals dec [0] to [i] in response to address signals a [0] to [h] changing in synchronization with the rising edge of clock signal CLK. Falls. One word line corresponding to the address signal is selected from the word lines of wl [0] to [n] and starts up. A plurality of bit line / inverted bit line pairs bt [0], bb [0] to bt [m in response to the memory holding state of a plurality ((m + 1)) of memory cells connected to the selected word line that has risen. ], Bb [m], the charge of one bit line of each bit line / inverted bit line pair begins to be extracted.

  While the plurality of replica word lines rplwl [0] to [p] are at the low level, the replica bit lines rplbt [0] to [p] have the plurality of precharge transistors PCH [0] to [p]. Is precharged to a high level power supply voltage VDD by a P channel MOS transistor. Therefore, in response to the high level of the plurality of replica bit lines rplbt [0] to [p], the output of the inverted replica bit line rplbtn and the buffer BUF at the output terminals of the plurality of inverters INV [0] to [p]. The sense amplifier enable signal sae at the terminal is at a low level.

  On the other hand, in response to the rise of the clock signal CLK, the potentials of the plurality of replica word lines rplwl [0] to [p] rise to a high level. Inside the plurality of replica memory cells RPLCELL, the high-level power supply voltage VDD is supplied to the input terminal of the CMOS inverter formed by the P-channel MOS transistor and the N-channel MOS transistor. The terminal is maintained at the ground potential GND.

  Since the potentials of the plurality of replica word lines rplwl [0] to [p] rise to a high level, N channel MOS transistors as transfer transistors inside the plurality of replica memory cells RPLCELL are turned on. The precharge charges of the replica bit lines rplbt [0] to [p] are discharged to the ground potential GND through the plurality of transfer transistors inside the plurality of replica memory cells RPLCELL. When the potentials of the plurality of replica bit lines rplbt [0] to [p] are lowered to a level lower than the logic threshold value of the plurality of inverters INV [0] to [p] by this discharge, the plurality of inverters INV [0]. The potential of the inverted replica bit line rplbtn of the outputs of .about. [P] rises.

  The signal of the inverted replica bit line rplbtn is supplied to the input terminal of the buffer BUF, and the sense amplifier enable signal sae generated from the output terminal of the buffer BUF is supplied to the plurality of sense amplifiers SA. The potential difference ΔV between the plurality of bit line / inverted bit line pairs bt [0], bb [0] to bt [m], bb [m] at the rising timing of the sense amplifier enable signal sae is amplified by the plurality of sense amplifiers SA. As a result, read data q [0] to [m] are output. When the potential difference ΔV between the bit line / inverted bit line pair is smaller than the offset of the input potential difference of the sense amplifier SA, data reading fails.

  The potential of the selected word line of any of the word lines wl [0] to [n] rises, and the timing at which the potential difference ΔV between the plurality of bit line / inverted bit line pairs becomes larger than the offset of the input potential difference of the sense amplifier SA. The timings at which the plurality of replica word lines rplwl [0] to [p] rise, the plurality of replica bit lines rplbt [0] to [p] fall, and the sense amplifier enable signal sae rises substantially simultaneously. Thus, the timing adjustment is performed. The adjustment of the rising timing of the potential of the sense amplifier enable signal sae can be performed by adjusting the number of the plurality of replica memory cells RPLCELL connected to the plurality of replica bit lines rplbt [0] to [p].

  In the SRAM according to the present embodiment shown in FIG. 2, the number of replica bit lines rplbt [0] to [p] is increased by the required number in the column direction, so that each replica bit line rplbt [0] to The delay amount of [p] is reduced. By reducing the delay amount of each replica bit line rplbt [0] to [p], the delay variation of each replica bit line rplbt [0] to [p] is reduced. As a result, the sense amplifier enable signal sae is generated by the reduced delay variation of each replica bit line rplbt [0] to [p] and the local variation of the logic threshold value of the plurality of inverters INV [0] to [p]. Timing variations are reduced.

<< Delay Variation of Replica Circuit Block of Present Embodiment >>
FIG. 4B shows the delay variation of the SRAM replica bit lines rplbt [0] to [p] and the logic of the inverters INV [0] to [p] described in FIGS. It is a figure which shows the mode of the fluctuation | variation of the production | generation timing (rise timing) of the sense amplifier enable signal sae by the local fluctuation | variation of a threshold value.

  In the example of FIG. 4B, the load capacity and delay amount of each replica bit line rplbt [0] to [p] using a plurality of replica bit lines rplbt [0] to [p] are significantly reduced. . That is, as compared with FIG. 4A, as shown in FIG. 4B, the delay amount of each replica bit line rplbt [0] to [p] is reduced to 1 / √ (p + 1). At this time, similarly to FIG. 4A, even in the case shown in FIG. 4B, the replica bit lines rplbt [0] to [p] have a small delay and the high-speed amplitude change characteristic rplbt_ft. The delay of the bit line rplbt may be large and become a low-speed amplitude change characteristic rplbt_sl. On the other hand, when the logic threshold value of the inverters INV [0] to [p] to which the signals of the replica bit lines rplbt [0] to [p] are supplied becomes the high logic threshold voltage Vth_high, The logic threshold voltage Vth_low may be obtained.

  Therefore, the generation timing of the small delay sae_ft of the sense amplifier enable signal sae is determined by the crossover between the high speed amplitude change characteristic rplbt_ft and the high logic threshold voltage Vth_high, and the crossover of the low speed amplitude change characteristic rplbt_sl and the low speed amplitude change characteristic rplbt_sl. Thus, the generation timing of the large delay sae_sl of the sense amplifier enable signal sae is determined.

  However, as shown in FIG. 4B, when a plurality of replica bit lines rplbt [0] to [p] are used, the delay variation of each replica bit line rplbt [0] to [p] and the inverter INV [ The fluctuation width Δt_sae of the generation timing of the sense amplifier enable signal sae due to the fluctuation of the logic threshold voltage from 0] to [p] is reduced as compared with FIG. More specifically, the replica bit lines rplbt [0] to [p] are changed according to the number ((p + 1)) of the replica circuit blocks RPLBLK [0] to [p] as shown in FIG. In the case of using a plurality, the variation width Δt_sae of the generation timing of the sense amplifier enable signal sae is reduced to a small value of Δt_sae = the delay variation amount of the replica circuit block RPLBLK × 1 / √ (p + 1). That is, the amount of delay variation when a plurality of replica bit lines rplbt [0] to [p] of the present embodiment is used is compared to the amount of delay variation when one replica bit line rplbt of the prior art is used. 1 / √ (p + 1).

<< Modification of Example Using Plural Replica Bit Lines of this Embodiment >>
In the SRAM configuration using a plurality of replica bit lines according to the present embodiment shown in FIG. 2, the number of a plurality of inverters INV [0] to [p] and a plurality of replica bit lines rplbt [0] to [p] However, the present invention is not limited to this example, and the number of inverters can be made smaller than the number of replica bit lines. It is possible to increase the number of replica bit lines.

  FIG. 5 is a diagram showing a modification of the SRAM configuration using a plurality of replica bit lines according to the present embodiment.

  The SRAM shown in FIG. 5 is an example in which the number of inverters INV that receive a plurality ((p + 1)) of replica bit lines rplbt [0] to [p] is reduced to one. For example, when the influence of the logical threshold value of the inverter due to local fluctuation is small, the number of inverters that receive the replica bit line may be reduced. When there is one inverter, the delay fluctuation amount due to the logic threshold fluctuation of the inverter is not reduced, but the delay fluctuation amount of the replica bit line is reduced, so the influence of the inverter logic threshold fluctuation is small It is effective when it is desired to reduce the number of elements.

  Although not shown, conversely, when the influence of the logical threshold value of the inverter due to local fluctuation is large, the number of inverters INV receiving a plurality of replica bit lines rplbt [0] to [p] Can be more than the number of lines.

<< Effects of the present embodiment >>
According to the SRAM using a plurality of replica bit lines of the present embodiment described above, the replica bit lines rplbt [0] to [p] are increased in the column direction, and a plurality of replica bit lines rplbt [0] to [P] are connected by a short-circuited replica bit line rplbtp, and the outputs of a plurality of inverters INV [0] to [p] receiving each replica bit line rplbt [0] to [p] are also inverted replica bit lines Each inverter INV [0]-[p] connected by rplbtn and receiving each circuit constituting each replica bit line rplbt [0]-[p] and each replica bit line rplbt [0]-[p] Is regarded as one independent replica circuit block RPLBLK [0] to [p], the following effects can be obtained.

  (1) Since the replica bit line is not divided as in the prior art (Patent Document 1), connection by an inverter is unnecessary, and a pure replica bit line delay can be used. Bit line delay can be tracked well. In other words, compared to a circuit in which the replica bit line is divided and connected by an inverter, the delay of the inverter for division is not included in the delay amount of the replica circuit block, so only the original replica bit line delay is effectively used. The bit line delay can be tracked well.

  (2) Since the fluctuation value of the replica circuit block is substantially normally distributed from the positive fluctuation value to the negative fluctuation value, the fluctuation amount is reduced according to the substantially normal distribution according to the number of replica circuit blocks arranged in the column direction. Is done. That is, the (p + 1) arrangement of replica circuit blocks, the connection between replica bit lines, and the connection of the output of a receiving inverter reduce the delay fluctuation amount of the replica circuit block in accordance with a substantially normal distribution, and the delay fluctuation amount × It can be reduced to 1 / √ (p + 1).

  (3) Even when the memory capacity is increased and the required delay amount is increased, the present embodiment of increasing the replica circuit blocks in the column direction can increase the desired number, thereby reducing the delay fluctuation amount. be able to.

  (4) When the influence of the logical threshold value of the inverter due to local fluctuation is small, the area can be reduced by reducing the number of elements by reducing the number of inverters that receive a plurality of replica bit lines. In addition, when the influence of the logical threshold value of the inverter due to local fluctuation is large, the amount of delay fluctuation can be reduced by increasing the number of inverters that receive a plurality of replica bit lines.

  (5) Since the amount of delay variation can be reduced, the access time of a product equipped with a memory can be improved.

  (6) Since the amount of delay variation can be reduced, the frequency of a product equipped with a memory can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective in SRAM because it is effective in reducing the amount of delay variation following the bit line. In addition, since it is effective in reducing the amount of delay variation following the bit line, it is effective in the memory LSI. Since the number of replica circuit blocks can be changed depending on the memory capacity, a compiled RAM capable of providing a desired memory capacity is effective.

WD... Word driver CTRL... Decode control circuit wl [0] to wl [n]... Word line bt [0], bb [0] to bt [m], bb [m] ... bit line / inverted bit line pair rplwl, rplwl [0] to rplwl [p] ... replica word lines rplbt, rplbt [0] to rplbt [p] ... replica bit lines rplbtp ... short-circuited replica bit lines rplbtn ... inverted replica bit lines MEMCELL ... SRAM memory cells RPLCELL ... Replica memory cell DMYCELL ... Dummy memory cell PCH, PCH [0] to PCH [p] ... Precharge transistors INV, INV [0] to INV [p] ... Inverter BUF ... Buffer SA ... Sense amplifiers RPLBLK, RPLBLK [0] to RPLBLK [p] ... replica circuit Lock CLK ... clock signal a [0] ~a [h] ... address signal dec [0] ~dec [i] ... decoder signal sae ... sense amplifier enable signal q [0] ~q [m] ... read data

Claims (11)

A plurality of word lines arranged in a row direction;
A plurality of bit lines arranged in the column direction;
A plurality of normal memory cells respectively connected to the plurality of word lines and the plurality of bit lines;
An access control circuit capable of selecting any one of the plurality of word lines in response to an address signal;
A semiconductor memory device having a plurality of sense amplifiers connected to the plurality of bit lines, respectively.
A plurality of replica bit lines arranged in the column direction;
A plurality of replica memory cells respectively connected to the plurality of replica bit lines;
A plurality of inverters respectively connected to the plurality of replica bit lines;
The plurality of replica bit lines are connected in common,
The input terminals of the plurality of inverters are connected to the plurality of replica bit lines, respectively, and the output terminals of the plurality of inverters are connected in common to generate a sense amplifier enable signal,
By supplying the sense amplifier enable signal to the plurality of sense amplifiers, a plurality of read signals of the plurality of bit lines are amplified by the plurality of sense amplifiers, and a plurality of signals are output from a plurality of output terminals of the plurality of sense amplifiers. Read data is generated. A semiconductor memory device. The semiconductor memory device according to claim 1.
A plurality of precharge transistors respectively connected to the plurality of replica bit lines;
Before the plurality of read data are generated from the plurality of output terminals of the plurality of sense amplifiers in response to the sense amplifier enable signal, the plurality of precharge transistors respectively connect the plurality of replica bit lines to a predetermined number. A semiconductor memory device characterized by being set to a precharge potential. The semiconductor memory device according to claim 1.
A semiconductor memory device further comprising a plurality of dummy memory cells respectively connected to the plurality of replica bit lines. The semiconductor memory device according to claim 1.
The semiconductor memory device, wherein the plurality of normal memory cells are SRAM memory cells. The semiconductor memory device according to claim 1.
The number of the plurality of inverters is the same as the number of the plurality of replica bit lines. The semiconductor memory device according to claim 1.
The number of the plurality of inverters is smaller than the number of the plurality of replica bit lines. The semiconductor memory device according to claim 1.
The number of the plurality of inverters is larger than the number of the plurality of replica bit lines. A plurality of word lines arranged in a row direction;
A plurality of bit lines arranged in the column direction;
A plurality of normal memory cells respectively connected to the plurality of word lines and the plurality of bit lines;
An access control circuit capable of selecting any one of the plurality of word lines in response to an address signal;
A semiconductor memory device having a plurality of sense amplifiers connected to the plurality of bit lines, respectively.
A plurality of replica bit lines arranged in the column direction;
A plurality of replica memory cells respectively connected to the plurality of replica bit lines;
And an inverter commonly connected to the plurality of replica bit lines,
The plurality of replica bit lines are connected in common,
An input terminal of the one inverter is connected to each of the plurality of replica bit lines, and a sense amplifier enable signal is generated from an output terminal of the one inverter,
By supplying the sense amplifier enable signal to the plurality of sense amplifiers, a plurality of read signals of the plurality of bit lines are amplified by the plurality of sense amplifiers, and a plurality of signals are output from a plurality of output terminals of the plurality of sense amplifiers. Read data is generated. A semiconductor memory device. The semiconductor memory device according to claim 8.
A plurality of precharge transistors respectively connected to the plurality of replica bit lines;
Before the plurality of read data are generated from the plurality of output terminals of the plurality of sense amplifiers in response to the sense amplifier enable signal, the plurality of precharge transistors respectively connect the plurality of replica bit lines to a predetermined number. A semiconductor memory device characterized by being set to a precharge potential. The semiconductor memory device according to claim 8.
A semiconductor memory device further comprising a plurality of dummy memory cells respectively connected to the plurality of replica bit lines. The semiconductor memory device according to claim 8.
The semiconductor memory device, wherein the plurality of normal memory cells are SRAM memory cells.

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