JP2012220594A - Liquid crystal display and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve display quality by reducing FPN in a display image by suppressing variance among pixels, to suppress bright points and black points to some extent, and further to suppress a flicker.SOLUTION: A plurality of pixels constituting a pixel part 123 each includes: a liquid crystal display element; first and second holding capacitors which individually hold a positive-polarity ramp signal and a negative-polarity ramp signal corresponding to a pixel value of digital data; and means of applying the first and second voltages to a pixel electrode alternately at a predetermined period shorter than a vertical scanning period. An external driving circuit supplies data in a normal state and data in an inverted state generated by inverting a data value of the data in the normal state to the pixel alternately in one-frame unit and also in 1H unit. When the pixel is read out, common electrode voltages of different potentials are alternated and applied according to whether a hold voltage applied to the pixel electrode is the data in the normal state or the data in the inverted state and whether the first holding voltage or the second holding voltage is applied.

Description

  The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, a reflective liquid crystal that drives a liquid crystal display element with an analog voltage obtained by digital-analog conversion (hereinafter referred to as DA conversion) of a digital video signal using a ramp signal or the like. The present invention relates to a liquid crystal display device used for a projector apparatus and the like and a driving method thereof.

  In recent years, a liquid crystal on silicon (LCOS) type liquid crystal display device is often used as a central part for projecting an image in a projector device or a projection television. In the display method of the liquid crystal display device such as LCOS, an analog video signal is conventionally input to a semiconductor element such as a CMOS (Complementary Metal Oxide Semiconductor), and the signal is held as it is on the pixel electrode of the liquid crystal display element for each pixel. A method of changing the orientation of the liquid crystal, a method of applying a video signal that has been subjected to pulse width modulation (PWM) by a digital signal to the pixel electrode of the liquid crystal display element, and driving by switching the orientation of the liquid crystal over time. there were. Among them, the method of directly applying an analog signal to the pixel electrode has a problem that liquid crystal burn-in easily occurs.

  In order to solve the problem, the present applicant firstly intersects each of a plurality of data lines each including two data lines (column signal lines) and a plurality of gate lines (row scanning lines). Each pixel is disposed in a portion, and in each of the pixels, a positive video signal and a negative video signal are separately sampled and held in two holding capacitors, and then the holding voltage is alternately applied to the pixel electrode to liquid crystal A liquid crystal display device in which the display element is AC driven has been proposed (see, for example, Patent Document 1).

  In this liquid crystal display device, as shown in FIG. 9, a positive electrode that monotonously increases in a period of one horizontal scanning period (1H) from a digital data value “00” (black level) to a digital data value “FF” (white level). And a negative ramp signal RAMP1- that monotonously decreases in one horizontal scanning period (1H) from the digital data value “00” (black level) to the digital data value “FF” (white level). A common number of video switches are simultaneously supplied to a number of video switches corresponding to the number of pixels in one line. Here, each set of video switches includes a positive video switch supplied with a positive ramp signal RAMP1 + and a negative video switch supplied with a negative ramp signal RAMP1-.

  After all sets of video switches are simultaneously turned on every time the horizontal scanning period starts, the counter value indicating the gradation obtained by counting the clocks synchronized with the ramp signals RAMP1 + and RAMP1- by the counter and the digital video signal A comparator that compares the pixel values in units of pixels of one line outputs a coincidence pulse when they coincide with each other, and simultaneously turns off a set of video switches provided corresponding to the pixels. Each voltage of the signals RAMP1 + and RAMP1- is sampled and supplied to a positive holding capacitor and a negative holding capacitor in a pixel connected to a set of turned off video switches via a set of data lines. Then, sampling and holding of the signal voltage obtained by converting the digital video signal into the analog video signal is performed.

  The voltage of the ramp signal RAMP1 + corresponding to the pixel value of the positive video signal sampled and held in the positive holding capacitor and the ramp corresponding to the pixel value of the negative video signal sampled and held in the negative holding capacitor The voltage of the signal RAMP1- is alternately switched at a predetermined cycle shorter than the vertical scanning cycle and applied to the pixel electrode of the liquid crystal display element. The liquid crystal display element has a known structure in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode provided to face each other. Here, when the voltage of the ramp signal RAMP1 + sampled and held in the positive holding capacitor is applied to the pixel electrode, the common electrode voltage at the level indicated by Vcom1 + in FIG. When the voltage of the ramp signal RAMP1- sampled and held in the capacitor is applied to the pixel electrode, the common electrode voltage at the level indicated by Vcom1- in FIG. 9 is applied to the common electrode.

  Accordingly, the voltage applied to the liquid crystal layer is a difference voltage between the applied voltage of the pixel electrode and the common electrode voltage, and therefore the voltage of the ramp signal RAMP1 + sampled and held in the positive holding capacitor is applied to the pixel electrode. Sometimes, the voltage is indicated by Vp1 in FIG. 9, and when the voltage of the ramp signal RAMP1- sampled and held in the negative holding capacitor is applied to the pixel electrode, the voltage is indicated by Vm1 in FIG. Accordingly, the voltage applied to the liquid crystal layer is the same in the voltage application direction when the voltage of the ramp signal RAMP1 + is applied to the pixel electrode and when the voltage of the ramp signal RAMP1- is applied. In the case of pixel values, the same voltage is applied to the liquid crystal layer, and by switching this at high speed, the brightness displayed for the same data does not change, but the voltage applied to the pixel electrode and the common electrode Since it has a reverse polarity, it is possible to make it difficult for image sticking to occur.

  In this liquid crystal display device, the voltage applied to the pixel electrode can be held in the holding capacitor for positive polarity and the holding capacitor for negative polarity for one frame period, respectively. Regardless of the frequency, it can be set freely in the inversion control cycle in the pixel circuit. As a result, according to this liquid crystal display device, the AC drive frequency can be set to be extremely higher than the vertical scanning frequency, thereby preventing burn-in and preventing deterioration in display quality such as reliability, stability, and spots. In addition, it is possible to obtain features such as that the gradation can be correctly expressed by the digital PWM method.

JP 2009-223289 A

  However, in the above-mentioned liquid crystal display device, each pixel outputs two ramp signal voltages separately held in two holding capacitors, one for positive polarity and one for negative polarity, through two source follower circuits separately. However, since it is a circuit configuration in which it is alternately selected by the switching transistor and applied to the pixel electrode, variation in the threshold voltage Vth of the transistor of the source follower circuit occurs for each pixel, which becomes a problem.

  That is, when the voltage of the ramp signal RAMP1 + sampled and held in the positive holding capacitor is the voltage indicated by Vp1 in FIG. 9, when the Vth of the transistor in the positive source follower circuit is higher than the average value, FIG. As shown in FIG. 5, the voltage is increased by Vlv1 corresponding to the error and applied to the pixel electrode. In this case, the pixel state is brighter than the correct brightness.

  On the other hand, when the voltage of the ramp signal RAMP1- sampled and held in the negative holding capacitor is the voltage indicated by Vm1 in FIG. 9, when the Vth of the transistor in the negative source follower circuit is higher than the average value, FIG. As shown in FIG. 9, the voltage becomes higher by Vlv2 corresponding to the error and is applied to the pixel electrode. In this case, the pixel state is darker than the correct brightness. As described above, if there is an error in which the Vth of the transistor of the source follower circuit on the positive polarity side in each pixel and the Vth of the transistor of the source follower circuit on the negative polarity side deviate from the normal values, the correct brightness is obtained. The shifted state is displayed.

  When the positive pixel electrode voltage and the negative pixel electrode voltage are switched, for example, at a cycle of 2 kHz, the brightness of the liquid crystal display element when these pixel electrodes are applied is averaged. Bright fixed pattern noise (FPN) or dark FPN occurs due to the difference between the average of the pixel electrode voltage and the negative pixel electrode voltage.

  Here, the brightness Xp of the liquid crystal display element when the positive pixel electrode voltage shown in FIG. 9 is applied is expressed by the following equation.

Xp = fp × (Vp1 + Vlv1) (1)
In the equation (1), fp is a function for calculating the display brightness when voltage is applied, Vp1 is an input voltage of the positive holding capacitor in the pixel, and Vlv1 is a variation voltage of the positive source follower circuit of the pixel. is there. Further, the brightness Xm of the liquid crystal display element when the negative pixel electrode voltage shown in FIG. 9 is applied is expressed by the following equation.

Xm = fm × (Vm1−Vlv2) (2)
In the equation (2), fm is a function for calculating display brightness when voltage is applied, Vm1 is an input voltage of a holding capacitor for negative polarity in the pixel, and Vlv2 is a variation voltage of the source follower circuit on the negative polarity side of the pixel. is there. The brightness seen by the observer is the average of the above brightness Xp and Xm, giving a feeling of roughness.

  In addition, the liquid crystal display device has a problem in that defective pixels such as bright spots and black spots are likely to occur because the number of devices used in the pixel circuit is large.

  Further, in the above liquid crystal display device, the voltage of the ramp signal RAMP1 + sampled and held in the positive polarity holding capacitor and the voltage of the ramp signal RAMP1- sampled and held in the negative polarity holding capacitor are shorter than the vertical scanning cycle. The configuration is such that the two levels of the common electrode voltage are alternately switched in synchronism with the switching of the two holding voltages, as described above in the case of the same pixel value. However, although the voltage application direction to the pixel electrode is reversed, the voltage applied to the liquid crystal layer is the same, and the displayed brightness does not change. However, if there are variations in the components of the panel drive driver circuit or if the input / output characteristics are non-linear, a deviation occurs between the ramp signal RAMP1 + and the ramp signal RAMP1-, resulting in asymmetry, resulting in flicker in the display image.

  The present invention has been made in view of the above points. By suppressing pixel variations, FPN in a display image can be reduced, display quality can be improved, and bright spots, black spots, and the like can be suppressed to some extent, and flicker can be further suppressed. An object of the present invention is to provide a liquid crystal display device and a driving method thereof that can suppress the occurrence of the above.

In order to achieve the above object, the liquid crystal display device of the present invention has a plurality of data lines provided at intersections where a plurality of sets of data lines and a plurality of row scanning lines intersect each other. Each of the pixels has a display element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode, and a positive digital signal supplied via one data line of a set of two data lines The first sampling and holding means for sampling the analog conversion voltage and holding it in the first holding capacitor for a fixed period, and the negative polarity supplied via the other data line of the set of two data lines A second sampling and holding means for sampling the digital-analog conversion voltage and holding it in the second holding capacitor for a certain period; a first holding voltage of the first holding capacitor; and a second holding of the second holding capacitor Voltage is the vertical scanning period Provided alternately in a short predetermined period and holding the voltage reading means applied to the pixel electrode,
The pixel value of the input digital data is compared with the reference gradation data that changes monotonically in the horizontal scanning cycle, and is synchronized with the reference gradation data when the pixel value matches the reference gradation data value. The voltage of the positive ramp signal, which is a periodic signal whose level increases monotonically within the horizontal scanning cycle, is supplied to one data line as a positive polarity digital-analog conversion voltage, and at the same time, in synchronization with the reference grayscale data Data input means for supplying the negative ramp signal, which is a periodic signal whose level decreases monotonically within the scanning cycle, to the other data line as a negative digital-analog conversion voltage, and the same digital data as that to be displayed The normal data of the data value and the inverted data obtained by inverting the data value of the digital data to be displayed are converted into a positive ramp signal and a negative ramp signal. Therefore, data is input as input digital data by alternately switching in units of N horizontal scanning cycles (N is a natural number of 1 or more) and switching the order of normal data and inverted data in units of one frame. The input data processing means for inputting to the means, and the holding voltage reading means for the pixels in which the positive and negative ramp signals corresponding to the pixel values of the data in the normal state are held in the first and second holding capacitors. At the time of reading, the first common electrode voltage having the first potential is applied to the common electrode when the first holding voltage is applied to the pixel electrode, and the first holding voltage is applied to the pixel electrode when the first holding voltage is applied to the pixel electrode. A second common electrode voltage having a second potential higher than the potential is applied to the common electrode, and a positive ramp signal and a negative ramp signal corresponding to the pixel value of the data in the inverted state are the first and first negative ramp signals. When reading the pixel held in the holding capacitor of 2 by the holding voltage reading means, the third common electrode voltage of the third potential is applied to the common electrode when the first holding voltage is applied to the pixel electrode, and And a common electrode voltage input means for applying a fourth common electrode voltage having a fourth potential lower than the third potential to the common electrode when the second holding voltage is applied to the pixel electrode. Features.

In order to achieve the above object, a driving method of a liquid crystal display device according to the present invention includes an intersection where a plurality of sets of data lines and a plurality of row scanning lines intersect each other. Each of the plurality of pixels provided in the pixel is supplied via a display element in which a liquid crystal layer is sandwiched between the opposing pixel electrode and the common electrode, and one data line of a set of two data lines. The first sampling and holding means for sampling the positive polarity digital-analog conversion voltage to be held in the first holding capacitor for a certain period, and supplying it through the other data line of the set of two data lines The second sampling and holding means for sampling the negative-polarity digital-analog conversion voltage and holding it in the second holding capacitor for a certain period of time, the first holding voltage and the second holding capacitor of the first holding capacitor The second holding voltage of The liquid crystal display device and a holding voltage reading means applied to the pixel electrode alternately at short predetermined period than the vertical scanning period,
The data in the normal state with the same data value as the digital data to be displayed and the data in the inverted state obtained by inverting the data value of the digital data to be displayed are synchronized with the positive ramp signal and the negative ramp signal. Input data processing for alternately switching in units of N horizontal scanning cycles (N is a natural number of 1 or more), and switching the switching order of normal state data and inverted state data alternately in units of one frame and outputting them as input digital data Comparing the pixel value of the input digital data output in the step and the input data processing step with the reference gradation data monotonously changing the level in the horizontal scanning cycle, the pixel value and the reference gradation data value match The voltage of the positive ramp signal, which is a periodic signal that monotonously increases in level within the horizontal scanning period in synchronization with the reference grayscale data, is positive. The negative polarity ramp signal voltage, which is a periodic signal that decreases monotonically within the horizontal scanning period in synchronization with the reference grayscale data, is supplied to one data line as a negative digital-analog conversion voltage. A data input step of supplying an analog conversion voltage to the other data line, and a pixel in which a positive ramp signal and a negative ramp signal corresponding to a pixel value of normal data are held in the first and second holding capacitors At the time of reading by the holding voltage reading means, the first common electrode voltage having the first potential is applied to the common electrode when the first holding voltage is applied to the pixel electrode, and the pixel electrode having the second holding voltage is applied. A first common electrode voltage input step of applying a second common electrode voltage having a second potential higher than the first potential to the common electrode when applied to the first electrode; At the time of reading by the holding voltage reading means of the pixel in which the positive polarity ramp signal and the negative polarity ramp signal corresponding to the value are held in the first and second holding capacitors, the first holding voltage is applied to the pixel electrode. A third common electrode voltage having a third potential is applied to the common electrode, and a fourth common electrode having a fourth potential that is lower than the third potential when the second holding voltage is applied to the pixel electrode. And a second common electrode voltage input step of applying a voltage to the common electrode.

  According to the present invention, it is possible to reduce the FPN in the display image and improve the display quality by suppressing the pixel variation without changing the basic pixel circuit, and to some extent bright spots, black spots, etc. It is possible to suppress the occurrence of flicker.

1 is a system configuration diagram of an embodiment of a liquid crystal display device of the present invention. It is a schematic block diagram of one Embodiment of the liquid crystal panel drive element in FIG. FIG. 2 is an equivalent circuit diagram of an example of one pixel constituting the pixel unit in FIG. 1. FIG. 3 is a block diagram of a pixel selection circuit with an identification flag and its peripheral circuits in FIG. 2. It is a timing chart which shows operation | movement of the pixel of the 1st line. It is a timing chart which shows operation | movement of the pixel of the 2nd line. It is a figure which shows the relationship between the data of the inversion state input into a liquid crystal panel drive element, a ramp signal, and a common electrode voltage. It is a figure which shows the combination of the input data of a frame unit and common electrode voltage in embodiment of FIG. It is a figure which shows the relationship between the data of a normal state input into a liquid crystal panel drive element, a ramp signal, and a common electrode voltage.

  Next, embodiments of the present invention will be described with reference to the drawings.

  Problems with conventional liquid crystal display devices are mainly caused by Vth variation of the transistors of the source follower circuit for each pixel, so it is conceivable to perform correction for each pixel. It is difficult to realize.

  The first problem is that when the correction circuit is configured in the pixel of the liquid crystal panel driving element, it is necessary to increase the number of elements, and when the pixel pitch is narrow, it is difficult to realize the correction circuit. A second problem is that when a correction memory is provided outside the liquid crystal panel driving element, a memory for a frame is required and the system becomes large. In addition, it is difficult to accurately import correction data using a camera or the like. The third problem is that in a liquid crystal display device having a storage capacitor for each of a positive signal voltage and a negative signal voltage in one pixel, the amount of data increases, and two types of data are required for accurate correction. This means that it is necessary to input data and high-speed data input is required.

  However, the variation in Vth of the transistors of the positive-side source follower circuit and the negative-side source follower circuit in the pixel is considered to be the difference between the average Vth of the transistors of the average source follower circuit of each pixel. In this case, although there is an influence of the substrate effect, it is shifted in the same direction for any input voltage with respect to a correct signal level, and its state is hardly changed.

  Therefore, in the liquid crystal display device of the present embodiment described below, paying attention to this point, the feeling of roughness and flicker are improved without using the above correction method.

  FIG. 1 shows a system configuration diagram of an embodiment of a liquid crystal display device according to the present invention. As shown in the figure, the liquid crystal display device 10 of the present embodiment includes a panel drive driver circuit 11 and a liquid crystal panel drive element 12. The panel drive driver circuit 11 generates n-bit digital data (digital video signal), a V shift clock, a pixel selection signal, and a common electrode voltage of the liquid crystal display element so as to be synchronized with each other to generate a liquid crystal panel. This is supplied to the drive element 12.

  The n-bit digital data uses the minimum value “00” to the maximum value “FF” when the n bit is 8 bits, for example. The minimum value “00” is the darkest, and the maximum value “FF” is the brightest. Data (hereinafter referred to as “normal state data”) and the minimum value “00”, the brightest data, and the maximum value “FF”, the darkest data (hereinafter referred to as “inverted state data”). Data ”). The panel drive driver circuit 11 alternately supplies the normal state data and the inverted state data to the liquid crystal panel drive element 12 in units of one frame. Since the inverted data is data obtained by inverting the normal data, the inverted data “00” is “FF” in the normal data value and the inverted data “FF”. “Is“ 00 ”in the data value in the normal state.

  The V shift clock is a clock for selecting a horizontal line for writing n-bit digital data for each horizontal line (hereinafter also referred to as one line) of the pixel portion in the liquid crystal panel driving element 12. The pixel selection signal is identified by a signal for selecting whether to read the signal voltage held in the positive holding capacitor to the pixel electrode or to read the signal voltage held in the negative holding capacitor to the pixel electrode. This is a signal including a flag for use.

  The identification flag is a 1-bit flag for identifying whether data to be written to a plurality of pixels in one line is normal data or inverted data, and a value “1” indicates normal data and value “0” indicates that the data is inverted. In addition, the binary value of the identification flag alternately changes every horizontal scanning period (1H) in synchronization with the V shift clock and the digital video signal. Further, the common electrode voltage is a voltage Vcom applied to the common electrode of the liquid crystal display element, and changes to one of two voltage values in synchronization with the switching signals 2k and 2kb generated from the pixel selection signal.

  FIG. 2 shows a schematic block diagram of an embodiment of the liquid crystal panel driving element 12. As shown in the figure, the liquid crystal panel driving element 12 includes an image processing circuit 120, a horizontal shift register and comparator 121, a horizontal driving circuit (video switch or the like) 122, and a plurality of pixels arranged in a two-dimensional matrix. The pixel unit 123, the vertical shift register 124, and the flagged pixel selection circuit 125 are included.

  The image processing circuit 120 receives a digital video signal to be displayed, which is n-bit digital data, as an input. When a digital video signal of an odd-numbered frame (odd frame) is input, the image processing circuit 120 is set to an odd-numbered frame based on the input identification flag. The normal line data (1H period) is generated, and the even line (1H period) is inverted and generated. Further, the image processing circuit 120, when the digital video signal of the even-numbered frame (even frame) is input, on the odd-numbered line (1H period), the inverted data, the even-numbered line (1H period) In the line (1H period), normal state data is generated and output. The image processing circuit 120 outputs the input digital video signal to the horizontal shift register and the comparator 121 as it is without inverting the polarity when outputting data in the normal state, and logically inverts the input digital video signal when outputting the data in the inverted state. Output to the horizontal shift register and comparator 121.

  Each of the plurality of pixels constituting the pixel portion 123 may be the same as the pixel described in Patent Document 1 and may be configured by the equivalent circuit shown in FIG. In FIG. 3, source follower P-channel MOS transistors (hereinafter referred to as PMOS transistors) Tr3 and Tr4 are source follower transistors whose gates are holding capacitors C1 and C2 and pixel selection N-channel MOS transistors (hereinafter NMOS transistors). The source is connected to the drain of the constant current PMOS transistor Tr7 through the drain / source of the switching PMOS transistors Tr5 and Tr6. Each connection point of the transistors Tr5, Tr6, and Tr7 is connected to the pixel electrode PE. The liquid crystal display element LC has a known structure in which a liquid crystal layer LCM is sandwiched between a pixel electrode PE and a common electrode CE that are arranged to face each other, and a common electrode voltage Vcom is applied to the common electrode CE.

  The i-th column positive data line Di + is connected to the drain of the NMOS transistor Tr1, and the i-th column negative data line Di- is connected to the drain of the NMOS transistor Tr2. The gates of the NMOS transistors Tr1 and Tr2 are commonly connected to a j-th row scanning line (gate line) Gj. Note that the drains of the NMOS transistors Tr1 and Tr2 of each pixel in the same i-th column are also connected to the data lines Di + and Di-. The gates of the NMOS transistors Tr1 and Tr2 of each pixel in the same j-th row are also connected to the row scanning line Gj. The gate of the transistor Tr7 is connected to a signal line for the control signal cur. A switching signal 2k is applied to the gate of the PMOS transistor Tr5, and a switching signal 2kb is applied to the gate of the PMOS transistor Tr6. As will be described later, the switching signals 2k and 2kb alternately turn on the PMOS transistors Tr5 and Tr6 at a predetermined cycle shorter than one vertical scanning cycle.

  In the pixel of this configuration, positive and negative analog signals (the ramp signal) input via the data lines Di + and Di− are sampled by the NMOS transistors Tr1 and Tr2 and held in the holding capacitors C1 and C2. Is done. At the time of subsequent reading, the PMOS transistors Tr5 and Tr6 are alternately turned on at a predetermined cycle shorter than the vertical scanning cycle by the switching signals 2k and 2kb, and held in the positive holding voltage and the holding capacitor C2 held in the holding capacitor C1. The negative holding voltage thus applied is alternately applied to the pixel electrode PE through the source follower PMOS transistors Tr3 and Tr4.

  That is, when the switching signal 2k is at a low level, the positive polarity side switching transistor Tr5 is turned on. When the control signal cur is set at a low level during this period, the source follower buffer circuit composed of the transistors Tr3 and Tr7 becomes active. The PE is charged to the positive signal level held in the holding capacitor C1. When the potential of the pixel electrode PE is fully charged, when the control signal cur is set to high level and the switching signal 2k is also switched to high level at that time, the pixel electrode PE becomes floating and the liquid crystal capacitance is increased. The positive drive voltage is maintained.

  On the other hand, when the switching signal 2 kb is at the low level, the negative polarity side switching transistor Tr 6 is turned on. When the control signal cur is set at the low level during this period, the source follower buffer circuit composed of the transistors Tr 4 and Tr 7 becomes active. The PE is charged to the negative signal level held in the holding capacitor C2. When the potential of the pixel electrode PE is fully charged, when the control signal cur is set to high level and the switching signal 2 kb is also switched to high level at that time, the pixel electrode PE becomes floating and the liquid crystal capacitance is increased. Negative drive voltage is maintained.

  Hereinafter, in synchronization with the switching in which the switching transistors Tr5 and Tr6 are alternately turned on, the operation of intermittently activating the constant current transistor Tr7 is repeated, whereby the pixel electrode PE of the liquid crystal element LC has positive polarity. A drive voltage converted into an alternating current with each negative signal is applied.

  In this pixel, the held charge is not transferred directly to the pixel driver, but is supplied with a voltage via the source follower buffer circuit. There is no problem, and driving without voltage level attenuation can be realized even if polarity switching is performed many times.

  Further, the liquid crystal common electrode voltage Vcom is applied to the common electrode CE of the liquid crystal display element LC from the panel drive driver circuit 11 of FIG. In the present embodiment, as will be described later, there are four types of common electrode voltages Vcom: Vcom1 +, Vcom1-, Vcom2 +, and Vcom2-.

  Returning to FIG. The vertical shift register 124 receives the V-shift clock from the panel drive driver circuit 11 and outputs each pixel of the pixel portion 123 within one vertical scanning period from the first horizontal line to the final horizontal line for one horizontal scanning period (1H). A row selection signal for selecting the pixels of each horizontal line in order from top to bottom is output every time.

  The pixel selection circuit with flag 125 receives a pixel selection signal from the panel drive driver circuit 11 and sets the switching PMOS transistors Tr5 and Tr6 of each pixel shown in FIG. A switching signal (2k, 2kb in FIG. 3) and a control signal (cur in FIG. 3) that are alternately turned on and off in a short cycle (for example, 2 kHz cycle) and a control signal (cur in FIG. 3) are output to the pixel unit 123 and a vertical shift register The row selection signal output from 124 is output to a row scanning line (gate line) Gj connected to the pixel portion 123.

  FIG. 4 is a block diagram showing the flagged pixel selection circuit 125 for one line in FIG. 2 together with its peripheral circuits. In FIG. 4, the flag-selected pixel selection circuit 125 for one line includes a D-type flip-flop (hereinafter referred to as DFF) 201, and a pixel control circuit 203 including a write control circuit unit 202a and a read control circuit unit 202b. Yes. The pixels 204 are a plurality of pixels for one line in the pixel portion 123 illustrated in FIG.

  In the DFF 201, the identification flag signal line is connected to the data input terminal D. The identification flag is determined so as to indicate normal state data when the value is “1” and inverted data when the value is “0”, and the value is switched in a cycle of 1H. Further, the DFF 201 receives one line of output signals corresponding to the output terminal from the 1-bit output terminal of the vertical shift register 124 to the clock input terminal Cl. When the DFF 201 latches the input identification flag of the data input terminal D by the input signal of the clock input terminal Cl and supplies a signal having the same value as the latched identification flag from the Q output terminal to the pixel control circuit 203 for one frame period. At the same time, a signal having a value opposite to the latched binary identification flag is supplied from the Qn output terminal to the pixel control circuit 203 for one frame period. A signal supplied from the vertical shift register 124 to the clock terminal Cl of the DFF 201 is also input to the pixel control circuit 203 at the same time.

  The write control circuit unit 202a in the pixel control circuit 203 supplies a row selection signal to the gate line of the corresponding one line of pixels 204. Further, the read control circuit unit 202b supplies the switching signals 2k and 2kb and the control signal cur to the corresponding one-line pixels 204. Each pixel of the pixel unit 123 is selected in units of each row (line) in order from the highest row to the lowest row by a row selection signal supplied through the flagged pixel selection circuit 125.

  Next, a schematic operation of the liquid crystal panel driving element 12 of FIG. 2 will be described.

  The normal state data and the inverted state data are alternately switched every 1H from the image processing circuit 120 in FIG. 2 to the horizontal shift register in the horizontal shift register and the comparator 121 in FIG. The order of switching is alternately switched and input.

  The horizontal shift register in the horizontal shift register and comparator 121 described above develops one line of input normal state data or inversion state data, and temporarily holds the comparator in the horizontal shift register and comparator 121. To supply. When the number of pixels in the horizontal direction of the pixel portion 123 is m, the comparator is configured to m data lines including the positive data line D + and the negative data line D− shown in FIG. Correspondingly, m are provided for each column. The m number of comparators are commonly supplied with reference gradation data from a counter (not shown) in which a plurality of gradation values change stepwise at regular intervals within a horizontal scanning period, for example, from a minimum value to a maximum value. On the other hand, the image data held by the shift register is supplied in units of m pixels of one line and compared with each other. When the two match, a matching pulse is supplied to the horizontal drive circuit 122.

  The horizontal drive circuit 122 includes a positive polarity video switch connected to one data line Di + of the pair of data lines Di + and Di−, and a negative polarity video switch connected to the other data line Di−. Are provided in total for each set of data lines, and coincidence pulses are supplied from the corresponding comparators among the m comparators in the shift register and comparator 121 described above.

  All the m sets of video switches are turned on simultaneously at the start of the horizontal scanning period, and then the counter value (reference gradation data) indicating the gradation obtained by counting the clock synchronized with the ramp signal by the gradation counter. ) And the pixel value of the input digital data (normal state data or inverted state data) in units of pixels of one line, the coincidence pulse is output only when the coincidence pulse is output when they coincide. A set of video switches of pixels provided corresponding to the output comparators are simultaneously turned off by coincidence pulse input, and the voltages of the positive ramp signal RAMP + and the negative ramp signal RAMP- at this time are turned off. Holding capacitor C1 for positive polarity and a negative electrode in a pixel connected via a set of data lines Di + and Di- connected to a set of video switches. Sampling holding is performed by supplying to the use holding capacitor C2. The ramp signal voltage at this time is an analog voltage obtained by digital-analog conversion of an input digital video signal (normal state data or inverted state data).

  Next, the operation of the pixel 3 will be described in detail with reference to the timing charts of FIGS. First, a pixel writing operation will be described.

  A writing operation when the input digital video signal is the digital video signal on the first line of the odd-numbered frame (odd frame) will be described. In this case, assuming that the DFF in the first line of the flagged pixel selection circuit 125 is the DFF 201 in FIG. 4, the DFF 201 outputs “V shift output (first line in FIG. 5E) supplied to the clock input terminal” in FIG. The odd frame identification flag shown in FIG. 5D is latched based on the output signal of the first line of the vertical shift register 124 indicated as “case)”. As shown in FIG. 5D, since the value of the odd frame identification flag is “1” in the odd-numbered line on the screen, the DFF 201 latches the identification flag of the value “1” and latches it. The signal having the value “1” is supplied to the pixel control circuit 203. The pixel control circuit 203 on the first line supplies a high-level row selection signal to the pixel 204 on the first line from the writing control circuit unit 202a to the wiring G1 (j = 1) to perform a writing operation.

  When a high-level row selection signal is supplied to the wiring G1, the pixel selection transistors Tr1 and Tr2 of the pixel 204 shown in FIG. 3 in the first line are turned on. As a result, the voltage of the positive polarity ramp signal RAMP + input through the positive polarity data line D + and corresponding to the pixel value of the pixel on the first line when the positive polarity video switch is turned off becomes the transistor Tr1. And is written and held in the positive polarity holding capacitor C1. At the same time, the voltage of the negative polarity ramp signal RAMP− corresponding to the pixel value of the pixel on the first line when the negative polarity video switch is turned off, which is input via the negative polarity data line D−, is obtained. It is sampled by the transistor Tr2 and written and held in the negative holding capacitor C2. The digital video signal on the first line of the odd frame is normal state data as described above, and the voltage of the positive ramp signal RAMP + obtained by digital-analog conversion of the normal state data is held. At the same time as being written and held in the capacitor C1, the voltage of the negative polarity ramp signal RAMP + obtained by digital-to-analog conversion of normal state data is written and held in the holding capacitor C2. FIG. 5C shows the ramp signal voltage of the data line D +.

  Here, when writing data in the normal state to the pixel, the positive polarity ramp signal RAMP + is RAMP1 + shown in FIG. 9, and the negative polarity ramp signal RAMP− is RAMP1− shown in FIG. . Accordingly, the writing of data in the normal state to the pixels is performed in the same manner as the pixel writing of the conventional liquid crystal display device.

  Subsequently, when the digital video signal of the second line of the odd-numbered frame (odd frame) is input, the DFF of the second line of the flagged pixel selection circuit 125 is assumed to be the DFF 201 of FIG. , DFF 201 is supplied to the clock input terminal based on the output signal of the second line of the vertical shift register 124 shown as “V shift output (in the case of the second line)” in FIG. The odd frame identification flag shown in FIG. As shown in FIG. 6D, the odd frame identification flag has a value of “0” in the even-numbered lines on the screen, so that the DFF 201 latches the identification flag of the value “0”. The signal having the value “0” is supplied to the pixel control circuit 203. The write control circuit unit 202a supplies a row selection signal G2 (j = 2) to the pixels 204 in the second line to perform a write operation. FIG. 6C shows the ramp signal voltage of the data line D +.

  As a result, as with each pixel on the first line, the positive polarity video switch input to the positive polarity holding capacitor C1 of each pixel on the second line via the positive polarity data line D + is turned off. The voltage (positive digital-analog conversion voltage) of the positive polarity ramp signal RAMP + corresponding to the pixel value of the pixel on the second line at the time is written and held, and at the same time, the negative polarity holding capacitor C2 has a negative polarity. The voltage of the negative ramp signal RAMP- (corresponding to the negative polarity digital-analog conversion voltage) corresponding to the pixel value of the pixel of the second line when the negative polarity video switch is turned off, which is input via the data line D- ) Is written and held. Note that the digital video signal on the second line of the odd frame is inverted data as described above.

  As shown in FIG. 7, the writing of the data in the inverted state monotonically increases in a cycle of 1H from the value “00” (white level) to the value “FF” (black level) of the data in the inverted state. The positive polarity ramp signal RAMP2 + and the negative polarity ramp signal RAMP2- that monotonously decreases in a 1H cycle from the value "00" (white level) to the value "FF" (black level) in the inverted state are shown in FIG. The signals are supplied simultaneously to a number of sets of video switches corresponding to the number of pixels in one line in the horizontal drive circuit 122. Here, each set of video switches includes a positive video switch to which a positive ramp signal RAMP2 + is supplied and a negative video switch to which a negative ramp signal RAMP2- is supplied.

  Then, after all sets of video switches are turned on at the same time when the horizontal scanning period of the even-numbered lines such as the second line is started, the gradation obtained by counting the clocks synchronized with the ramp signals RAMP2 + and RAMP2- by the counter is shown. A comparator that compares the counter value and the pixel value of the digital video signal in units of pixels of one line outputs a coincidence pulse when they coincide with each other, and simultaneously sets a set of video switches corresponding to the pixels. The pixels of the ramp signals RAMP2 + and RAMP2- sampled at this time are sampled and connected to the set of video switches that are turned off via a set of data lines (Di +, Di- in FIG. 3). The positive polarity holding capacitor (C1 in FIG. 3) and the negative polarity holding capacitor (C2 in FIG. 3) are supplied and held therein.

  Thereafter, in the same manner as described above, in the odd frame, normal state data is sampled and written in each pixel 204 in the odd-numbered line, and inverted data is sampled in each pixel 204 in the even-numbered line. Written. In the pixel portion 123 of FIG. 2, a solid line indicates an odd-numbered line in which normal state data is written, and a dotted line indicates an even-numbered line in which inverted data is written.

  In the even frame, contrary to the odd frame, inverted data is sampled and written in each pixel 204 in the odd-numbered line, and normal data is sampled in each pixel 204 in the even-numbered line. To be written.

  Next, a pixel reading operation will be described.

  The pixel readout operation for the first line of the odd-numbered frame (odd frame) will be described. In this case, assuming that the DFF in the first line of the flagged pixel selection circuit 125 is the DFF 201 in FIG. 4, the DFF 201 outputs “V shift output (first line in FIG. 5E) supplied to the clock input terminal” in FIG. Based on the output signal of the first line of the vertical shift register 124 indicated as “)”, the value “1” of the identification flag for the first line of the odd frame shown in FIG. 5D is latched and its Q output terminal From the Qn output terminal and a value “0” from the Qn output terminal.

  The read control circuit unit 202b receives the signals from the Q output terminal and the Qn output terminal of the DFF 201 and the output signal of the first line of the vertical shift register 124 as input signals. The switching signal 2k for turning on the transistor Tr5 in FIG. 3 is output first, and the switching signal 2kb for turning on the transistor Tr6 is alternately switched on for a predetermined cycle shorter than one vertical scanning cycle (for example, a cycle of 2 kHz). Output alternately with. Each high level period of the switching signals 2k and 2kb shown in FIGS. 5A and 5B schematically shows the ON period of the transistors Tr5 and Tr6, and the signal waveforms are shown in FIGS. B) is in reverse phase. This is because the transistors Tr5 and Tr6, which are PMOS transistors, are turned on at a low level. The same applies to the switching signals 2k and 2kb shown in FIGS.

  By alternately turning on the transistors Tr5 and Tr6, the positive polarity digital-analog conversion voltage of the normal state data held in the positive polarity holding capacitor C1 and the negative polarity holding capacitor C2 are held. The negative polarity digital-analog conversion voltage of the normal data is alternately applied to the pixel electrode PE.

  Here, when the positive polarity digital-analog conversion voltage (specifically, the sampled positive polarity ramp signal RAMP1 +) of the normal state data held in the positive polarity holding capacitor C1 is applied to the pixel electrode PE. The common electrode voltage Vcom is a low-level common electrode voltage indicated by Vcom1 + in FIG. 9, and is a negative polarity digital-analog conversion voltage (specifically, normal state data held in the negative polarity holding capacitor C2). The common electrode voltage Vcom when the sampled negative polarity ramp signal RAMP1-) is applied to the pixel electrode PE is a high-level common electrode voltage indicated by Vcom1- in FIG.

  Next, the pixel readout operation for the second line of the odd-numbered frame (odd frame) will be described. In this case, assuming that the DFF in the second line of the flagged pixel selection circuit 125 is the DFF 201 in FIG. 4, the DFF 201 outputs “V shift output (second line in FIG. 6E) supplied to the clock input terminal”. Based on the output signal of the second line of the vertical shift register 124 shown as “)), the value“ 0 ”of the identification flag of the second line of the odd frame shown in FIG. 6D is latched, and its Q output terminal From the Qn output terminal and a value “1” from the Qn output terminal.

  The readout control circuit unit 202b in the pixel control circuit 203 on the second line receives the signals from the Q output terminal and the Qn output terminal of the DFF 201 and the output signal on the second line of the vertical shift register 124 as input signals. When the pixels on the second line of the odd frame are read, the switching signal 2 kb that turns on the transistor Tr6 in FIG. 3 is output oddly, and the switching signal 2k that turns on the transistor Tr5 is alternately switched over one vertical scanning cycle. The signals are alternately output at a short predetermined period (for example, a period of 2 kHz).

  By alternately turning on the transistors Tr5 and Tr6, the negative polarity digital-analog conversion voltage of the inverted data held in the negative polarity holding capacitor C2 and the positive polarity holding capacitor C1 are held. The positive polarity digital-analog conversion voltage of the inverted data is alternately applied to the pixel electrode PE.

  Here, the negative polarity digital-analog conversion voltage (specifically, the sampled negative polarity ramp signal RAMP2- shown in FIG. 7) held in the negative polarity holding capacitor C2 is the pixel electrode PE. The common electrode voltage Vcom when applied to is a low-level common electrode voltage indicated by Vcom2- in FIG. Further, the positive polarity digital-analog conversion voltage (specifically, the positive polarity ramp signal RAMP2 + shown in FIG. 7 sampled) held in the positive polarity holding capacitor C1 is applied to the pixel electrode PE. The common electrode voltage Vcom at this time is the high-level common electrode voltage indicated by Vcom2 + in FIG.

  Thereafter, in the same manner as described above, in the odd frame, the positive polarity digital-analog conversion voltage of the normal state data held in the positive polarity holding capacitor C1 and the negative polarity holding capacitor C2 in the odd-numbered line are held. The negative-polarity digital-analog conversion voltage of the normal state data that has been applied is alternately applied to the pixel electrode PE at a predetermined cycle shorter than one vertical scanning cycle, and two types of common electrode voltages are synchronized with this. Alternates between Vcom1 + and Vcom1-. In the odd frame, in the even-numbered line, the positive polarity digital-analog conversion voltage of the inverted data held in the positive polarity holding capacitor C1 and the inverted state held in the negative polarity holding capacitor C2. The negative polarity digital-analog conversion voltage of data is alternately read at a predetermined cycle shorter than one vertical scanning cycle, and is read first from C2 in reverse to the reading order of the odd-numbered lines and is applied to the pixel electrode PE. In addition to being applied, in synchronization with this, two types of common electrode voltages Vcom2 + and Vcom2- are alternately switched.

  On the other hand, in the even frame, contrary to the odd frame described above, on the odd-numbered lines, the positive digital-analog conversion voltage of the inverted data and the negative digital-analog conversion voltage of the inverted data are one vertical scan. It is alternately read out at a predetermined cycle shorter than the cycle and applied to the pixel electrode PE, and in synchronization with this, it switches alternately to two types of common electrode voltages Vcom2 + and Vcom2-. The positive polarity digital-analog conversion voltage of normal state data and the negative polarity digital-analog conversion voltage of normal state data alternately in a predetermined cycle shorter than one vertical scanning cycle, and the reading order of odd-numbered lines On the contrary, C2 is read first and applied to the pixel electrode PE, and in synchronization with this, it is alternately switched to two types of common electrode voltages Vcom1 + and Vcom1-. Change.

  Next, reading data in the inverted state will be described in more detail.

  When the voltage of the positive ramp signal RAMP2 + sampled and held in the positive holding capacitor C1 is applied to the pixel electrode PE, the common electrode voltage at the level indicated by Vcom2 + in FIG. When the voltage of the negative ramp signal RAMP2- sampled and held in the holding capacitor C2 is applied to the pixel electrode PE, the common electrode voltage at the level indicated by Vcom2- in FIG. 7 is applied to the common electrode CE.

  Accordingly, the voltage applied to the liquid crystal layer LCM of the liquid crystal display element LC is a difference voltage between the applied voltage of the pixel electrode PE and the applied voltage of the common electrode CE, and therefore the lamp sampled and held in the positive holding capacitor C1. When the voltage of the signal RAMP2 + is applied to the pixel electrode PE, the voltage is indicated by Vp2 in FIG. 7, and when the voltage of the ramp signal RAMP2- sampled and held in the negative holding capacitor C2 is applied to the pixel electrode PE, Although the voltage is indicated by Vm2 in FIG. 7 and the direction of voltage application is reversed, the same applied voltage is applied to the liquid crystal layer LCM with the same data. As in the case of reading, the brightness displayed in the case of the same data does not change, but the voltages applied to the pixel electrode PE and the common electrode CE have opposite polarities. It is possible to make it difficult to cause seizure.

  Here, the voltage of the ramp signal RAMP2 + sampled and held in the positive holding capacitor C1 is a voltage indicated by Vp2 in FIG. 7, and the voltage of the transistor (PMOS transistor Tr3 in FIG. 3) in the source follower circuit on the positive polarity side. When Vth is higher than the average value, as shown in FIG. 7, the voltage is increased by Vlv1 corresponding to the error and applied to the pixel electrode PE. In this case, the pixel state is darker than the correct brightness.

  On the other hand, the voltage of the ramp signal RAMP2- sampled and held in the negative holding capacitor C2 is the voltage indicated by Vm2 in FIG. 7, but the transistor (PMOS transistor Tr4 in FIG. 3) in the source follower circuit on the negative polarity side. When Vth is higher than the average value, as shown in FIG. 7, the voltage is increased by Vlv2 corresponding to the error and applied to the pixel electrode PE. In this case, the pixel state is brighter than the correct brightness. As described above, if there is an error in which the Vth of the transistor of the source follower circuit on the positive polarity side in each pixel and the Vth of the transistor of the source follower circuit on the negative polarity side deviate from the normal values, the correct brightness is obtained. The display of the shifted state is the same as in the normal state data reading described with reference to FIG.

  Here, the brightness Xp2 of the liquid crystal display element when the positive pixel electrode voltage Vcom2 + shown in FIG. 7 is applied is expressed by the following equation.

Xp2 = fp × (Vp2−Vlv1) (3)
In the equation (3), fp is a function for calculating display brightness when voltage is applied, Vp2 is an input voltage of data in the inverted state of the positive polarity holding capacitor in the pixel, and Vlv1 is a source follower on the positive side of the pixel. It is the variation voltage of the circuit. The brightness Xm2 of the liquid crystal display element when the negative pixel electrode voltage Vcom2- shown in FIG. 7 is applied is expressed by the following equation.

Xm2 = fm × (Vm2 + Vlv2) (4)
In the equation (4), fm is a function for calculating the display brightness when voltage is applied, Vm2 is an input voltage of data in the inverted state of the negative holding capacitor in the pixel, and Vlv2 is a negative source follower of the pixel. It is the variation voltage of the circuit.

  Next, referring back to FIG. In the liquid crystal panel driving element 12 of FIG. 2, normal state data and inverted state data are alternately supplied in units of 1H from the panel driving driver circuit 11, and the positive polarity ramp signal and the negative polarity are input as described above. The signal is converted into an analog signal voltage using the negative ramp signal and written into the positive holding capacitor and the negative holding capacitor in each pixel.

  After normal data or inverted data is written, the written data is read at high speed in a predetermined cycle (for example, a 2 kHz cycle). In this embodiment, in this embodiment, in both the odd frame and the even frame, the normal state data and the inverted state data converted into the analog signal voltage using the positive polarity ramp signal and the negative polarity ramp signal are used. Are alternately switched in a 1H cycle.

  In addition, the common electrode voltage is alternately switched between a positive common electrode voltage (Vcom1 + or Vcom2 +) and a negative common electrode voltage (Vcom1- or Vcom2-) in a cycle of 2 kHz at the time of reading. -Depending on whether the analog conversion voltage is normal state data or inverted state data, and whether the analog conversion voltage is read from the positive holding capacitor or the negative holding capacitor, that is, positive according to the four types of combinations It is necessary to select whether to read from the common electrode voltage or the negative common electrode voltage.

  Therefore, in this embodiment, although not shown in FIG. 2, a circuit that changes the selection of the positive and negative common electrode voltages according to the identification flag is used. FIG. 8 shows the relationship between the input data and the common electrode voltage. In FIG. 8A, “+ side” indicates a case where normal state data or inverted state data is read from the positive holding capacitor, and “− side” indicates a case where the negative holding capacitor is read. In FIG. 6B, “Low” indicates Vcom1 + or Vcom2− where the common electrode voltage is a low level side voltage, and “High” indicates Vcom1− or Vcom2 + where the common electrode voltage is a high level side voltage. Indicates.

  In this way, according to the present embodiment, since all four types of combinations are displayed in time series, the brightness X of the display screen is the average of the four types of combinations, and the expressions (1) to (4) ) Is expressed by the following equation.

X = (Xm + Xm2 + Xp + Xp2) / 4
= (Fm × (Vm1 + Vlv2 + Vm2−Vlv2)
+ Fp × (Vp1 + Vlv1 + Vp2−Vlv1) / 4
= (Fm × (Vm1 + Vm2) + fp × (Vp1 + Vp2) / 4 (5)
Here, in the case of the same pixel, fm = fp = f, Vm1 = Vm2 = Vp1 = Vp2 = V
Therefore, the equation (5) is expressed by the following equation.

X = f × V (6)
Therefore, according to the present embodiment, as can be seen from the equation (6), the brightness X can be set to a brightness in which variation in Vth of the transistors of the source follower circuit for each pixel is suppressed. However, since the pixel variation slightly differs depending on the signal voltage, it is difficult to completely cancel it, but it can be suppressed.

  As a result, according to the present embodiment, FPN caused by variations in Vth of transistors of the source follower circuit for each pixel can be reduced, and display quality can be improved. Further, according to the present embodiment, a certain degree of suppression can be expected even when an incorrect voltage such as a bright spot or a black spot is applied to the pixel electrode in the same manner as pixel variations. Furthermore, according to the present embodiment, it is possible to visually suppress display image flicker caused by a waveform shift between a plurality of types of ramp signals.

  The present invention is not limited to the above embodiment. For example, the normal state data and the inverted state data are alternately switched and written to the pixels every 1H. Alternatively, the pixel may be written to the pixel. This is because flicker can be visually suppressed if there are approximately the same number of normal state data writes and inverted state data writes on the same screen.

DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 11 Panel drive driver circuit 12 Liquid crystal panel drive element 120 Image processing circuit 121 Horizontal shift register and comparator 122 Horizontal drive circuit (video switch etc.)
123 Pixel part 124 Vertical shift register 125 Pixel selection circuit with flag 201 D-type flip-flop (DFF)
202a Write control circuit section 202b Read control circuit section 203 Pixel control circuit 204 Pixel Tr1, Tr2 Pixel selection NMOS transistor Tr3, Tr4 Source follower PMOS transistor Tr5, Tr6 Switching PMOS transistor Tr7 Constant current load PMOS transistor LC Liquid crystal display element PE Pixel electrode CE Common electrode LCM Liquid crystal layer

Claims (2)

Each of a plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of row scanning lines intersect each other with two data lines as one set,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
First sampling and holding means for sampling a positive-polarity digital-analog conversion voltage supplied via one data line of the set of the two data lines and holding it in a first holding capacitor for a certain period; ,
Second sampling and holding means for sampling the negative-polarity digital-analog conversion voltage supplied through the other data line of the set of the two data lines and holding it in the second holding capacitor for a certain period of time When,
Holding voltage reading means for alternately applying the first holding voltage of the first holding capacitor and the second holding voltage of the second holding capacitor to the pixel electrode at a predetermined cycle shorter than the vertical scanning cycle. And
The reference gradation data at a time point when the pixel value of the input digital data is compared with the reference gradation data whose level is monotonously changed in the horizontal scanning cycle and the pixel value and the value of the reference gradation data match. At the same time as supplying the voltage of the positive ramp signal, which is a periodic signal that monotonously increases in level within a horizontal scanning period, to the one data line as the positive digital-analog conversion voltage, the reference gray scale Data input means for supplying the negative data signal to the other data line as the negative digital-to-analog conversion voltage as a negative voltage signal, which is a periodic signal whose level decreases monotonously within a horizontal scanning period in synchronization with data;
Synchronize the normal data with the same data value as the digital data to be displayed and the inverted data obtained by inverting the data value of the digital data to be displayed with the positive ramp signal and the negative ramp signal. The input digital data is switched alternately in units of N horizontal scanning periods (N is a natural number of 1 or more), and the switching order of the normal state data and the inverted state data is alternately switched in units of one frame. As input data processing means for input to the data input means,
When the pixel having the positive ramp signal and the negative ramp signal corresponding to the pixel value of the data in the normal state held in the first and second holding capacitors is read by the holding voltage reading unit, the first A first common electrode voltage having a first potential is applied to the common electrode when a holding voltage of 1 is applied to the pixel electrode, and the first common voltage is applied to the pixel electrode when the second holding voltage is applied to the pixel electrode. A second common electrode voltage having a second potential higher than the first potential is applied to the common electrode, and the positive ramp signal and the negative ramp signal corresponding to the pixel value of the data in the inverted state are When the pixels held in the first and second holding capacitors are read by the holding voltage reading means, the third common electrode voltage of the third potential is applied when the first holding voltage is applied to the pixel electrode. Common A common voltage applied to the common electrode, and a fourth common electrode voltage having a fourth potential lower than the third potential is applied to the common electrode when the second holding voltage is applied to the pixel electrode. Electrode voltage input means;
A liquid crystal display device comprising: Each of a plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of row scanning lines intersect each other with two data lines as one set,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
First sampling and holding means for sampling a positive-polarity digital-analog conversion voltage supplied via one data line of the set of the two data lines and holding it in a first holding capacitor for a certain period; ,
Second sampling and holding means for sampling the negative-polarity digital-analog conversion voltage supplied through the other data line of the set of the two data lines and holding it in the second holding capacitor for a certain period of time When,
Holding voltage reading means for alternately applying the first holding voltage of the first holding capacitor and the second holding voltage of the second holding capacitor to the pixel electrode at a predetermined cycle shorter than the vertical scanning cycle. For a liquid crystal display device comprising
Synchronize the normal data with the same data value as the digital data to be displayed and the inverted data obtained by inverting the data value of the digital data to be displayed with the positive ramp signal and the negative ramp signal. Then, it is alternately switched in units of N horizontal scanning cycles (N is a natural number of 1 or more), and the switching order of the normal state data and the inverted state data is alternately switched in units of one frame as input digital data. An input data processing step to output;
The pixel value of the input digital data output in the input data processing step is compared with the reference gradation data whose level changes monotonously in the horizontal scanning cycle, and the pixel value and the value of the reference gradation data are The data of the positive ramp signal, which is a periodic signal that monotonously increases in level within a horizontal scanning period in synchronization with the reference grayscale data at the time of coincidence, is used as the positive polarity digital-analog conversion voltage. The voltage of the negative ramp signal, which is a periodic signal that decreases monotonically within a horizontal scanning period in synchronization with the reference gradation data, is supplied to the line as the negative digital-analog conversion voltage. A data input step for supplying data lines;
When the pixel having the positive ramp signal and the negative ramp signal corresponding to the pixel value of the data in the normal state held in the first and second holding capacitors is read by the holding voltage reading unit, the first A first common electrode voltage having a first potential is applied to the common electrode when a holding voltage of 1 is applied to the pixel electrode, and the first common voltage is applied to the pixel electrode when the second holding voltage is applied to the pixel electrode. A first common electrode voltage input step of applying, to the common electrode, a second common electrode voltage having a second potential that is higher than the first potential;
When the pixel having the positive ramp signal and the negative ramp signal corresponding to the pixel value of the inverted data held in the first and second holding capacitors is read by the holding voltage reading means, the first A third common electrode voltage having a third potential is applied to the common electrode when a holding voltage of 1 is applied to the pixel electrode, and the third voltage is applied to the pixel electrode when the second holding voltage is applied to the pixel electrode. A second common electrode voltage input step of applying, to the common electrode, a fourth common electrode voltage of a fourth potential lower than the potential of
A method for driving a liquid crystal display device, comprising:

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