JP2012212911A - Solid state imaging device, and driving method of solid state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve various problems that occur when structure, where a p+ layer is formed on a rear side of a substrate, is employed so as to prevent occurrence of dark current from a silicon interface.SOLUTION: An insulating film 39 is provided on a rear surface of a silicon substrate 31, and a transparent electrode 40 is provided on the insulating film 39. The insulating film 39 is applied with negative voltage against potential of the silicon substrate 31 through the transparent electrode 40 from a voltage source 41, thereby positive holes are accumulated on a silicon interface on a rear surface side of the substrate. Thus, structure, which is equivalent to structure where a positive hole accumulation layer is present on the silicon interface, is generated.

Description

  The present invention relates to a solid-state imaging device and a driving method of the solid-state imaging device, and more particularly to a back-illuminated solid-state imaging device that captures incident light from the back side (the side opposite to the wiring forming side) of a substrate and the driving method of the solid-state imaging device.

  In a solid-state imaging device, for example, an XY address type solid-state imaging device represented by a CMOS image sensor, a wiring layer is formed on one surface (front surface) of a semiconductor substrate for the purpose of miniaturizing pixels and increasing the aperture ratio. In addition, a back-surface light receiving type pixel structure that takes in incident light from the surface (back surface) side opposite to the wiring layer is employed (for example, see Patent Documents 1 and 2).

  As shown in FIG. 15, the pixel structure according to the related art described in Patent Document 1 may be simply referred to as one surface of the silicon layer (substrate) 101 on which the photodiode 102 is formed (hereinafter simply referred to as “substrate surface”). ) Side, a wiring layer 103 in which a multi-layer wiring 106 is arranged through an interlayer insulating film is formed, and the other surface of the silicon layer 101, that is, a surface opposite to the wiring layer 103 (hereinafter simply referred to as “substrate back surface”). In some cases, visible light is taken in from the side. A p-type well region 107 reaching the back surface of the substrate is formed around the photodiode 102.

  In this back-illuminated CMOS image sensor, a p + layer 104 is formed on the back side of the substrate in order to prevent dark current from being generated from the silicon interface. There are the following two methods for forming the p + layer 104.

  In the first method, a wiring layer 103 including transistors and wirings is formed on the surface side of the substrate, and then the substrate is turned over to polish the back surface side of the substrate and then prevent injection of electrons such as a silicon oxide film (SiO 2). In this method, the layer 105 is formed, and then the p + layer 104 is formed by ion implantation.

  The second method is to form a p + layer 104 in a deep part of the substrate by high energy ion implantation from the substrate surface side during the process of forming a transistor on the substrate surface side, and then to form a wiring 106 to form the wiring layer 103. In this method, the substrate is turned upside down and polished to the position of the p + layer 104 to form a light receiving surface on the back surface side of the substrate.

  As shown in FIG. 16, the pixel structure according to the related art described in Patent Document 2 has an interlayer insulating film on one surface (front surface) side of a silicon portion (high resistance substrate) 201 on which a photodiode 202 is formed. In a back-illuminated CMOS image sensor that forms a wiring layer 203 on which multilayer wirings 207 are arranged and takes in light from the other surface (back surface) side, the photodiode 202 and the surrounding p-type well region 204 are formed on the back surface of the substrate. In this configuration, a negative voltage is applied to the transparent electrode 206 formed on the back surface of the substrate via the electron injection prevention film 205.

JP 2003-031785 A JP 2003-338615 A

  In the prior art described in Patent Document 1 described above, the p + layer 104 is formed on the back surface side of the substrate in order to prevent the generation of dark current from the silicon interface. Even when the method is adopted or when the second method is adopted, there are problems as described below.

(When using the first method)
If the ion-implanted p + layer 104 is not subjected to heat treatment for activation, the effect of reducing dark current cannot be maximized. However, since ion implantation is performed in a process after the formation of the wiring. If the heat treatment is performed using a normal diffusion furnace, the wiring melts and cannot be used.

  For this reason, it is assumed that the dark current is large without heat treatment for activation, or only a shallow region on the back side of the substrate is heat-treated by laser annealing or the like. However, laser annealing is expensive, and the wafers are scanned sequentially, so the throughput is poor compared to a diffusion furnace that can process dozens of wafers at once, and the scanning lines are uneven in the captured image. May appear.

(When using the second method)
Since ion implantation is performed before the wiring layer 103, activation heat treatment is possible. However, since ion implantation is performed at a high energy and deep site, the distribution of the p + layer 104 is widened. When the distribution of the p + layer 104 is widened, the probability of capturing photoelectrons with respect to blue light that is photoelectrically converted at a shallow portion on the back side of the substrate is lowered, that is, blue sensitivity is lowered.

  This decrease in blue sensitivity cancels the effect that there is no decrease in sensitivity due to the wiping of the wiring 106, which is a feature of the back surface light receiving type pixel structure. On the other hand, the sensitivity of the red light entering the deep part is increased as much as the wiring 106 is not damaged by the back side incidence. As the sensitivity of red is improved, the sensitivity of blue is relatively deteriorated, so that the spectral balance is lost.

  On the other hand, in the prior art described in Patent Document 2, even when the p-type well region 204 has a layer structure that does not reach the back surface of the substrate, the transparent electrode 206 is used to properly guide the photoelectrons incident from the back surface of the substrate to the photodiode 202. A negative voltage is applied to the substrate to generate an electric field in the depth direction in the substrate, and the reduction of dark current from the silicon interface on the back side of the substrate has not been considered.

  The present invention has been made in view of the above problems, and its object is to perform ion implantation on the back side of the substrate, to increase the concentration, or to perform heat treatment for activation. It is another object of the present invention to provide a solid-state imaging device and a driving method for the solid-state imaging device that can reduce the generation of dark current from the interface on the back side of the substrate.

  The solid-state imaging device according to the present invention has a wiring layer on the first surface (substrate surface) side of a semiconductor substrate on which pixels including photoelectric conversion elements are formed, and a second surface (substrate back surface) opposite to the wiring layer. A solid-state imaging device configured to capture incident light from the side of the insulating film formed on the second surface of the semiconductor substrate, and a voltage application that applies a voltage having a polarity opposite to the potential of the semiconductor substrate to the insulating film Means.

  In the solid-state imaging device of the present invention, in a back-illuminated solid-state imaging device that captures incident light from the back side of the substrate, a voltage having a polarity opposite to the potential of the semiconductor substrate (a negative voltage when the semiconductor substrate is n-type, p When a positive voltage is applied to the insulating film, holes are applied to the semiconductor interface (interface with the insulating film) on the back side of the substrate, for example, when the semiconductor substrate is n-type (electrons when p-type). This is equivalent to the presence of a hole accumulation layer (or electron accumulation layer) at the interface on the back side of the substrate. The generation of electrons (or holes) from the back side interface of the substrate, which is the dominant cause of dark current, is reduced by the action of the portion where the holes (or electrons) are accumulated.

  The solid-state imaging device according to the present invention has a wiring layer on the first surface side of a semiconductor substrate on which pixels including photoelectric conversion elements are formed, and captures incident light from the second surface side opposite to the wiring layer. An apparatus is a device in which a voltage having the same polarity as the signal charge of the photoelectric conversion element is applied to the insulating film formed on the second surface of the semiconductor substrate, and a charge having a polarity opposite to that of the signal charge is applied to the semiconductor substrate. And a voltage applying means for inducing on the two sides.

  In the solid-state imaging device of the present invention, in a back-illuminated solid-state imaging device that captures incident light from the back side of the substrate, a voltage having the same polarity as the signal charge of the photoelectric conversion element is applied to the insulating film, so that the polarity is opposite to that of the signal charge. Electric charges are induced on the second surface side of the semiconductor substrate. This reduces the generation of charges having the same polarity as the signal charges from the back side of the substrate, which is the cause of dark current.

  The solid-state imaging device driving method according to the present invention has a wiring layer on the first surface side of a semiconductor substrate on which pixels including photoelectric conversion elements are formed, and receives incident light from the second surface side opposite to the wiring layer. A method for driving a solid-state imaging device to be captured, wherein a voltage having a polarity opposite to a potential of a semiconductor substrate is applied to an insulating film formed on a second surface of the semiconductor substrate.

In the driving method of the solid-state imaging device of the present invention, in the driving method of the back-illuminated solid-state imaging device that captures incident light from the back side of the substrate, when a voltage having a polarity opposite to the potential of the semiconductor substrate is applied to the insulating film, the substrate For example, when the semiconductor substrate is n-type, holes (electrons when the semiconductor substrate is p-type) are stored in the semiconductor interface (interface with the insulating film) on the back side, and hole accumulation layers (or electrons are stored on the back side interface of the substrate). This is equivalent to the existence of a storage layer.
Due to the action of the portion where the holes (or electrons) are accumulated, the generation of electrons (or holes) from the back side interface of the substrate, which is a dominant cause of dark current, is reduced.

  In the solid-state imaging device according to the present invention, a pixel including a photoelectric conversion element is formed on a semiconductor substrate, an insulating film is formed on the back side of the semiconductor substrate, and incident light is captured from the back side of the semiconductor substrate plate. In the array portion, a back electrode is formed through an insulating film, and a leak current blocking region for blocking a leak current between the pad portion and the semiconductor substrate is provided immediately below the pad portion of the back electrode. .

  In the solid-state imaging device of the present invention, the occurrence of dark current from the substrate rear surface side interface is reduced by applying a voltage having a reverse polarity to the potential of the semiconductor substrate to the rear electrode as described above. In addition, since a leakage current blocking region is provided directly under the pad portion, even if the inspection needle is repeatedly applied to the pad portion, the insulating film under the back electrode can be prevented from being broken, or even if the insulating film is broken. Leakage current between the pad portion and the semiconductor substrate can be prevented.

According to the solid-state imaging device of the present invention, an insulating film is formed on the back surface of the semiconductor substrate, and a voltage having a polarity opposite to the potential of the semiconductor substrate is applied to the insulating film, so that holes are formed on the back surface side interface of the substrate. A structure equivalent to the storage layer (or electron storage layer) can be made, so even if ion implantation is performed on the back side of the substrate, concentration is increased, or heat treatment for activation is not performed, Generation of dark current from the substrate rear surface side interface can be reduced.
According to the solid-state imaging device of the present invention, an insulating film is formed on the back surface of the semiconductor substrate plate, and a voltage having the same polarity as the signal charge of the photoelectric conversion element is applied to the insulating film, so Since a structure equivalent to the hole accumulation layer (or electron accumulation layer) can be made, it is possible to perform ion implantation on the back side of the substrate, increase the concentration, or heat treatment for activation. The generation of dark current from the substrate back side interface can be reduced.

  According to the driving method of the solid-state imaging device according to the present invention, ions are implanted into the back surface side of the substrate by applying a voltage having a polarity opposite to the potential of the semiconductor substrate to the insulating film formed on the back surface of the semiconductor substrate. Even if the concentration is not increased or heat treatment for activation is not performed, driving can be performed while reducing the generation of dark current from the substrate rear surface side interface.

  According to the solid-state imaging device according to the present invention, it is possible to reduce the generation of dark current from the interface on the back side of the substrate, and to generate leakage current between the pad portion and the semiconductor substrate in the leakage current blocking region immediately below the pad portion. Since this can be prevented, the thickness of the insulating film under the back electrode can be reduced. Thereby, it is possible to prevent the leak current from being generated in the pad portion while suppressing the voltage applied to the back electrode to a low level.

It is a block diagram which shows the whole structure of the CMOS image sensor to which this invention is applied. It is a circuit diagram which shows an example of the circuit structure of a pixel. 1 is a cross-sectional view showing a main part of a solid-state imaging device according to a first embodiment of the present invention, in particular, a backside light receiving pixel structure thereof. It is sectional drawing which shows the principal part of the solid-state imaging device which concerns on 3rd Embodiment of this invention, especially its back surface light reception type pixel structure. It is an enlarged view of the principal part which shows the desirable aspect of p well area | region. It is sectional drawing which shows the principal part of the solid-state imaging device which concerns on 4th Embodiment of this invention. It is the top view seen from the board | substrate back surface side which shows an example of the taking-out method of the pad part in the solid-state imaging device which concerns on this invention. It is the top view seen from the board | substrate back surface side which shows the other example of the extraction method of the pad part in the solid-state imaging device which concerns on this invention. It is sectional drawing which shows the principal part of the solid-state imaging device which concerns on 5th Embodiment of this invention. It is sectional drawing which shows an example of the contact part in the back surface electrode of the two-layer structure applied to this invention. It is sectional drawing which shows the other example of the contact part in the back surface electrode of the two-layer structure applied to this invention. It is sectional drawing which shows the principal part of the solid-state imaging device which concerns on 6th Embodiment of this invention. It is sectional drawing which shows the principal part of the solid-state imaging device which concerns on 7th Embodiment of this invention. It is sectional drawing which shows the principal part of the solid-state imaging device which concerns on 8th Embodiment of this invention. It is sectional drawing which shows an example of the pixel of the conventional back-illuminated type solid-state imaging device. It is sectional drawing which shows the other example of the pixel of the conventional back-illuminated type solid-state imaging device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the overall configuration of a solid-state imaging device to which the present invention is applied, for example, a CMOS image sensor. Here, the case where the present invention is applied to a CMOS type solid-state imaging device will be described as an example. However, the present invention is not limited to this application example, and an XY addressing type solid-state device such as a MOS type solid-state imaging device or the like. The present invention can be similarly applied to all imaging apparatuses.

  As shown in FIG. 1, the CMOS image sensor 10 according to this application example includes a vertical drive in addition to a pixel array unit 12 in which a large number of pixels 11 including photoelectric conversion elements are two-dimensionally arranged in a matrix (matrix). The system configuration includes a circuit 13, a column signal processing circuit 14, a horizontal drive circuit 15, a horizontal signal line 16, an output circuit 17, and a control circuit 18.

  In this system configuration, the control circuit 18 receives data for instructing the operation mode and the like of the CMOS image sensor 10 from the outside, outputs data including information on the CMOS image sensor 10 to the outside, and outputs the vertical synchronization signal Vsync. Based on the horizontal synchronization signal Hsync and the master clock MCK, the vertical drive circuit 13, the column signal processing circuit 14, the horizontal drive circuit 15 and the like generate clock signals and control signals that serve as reference for operation. This is applied to the column signal processing circuit 14 and the horizontal drive circuit 15.

  In the pixel array section 12, the pixels 11 are two-dimensionally arranged, and row control lines for each pixel row are wired in the horizontal direction (left-right direction) in the drawing with respect to this pixel arrangement, and vertical signal lines are provided for each pixel column. 19 is wired in the vertical direction (vertical direction) in the figure. The vertical drive circuit 13 is configured by a shift register or the like, sequentially selects and scans each pixel 11 of the pixel array unit 12 in units of rows, and supplies necessary control pulses to the pixels in the selected row through the row control line. To do.

  A signal output from each pixel in the selected row is supplied to the column signal processing circuit 14 through the vertical signal line 19. The column signal processing circuit 14 is disposed, for example, for each pixel column of the pixel array unit 12, receives a signal output from the pixel 11 for one row for each pixel column, and is specific to the pixel 11 with respect to the signal. Signal processing such as CDS (Correlated Double Sampling) and signal amplification for removing fixed pattern noise is performed.

  As shown in FIG. 2, a load transistor 141 as a constant current source is provided at the input stage of the column signal processing circuit 14. The load transistor 141 is connected between the vertical signal line 19 and a reference potential, for example, the ground, the gate is connected to the load wiring 25, and constitutes a source follower circuit with the amplification transistor 114 of the pixel in the selected row. A signal is output from the pixel in the selected row to the vertical signal line 19.

  At the output stage of the column signal processing circuit 14, a horizontal selection switch (not shown) is provided connected to the horizontal signal line 16. It is also possible to adopt a configuration in which the column signal processing circuit 14 has an A / D (analog / digital) conversion function.

  The horizontal driving circuit 15 is configured by a shift register or the like, and sequentially selects the column signal processing circuits 14 by sequentially outputting horizontal scanning pulses φH1 to φHn, and horizontally outputs the pixel signals from each of the column signal processing circuits 14. The signal line 16 is output.

  The output circuit 17 performs various signal processing on the signals sequentially supplied from each of the column signal processing circuits 14 through the horizontal signal line 16 and outputs the processed signals. As specific signal processing in the output circuit 17, for example, only buffering may be performed, or black level adjustment, correction of variation for each column, signal amplification, color-related processing, and the like are performed before buffering. Sometimes.

  FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the pixel 11. As shown in FIG. 2, the pixel 11 according to this circuit example includes, in addition to a photoelectric conversion element, for example, a photodiode 111, four transistors, for example, a transfer transistor 112, a reset transistor 113, an amplification transistor 114, and a selection transistor 115. It is a pixel circuit. Here, as these transistors 112 to 115, for example, N-channel MOS transistors are used.

  The photodiode 111 photoelectrically converts the received light into photoelectric charges (here, electrons) having a charge amount corresponding to the amount of light. The cathode (n-type region) of the photodiode 111 is connected to the gate of the amplification transistor 114 via the transfer transistor 112. A node 116 electrically connected to the gate of the amplification transistor 114 is referred to as an FD (floating diffusion) portion.

  The transfer transistor 112 is connected between the cathode of the photodiode 111 and the FD unit 116, and is turned on when a transfer pulse φTRG is applied to the gate via the transfer line 21, and the light photoelectrically converted by the photodiode 111. The charge is transferred to the FD unit 116.

  The reset transistor 113 is turned on when the drain is connected to the pixel power supply Vdd, the source is connected to the FD unit 116, and a reset pulse φRST is applied to the gate via the reset line 22, and the photodiode 111 to the FD unit 116. Prior to the transfer of the signal charge, the FD unit 116 is reset by discarding the charge of the FD unit 116 to the pixel power supply Vdd.

  The amplification transistor 114 has a gate connected to the FD unit 116 and a drain connected to the pixel power supply Vdd, and outputs the potential of the FD unit 116 after being reset by the reset transistor 113 as a reset level. The potential of the FD unit 116 after the transfer is output as a signal level.

  For example, the selection transistor 115 is turned on when the drain is connected to the source of the amplification transistor 114, the source is connected to the vertical signal line 19, and the selection pulse φSEL is applied to the gate via the selection line 23. As a selected state, a signal output from the amplification transistor 114 is relayed to the vertical signal line 19.

  The horizontal wiring, that is, the transfer line 21, the reset line 22, and the selection line 23 are common to the pixels in the same row, and are controlled by the vertical drive circuit 13. However, the p-well wiring 24 for fixing the p-well potential of the pixel 11 is fixed to the ground potential.

  The selection transistor 115 may have a circuit configuration connected between the pixel power supply Vdd and the drain of the amplification transistor 114.

  Further, the pixel 11 is not limited to the four-transistor configuration described above, and may have a three-transistor configuration that combines the amplification transistor 114 and the selection transistor 115.

  In the pixel 11 having the above-described configuration, a wiring layer is formed on the first surface (substrate surface) of the semiconductor substrate and the second surface (substrate) opposite to the wiring layer for the purpose of miniaturizing the pixel and increasing the aperture ratio. A backside light receiving type (backside incident type) pixel structure that takes in incident light from the back side is employed. A specific configuration of the backside light receiving type pixel structure is a feature of the present invention. Further, in addition to the back surface light receiving type pixel structure, the structure of the bonding pad portion formed on the back surface side of the substrate is also a feature of the present invention. Specific embodiments of the present invention will be described below.

[First Embodiment]
FIG. 3 is a cross-sectional view showing the main part of the back-illuminated CMOS image sensor according to the first embodiment of the present invention, particularly its back-side light-receiving pixel structure. In the backside light receiving pixel structure according to the present embodiment, a first conductivity type, for example, an n-type (n−) silicon substrate is used as the semiconductor substrate.

  In FIG. 3, the wafer is polished by CMP (Chemical Mechanical Polishing) to form a silicon portion (hereinafter referred to as a “silicon substrate”) 31 having a predetermined thickness. A photodiode 33 (corresponding to the photodiode 111 in FIG. 2) is formed in the inside using the substrate (n− type region 32). The thickness of the silicon substrate 31 is preferably about 5 μm to 10 μm for visible light. With this thickness setting, visible light can be favorably photoelectrically converted by the photodiode 32.

  The photodiode 33 includes an n-type region 32 in which the n − type region 32 becomes a photoelectric conversion region, and photoelectric charges (electrons in this example) photoelectrically converted in the n − type region 32 are accumulated. 1st surface) It is a buried diode (HAD; Hole Accumulated Diode) which has the p + layer 35 which accumulate | stores a carrier in this example, a hole, and a hole in this example, The p-type semiconductor well area | region (henceforth p-type well area | region) 36) so as to reach the back surface (second surface) of the silicon substrate 31.

  On the surface side of the silicon substrate 31, various wirings of the pixel 11, more specifically, a wiring layer in which the transfer line 21, the reset line 22, the selection line 23, the p-well wiring 24 and the like described above are wired, that is, interlayer insulation. A wiring layer 37 having a multilayer wiring 45 is formed through the film. In the wiring layer 37, the gate electrode 38 of the transfer transistor 112 and the gate electrodes (not shown) of other transistors are also formed.

  As described above, the p-well region 36 is formed so as to reach the back surface of the silicon substrate 31, and a reference potential, for example, a ground (GND) potential is supplied through the wiring layer 37, specifically, the p-well wiring 24. Is given. In FIG. 3, only the transfer transistor is shown as the MOS transistor. The transfer transistor is formed by using a photodiode 33, in particular, an n-type region 34 as a source, an n-type source / drain region 46 to be an FD portion, and a gate electrode 38 formed through a gate insulating film.

  In this way, by surrounding the photodiode 33 with the p-well region 36 that is formed so as to reach the back surface of the substrate and to which a reference potential is applied, the photoelectric charge photoelectrically converted at a portion close to the back surface of the substrate is n. The mold region 34 can be properly guided.

  An insulating film 39 is formed on the back surface of the silicon substrate 31. The insulating film 39 has, for example, a single layer structure of a silicon oxide film (SiO 2). However, the insulating film 39 is not limited to a single layer structure of a silicon oxide film, and may be a two layer structure of a silicon oxide film and a silicon nitride film, for example. By adopting this two-layer structure, an antireflection effect by the silicon nitride film can be obtained, and more incident light can be taken in, so that there is an advantage that sensitivity can be improved.

  On the insulating film 39, an electrode for applying, for example, a negative voltage (for example, about −3 V) from the voltage source 41 to the insulating film 39, a so-called back electrode is formed. In the illustrated example, a transparent electrode 40 made of ITO (indium and tin oxide) is formed. The transparent electrode 40 and the voltage source 41 constitute voltage applying means for applying a voltage having a polarity opposite to the potential of the silicon substrate 31 (in this example, a positive potential), that is, a negative voltage, to the insulating film 39. Yes.

  In this example, the transparent electrode 40 is used as an electrode for applying a voltage to the insulating film 39. However, it is not always necessary to be a transparent electrode over the entire surface, and at least an n-type in which photoelectric conversion is performed. Any electrode having a configuration capable of taking incident light into the n − -type region 32, such as an electrode having one through hole in a region corresponding to the region 32 or a plurality of through holes in the region, may be used.

  As described above, the insulating film 39 is provided on the back surface of the silicon substrate 31, and a voltage having a polarity opposite to the potential of the silicon substrate 31 is applied to the insulating film 39, for example, a voltage of about −3V. This is equivalent to the accumulation of holes at the back side silicon interface and the presence of a hole accumulation layer at the silicon interface. At this time, since the silicon substrate 31 and the transparent electrode 40 are electrically insulated by the insulating film 39, an electric field is basically not formed in the p-well region 36 that is not depleted. Then, due to the action of the silicon interface where holes are accumulated, the generation of electrons from the silicon back-side silicon interface, which is the dominant cause of dark current, is reduced.

  The action of the interface portion (hole accumulation layer) in which holes are accumulated is the same as the action of the p + layer 35 in the photodiode 33 having a buried diode configuration. The action of the p + layer 35 is as follows. That is, the free charge existing in the p + layer 35 on the surface of the photodiode 33 is only holes, and the electrons are depleted. As a result, the silicon interface is filled with holes, and the generation of electrons from the silicon interface, which is the dominant cause of dark current, is significantly reduced. Due to the action of the p + layer 35, a photodiode with little dark current can be realized. The same applies to the back side of the substrate.

  Thus, according to the first embodiment, by adopting the configuration having such a back electrode, a structure equivalent to the hole accumulation layer can be formed at the silicon interface on the back surface side of the substrate. Generation of dark current from the side interface can be reduced. In particular, the manufacturing process is very simple because there is no need to perform ion implantation, concentration increase, or heat treatment for activation as in the prior art. Since the distribution of the hole accumulation layer to be formed in the substrate depth direction is very shallow, the blue sensitivity can be maximized.

  By the way, in the back-illuminated type, it is important that the photoelectrons generated on the back side of the substrate do not recombine with holes before reaching the surface. In particular, as in this example, when no potential difference greater than the band gap of silicon is generated from the front surface to the back surface of the photodiode 33, the force to collect electrons on the surface is limited. It is important to pull out the holes quickly.

  Therefore, the potential of the p-well region 36 is set not only around the pixel 11 but also through the wiring inside the pixel 11, specifically, through the p-well wiring 24 (see FIG. 2) for each pixel or at every one pixel. It is desirable to provide a fixed contact. Thereby, when holes become excessive in the p-well region 36, it can be quickly extracted, so that the sensitivity can be improved.

(Production method)
Next, a process for producing a CMOS image sensor having a back side light receiving pixel structure (back side incident type) having the above configuration will be described.

(1) The photodiode 33 and the p-well region 36 are formed from the surface side of the silicon substrate 31, and the transistors of the pixel 11 (transfer transistor 112, reset transistor 113, amplification transistor 114, selection transistor 115 are formed on the surface side of the silicon substrate 31. Then, a wiring layer 37 including a gate electrode of the transistor and various wirings (transfer line 21, reset line 22, selection line 23, p-well wiring 24, etc.) is formed.

(2) A support substrate is attached, the wafer is turned over and polished, and the back side is formed so as to have a thickness of the silicon substrate 31 of about 5 μm to 10 μm.
(3) An insulating film 39, specifically, a TEOS film, which is a silicon oxide film, is formed to a thickness of about 20 nm to 40 nm by LPCVD (low pressure chemical vapor deposition) at a low temperature recipe of about 320 ° C.
(4) An ITO film as the transparent electrode 40 is formed to a thickness of about 50 nm to 100 nm by sputtering.

  Through the above-described process, a back-side light-receiving pixel structure can be manufactured. Thereafter, another electrode for light shielding, a color filter, and an on-chip lens may be formed on the transparent electrode 40 as necessary.

  However, the manufacturing method of the CMOS image sensor having the backside light receiving type pixel structure is not limited to the above manufacturing method. For example, using an SOI substrate (a substrate having a silicon-oxide film-silicon structure), a method of removing the oxide film and the silicon on the substrate side may be used as a method of forming the back side in the step (2). good.

  Alternatively, if a method of thinly oxidizing silicon at a low temperature of about 300 ° C. at which the wiring 45 does not melt is found, it may be formed by oxidizing the method in the step (3). Further, in the step (3), in order to prevent reflection, the insulating film 39 may be formed in a two-layer structure by attaching a silicon oxide film immediately after attaching a silicon oxide film.

[Second Embodiment]
In the first embodiment, a voltage of about −3 V is applied to the insulating film 39 using the transparent electrode 40 and the voltage source 41. However, in the second embodiment, the insulating film 39 is substantially covered with silicon. A transparent electrode is formed using a material having a work function difference that gives a negative voltage, and the negative voltage of the work function difference of the transparent electrode and the negative voltage by the voltage source 41 are applied to the insulating film 39 in combination. Like that.

  Note that, as in the case of the first embodiment, the transparent electrode made of a substance having a work function difference that gives a negative voltage is not necessarily a transparent electrode over the entire surface, and at least photoelectric conversion is performed. An electrode having a configuration capable of taking incident light into the n − type region 32, such as an electrode having a configuration having one through hole in a region corresponding to the n − type region 32 or a plurality of through holes in the region. It ’s fine.

  In this way, by using a material that has applied a negative work function difference in a state of 0 V using a work function difference as a transparent electrode, a voltage corresponding to the value of the negative voltage is obtained. The negative voltage value of the source 41 can be reduced.

  As an example, an insulating film 39, in this example, a silicon oxide film having a film thickness of 20 nm or less and a material having a work function difference that gives a negative voltage is a semiconductor having a conductivity type different from that of the silicon substrate 31, for example, a thin film of about 30 nm. By forming the transparent electrode using p-type polysilicon, the negative voltage of the voltage source 41 can be set to −2.5V because the transparent electrode can obtain about −0.5V as the negative voltage of the work function difference. Can be reduced.

  Further, if the thickness of the insulating film 39, that is, the silicon oxide film is reduced to about several nanometers, holes can be stored at the silicon interface at a voltage of about -0.5V. Can be reduced to 0V. This means that the voltage source 41 need not be used.

  Since polysilicon lowers the blue sensitivity, it is preferable to thin the polysilicon (transparent electrode) as described above in order to minimize the influence.

[Third Embodiment]
FIG. 4 is a cross-sectional view showing the main part of the back-illuminated CMOS image sensor according to the third embodiment of the present invention, particularly its back-side light receiving pixel structure. In FIG. A reference numeral is attached.

  In the back surface light receiving pixel structure according to the third embodiment, an insulating film 39 is provided on the back surface of the silicon substrate 31, and a voltage having a polarity opposite to the potential of the silicon substrate 31 is provided on the insulating film 39, for example, about -3V. This is the same as in the first and second embodiments in that a hole is accumulated at the silicon back surface side of the substrate by applying the above voltage.

  The differences from the first and second embodiments are that a high-resistance substrate 42 close to an intrinsic semiconductor is used as a semiconductor substrate and that the p-well region 43 does not reach the back surface of the substrate. 15 differs from the prior art shown in FIG. 15 in that the electron injection preventing film 205 is a film that allows holes to pass therethrough, whereas the insulating film 39 is a film that does not pass holes.

  The photodiode 33 includes a p + layer 35, an n-type region 34, and a high resistance substrate region 42 below the p + layer 35. In the backside light-receiving pixel structure having such a configuration, when the thickness of the high-resistance substrate 42 is thin, a depletion layer expands from the n-type region 34 to the backside of the photodiode 33, so that most electrons are collected in the nearest photodiode. can do. Alternatively, when the color mixing specification is loose, the thickness of the high resistance substrate 42 can be increased.

  An effect of accumulating holes at the silicon back surface side silicon interface by providing an insulating film 39 on the back surface of the silicon substrate 31 and applying a negative voltage with respect to the potential of the silicon substrate 31 to the insulating film 39. The effect is the same as in the first and second embodiments.

  Next, a desirable shape of the p-well region 43 in the backside light receiving pixel structure according to the third embodiment will be described.

  As a desirable mode of the p-well region 43 ′, as shown in FIG. 5, the opening on the substrate back side is made larger than the opening on the substrate surface side. As described above, in the pixel structure in which the p-well region 43 ′ does not reach the back surface of the substrate, the opening on the back surface side of the p-well region 43 ′ is increased, so that the photoelectrons photoelectrically converted by the high-resistance substrate 42 are n There is an advantage that the mold region 34 is easily collected.

  As a method for producing the p-well region 43 ′ having such a shape, for example, when ions are formed at different depths by a plurality of ion implantations, ion implantation into a deep portion is performed using another mask. A method of forming in a process can be used.

[Fourth embodiment]
FIG. 6 is a cross-sectional view showing a main part of a back-illuminated CMOS image sensor according to the fourth embodiment of the present invention, that is, a pixel array part, a peripheral circuit part, and a bonding pad part. As shown in FIG. 6, the CMOS image sensor 50 of the present embodiment includes a photodiode 55 (a photoelectric conversion element) in a pixel array portion 51 of a first conductivity type semiconductor substrate, for example, an n-type silicon substrate 54. 2 (corresponding to the photodiode 111 in FIG. 2) and a plurality of MOS transistors provided in the p-type well region 56 (corresponding to the pixel 11 in FIG. 1) are two-dimensionally arranged in a matrix form. It is formed with a typical arrangement. The MOS transistor is formed on the surface side of the silicon substrate 54. FIG. 6 shows only the transfer transistor 57 (corresponding to the transfer transistor 112 in FIG. 2) as the MOS transistor. The transfer transistor 57 is formed with a photodiode 55 as a source, and an n-type source / drain region 58 to be an FD portion and a gate electrode 59 formed through a gate insulating film.

  In the peripheral circuit 52 of the silicon substrate 54, a CMOS transistor is formed. That is, an n-channel MOS transistor Trn composed of n-type source / drain regions 61 and 62 and a gate electrode 63 formed through a gate insulating film is formed in the p-type well region 56. A p-channel MOS transistor Trp including p-type source / drain regions 66 and 67 and a gate electrode 68 formed through a gate insulating film is formed in the type well region 65.

  A wiring layer 73 in which a multilayer wiring 72 is formed via an interlayer insulating film 71 is formed on the surface side of the silicon substrate 54 on which the pixel 60 including the photodiode 55 is formed.

  On the other hand, on the back surface side of the silicon substrate 54, a transparent electrode (for example, ITO film: indium and tin oxide) is formed through the insulating film 75 over almost the entire surface including the periphery where the peripheral circuit section 52 and the pad section 53 are formed. ) 76 is formed, and a metal film, for example, an AlSi film 77 to be a light shielding film (light shielding electrode) is formed on the transparent electrode 6676 except for a portion corresponding to the photodiode 55. A back electrode 78 having a two-layer structure is formed by the transparent electrode 76 and the AlSi film 77 serving as a light shielding film. Further, a protective passivation film 79 is formed on the back surface. A part of the passivation film 79 is selectively removed in the peripheral part on the back surface side of the silicon substrate 54, and a pad part (so-called bonding pad part) 53 in which the AlSi film 77 is exposed from the opening 80 of the passivation film 79 is formed. As described above, when the signal charge of the photodiode 55 is an electron, the pad portion 53 is given a required negative voltage.

  The purpose of the back surface electrode 78 is to apply a negative voltage to the back surface electrode of the pixel array portion 51 to suppress the generation of dark current at the interface on the back surface of the substrate when the signal charge of the photodiode is an electron. ) And shielding light from unnecessary portions. In the pixel array portion, the transparent electrode 76 exists on the entire surface, but the metal film 77 is formed in a lattice shape in which openings are formed only in the photoelectric conversion element (photodiode) 6755 portion. The light-shielding portion and the peripheral circuit of the pixel portion are covered with a back electrode including a metal film so that light does not enter.

  The pad portion 53 is a portion having a physical interface with the outside world, and a voltage is applied to the pad portion 53 by applying a needle of the inspection device to the pad portion 53 at the time of inspection, or wire bonding is performed to the pad portion at the time of mounting.

  The silicon substrate 54 is formed to have a required thickness by polishing, for example, by CMP (Chemical Mechanical Polishing). The thickness of the silicon substrate 54 is preferably about 5 μm to 10 μm for visible light. By setting the thickness, visible light can be favorably photoelectrically converted by the photodiode 55.

  The photodiode 55 has a low concentration n− region formed by the silicon substrate 54 as a photoelectric conversion region, and has a high concentration n region for accumulating the photoelectrically converted photocharges (electrons in this example). It is a buried diode (HAD: Hole Accumulated Diode) having a p + region (so-called p + accumulation layer) that accumulates carriers (holes in this example) at the silicon interface.

  The p-type well region 56 is supplied with a reference potential, for example, a ground (GND) potential, through the wiring 72, specifically, the p-well wiring 24 (see FIG. 2). The reset transistor 113, amplification transistor 114, and selection transistor 115 (see FIG. 2) of the pixel 60 are formed on the p-type well region 56.

  The insulating film 75 on the back surface of the substrate has, for example, a one-layer structure of a silicon oxide film (SiO 2). However, the insulating film 75 is not limited to a single layer structure of a silicon oxide film, and may be a multi-layer structure of a silicon oxide film and a silicon nitride film, for example. When this multi-layer structure is adopted, the antireflection effect by the silicon nitride film can be obtained by appropriately taking the thickness of each layer, and more incident light can be taken in, so that the sensitivity can be improved.

  The negative voltage applied to the light shielding film 77 and the transparent electrode 76 made of AlSi through the pad portion 53 can be set to about -3V, for example.

  As described above, the insulating film 75 is provided on the back surface of the silicon substrate 54, and a voltage having the same polarity as the signal charge of the photodiode 45, for example, a negative voltage of about −3 V, is applied on the insulating film 5575. It is equivalent if holes are induced at the silicon interface on the back side and a hole accumulation layer (so-called p + accumulation layer) exists at the silicon interface. At this time, since the silicon substrate 54 and the transparent electrode 76 are electrically insulated by the insulating film 75, basically no electric field is formed in the p-type well region 56 that is not depleted. As described above, due to the action of the silicon interface induced by the holes, generation of electrons from the silicon back surface side silicon interface, which is a dominant cause of dark current, is reduced.

  Since it is a back-illuminated type, the main circuit including the pixel array unit 51 is formed on the surface side of the silicon substrate 54. A back electrode 78 having a two-layer structure made of a transparent electrode 76 and an AlSi film 77 as a light shielding film is formed on the back side, and a schematic plan view thereof is shown in FIG. The portion corresponding to the photodiode of the pixel is such that light is transmitted through at least the opening 77a of the AlSi film 77 as the light shielding film in the back surface electrode 78, and the other portions are also covered for light shielding. However, an opening is not formed in the AlSi film 77 in a light-shielding pixel or the like for dark level detection. The pad portion 53 for applying a voltage to the AlSi film 77 is formed by hollowing out the passivation film 79 on the AlSi film 77 as described above. In the example of FIG. 7, the pad portion of the front-side wiring 72 is formed on the front side. As shown in FIG. 8, the pad portion 53 of the back electrode 78 is formed on the back surface side, and the front-side wiring pad portion 89 is led through the silicon substrate 54 to the back surface side. It can also be formed as described above.

  As described above, the back-illuminated CMOS image sensor 50 of FIG. 6 can make a structure equivalent to the hole accumulation layer at the silicon interface on the back surface side of the substrate. Can be reduced. In particular, there is no need for a step of ion implantation, increasing the concentration, or performing heat treatment for activation as in the prior art. For this reason, the manufacturing process is also very simple, and the distribution of the hole accumulation layer formed in the substrate depth direction is very shallow, so that the blue sensitivity can be maximized.

  The back-illuminated CMOS image sensor 50 according to the above-described fourth embodiment is a basic type, but even when the pad portion 53 is inspected by applying a needle of an inspection device or wire-bonded, the insulating film It is necessary to surely prevent leakage current from being generated due to short circuit between the back electrode (the transparent electrode 76 and the AlSi film 77 serving as a light shielding film) and the silicon substrate 54 due to breakage of 75.

  The back electrode 78 only applies voltage, and a steady current should not flow. However, if there is a possibility that a leak current flows, it is necessary to reliably prevent this. When the leakage current flows, the substrate voltage becomes unstable, and a problem that power is consumed even during standby occurs, resulting in a decrease in yield.

  The cause of this leakage current is that the thickness of the insulating film 75 on the back surface of the substrate is about 100 nm or less, so that an inspection needle is repeatedly applied to the pad portion 53, or depending on the manner of boarding, It is considered that the insulating film 75 is broken and the back electrode 78 and the silicon substrate 54 are electrically short-circuited. However, if the insulating film 75 is thickened, the voltage applied to the back electrode 78 must be increased.

  Next, an embodiment in which this point is improved and the leakage current at the pad portion can be prevented by suppressing the voltage applied to the back surface electrode 78 to a low level will be described.

[Fifth Embodiment]
FIG. 9 is a cross-sectional view showing the main part (the same part as the fourth embodiment) of the back-illuminated CMOS image sensor of the fifth embodiment according to the above improvement. In FIG. 9, parts corresponding to those in FIG. In the CMOS image sensor 81 of the present embodiment, a photodiode 55 serving as a photoelectric conversion element in the region of the pixel array portion 51 of the first conductivity type semiconductor substrate, for example, an n-type silicon substrate 54, and the substrate surface side are the same as described above. Of the plurality of MOS transistors (only the transfer transistor 57 is shown in the figure) are two-dimensionally arranged in a matrix form (multiple), and a multilayer wiring layer 73 is formed on the substrate surface. A back electrode 78 having a two-layer structure composed of a transparent electrode (for example, an ITO film) 76 and a metal film to be a light-shielding film, for example, an AlSi film 77, is formed thereon via an insulating film 75.

  In this embodiment, in particular, the transparent electrode 76 is formed only in the region of the pixel array portion 51, and an interlayer insulating film 91 is formed on the entire surface of the back side of the substrate including the transparent electrode 76. An AlSi film 77 serving as a light shielding film is formed on the film 91. The AlSi film 77 is formed in a lattice shape in the pixel array unit 51 except for the region corresponding to the photodiode 55. In the pixel array unit 51, the AlSi film 77 and the transparent electrode 76 are electrically connected through a plurality of contact parts 92 provided at a plurality of positions of the interlayer insulating film 91, preferably at four positions sandwiching the openings of the AlSi film. ing. Further, a passivation film 79 is formed on the entire surface including the pixel array portion 51 and the peripheral circuit portion 52 on the back surface of the substrate, and excluding the pad portion 53. Here, the interlayer insulating film 91 can be formed of, for example, a silicon oxide film, a silicon nitride film, or the like. The interlayer insulating film 91 immediately below the pad portion 53 becomes a leakage current blocking region. The film thickness t1 of the insulating film 75 is preferably as thin as possible as long as electrical insulation between the silicon substrate 54 and the transparent electrode 76 can be maintained, and can be set to 60 nm or less, for example. Further, the film thickness t2 of the interlayer insulating film 91 immediately below the pad part 53 should be such that even if a test needle is applied to the pad part 53, dielectric breakdown with the silicon substrate 54 is avoided and no leakage current is generated. That's fine. For example, the total thickness t3 of the AlSi film 77 of the pad portion 53, the insulating film 75 up to the silicon substrate 54, and the interlayer insulating film 91 can be, for example, 100 nm or more, preferably about 150 nm to 800 nm. The thick side of t3 is determined in such a range that the manufacturing process is easy and the oblique incident light can be easily collected. For example, t3 can be several hundred nm. Other configurations are the same as those in FIG.

  Next, a manufacturing method of the CMOS image sensor 81 according to the fifth embodiment shown in FIG. 9 will be described. Here, of the manufacturing process, the process of each film 75, 76, 77, 91, 79 on the back surface of the substrate related to the present embodiment is shown.

First, an insulating film 75 on the back side, for example, a silicon oxide film (SiO 2) is formed on the entire back surface of the silicon substrate 54 by a CVD method or a low temperature oxidation method.
Next, a transparent electrode 76 such as an ITO film is formed on the entire surface of the insulating film 75 by sputtering.
Next, the transparent electrode 76 is selectively removed by wet etching, leaving only the pixel array portion 51.
Next, annealing is performed to adjust the characteristics of the transparent electrode 76.
Next, an interlayer insulating film 91 is formed on the entire surface. For example, the interlayer insulating film 91 is formed by a CVD oxide film formed by low-pressure CVD using organosilane (TEOS).
Next, contact holes are formed in the interlayer insulating film 91 of the pixel array unit 51.
Next, a contact portion made of a conductor is embedded in the contact hole.
Next, a metal film to be a light shielding film, for example, an AlSi film 77 is formed on the entire surface by sputtering.
Next, the AlSi film 77 is selectively etched to form an opening in a portion corresponding to the photodiode 45 in the pixel array portion 55.
Next, a passivation film 79 such as a silicon nitride film (SiN) is formed on the entire surface.
Next, the passivation film 79 is selectively etched to form an opening 79 a in a portion corresponding to the pad portion 53 to expose the AlSi film 77, thereby forming the pad portion 53.

  As for contact embedding, for example, as shown in FIG. 10, a method of embedding a normal tungsten (W) layer 94 in the contact hole 91 a of the interlayer insulating film 91 can be used. In this case, it is preferable to insert a Ti / TiN film 95 as a barrier metal between the tungsten layer 94, the transparent electrode 76, the AlSi layer 77, and the interlayer insulating film 91 in order to reduce adhesion and contact resistance. When the aspect ratio of the contact hole 91a is small, it is preferable to omit the contact embedding step and form the AlSi film 77 directly embedded in the contact hole 91a by sputtering as shown in FIG. In this case as well, it is preferable to sandwich a Ti / TiN film 95 serving as a barrier metal in order to reduce adhesion and contact resistance.

  The transparent electrode (for example, ITO film) 76 may be left almost on the entire surface as shown in FIG. 6 described above, but in this example, it is configured to remain only in the vicinity of the pixel array portion 51. When the transparent electrode 76 is almost on the entire surface, if a negative voltage is applied to the transparent electrode 76, a parasitic MOS transistor works in a portion other than the pixel array unit 51, causing a leak between P wells having different potentials, for example. May cause malfunctions. By leaving the transparent electrode 76 on the side close to the Si substrate only in the pixel array portion 51 and the vicinity thereof, the peripheral circuit portion is shielded by the AlSi layer 77 from a distance of the Si substrate through the interlayer film 91, thereby the parasitic MOS transistor. Can be prevented. In this case, it is generally considered that a step of about several tens of nanometers is formed on the interlayer insulating film 91 at the boundary between the presence and absence of the transparent electrode 76 in the lower layer, which makes etching of the AlSi layer 77 difficult, but the step is small. In addition, since the etching of the AlSi film 77 is performed on the thick interlayer insulating film 91, it is possible to process with a large amount of overetching. Of course, a step of planarizing the interlayer insulating film 91 may be included.

  In FIG. 6 described above, there is no insulating film 75 on the outer periphery of the transparent electrode 76, but in the fifth embodiment of FIG. 9, the insulating film 75 is provided up to the outer periphery of the transparent electrode 76. In the fourth embodiment shown in FIG. 6, when the AlSi film 77 is etched, the peripheral insulating film 75 is also eliminated by overetching. However, in the fifth embodiment shown in FIG. The insulating film 75 is not etched up to the silicon substrate 54. Incidentally, the etching of the transparent electrode 76 enables selective etching with little etching of the insulating film 75 by wet etching.

  A color filter or an on-chip lens may be formed above the back electrode 78. In the fifth embodiment shown in FIG. 9, the opening of the AlSi film 77 is formed for each pixel, and the contact is formed for one pixel and one pixel of the pixel array unit 51. The whole 51 may be an opening of the AlSi film, and contact may be made around the pixel array unit 51.

  According to the fifth embodiment, since the insulating film 75 of the pixel array unit 51 can be formed thin, the back surface voltage can be applied to the back surface electrode 78 at a low voltage with respect to the pixels 55. That is, holes that can prevent dark current from being generated at the silicon interface on the back surface of the substrate can be induced at a low voltage. In addition, since the thick interlayer insulating film 91 exists under the pad portion 53, it can be protected from dielectric breakdown. Although not shown in FIG. 9, a circuit can be formed on the lower surface side of the pad portion 53.

[Sixth Embodiment]
In the fifth embodiment, the AlSi film 77 is formed at a position away from the silicon substrate 54. In this case, if the opening 77a is formed in the AlSi film 77 for each pixel, it is separated from the silicon substrate 54 by the thickness of the interlayer insulating film 91. Therefore, the oblique light is kicked at the opening 77a, which is disadvantageous for light collection. It becomes. Next, a sixth embodiment in which this point is improved will be described.

  FIG. 12 is a cross-sectional view showing the main part (the same part as the fourth embodiment) of a back-illuminated CMOS image sensor according to the sixth embodiment. In FIG. 12, parts corresponding to those in FIG. As described above, the CMOS image sensor 82 of the present embodiment includes a photodiode 55 serving as a photoelectric conversion element in the region of the pixel array portion 51 of the first conductivity type semiconductor substrate, for example, an n-type silicon substrate 54, and the substrate surface side. Of the plurality of MOS transistors (only the transfer transistor 57 is shown in the figure) are two-dimensionally arranged in a matrix form (multiple), and a multilayer wiring layer 73 is formed on the substrate surface. A back electrode 78 having a two-layer structure comprising a transparent electrode (for example, an ITO film) 75 and a metal film for forming a light shielding film, for example, an AlSi film 77, is formed thereon via an insulating film 75.

  In this embodiment, in particular, the transparent electrode 76 is formed over almost the entire back surface of the substrate, and the AlSi film 77 serving as a light-shielding film is formed only in the region corresponding to the pixel array unit 51 and directly on the transparent electrode 76. Overlapping to form. An opening 77 a for each pixel is formed in the AlSi film 77. Next, an interlayer insulating film 91 is formed on the entire surface, and an AlSi film 96 serving as a second light-shielding film is formed only in the peripheral circuit portion 52 and the pad portion 53 on the interlayer insulating film 91. The second-layer AlSi film 96 and the first-layer AlSi film 77 are connected around the pixel array section 51 via the contact section 97. The interlayer insulating film 91 is formed so as to be in contact with the back surface of the substrate at the outer periphery surrounding the insulating film 75 and the transparent electrode 76. Further, a passivation film 79 is formed on the entire surface, and the passivation film 79 is selectively etched to form an opening 79 a in a portion corresponding to the pad portion 53 to expose the AlSi film 96, thereby forming the pad portion 53. The interlayer insulating film 91 immediately below the pad portion 53 becomes a leakage current blocking region. Other configurations are the same as those in FIG.

  According to the sixth embodiment, in the pixel array section 51, the distance between the AlSi film 77 serving as a light shielding film and the silicon substrate 54 is smaller than in the case of FIG. In addition, as described with reference to FIG. 9, the back surface voltage applied to the back surface electrode 78 can be suppressed to a low level, the dielectric breakdown in the pad portion 53 can be prevented, and the occurrence of leakage current can be prevented.

[Seventh embodiment]
FIG. 13 is a cross-sectional view showing the main part (the same part as the fourth embodiment) of the back-illuminated CMO image sensor according to the seventh embodiment. In FIG. 13, parts corresponding to those in FIG. The back-illuminated CMOS image sensor 83 according to the present embodiment has a photodiode 55 serving as a photoelectric conversion element in the region of the pixel array portion 51 of the first conductivity type semiconductor substrate, for example, the n-type silicon substrate 54, as described above. And a plurality of MOS transistors on the substrate surface side (only the transfer transistor 57 is shown in the figure) are two-dimensionally arranged in a matrix form (multiple), and a multilayer wiring layer 73 is formed on the substrate surface. Then, a back-surface electrode 78 having a two-layer structure made of a transparent electrode (for example, an ITO film) 76 and a metal film to be a light-shielding film, for example, an AlSi film 77, is formed on the back surface of the substrate via an insulating film 75.

  In the present embodiment, the transparent electrode 76 is formed over substantially the entire back surface of the substrate, and the interlayer insulating film, that is, the interlayer insulating film serving as a cushion is limited to the position corresponding to the pad portion 53 on the transparent electrode 76. 91A is formed. A metal film, such as an AlSi film 77, which becomes a light shielding film is formed on almost the entire surface including the pixel array portion 51 and the peripheral circuit portion 52 so as to run on the interlayer insulating film 91A. Further, a passivation film 79 is formed on the entire surface, and the passivation film 79 is selectively etched to form an opening 79 a in a portion corresponding to the pad portion 53 to expose the AlSi film 77, thereby forming the pad portion 53. The interlayer insulating film 91A immediately below the pad portion 53 becomes a leakage current blocking region. The interlayer insulating film 91 </ b> A serving as a cushion may be formed between the transparent electrode 76 and the insulating film 75. However, since the interlayer insulating film 91A has a thickness of 100 nm or more as described above, it is preferable to provide the interlayer insulating film 91A on the transparent electrode 76 that serves as an etching stopper during selective etching of the interlayer insulating film 91A. Other configurations are the same as those in FIG.

  According to the seventh embodiment, since the interlayer insulating film 91A serving as a cushion is formed just below the pad portion 53, the distance between the pad portion 53 and the silicon substrate 54 is increased. On the other hand, in the pixel array unit 51, the AlSi film 77, which is a light shielding film, is formed directly on the transparent electrode 76, so that the light condensing on the photodiode 55 is advantageous. Accordingly, as in the sixth embodiment, the light collection efficiency to the photodiode is increased, the back surface voltage applied to the back surface electrode 78 is suppressed to a low level, and the dielectric breakdown in the pad portion 53 is prevented, and the leakage current is reduced. Generation can be prevented.

  Here, since a step of 100 nm or more is generated around the interlayer insulating film 91A serving as a cushion, an etching residue is likely to be generated in the stepped portion by selective etching of the AlSi film 77, but the interlayer insulating film 91A of the cushion is formed only on the pad portion 53. If they are formed, they will not be short-circuited with other wirings even if etching remains. Alternatively, if the AlSi film 77 covers the interlayer insulating film 91A, the etching residue at the step portion does not occur in the first place.

[Eighth Embodiment]
FIG. 14 is a cross-sectional view showing the main part (the same part as the fourth embodiment) of a back-illuminated CMOS image sensor according to the eighth embodiment. In FIG. 14, parts corresponding to those in FIG. In the CMOS image sensor 84 of the present embodiment, the back surface electrode 78 having a two-layer structure on the back surface of the substrate is configured in the same manner as in FIG. That is, a transparent electrode (for example, an ITO film) 66 and, for example, an AlSi film 77 to be a light shielding film are laminated on the back surface of the substrate via an insulating film 75, and an opening is formed in a portion corresponding to the photodiode 55 of the pixel array unit 51. The Then, a passivation film 79 is formed on the entire surface except for the pad portion 53.

  In the present embodiment, in particular, in the silicon substrate 54 immediately below the pad portion 53, a semiconductor well region 98 that is electrically floating or has the same potential as the back electrode 78 is formed so as to be in contact with at least the back surface of the silicon substrate 54. The semiconductor well region 98 is surrounded by a reverse conductivity type semiconductor region which is reverse-biased with respect to the potential of the back electrode 78. In the figure, the semiconductor well region 98 is formed of an n-type silicon substrate 54 and a p-type well region having a reverse conductivity type. The p-type well region 98 is formed from the back surface to the front surface of the silicon substrate 54. However, the p-type well region 98 may be formed from the back surface to the middle of the substrate thickness direction without reaching the substrate surface. The semiconductor well region 98 becomes a leakage current blocking region. Other configurations are the same as those in FIG.

  In the eighth embodiment, a power supply voltage is applied to the n-type silicon substrate 54, and a negative voltage is applied to the back electrode 78. Accordingly, even if the insulating film 75 under the pad portion 53 is broken and the pad portion 53 and the p-type well region 98 are short-circuited, a negative voltage of the back surface voltage is applied to the p-type well region 98. The pn junction formed by the region 98 and the n-type silicon substrate 54 is reverse-biased, and almost no leakage current flows. Essentially, even if the insulating film 75 is destroyed, the region on the silicon substrate 54 side that is short-circuited to the pad portion 53 is reverse-biased with the surroundings to prevent leakage current. The substrate conductivity type or semiconductor well structure may be used.

  According to the eighth embodiment, the semiconductor well region 98 that is electrically floating or reverse-biased is provided in the silicon substrate 54 immediately below the pad portion 53, thereby preventing leakage current even if the insulating film 75 is broken. be able to. At the same time, since the thickness of the insulating film 75 can be reduced, the voltage applied to the back electrode 78 can be reduced.

  According to the fifth to eighth embodiments described above, in the back-illuminated CMOS image sensor, it is possible to prevent the dielectric breakdown in the pad portion while keeping the voltage applied to the back electrode at a low level, or Leakage current can be prevented even if dielectric breakdown occurs.

  In the above example, the back electrode 78 has a two-layer structure of the transparent electrode 76 and the light-shielding film (light-shielding electrode) 77 on almost the entire back surface of the silicon substrate 54. The structure of can be applied. For example, in the case where the peripheral circuit portion 52 is entirely formed of a digital circuit and does not require light shielding, the light shielding film 77 may be formed only in the pixel array portion 51.

  In each of the above-described embodiments, an n-type substrate is used as the semiconductor substrate. However, a p-type substrate may be used. In this case, as a matter of course, in each embodiment, the polarity of n-type and p, electrons and holes, and voltage can be reversed.

  The solid-state imaging device according to the present invention can be used as an imaging device for an imaging device such as a video camera or a digital still camera, and can also be used as an imaging device for a portable device such as a mobile phone with a camera.

  10..CMOS image sensor, 11..pixel, 12..pixel array section, 13..vertical drive circuit, 14..column signal processing circuit, 15..horizontal drive circuit, 16..horizontal signal line, 17 .. -Output circuit, 18-Control circuit, 19-Vertical signal line, 21-Transfer line, 22-Reset line, 23-Selection line, 31-Silicon substrate, 32-n-type region, 33 ..Photodiode, 35..p + layer, 36, 43, 43 '.. p well region, 37..wiring layer, 39..insulating film, 40..transparent electrode, 41..voltage source, 42 .. High resistance substrate, 50, 81, 82, 83, 84... CMOS image sensor, 51... Pixel array part, 52 .. Peripheral circuit part, 53 .. Pad part, 54 .. Semiconductor substrate, 55. , 56... P-type semiconductor well region, 7 ..Transfer transistor, 60 ..pixel, 65 ..n-type semiconductor well region, Trn ..n channel MOS transistor, Trp ..p channel MOS transistor, 73 ..wiring layer, 75 ..insulating film, 76. .. Transparent electrode, 77 .. Light shielding film (metal film), 78.. Back electrode, 79 .. Passivation film, 91, 91 A.. Interlayer insulating film, 92, 97. ..P-type semiconductor well region

A solid-state imaging device according to the present invention has a wiring layer on a first surface (substrate surface) side of a semiconductor substrate on which pixels including photoelectric conversion elements are formed, and a second surface (substrate back surface) opposite to the wiring layer. ) the solid-state imaging device in which light is incident from the side, the photoelectric conversion region of the first conductivity type formed in the semiconductor substrate, the periphery of the photoelectric conversion region, the second surface from the first surface side of the semiconductor substrate Formed at the interface of the second conductivity type semiconductor well region formed so as to reach the surface, the insulating film formed on the second surface of the semiconductor substrate, and the insulating film on the second surface side in the semiconductor substrate. The hole accumulation layer is formed by applying a negative voltage to the insulating film.

The solid-state imaging device of the present invention has a wiring layer on the first surface side of the semiconductor substrate which pixels including photoelectric conversion elements are formed, the solid-state imaging device captures incident light from the second surface side opposite to the wiring layer And applying a voltage having the same polarity as the signal charge of the photoelectric conversion element to the insulating film formed on the second surface of the semiconductor substrate, and applying a charge opposite in polarity to the signal charge to the second of the semiconductor substrate. Voltage applying means for inducing on the surface side .

The driving method of the solid-state imaging device according to the present invention has a wiring layer on the first surface side of the semiconductor substrate on which pixels including photoelectric conversion elements are formed, and light is incident from the second surface side opposite to the wiring layer. A method for driving a solid-state imaging device, wherein a negative voltage is applied to an insulating film formed on the second surface of the semiconductor substrate, thereby interfacing with the insulating film on the second surface side in the semiconductor substrate A hole accumulation layer is formed on the substrate .

In the solid-state imaging device according to the present invention, a pixel including a photoelectric conversion element is formed on a semiconductor substrate, light is incident from the back side of the semiconductor substrate, an insulating film is formed on the back side, and at least a pixel array unit Then, a back surface electrode is formed through the insulating film, and a negative voltage is applied to the insulating film by the back surface electrode to form a hole accumulation layer at the interface with the insulating film on the back surface side in the semiconductor substrate. A leakage current blocking region for blocking leakage current between the pad portion and the semiconductor substrate is provided immediately below the pad portion.

Claims (18)

A solid-state imaging device having a wiring layer on a first surface side of a semiconductor substrate on which a pixel including a photoelectric conversion element is formed and taking incident light from a second surface side opposite to the wiring layer,
An insulating film formed on the second surface of the semiconductor substrate;
A solid-state imaging device comprising: voltage applying means for applying a voltage having a polarity opposite to the potential of the semiconductor substrate to the insulating film. A solid-state imaging device having a wiring layer on a first surface side of a semiconductor substrate on which a pixel including a photoelectric conversion element is formed and taking incident light from a second surface side opposite to the wiring layer,
An insulating film formed on the second surface of the semiconductor substrate;
Voltage applying means for applying a voltage having the same polarity as the signal charge of the photoelectric conversion element to the insulating film and inducing a charge having a polarity opposite to that of the signal charge to the second surface side of the semiconductor substrate. Solid-state imaging device. The voltage applying means includes an electrode formed on the insulating film and capable of taking incident light into the semiconductor substrate, and a voltage source for applying the voltage to the electrode. The solid-state imaging device described. The solid-state imaging device according to claim 3, wherein the electrode is a transparent electrode. The semiconductor substrate is a silicon substrate;
The solid-state imaging device according to claim 1, wherein the insulating film has a one-layer structure of a silicon oxide film or a two-layer structure of a silicon oxide film and a silicon nitride film. The solid-state imaging device according to claim 1, wherein the pixel has a well region to which a reference potential is applied through the wiring layer. The solid state imaging device according to claim 6, wherein the well region reaches a second surface of the semiconductor substrate. The solid-state imaging device according to claim 6, wherein the well region does not reach the second surface of the semiconductor substrate, and the opening on the second surface side is larger than the opening on the first surface side. The solid-state imaging device according to claim 1, wherein the photoelectric conversion element is a buried diode having a layer that accumulates carriers at a semiconductor interface on the wiring layer side. The photoelectric conversion element includes a photoelectric conversion region provided to reach the second surface of the semiconductor substrate, and a region for accumulating photoelectric charges provided by being bonded to the photoelectric conversion region and the layer for accumulating the carriers. The solid-state imaging device according to claim 9. 11. The solid according to claim 1, wherein the voltage applying unit is a layer of a material formed on the insulating film and having a work function difference that applies the voltage to the insulating film. Imaging device. The solid-state imaging device according to claim 11, wherein the substance is a semiconductor having a conductivity type different from that of the semiconductor substrate. A driving method of a solid-state imaging device having a wiring layer on a first surface side of a semiconductor substrate on which pixels including photoelectric conversion elements are formed and taking incident light from a second surface side opposite to the wiring layer,
A method for driving a solid-state imaging device, wherein a voltage having a polarity opposite to the potential of the semiconductor substrate is applied to an insulating film formed on the second surface of the semiconductor substrate. A pixel including a photoelectric conversion element is formed on a semiconductor substrate,
Incident light is taken from the back side of the semiconductor substrate,
An insulating film is formed on the back surface;
At least in the pixel array portion, a back electrode is formed through the insulating film,
A solid-state imaging device, wherein a leakage current blocking region for blocking a leakage current between the pad portion and the semiconductor substrate is provided immediately below the pad portion of the back electrode. The back electrode has a two-layer structure separated by an interlayer insulating film,
The two-layer structure is connected at a contact portion;
The solid-state imaging device according to claim 14, wherein the leakage current blocking region is formed by the interlayer insulating film immediately below the pad portion of the back electrode. The back electrode has a two-layer structure;
An interlayer insulating film is interposed in the two-layer structure corresponding to the pad portion of the back electrode,
The solid-state imaging device according to claim 14, wherein the leakage current blocking region is formed by the interlayer insulating film. A floating or semiconductor well region having the same potential as the back electrode is formed in contact with at least the back surface of the semiconductor substrate immediately below the pad portion,
The semiconductor well region is surrounded by a semiconductor region having a conductivity type opposite to that of the semiconductor well region which is reversely biased with respect to the potential of the back electrode, and the leakage current blocking region is formed by the semiconductor well region. The solid-state imaging device according to claim 14, characterized in that: The solid-state imaging device according to claim 15, wherein a layer closer to the Si substrate in the two-layer structure is formed only in the vicinity of the pixel array unit.

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