JP2012204488A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of lengthening a service life of a peripheral circuit element and preventing a crystal defect caused by heat treatment of a post step or the like from occurring in an element isolation groove part of a peripheral circuit region.SOLUTION: A manufacturing method of a semiconductor device of an embodiment for forming a plurality of memory cells in a first region of a semiconductor substrate and a peripheral circuit element in a second region on the semiconductor substrate comprises a step of forming a plurality of first element isolation grooves having a first opening width in the first region and a second element isolation groove having a second opening width sider than the first opening width in the second region, respectively. This manufacturing method further includes a step of collectively forming an oxide film of a first film thickness on an inner surface of the first element isolation groove and an oxide film of a second film thickness thicker than the first film thickness on an inner surface of the second element isolation groove via plasma oxidation.

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  In a nonvolatile semiconductor memory device such as a flash memory device, a plurality of memory cells are arranged in a word line direction and a bit line direction. In order to increase the integration of such a semiconductor memory device and improve the writing speed, it is necessary to reduce the thickness of the tunnel insulating film (gate insulating film) of the memory cell. However, since a high voltage is applied to the peripheral circuit element disposed in the peripheral circuit region, when the tunnel insulating film is thinned, a high electric field concentration is generated at the end (corner) of the tunnel insulating film of the peripheral circuit element. Occurs, causing deterioration of the withstand voltage and deteriorating the life of peripheral circuit elements.

  As the semiconductor memory device is highly integrated, it is necessary to increase the aspect ratio of the element isolation groove in order to suppress interference between memory cells. However, since the width dimension of the element isolation groove in the peripheral circuit region is wider than the width dimension of the element isolation groove in the memory cell area, the volume of the embedding material that fills the element isolation groove in the peripheral circuit area, such as a coating type insulating film, is large. Become more. This coating type insulating film shrinks by heat treatment or the like in a later process, and shrinkage increases in proportion to its volume. Due to the shrinkage of the coating type insulating film, crystal defects may occur in the element isolation trench portion in the peripheral circuit region.

JP 2008-177277 A International Publication Number WO2008 / 123431A1

  Accordingly, a method of manufacturing a semiconductor device is provided in which the lifetime of a peripheral circuit element can be extended, and crystal defects can be prevented from occurring in the element isolation trench portion in the peripheral circuit region due to heat treatment or the like in a subsequent process.

  The method for manufacturing a semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device in which a plurality of memory cells are formed in a first region on a semiconductor substrate, and peripheral circuit elements are formed in a second region on the semiconductor substrate. There is a step of sequentially forming an insulating film and a conductive layer on the semiconductor substrate. A plurality of first element isolation trenches having a first opening width in the first region of the semiconductor substrate on which the insulating film and the conductive layer are formed; and the semiconductor on which the insulating film and the conductive layer are formed. Forming a second element isolation trench having a second opening width wider than the first opening width in the second region of the substrate. Furthermore, an oxide film having a first film thickness is formed on the inner surface of the first element isolation groove, and an oxide film having a second film thickness larger than the first film thickness is formed on the inner surface of the second element isolation groove. And a step of collectively forming by plasma oxidation, and a step of embedding a coating type insulating film in the first element isolation groove and the second element isolation groove in which the oxide film is formed on the inner surface.

1 is an equivalent circuit diagram showing a part of a memory cell array of a NAND flash memory device according to a first embodiment; (A) is a schematic plan view showing a partial layout pattern of the memory cell region, (b) is a schematic plan view showing a partial layout pattern of the peripheral circuit region. Typical sectional drawing shown along the BB line in Fig.2 (a) Typical sectional drawing shown along the AA line in Fig.2 (a) Typical sectional drawing shown along CC line in FIG.2 (b) (A) is sectional drawing (the 1) shown along the BB line in FIG. 2 (a) in the middle of manufacture, (b) is along the CC line in FIG. 2 (b) in the middle of manufacture. Sectional view (Part 1) (A) is sectional drawing (the 2) shown along the BB line in FIG. 2 (a) in the middle of manufacture, (b) is along the CC line in FIG. 2 (b) in the middle of manufacture. Sectional view (Part 2) (A) is sectional drawing (the 3) shown along the BB line in FIG. 2 (a) in the middle of manufacture, (b) is along the CC line in FIG. 2 (b) in the middle of manufacture. Sectional view (Part 3) (A) is sectional drawing (the 4) shown along the BB line in FIG. 2 (a) in the middle of manufacture, (b) is along the CC line in FIG. 2 (b) in the middle of manufacture. Sectional view (Part 4) Characteristic diagram showing the relationship between the thickness of the silicon oxide film and the width of the isolation trench FIG. 7B is a view corresponding to a state in which a bird's beak is introduced into the gate insulating film. Characteristic diagram showing the relationship between the thickness of the gate insulating film and the width of the isolation trench The figure which shows a mode that a bird's beak is introduced into the gate insulating film of a peripheral circuit area and a memory cell area FIG. 7B equivalent view showing a state in which the silicon oxide film is formed in a tapered shape. Characteristic diagram showing the relationship between oxidizing species and processing pressure in plasma oxidation Characteristic diagram showing the relationship between the thickness of the silicon oxide film and the height position in the vertical direction

  Hereinafter, embodiments will be described with reference to the drawings. In the embodiment, substantially the same components are denoted by the same reference numerals, and description thereof is omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

(First embodiment)
First, FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region (first region) of the NAND flash memory device of the first embodiment. As shown in FIG. 1, the memory cell array of the NAND flash memory device includes two select gate transistors Trs1 and Trs2, and a plurality of (for example, 32) connected in series between the select gate transistors Trs1 and Trs2. ) Memory cell transistors Trm are formed in a matrix. In the NAND cell unit SU, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions.

  The memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line WL. Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  FIG. 2A is a plan view showing a layout pattern of a part of the memory cell region. A plurality of STIs (shallow trench isolation) 2 as element isolation regions extending along the Y direction in FIG. 2 are formed at a predetermined interval in the X direction in FIG. 2 on a silicon substrate 1 as a semiconductor substrate. Thus, the active regions 3 extending along the Y direction in FIG. 2 are separately formed in the X direction in FIG. The width dimensions of the STI 2 and the active region 3 are both about 20 nm to 30 nm, for example. The word lines WL of the memory cell transistors are formed so as to extend along a direction (X direction in FIG. 2) orthogonal to the active region 3, and a plurality of word lines WL are formed at predetermined intervals in the Y direction in FIG.

  Further, the selection gate line SGL1 of the pair of selection gate transistors is formed so as to extend along the X direction in FIG. Bit line contacts CB are formed in the active region 3 between the pair of select gate lines SGL1. A gate electrode MG of the memory cell transistor is formed on the active region 3 intersecting with the word line WL, and a gate electrode SG of the selection gate transistor is formed on the active region 3 intersecting with the selection gate line SGL1.

  Further, in FIG. 2B showing the peripheral circuit region (second region), an STI 22 as an element isolation region is formed on the silicon substrate 1 in the same manner as the memory cell region, and this STI 22 serves as an element formation region. The active regions 23 are formed separately. A gate electrode PG (peripheral gate electrode) is formed in a direction orthogonal to the active region 23. The element isolation groove (second element isolation groove) of the STI 22 in the peripheral circuit region is the opening width (the opening width in the X direction in FIG. 2, the first element isolation groove) of the STI 2 in the memory cell region. 1 (opening width of 1), and an opening width (second opening width) larger. Peripheral circuit transistors (peripheral circuit elements) are formed at the intersections of the gate electrode PG and the active region 23. Such transistors are also formed in other parts of the peripheral circuit region, and are formed as various transistors for driving the transistors in the memory cell region, such as high breakdown voltage transistors and low breakdown voltage transistors.

  Next, the gate electrode structure in the memory cell region of the present embodiment will be described with reference to FIGS. FIG. 3 is a diagram schematically showing a cross section taken along the line BB (word line direction, X direction) in FIG. 2A, and FIG. 4 is an AA line in FIG. It is a figure which shows typically the cross section which follows (bit line direction, Y direction).

  As shown in FIGS. 3 and 4, a plurality of element isolation grooves (first element isolation grooves) 4 are formed on the p-type silicon substrate 1 so as to be spaced apart from each other in the X direction. These element isolation trenches 4 isolate the active region 3 in the X direction in FIG. An element isolation insulating film 5 is formed in the element isolation trench 4 and constitutes an element isolation region (STI) 2. The element isolation insulating film 5 includes a silicon oxide film 24 formed on the inner surface of the element isolation groove 4 and a coating type insulating film 25 formed on the silicon oxide film 24.

  The memory cell transistor includes an n-type diffusion layer 6 formed on the silicon substrate 1, a gate insulating film 7 formed on the silicon substrate 1, and a gate electrode MG provided on the gate insulating film 7. Composed. The gate electrode MG includes a floating gate electrode FG serving as a charge storage layer (conductive layer), an interelectrode insulating film 9 formed on the floating gate electrode FG, and a control gate electrode CG formed on the interelectrode insulating film 9. And have. The diffusion layer 6 is formed on both sides of the gate electrode MG of the memory cell transistor in the surface layer of the silicon substrate 1 and constitutes a source / drain region of the memory cell transistor.

  The gate insulating film 7 is formed on the silicon substrate 1 (active region 3). As the gate insulating film 7, for example, a silicon oxide film is used. As the floating gate electrode FG, a polycrystalline silicon layer (conductive layer) 8 doped with an impurity such as phosphorus is used. The inter-electrode insulating film 9 is formed along the upper surface of the element isolation insulating film 5, the upper side surface of the floating gate electrode FG, and the upper surface of the floating gate electrode FG, and includes an interpoly insulating film, a conductive interlayer insulating film, an electrode It functions as an insulating film. As the interelectrode insulating film 9, for example, a film having a laminated structure of silicon oxide film / silicon nitride film / silicon oxide film (each film thickness is 3 nm to 10 nm, for example), that is, a so-called ONO film is used. Yes.

  The control gate electrode CG is composed of the conductive layer 10 that functions as the word line WL of the memory cell transistor. The conductive layer 10 is made of, for example, a polycrystalline silicon layer doped with an impurity such as phosphorus, and any one of tungsten (W), cobalt (Co), nickel (Ni), etc. formed immediately above the polycrystalline silicon layer. It has a stacked structure with a silicide layer silicided with metal. Note that all of the conductive layer 10 may be formed of a silicide layer (that is, a silicide layer alone).

  As shown in FIG. 4, the gate electrodes MG of the memory cell transistors are arranged in parallel in the Y direction, and the gate electrodes MG are electrically separated from each other by the electrode separation grooves 11. An insulating film 12 between memory cells is formed in the groove 11. As the insulating film 12 between the memory cells, for example, a silicon oxide film or a low dielectric constant insulating film using TEOS (tetraethyl orthosilicate) is used.

  A liner insulating film 13 made of, for example, a silicon nitride film is formed on the upper surface of the inter-memory cell insulating film 12, the side surfaces and the upper surface of the control gate electrode CG. On the liner insulating film 13, an interlayer insulating film 14 made of, for example, a silicon oxide film is formed. The liner insulating film 13 has a function of preventing the oxidant from reaching the control gate electrode CG when forming the interlayer insulating film 14 made of a silicon oxide film, and in particular, preventing the resistance of the word line WL from being increased due to oxidation of the silicide layer. . Further, since the liner insulating film 13 is not completely embedded between the control gate electrodes CG, it is possible to reduce the influence of wiring delay due to an increase in parasitic capacitance.

  In FIG. 5 showing the gate electrode structure in the peripheral circuit region, STIs (element isolation regions) 22 are formed at predetermined intervals on the silicon substrate 1, and active regions (element formation regions) 23 are formed by the STIs 22. Are separated. FIG. 5 is a diagram schematically showing a cross section taken along line CC (word line direction, X direction) in FIG. The STI 22 includes an element isolation groove (second element isolation groove) 26 having an opening width (second opening width) larger than the opening width (first opening width) of the element isolation groove 4 of the STI 2 in the memory cell region. And an element isolation insulating film 27 formed in the element isolation trench 26.

  The element isolation insulating film 27 includes a silicon oxide film 28 formed on the inner surface of the element isolation groove 26 and a coating type insulating film 29 formed on the silicon oxide film 28. The film thickness (second film thickness) of the silicon oxide film 28 formed on the inner surface of the element isolation groove 26 in the peripheral circuit region is the same as that of the silicon oxide film 24 formed on the inner surface of the element isolation groove 4 in the memory cell region. It is thicker than the film thickness (first film thickness).

  On the active region 23, for example, a gate insulating film 30 for a high voltage transistor having a thicker end than the gate insulating film 7 of the memory cell transistor is formed (see FIG. 11). A structure in which the thickness of the end portion of the gate insulating film 30 is thick will be described later. As the gate insulating film 30, for example, a silicon oxide film is used. On the gate insulating film 30, as in the memory cell transistor, the floating gate electrode FG (polycrystalline silicon layer 8) constituting the gate electrode PG, the interelectrode insulating film 9, and the control gate electrode CG (conductive layer) 10) are laminated. A through hole (not shown) is formed in the interelectrode insulating film 9, and the polycrystalline silicon layer 8 and the conductive layer 10 are electrically connected. Further, a liner insulating film 13 and an interlayer insulating film 14 are formed on the control gate electrode CG.

  Next, an example of a method for manufacturing the NAND flash memory device according to the present embodiment will be described with reference to process cross-sectional views shown in FIGS. FIGS. 6A to 9A schematically show a manufacturing stage of a cross-sectional structure (memory cell region) corresponding to FIG. 3, and FIGS. 6B to 9B are shown in FIG. A manufacturing stage of a corresponding cross-sectional structure (peripheral circuit region) is schematically shown.

  First, as shown in FIG. 6, gate insulating films 7 and 30 are formed on the surface of a p-type silicon substrate 1 (or a silicon substrate having a p-type well formed on the surface layer) by a known method, for example, about 1 nm to 15 nm. . Thereafter, for example, a doped polycrystalline silicon layer 8 to be the floating gate electrode FG is formed by a chemical vapor deposition method with a thickness of about 10 nm to 200 nm. For example, phosphorus (P) is used as the impurity of the doped polycrystalline silicon layer 8.

  Next, a silicon nitride film 15 is formed to a thickness of about 50 nm to 200 nm on the doped polycrystalline silicon layer 8 by chemical vapor deposition. Subsequently, a silicon oxide film 16 is formed on the silicon nitride film 15 by 50 nm by chemical vapor deposition. To about 400 nm. Thereafter, a photoresist (not shown) is applied on the silicon oxide film 16, and the photoresist is patterned by exposure and development. Next, the silicon oxide film 16 is etched by the RIE method using the resist as a mask.

  After the etching, the photoresist is removed. Then, the silicon nitride film 15 is etched using the silicon oxide film 16 as a mask, and then the doped polycrystalline silicon layer 8 (floating gate electrode FG), the gate insulating films 7 and 30 and the silicon substrate 1 are etched, whereby the element Separation grooves 4 and 26 are formed (see FIG. 6).

  Next, as shown in FIG. 7, the inner surfaces of the element isolation grooves 4 and 26, that is, the upper surface (bottom surface) and side surfaces of the silicon substrate 1, the side surfaces of the gate insulating films 7 and 30, and the side surfaces of the polycrystalline silicon layer 8 are sparse. Oxidation is performed by an oxidation process (described later in detail) to form silicon oxide films 24 and 28 at once. Thereby, etching processing damage can be repaired. At this time, the silicon oxide film 28 on the inner surface of the element isolation trench 26 in the peripheral circuit region can be formed thicker than the silicon oxide film 24 on the inner surface of the element isolation trench 4 in the memory cell region. Further, the thickness of the end portion of the gate insulating film 30 of the peripheral circuit transistor (high voltage transistor) can be made larger than the thickness of the end portion of the gate insulating film 7 of the memory cell transistor (FIGS. 11 and 13). reference). The structure of the silicon oxide film 28 and the gate insulating film 30 in the peripheral circuit region will be described in detail later.

  Thereafter, as shown in FIG. 8, coating-type insulating films (silicon oxide films) 25 and 29 are formed to a thickness of, for example, about 200 nm to 1500 nm using a coating technique, thereby filling the element isolation grooves 4 and 26. Subsequently, the coating type insulating films 25 and 29 are densified by performing heat treatment in an oxygen atmosphere or a water vapor atmosphere. Next, planarization is performed using chemical mechanical polishing (CMP) until the silicon nitride film 15 is exposed.

  Next, only the element isolation insulating films 5 and 27 (the silicon oxide films 24 and 28 and the coating type insulating films 25 and 29) are etched back using the RIE method under etching conditions having a selection ratio with the silicon nitride film 15. By selective etching of the element isolation insulating films 5 and 27, the element isolation insulating films 5 and 27 between the floating gate electrodes FG (polycrystalline silicon layer 8) are dropped. Thereafter, the silicon nitride film 15 remaining on the polycrystalline silicon layer 8 is selectively removed by wet etching, for example.

  Next, as shown in FIG. 9, an interelectrode insulating film 9 is formed on the exposed surfaces of the polycrystalline silicon layer 8 and the element isolation insulating films 5 and 27. As the interelectrode insulating film 9, a film having a laminated structure of silicon oxide film / silicon nitride film / silicon oxide film is formed by a known process. As the interelectrode insulating film 9, a single high dielectric constant insulating film, a silicon oxide film / high dielectric constant insulating film / silicon oxide film laminated structure, or silicon nitride film / silicon oxide film / silicon nitride film / A film having a laminated structure of a silicon oxide film / silicon nitride film or the like may be formed.

  Thereafter, a doped polycrystalline silicon layer to be the conductive layer 10 (control gate electrode CG) is formed on the interelectrode insulating film 9 by a chemical vapor deposition method, for example, about 100 nm. As an impurity of the doped polycrystalline silicon layer, for example, phosphorus (P) is used. A through hole (not shown) is formed in the interelectrode insulating film 9 in the peripheral circuit region, and the polycrystalline silicon layer 8 and the doped polycrystalline silicon layer are electrically connected.

  Thereafter, an electrode separating groove 11 (see FIG. 4) is formed by a known process to obtain a plurality of gate electrode structures. The width dimension of the gate electrodes (floating gate electrode FG and control gate electrode CG) and the distance dimension between the gate electrodes are both about 50 nm, for example. Further, a gate sidewall film (not shown) having a thickness of about 10 nm may be formed by a thermal oxidation method and a CVD method. Next, the surface of the silicon substrate 1 at the inner bottom portion of the groove 11 is doped with an impurity by using an ion implantation method to form a diffusion layer 6. Subsequently, an inter-memory cell insulating film 12 is formed in the trench 11 as an inter-cell gate insulating film, and then planarized and dropped. Next, after forming, for example, a nickel silicide (NiSi) layer on the polycrystalline silicon layer (conductive layer 10), a liner insulating film 13 and an interlayer insulating film 14 are formed as shown in FIG. Further, wiring or the like (not shown) is formed using a known technique.

  In each memory cell of the NAND flash memory device manufactured as described above, an electric field according to the coupling ratio is generated by applying a high voltage between the silicon substrate 1 and the control gate electrode CG. Applied to the gate insulating film 7), a tunnel current flows through the tunnel insulating film. As a result, the amount of charge accumulated in the floating gate electrode FG changes, the threshold value of the memory cell changes, and data writing or erasing operation is performed.

  Next, the dense oxidation process after the element isolation grooves 4 and 26 are formed will be described in detail. By performing this density oxidation step, the processing damage of the element isolation trenches 4 and 26 can be repaired, and the gate insulating film 30 in the memory cell region is added to the gate insulating film 30 in the peripheral circuit region under the oxidation conditions described later. Birds beaks larger than 7 (see FIG. 11 and FIG. 13B) can be introduced (formed). Furthermore, by performing the above-described sparse and dense oxidation step, a thick silicon oxide film 28 can be formed on the inner surface of the element isolation trench 26 in the peripheral circuit region that is a sparse pattern region. As a result, the filling volume of the coating type insulating film 29, which is a filling material of the element isolation trench 26, can be reduced, so that generation of crystal defects in the peripheral circuit region can be suppressed.

  As oxidation conditions in the dense oxidation step of the present embodiment, a thin silicon oxide film 24 is formed on the inner surface of an opening (space) in which the width of the element isolation trench 4 in the memory cell region is narrow, and the periphery A condition is selected such that a thick silicon oxide film 28 is formed on the inner surface of an opening (space) where the width of the element isolation trench 26 in the circuit region is wide.

  Specifically, plasma oxidation is used in the dense oxidation step of the present embodiment, and the oxidation conditions of this plasma oxidation include a rare gas such as argon gas and oxygen gas, and the flow rate ratio of oxygen gas is about 20% or less. The processing pressure (chamber internal pressure) was set to a low pressure, for example, about 300 Pa or less. By performing sparse / dense oxidation using microwave-excited plasma generated under this oxidation condition, the film thickness difference between the silicon oxide films 24 and 28 is effectively increased between the sparse and dense regions of the pattern, and It became desirable as a high oxidation rate condition from the viewpoint of productivity. The oxidation conditions for plasma oxidation are not limited to the above example, and it is even more preferable that the oxygen flow rate ratio is, for example, about 0.5 to 10%, and the processing pressure is, for example, about 1.3 to 133 Pa. Preferred oxidation conditions.

  Here, when the width dimension (space width dimension) of the element isolation grooves 4 and 26 is changed, the oxide film thickness formed on the inner surfaces (STI side walls) of the element isolation grooves 4 and 26 by the above-described dense oxidation process is measured. The results are shown in FIG. The horizontal axis in FIG. 10 is the width dimension (space width dimension) of the element isolation grooves 4 and 26. The vertical axis represents the film thickness (STI sidewall oxide film thickness) of the silicon oxide film 28 when the film thickness of the silicon oxide film 24 formed on the inner surface of the element isolation trench 4 in the memory cell region is standardized as 1. FIG. 10 shows that the oxide film thickness increases as the space width dimension increases.

  Further, when the above-described dense oxidation step is executed, the end portions of the gate insulating films (tunnel insulating films) 7 and 30 increase as the thickness of the silicon oxide films 24 and 28 formed on the inner surfaces of the element isolation grooves 4 and 26 increases. It has been found that the size of the bird's beak introduced into increases. For this reason, as shown in FIGS. 11 and 13B, the bird's beak is further increased in the peripheral circuit region where the space width of the element isolation trench 26 is wide.

  Here, when the width dimension (space width dimension) of the element isolation grooves 4 and 26 is changed, for example, the result of measuring the film thickness of the end portions of the gate insulating films 7 and 30 is used as an index of the bird's beak size. As shown in FIG. The horizontal axis in FIG. 12 is the width dimension (space width dimension) of the element isolation grooves 4 and 26. The vertical axis in FIG. 12 represents the film thickness of the end portion of the gate insulating film in the peripheral circuit region when the thickness of the end portion of the gate insulating film 7 in the memory cell region is standardized as 1. From FIG. 12, it can be seen that as the space width dimension increases, the film thickness at the end of the gate insulating film increases, and further, the bird's beak size unique to the space width dimension can be obtained.

  Then, from FIG. 12, the bird's beak is selectively and actively applied in the peripheral circuit region where the pattern (element isolation groove 26) is sparse compared with the memory cell region where the pattern (element isolation groove 4) is dense. It can be seen that it can be introduced. This result is schematically shown in FIG. FIG. 13 (a) schematically shows a state before the sparse oxidation process.

  In this case, as indicated by a dot-dash line circle in FIG. 13A, when the upper end of the silicon substrate 1 is angular, high electric field concentration occurs and the breakdown voltage is degraded. Therefore, it is preferable to introduce a large bird's beak in the peripheral circuit region to which a higher voltage is applied, and to introduce a minute bird's beak in the memory cell region.

  When the dense oxidation process of this embodiment is performed, the bird's beak in the peripheral circuit region becomes larger than the bird's beak in the memory cell region as shown in FIG. Rounding could be realized in the peripheral circuit region and the memory cell region, respectively. Thus, according to the present embodiment, it is possible to improve the breakdown voltage of peripheral circuit elements to which a particularly high electric field is applied, and it is possible to maintain a good coupling ratio because the bird's beak is small in the memory cell region. It is.

  In addition, in this embodiment, by performing the above-described dense oxidation step, as shown in FIG. 14, the side wall of the element isolation trench 26, particularly the side wall of the polycrystalline silicon layer 8, is formed at the upper part. It has been found that the thickness of the silicon oxide film 28 is larger than the thickness of the silicon oxide film 28 formed below, that is, a tapered shape is formed. When this tapered shape is formed, there is an effect that the embedding property is improved when the conductive layer 10 (control gate electrode CG) is embedded via the interelectrode insulating film 9 after the element isolation insulating film 27 is dropped in a subsequent process. can get.

  Further, in the present embodiment, after the element isolation grooves 4 and 26 are processed and before the coating type insulating films 25 and 29 are embedded, the above-described dense oxidation process is performed, so that comparison is made in a peripheral circuit region having a large space width. A thick silicon oxide film 28 was formed. As a result, the volume of the coating type insulating film 29 embedded in the element isolation trench 26 in the peripheral circuit region can be reduced. Crystal defects in the element isolation trench 26 can be suppressed.

  It is possible to suppress crystal defects even if the silicon oxide film 28 is replaced with a thermal CVD film. However, since the pattern density difference is small in the thermal CVD film, if a thick thermal CVD film is formed to suppress crystal defects in the peripheral circuit region, the deposition thickness of the thermal CVD film in the memory cell region is inevitably comparable. Therefore, there is a risk of causing problems such as pattern blockage and pattern collapse in the memory cell region. For this reason, as a film (side wall film) formed on the inner surfaces of the element isolation trenches 4 and 26, a single film of the silicon oxide films 24 and 28 formed by the dense oxidation or the silicon oxide films 24 and 28 formed by the dense oxidation are formed. A laminated film in which a CVD film is formed after the formation is preferably used.

Next, the action (operation) of the above-described dense oxidation step will be considered.
In this embodiment, plasma oxidation is used when performing the above-described dense oxidation step. In this plasma oxidation, for example, argon gas (Ar) is mixed with oxygen gas (O ₂ ) to excite the plasma, and oxygen molecules are dissociated using the energy of the metastable state of argon gas (rare gas). Is used. In this case, the energy values at which the oxygen gas dissociates into oxygen ions and oxygen radicals are different, and the amount of these oxidized species generated can be controlled mainly by increasing or decreasing the processing pressure.

  FIG. 15 shows the pressure dependency of the oxygen ion irradiation amount (Ion Flux Density) in the plasma and the pressure dependency of the emission intensity of oxygen radicals (O (777 nm) intensity). As shown in FIG. 15, when the processing pressure is set to a low pressure, the amount of oxygen ions generated increases, whereas when the processing pressure is set to a high pressure, the amount of oxygen radicals generated tends to increase. This shows that the silicon oxidation reaction of oxygen ions is dominant when the processing pressure is low, and the silicon oxidation reaction of oxygen radicals is dominant when the processing pressure is high.

  Furthermore, the present inventors have obtained the knowledge that when the oxidation treatment with oxygen ions is performed at a low treatment pressure, the dense oxidation step of this embodiment can be realized. This is because, in the case of oxidation treatment with oxygen ions under low pressure, when oxygen ions generated in the processing apparatus are drawn toward the sample by the sheath potential generated between the sample and the plasma, the sample structure, particularly the sample top surface is angular. This is thought to be due to the more aggressive oxidation due to the concentration of the electric field at the location where it is present. In other words, in the dense region (memory cell region) of the pattern, oxygen ions generated under a low pressure are consumed in a large portion at the upper corner of the side wall of the element isolation groove 4. ), The oxidation rate is relatively slow, and the thickness of the formed silicon oxide film 24 is reduced. On the other hand, in the sparse region (peripheral circuit region) of the pattern, oxygen ions generated at a low pressure are uniformly drawn by the sheath potential, so that there is a large difference in the oxidation rate between the upper side wall and the inside (bottom) of the element isolation groove 26. not exist. As a result, it can be considered that the oxidation proceeds smoothly on the inner surface of the element isolation groove 26 and the thickness of the formed silicon oxide film 28 is increased.

  FIG. 16 shows the height position dependency of the film thickness of the silicon oxide film 24 formed on the inner surface (side wall) of the element isolation trench 4 in the memory cell region when the dense oxidation step is executed. The horizontal axis in FIG. 16 indicates the height position. The vertical axis represents the film thickness of the silicon oxide film 24 and is normalized with the film thickness of the silicon oxide film 24 formed at the Btm (bottom) position inside the element isolation trench 4 being taken as 1. From FIG. 16, it can be seen that the silicon oxide film 24 having a thickness about 2.5 times as large as that at the top position is formed as compared with the Btm position inside the element isolation trench 4. Further, it can be seen that the oxidation rate is much faster in the angular portion above the element isolation trench 4.

  In such a dense oxidation process, oxidation conditions in which the processing pressure is in the range of, for example, about 20 Pa to 60 Pa and the oxygen flow rate ratio is in the range of about 2.4 to 14.3% are particularly applicable to NAND flash memory devices. It was confirmed to be effective. The reason why the above oxidation conditions are effective is that the uniformity of the oxide film thickness in the substrate surface is good and that the oxidation rate is relatively fast in obtaining a desired oxide film thickness (in terms of productivity). Is mentioned.

  By the way, Patent Document 1 discloses a configuration in which a silicon oxide film (liner insulating film) is formed as a CVD film on the inner surface of the element isolation groove. When this liner insulating film is formed, an element is formed in the memory cell region. The electric field concentration in the upper corner portion of the separation groove is relaxed. For this reason, even if plasma oxidation is performed after the liner insulating film is formed, a dense oxidation action due to electric field concentration is hardly exhibited.

  On the other hand, in the present embodiment, the dense oxidation process is performed using the oxygen ions directly (or in the state where a natural oxide film is present) directly on the inner surfaces of the element isolation grooves 4 and 26. Therefore, the film thickness of the silicon oxide film 28 formed on the inner surface of the element isolation trench 26 in the peripheral circuit region can be made thicker than that in the memory cell region.

(Other embodiments)
In the above-described embodiment, the present invention is applied to the NAND type flash memory device. However, the present invention is not limited to this and may be applied to other semiconductor memories.

  As described above, according to the manufacturing method of the semiconductor device of the present embodiment, the oxide film having the first film thickness is formed on the inner surface of the first element isolation groove having the first opening width than the first opening width. An oxide film having a second film thickness larger than the first film thickness is collectively formed by plasma oxidation on the inner surface of the second element isolation groove having a wide second opening width, and then the first element isolation groove is formed. In addition, since the coating type insulating film is embedded in the second element isolation groove, the life of the peripheral circuit element can be extended, and crystal defects are generated in the element isolation groove portion of the peripheral circuit area by heat treatment or the like in the subsequent process. Can be prevented.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  In the drawings, 1 is a silicon substrate, 2 is an STI, 3 is an active region, 4 is an element isolation trench (first element isolation trench), 7 is a gate insulating film, 8 is a polycrystalline silicon layer (conductive layer), 22 is STI, 23 is an active region, 24 is a silicon oxide film, 25 is a coating type insulating film, 26 is an element isolation trench (second element isolation trench), 28 is a silicon oxide film, 29 is a coating type insulating film, and 30 is a gate. It is an insulating film.

Claims (5)

A method for manufacturing a semiconductor device, comprising: forming a plurality of memory cells in a first region on a semiconductor substrate; and forming a peripheral circuit element in a second region on the semiconductor substrate,
Forming an insulating film and a conductive layer on the semiconductor substrate in order;
A plurality of first element isolation grooves having a first opening width in the first region of the semiconductor substrate on which the insulating film and the conductive layer are formed, and the semiconductor substrate on which the insulating film and the conductive layer are formed. Forming a second element isolation trench having a second opening width wider than the first opening width in each of the second regions;
An oxide film having a first film thickness is formed on the inner surface of the first element isolation trench, and an oxide film having a second film thickness larger than the first film thickness is formed on the inner surface of the second element isolation groove. A process of batch formation by oxidation;
A method of manufacturing a semiconductor device, comprising: embedding a coating type insulating film in the first element isolation trench and the second element isolation trench in which the oxide film is formed on an inner surface.   The method of manufacturing a semiconductor device according to claim 1, wherein the plasma oxidation is performed at a processing pressure of 300 Pa or less.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the plasma oxidation is performed using a processing gas containing a rare gas and an oxygen gas, and a flow rate ratio of the oxygen gas is 20% or less.   By the plasma oxidation, a bird's beak is introduced into an end portion of the insulating film in the first region and the second region, and a bird's beak introduced into an end portion of the insulating film in the second region is The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is larger than a bird's beak introduced into an end portion of the insulating film in the first region.   The oxide film formed on the upper side wall of the conductive layer in the first region by the plasma oxidation has a thickness lower than the side wall of the conductive layer in the first region. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness is larger than the thickness of the semiconductor device.

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