JP2012191013A - Multi-wavelength light-emitting element and manufacturing method for the same - Google Patents

Multi-wavelength light-emitting element and manufacturing method for the same Download PDF

Info

Publication number
JP2012191013A
JP2012191013A JP2011053393A JP2011053393A JP2012191013A JP 2012191013 A JP2012191013 A JP 2012191013A JP 2011053393 A JP2011053393 A JP 2011053393A JP 2011053393 A JP2011053393 A JP 2011053393A JP 2012191013 A JP2012191013 A JP 2012191013A
Authority
JP
Japan
Prior art keywords
semiconductor
light emitting
crystal growth
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011053393A
Other languages
Japanese (ja)
Other versions
JP5822190B2 (en
Inventor
Kazuyuki Tadatomo
一行 只友
Narihito Okada
成仁 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaguchi University NUC
Original Assignee
Yamaguchi University NUC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaguchi University NUC filed Critical Yamaguchi University NUC
Priority to JP2011053393A priority Critical patent/JP5822190B2/en
Priority to PCT/JP2012/001607 priority patent/WO2012120891A1/en
Publication of JP2012191013A publication Critical patent/JP2012191013A/en
Application granted granted Critical
Publication of JP5822190B2 publication Critical patent/JP5822190B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Abstract

PROBLEM TO BE SOLVED: To provide a multi-wavelength light-emitting element that can be manufactured efficiently.SOLUTION: A multi-wavelength light-emitting element 100 includes: a substrate 110 including on a surface, first and second crystal growth planes 121 and 122 whose plane orientations are different from each other; a first semiconductor layer 131 formed by crystal growth of a semiconductor from the first crystal growth plane 121 on the substrate 110; a first semiconductor light-emitting layer 151 formed by crystal growth of a semiconductor on the first semiconductor layer 131; a second semiconductor layer 132 which is formed by crystal growth of a semiconductor from the second crystal growth plane 122 on the substrate 110 and whose main surface is the crystal plane different from a main surface of the first semiconductor layer 131; and a second semiconductor light-emitting layer 152 formed by crystal growth of a semiconductor whose component element is the same as the semiconductor forming the first semiconductor light-emitting layer 151 and whose element composition ratio is different from that of the semiconductor included in the first semiconductor light-emitting layer 151.

Description

本発明は多波長発光素子及びその製造方法に関する。   The present invention relates to a multi-wavelength light emitting device and a method for manufacturing the same.

発光波長が相互に異なる複数の半導体発光層を同一基板上に形成した多波長発光素子が種々提案されている。   Various multi-wavelength light emitting devices have been proposed in which a plurality of semiconductor light emitting layers having different emission wavelengths are formed on the same substrate.

例えば、特許文献1には、同一基板上に、GaP系、AlGaAs系、またはAlGaInP系化合物半導体からなる発光ダイオード部を少なくとも1個積層し、その発光ダイオード部上に、GaN系化合物半導体からなる発光ダイオード部を1個以上積層した多波長発光素子が開示されている。   For example, in Patent Document 1, at least one light emitting diode portion made of a GaP-based, AlGaAs-based, or AlGaInP-based compound semiconductor is stacked on the same substrate, and light emission made of a GaN-based compound semiconductor is formed on the light-emitting diode portion. A multi-wavelength light emitting element in which one or more diode portions are stacked is disclosed.

特許文献2には、1つの基板材料上に少なくとも2種類以上の半導体発光素子を形成し、各々の半導体発光素子上に、それぞれの素子の発光波長に反応する蛍光体を複数種類塗布し、各々の半導体発光素子を同時に発光させることにより、広範囲の発光波長を有する可視光を発光する多波長発光装置が開示されている。   In Patent Document 2, at least two types of semiconductor light emitting elements are formed on one substrate material, and a plurality of types of phosphors that react to the emission wavelength of each element are applied on each semiconductor light emitting element, A multi-wavelength light-emitting device that emits visible light having a wide range of emission wavelengths by simultaneously emitting the semiconductor light-emitting elements is disclosed.

特開平9−55538号公報JP-A-9-55538 特開2008−71805号公報JP 2008-71805 A

特許文献1に記載された技術では、発光波長が相互に異なる複数の半導体層を積層するため、それらの複数の半導体層を別々の工程で形成する必要がある。また、特許文献2に記載された技術でも、基板上に、第1の半導体発光素子を形成した後、別工程で第2の半導体発光素子を形成する。   In the technique described in Patent Document 1, in order to stack a plurality of semiconductor layers having different emission wavelengths, it is necessary to form the plurality of semiconductor layers in separate steps. In the technique described in Patent Document 2, after forming the first semiconductor light emitting element on the substrate, the second semiconductor light emitting element is formed in a separate process.

本発明の課題は、効率的な製造が可能な多波長発光素子及びその製造方法を提供することである。   An object of the present invention is to provide a multi-wavelength light emitting device capable of efficient manufacture and a method for manufacturing the same.

本発明の多波長発光素子は、
表面に面方位が相互に異なる第1及び第2結晶成長面を有すると共に該第1及び第2結晶成長面に対応する第1及び第2発光領域が構成された基板と、
上記基板上の上記第1発光領域に積層されるように設けられ上記第1結晶成長面を起点として半導体が結晶成長して形成された第1半導体層と、
上記第1半導体層上に積層されるように設けられ半導体が結晶成長して形成された所定の波長の光を発光する第1半導体発光層と、
上記基板上の上記第2発光領域に積層されるように設けられ上記第2結晶成長面を起点として半導体が結晶成長して形成された、上記第1半導体層の主面とは異なる結晶面を主面とする第2半導体層と、
上記第2半導体層上に積層されるように設けられ上記第1半導体発光層を形成する半導体と同一の構成元素で且つ元素組成比が異なる半導体が結晶成長して形成された、及び/又は、上記第1半導体発光層を形成する半導体と同一の構成元素の半導体が結晶成長して形成され且つ上記第1半導体発光層とは層厚が異なる、上記第1半導体発光層が発光する光の波長と異なる波長の光を発光する第2半導体発光層と、
を備える。
The multi-wavelength light emitting device of the present invention is
A substrate having first and second crystal growth planes having different plane orientations on the surface, and first and second light emitting regions corresponding to the first and second crystal growth planes;
A first semiconductor layer provided to be stacked on the first light emitting region on the substrate and formed by crystal growth of a semiconductor from the first crystal growth surface;
A first semiconductor light emitting layer configured to be laminated on the first semiconductor layer and emitting light of a predetermined wavelength formed by crystal growth of a semiconductor;
A crystal plane different from the main surface of the first semiconductor layer, which is provided so as to be stacked on the second light emitting region on the substrate and is formed by crystal growth of a semiconductor starting from the second crystal growth plane. A second semiconductor layer as a main surface;
A semiconductor having the same constituent element as that of the semiconductor forming the first semiconductor light emitting layer and having a different element composition ratio is formed by crystal growth and / or formed on the second semiconductor layer; and / or The wavelength of light emitted from the first semiconductor light-emitting layer, which is formed by crystal growth of a semiconductor having the same constituent element as the semiconductor forming the first semiconductor light-emitting layer and has a layer thickness different from that of the first semiconductor light-emitting layer A second semiconductor light emitting layer that emits light of a different wavelength from
Is provided.

本発明の多波長発光素子の製造方法は、
表面に面方位が相互に異なる第1及び第2結晶成長面を有する基板を準備する準備工程と、
上記準備工程で準備した基板の第1結晶成長面を起点として半導体を結晶成長させることにより、基板上に第1発光領域を構成して積層するように第1半導体層を形成する第1半導体層形成工程と、
上記準備工程で準備した基板の第2結晶成長面を起点として半導体を結晶成長させることにより、基板上に第2発光領域を構成して積層するように、第1半導体層の主面とは異なる結晶面を主面とする第2半導体層を形成する第2半導体層形成工程と、
上記第1半導体層形成工程で形成した第1半導体層上に積層するように半導体を結晶成長させて所定の波長の光を発光する第1半導体発光層を形成すると同時に、上記第2半導体層形成工程で形成した第2半導体層上に積層するように、上記第1半導体発光層を形成する半導体と同一の構成元素で且つ元素組成比が異なる半導体を結晶成長させて、及び/又は、上記第1半導体発光層を形成する半導体と同一の構成元素の半導体を、上記第1半導体発光層とは層厚が異なるように結晶成長させて、上記第1半導体発光層が発光する光の波長と異なる波長の光を発光する第2半導体発光層を形成する第1及び第2半導体発光層形成工程と、
を備える。
The method for producing the multi-wavelength light emitting device of the present invention includes:
Preparing a substrate having first and second crystal growth surfaces having different plane orientations on the surface;
A first semiconductor layer that forms a first light emitting region on the substrate to form a first semiconductor layer by crystal growth of the semiconductor starting from the first crystal growth surface of the substrate prepared in the preparation step Forming process;
Different from the main surface of the first semiconductor layer so that the second light emitting region is formed and stacked on the substrate by crystal growth of the semiconductor starting from the second crystal growth surface of the substrate prepared in the preparation step. A second semiconductor layer forming step of forming a second semiconductor layer having a crystal plane as a main surface;
At the same time as forming the first semiconductor light emitting layer for emitting light of a predetermined wavelength by crystal growth of the semiconductor so as to be laminated on the first semiconductor layer formed in the first semiconductor layer forming step, the second semiconductor layer formation is performed. A semiconductor having the same constituent element as that of the semiconductor forming the first semiconductor light emitting layer and having a different element composition ratio is crystal-grown so as to be stacked on the second semiconductor layer formed in the process and / or the first semiconductor layer is formed. A semiconductor having the same constituent elements as the semiconductor forming the semiconductor light emitting layer is crystal-grown so as to have a layer thickness different from that of the first semiconductor light emitting layer, so that the wavelength of light emitted by the first semiconductor light emitting layer is different. First and second semiconductor light emitting layer forming steps for forming a second semiconductor light emitting layer that emits light of a wavelength;
Is provided.

本発明によれば、面方位が相互に異なる第1及び第2結晶成長面から半導体が結晶成長して形成された、主面の結晶面が相互に異なる第1及び第2半導体層上には、同一の構成元素で且つ元素組成比が異なる半導体が結晶成長しても、及び/又は、同一の構成元素の半導体が層厚が異なって結晶成長しても、発光波長が異なる第1及び第2半導体発光層が形成され得ることから、第1及び第2半導体発光層を同一工程で形成することができ、従って、多波長発光素子の効率的な製造が可能となる。   According to the present invention, on the first and second semiconductor layers formed by crystal growth of the semiconductor from the first and second crystal growth planes having different plane orientations, the main plane crystal planes are different from each other. Even if a semiconductor having the same constituent element and different element composition ratio is crystal-grown and / or a semiconductor having the same constituent element is crystal-grown with a different layer thickness, the first and second emission wavelengths are different. Since the two semiconductor light-emitting layers can be formed, the first and second semiconductor light-emitting layers can be formed in the same process, and thus the multi-wavelength light-emitting element can be efficiently manufactured.

実施形態に係る多波長発光素子の平面図である。It is a top view of the multiwavelength light emitting element concerning an embodiment. 図1におけるII-II断面図である。It is II-II sectional drawing in FIG. 図1におけるIII-III断面図である。FIG. 3 is a sectional view taken along line III-III in FIG. 1. (a)〜(d)は基板及び第1〜第3u-半導体層の具体例の断面図である。(A)-(d) is sectional drawing of the specific example of a board | substrate and the 1st-3rd u <-> semiconductor layer. (a)〜(f)は実施形態に係る多波長発光素子の製造方法の説明図である。(A)-(f) is explanatory drawing of the manufacturing method of the multiwavelength light emitting element which concerns on embodiment.

以下、実施形態について図面に基づいて説明する。   Hereinafter, embodiments will be described with reference to the drawings.

(多波長発光素子)
図1〜3は本実施形態に係る多波長発光素子100を示す。
(Multi-wavelength light emitting device)
1 to 3 show a multiwavelength light emitting device 100 according to the present embodiment.

<基板>
本実施形態に係る多波長発光素子100はベースとなる基板110を備えている。
<Board>
The multi-wavelength light emitting device 100 according to this embodiment includes a substrate 110 serving as a base.

基板110としては、例えば、サファイア基板、SiC基板等が挙げられる。これらのうち汎用性の観点からAl23のコランダム構造の単結晶基板であるサファイア基板が好ましい。基板110の主面(基板の厚さ方向を法線方向とし、それに直交する面)は、法線方向がa軸であるa面<{11−20}面>、法線方向がc軸であるc面<{0001}面>、及び法線方向がm軸であるm面<{1−100}面>のいずれであってもよく、また、r面<{1−102}面>、n面<{11−23}面>等の他の結晶面であってもよい。さらに、基板110の主面は、a軸等が主面の法線方向に対して所定の角度(例えば45°や60°、あるいは数度以内の微少角)傾斜したミスカット面であってもよい。つまり、基板110はミスカット基板であってもよい。なお、a面、c面、及びm面は面方位が相互に直交する。 Examples of the substrate 110 include a sapphire substrate and a SiC substrate. Of these, a sapphire substrate which is a single crystal substrate having an Al 2 O 3 corundum structure is preferable from the viewpoint of versatility. The main surface of the substrate 110 (the surface perpendicular to the thickness direction of the substrate) is the a-plane <{11-20} plane> in which the normal direction is the a-axis, and the normal direction is the c-axis. Any c-plane <{0001} plane> and m-plane <{1-100} plane> whose normal direction is the m-axis may be used, and r-plane <{1-102} plane>, Other crystal planes such as n-plane <{11-23} plane> may be used. Further, the main surface of the substrate 110 may be a miscut surface in which the a-axis or the like is inclined at a predetermined angle (eg, 45 °, 60 °, or a slight angle within several degrees) with respect to the normal direction of the main surface. Good. That is, the substrate 110 may be a miscut substrate. The plane directions of the a-plane, c-plane, and m-plane are orthogonal to each other.

基板110は、表面に面方位が相互に異なる第1〜第3結晶成長面121〜123を有しており、それらの第1〜第3結晶成長面121〜123に対応する第1〜第3発光領域A1〜A3が構成されている。なお、基板110は、表面に面方位が相互に異なる第1及び第2結晶成長面121,122のみを有し、それらの第1及び第2結晶成長面121,122に対応する第1及び第2発光領域A1,A2が構成されたものであってもよい。また、基板110は、表面に第1〜第3結晶成長面121〜123とは面方位が異なる結晶成長面を有し、その結晶成長面に対応する発光領域が1つ乃至複数構成されていてもよい。つまり、発光領域が3つよりも多く構成されていてもよい。   The substrate 110 has first to third crystal growth surfaces 121 to 123 having different surface orientations on the surface, and the first to third corresponding to the first to third crystal growth surfaces 121 to 123. Light emitting areas A1 to A3 are configured. The substrate 110 has only first and second crystal growth surfaces 121 and 122 having different surface orientations on the surface, and the first and second crystal growth surfaces 121 and 122 corresponding to the first and second crystal growth surfaces 121 and 122 are provided. Two light emitting areas A1 and A2 may be configured. The substrate 110 has a crystal growth surface having a surface orientation different from that of the first to third crystal growth surfaces 121 to 123 on the surface, and one or more light emitting regions corresponding to the crystal growth surface are formed. Also good. That is, more than three light emitting regions may be configured.

第1〜第3結晶成長面121〜123は、基板110の主面、基板110に形成された第1凹溝111の一方の側面、第1凹溝111の延びる方向に角度(典型的には90°)を有して延びる第2凹溝112の一方の側面によって構成されている。第1及び第2凹溝111,112は、側面を有せば、コの字溝であってもよく、V字溝であってもよく、台形溝であってもよい。第1及び第2凹溝111,112は、例えば、溝開口幅が0.5〜10μm、溝深さが0.75〜100μm、及び溝側面の主面に対してなす角度が70〜120°である。第1及び第2凹溝111,112は、1本だけが形成されていてもよく、また、複数本が相互に間隔をおいて並行に延びるように形成されていてもよい。後者の場合、溝間隔は例えば1〜100μmである。なお、第1〜第3結晶成長面121〜123は、その他の凹部の側面や凸部乃至凸状の側面で構成されていてもよい。   The first to third crystal growth surfaces 121 to 123 are angled (typically, the main surface of the substrate 110, one side surface of the first groove 111 formed in the substrate 110, and the direction in which the first groove 111 extends). 90 °) and extending from one side surface of the second concave groove 112. The first and second concave grooves 111 and 112 may be U-shaped grooves, V-shaped grooves, or trapezoidal grooves as long as they have side surfaces. The first and second concave grooves 111 and 112 have, for example, a groove opening width of 0.5 to 10 μm, a groove depth of 0.75 to 100 μm, and an angle formed with respect to the main surface of the groove side surface of 70 to 120 °. It is. Only one of the first and second concave grooves 111 and 112 may be formed, or a plurality of the first and second concave grooves 111 and 112 may be formed to extend in parallel with an interval between each other. In the latter case, the groove interval is, for example, 1 to 100 μm. The first to third crystal growth surfaces 121 to 123 may be configured by other concave side surfaces or convex or convex side surfaces.

具体的には、例えば、基板110がサファイア基板であるとき、図4(a)に示すように、第1結晶成長面121が基板110の主面であるa面、第2結晶成長面122がm軸方向に延びる台形溝である第1凹溝111の一方の側面、及び第3結晶成長面123が第1凹溝111に直交してc軸方向に延びる台形溝である第2凹溝112の一方の側面である第1構成、図4(b)に示すように、第1結晶成長面121が基板110の主面であるc面、第2結晶成長面122がm軸方向に延びる台形溝である第1凹溝111の一方の側面、及び第3結晶成長面123が第1凹溝111に直交してa軸方向に延びる台形溝である第2凹溝112の一方の側面である第2構成、図4(c)に示すように、第1結晶成長面121が基板110の主面であるn面、第2結晶成長面122がm軸方向に延びる台形溝である第1凹溝111の一方の側面であるc面、及び第3結晶成長面123が第1凹溝111に直交する方向に延びる台形溝である第2凹溝112の一方の側面である第3構成、並びに、図4(d)に示すように、第1結晶成長面121が基板110の主面であるr面、第2結晶成長面122がa軸方向に延びる台形溝である第1凹溝111の一方の側面、及び第3結晶成長面123が第1凹溝111に直交する方向に延びる台形溝である第2凹溝112の一方の側面である第4構成が挙げられる。   Specifically, for example, when the substrate 110 is a sapphire substrate, the first crystal growth surface 121 is a main surface of the substrate 110 and the second crystal growth surface 122 is as shown in FIG. One side surface of the first groove 111 that is a trapezoidal groove extending in the m-axis direction and the second groove 112 that is a trapezoidal groove in which the third crystal growth surface 123 extends in the c-axis direction perpendicular to the first groove 111. As shown in FIG. 4B, the first crystal growth surface 121 is a c-plane which is the main surface of the substrate 110, and the second crystal growth surface 122 is a trapezoid extending in the m-axis direction. One side surface of the first concave groove 111 that is a groove and one side surface of the second concave groove 112 that is a trapezoidal groove in which the third crystal growth surface 123 extends in the a-axis direction perpendicular to the first concave groove 111. As shown in the second configuration, FIG. 4C, the first crystal growth surface 121 is the main surface of the substrate 110. The n-plane, the c-plane which is one side surface of the first groove 111 which is a trapezoidal groove in which the second crystal growth surface 122 extends in the m-axis direction, and the third crystal growth surface 123 are orthogonal to the first groove 111. A third configuration which is one side surface of the second concave groove 112 which is a trapezoidal groove extending in the direction, and an r-plane in which the first crystal growth surface 121 is the main surface of the substrate 110 as shown in FIG. The second crystal growth surface 122 is a trapezoidal groove extending in the direction orthogonal to the first concave groove 111, and one side surface of the first concave groove 111, which is a trapezoidal groove extending in the a-axis direction. The 4th structure which is one side surface of the 2nd ditch | groove 112 is mentioned.

<第1〜第3u-半導体層>
本実施形態に係る多波長発光素子100は、基板110上の第1〜第3発光領域A1〜A3に積層されるように設けられた第1〜第3u-半導体層131〜133を備えている。これらの第1〜第3u-半導体層131〜133は、第1〜第3結晶成長面121〜123を起点として、それぞれアンドープの半導体が結晶成長して形成されたものである。
<First to third u-semiconductor layers>
The multi-wavelength light emitting device 100 according to this embodiment includes first to third u− semiconductor layers 131 to 133 provided to be stacked in the first to third light emitting regions A1 to A3 on the substrate 110. . These first to third u− semiconductor layers 131 to 133 are formed by crystal growth of undoped semiconductors starting from the first to third crystal growth surfaces 121 to 123, respectively.

第1〜第3u-半導体層131〜133を形成する半導体としては、例えば、GaN、InGaN、AlGaN等が挙げられる。第1〜第3u-半導体層131〜133は、同一の半導体で形成されていてもよく、また、異なる半導体を含んで形成されていてもよい。第1〜第3u-半導体層131〜133の厚さは例えば2〜100μmである。   Examples of the semiconductor forming the first to third u− semiconductor layers 131 to 133 include GaN, InGaN, and AlGaN. The first to third u− semiconductor layers 131 to 133 may be formed of the same semiconductor or may include different semiconductors. The thickness of the first to third u− semiconductor layers 131 to 133 is, for example, 2 to 100 μm.

第1u-半導体層131は、基板110の主面の結晶面と同じ結晶面を主面としてもよく、また、基板110の主面の結晶面と異なる結晶面を主面としてもよい。第2u-半導体層132は、第1半導体層の主面とは異なる結晶面を主面とする。第3u-半導体層133は、第1及び第2半導体層の主面とは異なる結晶面を主面とする。   The first u− semiconductor layer 131 may have a crystal plane that is the same as the crystal plane of the main surface of the substrate 110 as a main surface, or may have a crystal plane that is different from the crystal plane of the main surface of the substrate 110 as a main surface. The second u − semiconductor layer 132 has a crystal plane different from the main surface of the first semiconductor layer as the main surface. The third u− semiconductor layer 133 has a crystal plane different from the main surfaces of the first and second semiconductor layers as a main surface.

具体的には、第1〜第3u-半導体層131〜133を形成する半導体がGaNのとき、第1構成の場合、図4(a)に示すように、第1結晶成長面121である基板110の主面のa面を起点としてアンドープのGaNが結晶成長し、第1u-半導体層131として、c面を主面とすると共に、第1凹溝111の延びる方向がa軸方向で、且つ第2凹溝112の延びる方向がm軸方向である第1u-GaN層131が形成され、また、第2結晶成長面122である第1凹溝111の一方の側面を起点としてアンドープのGaNが結晶成長し、第2u-半導体層132として、m面を主面とすると共に、第1凹溝111の延びる方向がa軸方向で、且つ第2凹溝112の延びる方向がc軸方向である第2u-GaN層132が形成され、さらに、第3結晶成長面123である第2凹溝112の一方の側面を起点としてアンドープのGaNが結晶成長し、第3u-半導体層133として、a面を主面とすると共に、第1凹溝111の延びる方向がm軸方向で、且つ第2凹溝112の延びる方向がc軸方向である第3u-GaN層133が形成される。   Specifically, when the semiconductor forming the first to third u− semiconductor layers 131 to 133 is GaN, in the first configuration, as shown in FIG. 4A, the substrate that is the first crystal growth surface 121. The undoped GaN crystal grows starting from the a-plane of the main surface of 110, and the first u-semiconductor layer 131 has the c-plane as the main surface, and the extending direction of the first groove 111 is the a-axis direction, and The first u-GaN layer 131 in which the extending direction of the second groove 112 is the m-axis direction is formed, and undoped GaN is formed from one side surface of the first groove 111 that is the second crystal growth surface 122. The crystal grows, and the second u− semiconductor layer 132 has an m-plane as a main surface, the extending direction of the first groove 111 is the a-axis direction, and the extending direction of the second groove 112 is the c-axis direction. A second u-GaN layer 132 is formed and further The undoped GaN crystal grows starting from one side surface of the second concave groove 112 which is the crystal growth surface 123, and the third u-semiconductor layer 133 has the a-plane as the main surface and extends the first concave groove 111. A third u-GaN layer 133 is formed in which the direction is the m-axis direction and the direction in which the second groove 112 extends is the c-axis direction.

第2構成の場合、図4(b)に示すように、第1結晶成長面121である基板110の主面のc面を起点としてアンドープのGaNが結晶成長し、第1u-半導体層131として、c面(又はm面)を主面とすると共に、第1凹溝111の延びる方向がa軸方向で、且つ第2凹溝112の延びる方向がm軸(又はc軸)方向である第1u-GaN層131が形成され、また、第2結晶成長面122である第1凹溝111の一方の側面を起点としてアンドープのGaNが結晶成長し、第2u-半導体層132として、m面を主面とすると共に、第1凹溝111の延びる方向がa軸方向で、且つ第2凹溝112の延びる方向がc軸方向である第2u-GaN層132が形成され、さらに、第3結晶成長面123である第2凹溝112の一方の側面を起点としてアンドープのGaNが結晶成長し、第3u-GaN層133として、c面を主面とすると共に、第1凹溝111の延びる方向がm軸方向で、且つ第2凹溝112の延びる方向がa軸方向である第3u-GaN層133が形成される。   In the case of the second configuration, as shown in FIG. 4B, undoped GaN grows from the c-plane of the main surface of the substrate 110, which is the first crystal growth surface 121, to form the first u-semiconductor layer 131. The c-plane (or m-plane) is the main surface, the extending direction of the first groove 111 is the a-axis direction, and the extending direction of the second groove 112 is the m-axis (or c-axis) direction. The 1u-GaN layer 131 is formed, and undoped GaN grows from one side surface of the first concave groove 111 which is the second crystal growth surface 122, and the m-plane is formed as the second u-semiconductor layer 132. A second u-GaN layer 132 is formed which has a main surface, the first groove 111 extends in the a-axis direction, and the second groove 112 extends in the c-axis direction. Starting from one side surface of the second concave groove 112 that is the growth surface 123 As the third u-GaN layer 133, the undoped GaN crystal grows, the c-plane is the main surface, the extending direction of the first groove 111 is the m-axis direction, and the extending direction of the second groove 112 is A third u-GaN layer 133 that is in the a-axis direction is formed.

第3構成の場合、図4(c)に示すように、第1結晶成長面121である基板110の主面のn面を起点としてアンドープのGaNが結晶成長し、第1u-半導体層131として、c面を主面とすると共に、第1凹溝111の延びる方向がa軸方向で、且つ第2凹溝112の延びる方向がm軸方向である第1u-GaN層131が形成され、また、第2結晶成長面122である第1凹溝111の一方の側面を起点としてアンドープのGaNが結晶成長し、第2u-半導体層132として、半極性{0−101}面を主面とすると共に、第1凹溝111の延びる方向がa軸方向で、且つ第2凹溝112の延びる方向がc軸とm軸との中間の方向である第2u-GaN層132が形成され、さらに、第3結晶成長面123である第2凹溝112の一方の側面を起点としてアンドープのGaNが結晶成長し、第3u-半導体層133として、a面とc面との中間の結晶面を主面とすると共に、第1凹溝111の延びる方向がm軸方向で、且つ第2凹溝112の延びる方向がa軸とc軸との中間の方向である第3u-GaN層133が形成される。   In the case of the third configuration, as shown in FIG. 4C, undoped GaN grows from the n-plane of the main surface of the substrate 110, which is the first crystal growth surface 121, to form the first u-semiconductor layer 131. A first u-GaN layer 131 having a c-plane as a main surface, the first groove 111 extending in the a-axis direction, and the second groove 112 extending in the m-axis direction is formed. The undoped GaN crystal grows starting from one side surface of the first groove 111 which is the second crystal growth surface 122, and the semipolar {0-101} plane is the main surface as the second u− semiconductor layer 132. In addition, a second u-GaN layer 132 is formed in which the extending direction of the first concave groove 111 is the a-axis direction and the extending direction of the second concave groove 112 is an intermediate direction between the c-axis and the m-axis, One of the second concave grooves 112 which is the third crystal growth surface 123 The undoped GaN crystal grows starting from the side surface, and the third u-semiconductor layer 133 has a crystal plane intermediate between the a plane and the c plane as the main plane, and the extending direction of the first concave groove 111 is the m-axis direction. In addition, the third u-GaN layer 133 is formed in which the extending direction of the second groove 112 is an intermediate direction between the a-axis and the c-axis.

第4構成の場合、図4(d)に示すように、第1結晶成長面121である基板110の主面のr面を起点としてアンドープのGaNが結晶成長し、第1u-半導体層131として、a面を主面とすると共に、第1凹溝111の延びる方向がm軸方向で、且つ第2凹溝112の延びる方向がc軸方向である第1u-GaN層131が形成され、また、第2結晶成長面122である第1凹溝111の一方の側面を起点としてアンドープのGaNが結晶成長し、第2u-半導体層132として、{11−22}面を主面とすると共に、第1凹溝111の延びる方向がm軸方向で、且つ第2凹溝112の延びる方向がa軸とc軸との中間の方向である第2u-GaN層132が形成され、さらに、第3結晶成長面123である第2凹溝112の一方の側面を起点としてアンドープのGaNが結晶成長し、第3u-半導体層133として、m面を主面とすると共に、第1凹溝111の延びる方向がc軸方向で、且つ第2凹溝112の延びる方向がa軸方向である第3u-GaN層133が形成される。   In the case of the fourth configuration, as shown in FIG. 4D, undoped GaN crystal grows from the r-plane of the main surface of the substrate 110 which is the first crystal growth surface 121, and the first u− semiconductor layer 131 is formed. , A first u-GaN layer 131 is formed in which the a-plane is the main surface, the extending direction of the first groove 111 is the m-axis direction, and the extending direction of the second groove 112 is the c-axis direction. The undoped GaN crystal grows starting from one side surface of the first concave groove 111 which is the second crystal growth surface 122, and the {11-22} plane is the main surface as the second u− semiconductor layer 132, A second u-GaN layer 132 is formed in which the direction in which the first groove 111 extends is the m-axis direction and the direction in which the second groove 112 extends is an intermediate direction between the a-axis and the c-axis. One side surface of the second groove 112 which is the crystal growth surface 123 is Undoped GaN crystal grows as a starting point, and the third u-semiconductor layer 133 has an m-plane as a main surface, the extending direction of the first groove 111 is the c-axis direction, and the extending direction of the second groove 112 A third u-GaN layer 133 is formed in the direction of the a-axis.

なお、基板110と第1〜第3u-半導体層131〜133との間には、厚さが20〜30nm程度の低温バッファ層が設けられていてもよい。また、上記で構成された第1〜第3u-半導体層131〜133の高さは結晶成長の困難さより揃わないことも予想され、その場合は研磨等を施すことによって高さを揃えてもよい。   A low temperature buffer layer having a thickness of about 20 to 30 nm may be provided between the substrate 110 and the first to third u− semiconductor layers 131 to 133. In addition, it is expected that the heights of the first to third u− semiconductor layers 131 to 133 configured as described above are not aligned with difficulty in crystal growth, and in that case, the heights may be aligned by performing polishing or the like. .

<第1〜第3n型半導体層>
本実施形態に係る多波長発光素子100は、第1〜第3u-半導体層131〜133に積層されるように設けられた第1〜第3n型半導体層141〜143を備えている。これらの第1〜第3n型半導体層141〜143は、第1〜第3u-半導体層131〜133の主面を起点として、それぞれn型ドーパントがドープされた半導体がエピタキシャル結晶成長して形成されたものである。従って、第1〜第3n型半導体層141〜143は、第1〜第3u-半導体層131〜133の主面と同一の結晶面を主面とする。
<First to third n-type semiconductor layers>
The multi-wavelength light emitting device 100 according to the present embodiment includes first to third n-type semiconductor layers 141 to 143 provided to be stacked on the first to third u− semiconductor layers 131 to 133. The first to third n-type semiconductor layers 141 to 143 are formed by epitaxially growing a semiconductor doped with an n-type dopant, starting from the main surface of the first to third u− semiconductor layers 131 to 133. It is a thing. Therefore, the first to third n-type semiconductor layers 141 to 143 have the same crystal plane as the main surface of the first to third u− semiconductor layers 131 to 133 as the main surface.

第1〜第3n型半導体層141〜143を構成する半導体としては、例えば、GaN、InGaN、AlGaN等が挙げられる。第1〜第3n型半導体層141〜143は、同一の半導体で構成されていてもよく、また、異なる半導体を含んで構成されていてもよい。   Examples of the semiconductor constituting the first to third n-type semiconductor layers 141 to 143 include GaN, InGaN, and AlGaN. The first to third n-type semiconductor layers 141 to 143 may be composed of the same semiconductor, or may be composed of different semiconductors.

第1〜第3n型半導体層141〜143に含まれるn型ドーパントとしては、例えば、Si、Ge等が挙げられる。n型ドーパントの濃度は例えば1.0×1017〜20×1017/cm3である。 Examples of the n-type dopant contained in the first to third n-type semiconductor layers 141 to 143 include Si, Ge, and the like. The concentration of the n-type dopant is, for example, 1.0 × 10 17 to 20 × 10 17 / cm 3 .

第1〜第3n型半導体層141〜143は、単一層で構成されていてもよく、また、n型ドーパントの種類や濃度の異なる複数の層で構成されていてもよい。第1〜第3n型半導体層141〜143の厚さは例えば2〜10μmである。   The first to third n-type semiconductor layers 141 to 143 may be composed of a single layer, or may be composed of a plurality of layers having different types and concentrations of n-type dopants. The thickness of the first to third n-type semiconductor layers 141 to 143 is, for example, 2 to 10 μm.

<第1〜第3発光層>
本実施形態に係る多波長発光素子100は、第1〜第3n型半導体層141〜143に積層されるように設けられた第1〜第3発光層151〜153を備えている。これらの第1〜第3発光層151〜153は、第1〜第3n型半導体層141〜143の主面を起点として、それぞれ半導体がエピタキシャル結晶成長して形成されたものである。従って、第1〜第3発光層151〜153は、第1〜第3n型半導体層141〜143及び第1〜第3u-半導体層131〜133の主面と同一の結晶面を主面とする。
<First to third light emitting layers>
The multi-wavelength light emitting device 100 according to the present embodiment includes first to third light emitting layers 151 to 153 provided to be stacked on the first to third n-type semiconductor layers 141 to 143. These first to third light emitting layers 151 to 153 are formed by epitaxially growing a semiconductor from the main surface of the first to third n-type semiconductor layers 141 to 143, respectively. Accordingly, the first to third light emitting layers 151 to 153 have the same crystal plane as the main surface of the first to third n-type semiconductor layers 141 to 143 and the first to third u− semiconductor layers 131 to 133. .

第1〜第3発光層151〜153は、第1〜第3井戸層(第1〜第3半導体発光層)151a〜153aと第1〜第3障壁層151b〜153bとの交互積層構造を有する多重量子井戸層によって構成されている。第1〜第3井戸層151a〜153a及び第1〜第3障壁層151b〜153bの層数は例えば5〜15層である。   The first to third light emitting layers 151 to 153 have an alternately stacked structure of first to third well layers (first to third semiconductor light emitting layers) 151a to 153a and first to third barrier layers 151b to 153b. It is composed of multiple quantum well layers. The number of layers of the first to third well layers 151a to 153a and the first to third barrier layers 151b to 153b is, for example, 5 to 15.

第1〜第3井戸層151a〜153aを形成する半導体としては、例えば、InGaN、InGaAlN等が挙げられる。第1〜第3井戸層151a〜153aの厚さは例えば1〜20nmである。   Examples of the semiconductor forming the first to third well layers 151a to 153a include InGaN, InGaAlN, and the like. The thickness of the first to third well layers 151a to 153a is, for example, 1 to 20 nm.

第1〜第3障壁層151b〜153bを形成する半導体としては、例えば、GaN、InGaN(ただし、第1〜第3井戸層151a〜153aのバンドギャップより大きい)等が挙げられる。第1〜第3障壁層151b〜153bの厚さは例えば5〜20nmである。   Examples of the semiconductor forming the first to third barrier layers 151b to 153b include GaN, InGaN (however, larger than the band gap of the first to third well layers 151a to 153a). The thickness of the first to third barrier layers 151b to 153b is, for example, 5 to 20 nm.

第1〜第3発光層151〜153は、第1〜第3井戸層151a〜153aが同一の構成元素(例えば、構成元素がIn、Ga、及びNで同一である。)からなる半導体が結晶成長して形成されていると共に、第1〜第3障壁層151b〜153bも同一の構成元素(例えば、構成元素がGa及びNで同一である。)からなる半導体が結晶成長して形成されている。第1〜第3井戸層151a〜153aは、相互に異なる結晶面を主面とする第1〜第3n型半導体層141〜143、従って、第1〜第3u-半導体層131〜133の主面と同一の結晶面を主面とするので、例えばInGaNで形成されている場合、層内へのInNの取り込まれ効率(InN混晶比)が相異し、そのため、元素組成比が相互に異なることとなり、及び/又は、層厚が相互に異なることとなり、その結果、相互に異なる波長の光を発光するように構成されている。   In the first to third light emitting layers 151 to 153, the first to third well layers 151a to 153a are made of the same constituent element (for example, the constituent elements are the same for In, Ga, and N). In addition to being formed, the first to third barrier layers 151b to 153b are also formed by crystal growth of a semiconductor made of the same constituent element (for example, the constituent elements are the same in Ga and N). Yes. The first to third well layers 151a to 153a are first to third n-type semiconductor layers 141 to 143 having crystal planes different from each other as main surfaces, and accordingly, main surfaces of the first to third u− semiconductor layers 131 to 133 Since the same crystal plane as the main surface is used, for example, when it is formed of InGaN, the efficiency of incorporation of InN into the layer (InN mixed crystal ratio) is different, so that the elemental composition ratios are different from each other. Therefore, and / or the layer thicknesses are different from each other, and as a result, they are configured to emit light having different wavelengths.

第1〜第3発光層151〜153は、例えば、それぞれR(赤)、G(緑)、及び(青)の光を発光するように構成されていてもよい。これによりワンチップの白色発光素子(白色LED)を構成することができる。   The first to third light emitting layers 151 to 153 may be configured to emit R (red), G (green), and (blue) light, for example. Thus, a one-chip white light emitting element (white LED) can be configured.

<第1〜第3p型半導体層>
本実施形態に係る多波長発光素子100は、第1〜第3発光層151〜153に積層されるように設けられた第1〜第3p型半導体層161〜163を備えている。
<First to third p-type semiconductor layers>
The multi-wavelength light emitting device 100 according to the present embodiment includes first to third p-type semiconductor layers 161 to 163 provided to be stacked on the first to third light emitting layers 151 to 153.

第1〜第3p型半導体層161〜163を構成する半導体としては、例えば、GaN、InGaN、AlGaN等が挙げられる。第1〜第3p型半導体層161〜163は、同一の半導体で構成されていてもよく、また、異なる半導体を含んで構成されていてもよい。   Examples of the semiconductor constituting the first to third p-type semiconductor layers 161 to 163 include GaN, InGaN, and AlGaN. The first to third p-type semiconductor layers 161 to 163 may be composed of the same semiconductor, or may be composed of different semiconductors.

第1〜第3p型半導体層161〜163に含まれるp型ドーパントとしては、例えば、Mg、Cd等が挙げられる。ホール効果測定で測定される自由正孔濃度は例えば2.0×1017〜10×1017/cm3である。 Examples of the p-type dopant contained in the first to third p-type semiconductor layers 161 to 163 include Mg and Cd. The free hole concentration measured by the Hall effect measurement is, for example, 2.0 × 10 17 to 10 × 10 17 / cm 3 .

第1〜第3p型半導体層161〜163は、単一層で構成されていてもよく、また、p型ドーパントの種類や濃度の異なる複数の層で構成されていてもよい。第1〜第3p型半導体層161〜163の厚さは例えば50〜200nmである。   The first to third p-type semiconductor layers 161 to 163 may be composed of a single layer, or may be composed of a plurality of layers having different types and concentrations of the p-type dopant. The thickness of the first to third p-type semiconductor layers 161 to 163 is, for example, 50 to 200 nm.

<n型電極及びp型電極>
本実施形態に係る多波長発光素子100は、第1〜第3n型半導体層141〜143に電気的に接続するように設けられた第1〜第3n型電極171〜173、及び第1〜第3p型半導体層161〜163に電気的に接続するように設けられた第1〜第3p型電極181〜183を備えている。
<N-type electrode and p-type electrode>
The multi-wavelength light emitting device 100 according to the present embodiment includes first to third n-type electrodes 171 to 173 and first to first electrodes provided to be electrically connected to the first to third n-type semiconductor layers 141 to 143. First to third p-type electrodes 181 to 183 are provided so as to be electrically connected to the 3p-type semiconductor layers 161 to 163.

第1〜第3n型電極171〜173の構成電極材料としては、例えば、Ti/Al、Ti/Al/Mo/Au、Hf/Au等の積層構造、或いは合金等が挙げられる。第1〜第3n型電極171〜173の厚さは例えばTi/Al(10nm/500nm)である。   Examples of the constituent electrode material of the first to third n-type electrodes 171 to 173 include a laminated structure such as Ti / Al, Ti / Al / Mo / Au, and Hf / Au, or an alloy. The thicknesses of the first to third n-type electrodes 171 to 173 are, for example, Ti / Al (10 nm / 500 nm).

第1〜第3p型電極181〜183としては、例えば、Pd/Pt/Au、Ni/Au、Pd/Mo/Au等の積層構造、或いは合金等、又はITO(酸化インジウム錫)などの酸化物系透明導電材料が挙げられる。なお、第1〜第3p型電極181〜183の上にはワイヤーボンディング用のパッド電極が必要であり、多くの場合は第1〜第3n型電極171〜173と同じ材料系が用いられる。第1〜第3p型電極181〜183の厚さは例えばITOの場合10〜200nmである。   Examples of the first to third p-type electrodes 181 to 183 include a laminated structure such as Pd / Pt / Au, Ni / Au, and Pd / Mo / Au, an alloy, or an oxide such as ITO (indium tin oxide). System transparent conductive material. Note that pad electrodes for wire bonding are necessary on the first to third p-type electrodes 181 to 183, and in many cases, the same material system as that of the first to third n-type electrodes 171 to 173 is used. The thickness of the first to third p-type electrodes 181 to 183 is, for example, 10 to 200 nm in the case of ITO.

(多波長発光素子の製造方法)
次に、本実施形態に係る多波長発光素子100の製造方法について図5(a)〜(f)に基づいて説明する。以下の本実施形態に係る多波長発光素子100の製造方法では、ウエハ110’(基板110)上に第1〜第3u-半導体層131〜133としてのu-GaN層、第1〜第3n型半導体層141〜143としてのSiをドープしたn型GaN層、第1〜第3発光層151〜153としての多重量子井戸層(第1〜第3井戸層151a〜153a:InGaN層、第1〜第3障壁層151b〜153b:GaN層)、及び第1〜第3p型半導体層161〜163としてのMgをドープしたp型GaN層の各半導体層を順に形成した後、第1〜第3n型GaN層141〜143及び第1〜第3p型GaN層161〜163の上に第1〜第3n型電極171〜173及び第1〜第3p型電極181〜183をそれぞれ形成するものを例とする。
(Manufacturing method of multi-wavelength light emitting device)
Next, a method for manufacturing the multi-wavelength light emitting device 100 according to the present embodiment will be described with reference to FIGS. In the manufacturing method of the multi-wavelength light emitting device 100 according to the following embodiment, u-GaN layers as first to third u-semiconductor layers 131 to 133 on the wafer 110 '(substrate 110), first to third n-type. N-type GaN layer doped with Si as the semiconductor layers 141 to 143, multiple quantum well layers as the first to third light emitting layers 151 to 153 (first to third well layers 151a to 153a: InGaN layers, first to first Third barrier layers 151b to 153b: GaN layers) and Mg-doped p-type GaN layers as first to third p-type semiconductor layers 161 to 163 are sequentially formed, and then first to third n-type semiconductor layers are formed. For example, the first to third n-type electrodes 171 to 173 and the first to third p-type electrodes 181 to 183 are formed on the GaN layers 141 to 143 and the first to third p-type GaN layers 161 to 163, respectively. .

<ウエハ(基板)準備工程>
ウエハ110’の各多波長発光素子100の形成領域において、図5(a)に示すように、凹溝形成予定部分だけが開口部となるようにフォトレジストのパターニングを形成し、図5(b)に示すように、フォトレジスト200をエッチングレジストとしてエッチングすることにより、ウエハ110’の表面に第1及び第2凹溝111,112を形成した後、フォトレジスト200を除去する。
<Wafer (substrate) preparation process>
In the formation region of each multi-wavelength light emitting element 100 on the wafer 110 ′, as shown in FIG. 5A, the photoresist patterning is formed so that only the groove formation planned portion becomes an opening. As shown in FIG. 2B, the photoresist 200 is etched using the photoresist 200 as an etching resist to form the first and second concave grooves 111 and 112 on the surface of the wafer 110 ′, and then the photoresist 200 is removed.

このとき、ウエハ110’の各多波長発光素子100の形成領域には、表面に、相互に面方位が異なる第1結晶成長面121である基板110の主面、第2結晶成長面122である第1凹溝111の一方の側面、及び第3結晶成長面123である第2凹溝112の一方の側面が露出する。   At this time, in the formation region of each multi-wavelength light emitting device 100 of the wafer 110 ′, the main surface of the substrate 110 and the second crystal growth surface 122 are the first crystal growth surfaces 121 having different plane orientations on the surface. One side surface of the first concave groove 111 and one side surface of the second concave groove 112 that is the third crystal growth surface 123 are exposed.

<半導体層の形成工程>
以下の各半導体層の形成方法としては、有機金属気相成長法(Metal Organic Vapor Phase Epitaxy:MOVPE)、分子線エピタキシ法(Molecular Beam Epitaxy:MBE)、ハイドライド気相成長法(Hydride Vapor Phase Epitaxy:HVPE)等が挙げられ、これらのうち有機金属気相成長法が最も一般的である。以下では、有機金属気相成長法を利用した各半導体層の形成方法について説明する。
<Semiconductor layer formation process>
The following methods for forming each semiconductor layer include metal organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (Hyride Vapor Phase Epitaxy). HVPE) and the like, and among these, metalorganic vapor phase epitaxy is the most common. Below, the formation method of each semiconductor layer using a metal organic chemical vapor deposition method is demonstrated.

各半導体層の形成に用いるMOVPE装置は、各々、電子制御される、ウエハ搬送系、ウエハ加熱系、ガス供給系、及びガス排気系で構成されている。ウエハ加熱系は、熱電対及び抵抗加熱ヒータ、その上に設けられた炭素製或いはSiC製のサセプタで構成されている。そして、MOVPE装置は、ウエハ加熱系において、搬送される石英トレイのサセプタの上にセットされたウエハ110’上に反応ガスにより半導体層を結晶成長させるように構成されている。   The MOVPE apparatus used for forming each semiconductor layer includes a wafer transfer system, a wafer heating system, a gas supply system, and a gas exhaust system, which are electronically controlled. The wafer heating system is composed of a thermocouple, a resistance heater, and a carbon or SiC susceptor provided thereon. The MOVPE apparatus is configured so that a semiconductor layer is crystal-grown by a reactive gas on a wafer 110 'set on a susceptor of a quartz tray to be conveyed in a wafer heating system.

−u-GaN層形成工程−
上記MOVPE装置を用い、表面に第1及び第2凹溝111,112を形成加工したウエハ110’を、表面が上向きになるように石英トレイ上にセットした後、ウエハ110’を1050〜1150℃に加熱すると共に反応容器内の圧力を10k〜100kPaとし、また、反応容器内に設置したフローチャネル内にキャリアガスとしてH2を流通させ、その状態を数分間保持することによりウエハ110’をサーマルクリーニングする。
-U-GaN layer formation process-
Using the MOVPE apparatus, the wafer 110 ′ having the first and second concave grooves 111 and 112 formed on the surface is set on a quartz tray so that the surface faces upward. And the pressure in the reaction vessel is set to 10 to 100 kPa, and H 2 is circulated as a carrier gas in a flow channel installed in the reaction vessel, and this state is maintained for several minutes to thermally Clean it.

次いで、ウエハ110’の温度を1050〜1150℃とすると共に反応容器内の圧力を10k〜100kPaとし、また、反応容器内にキャリアガスH2を10L/min程度の流量で流通させながら、そこに反応ガスとして、V族元素供給源(NH3)、及びIII族元素供給源(TMG)を、それぞれの供給流量が0.1〜5L/min、及び50〜150μmol/minとなるように流す。 Next, the temperature of the wafer 110 ′ is set to 1050 to 1150 ° C., the pressure in the reaction vessel is set to 10 to 100 kPa, and the carrier gas H 2 is circulated in the reaction vessel at a flow rate of about 10 L / min. As a reaction gas, a group V element supply source (NH 3 ) and a group III element supply source (TMG) are flowed so that the respective supply flow rates are 0.1 to 5 L / min and 50 to 150 μmol / min.

このとき、図5(c)に示すように、結晶成長条件の選択により、第1結晶成長面121である基板110の主面を起点として、アンドープのGaNが基板110上に積層するように結晶成長して第1u-GaN層131が形成され、それによって第1発光領域A1が構成される。また、第2結晶成長面122である第1凹溝111の一方の側面を起点として、アンドープのGaNが基板110上に積層するように結晶成長して第2u-GaN層132が形成され、それによって第2発光領域A2が構成される。さらに、第3結晶成長面123である第2凹溝112の一方の側面を起点として、アンドープのGaNが基板110上に積層するように結晶成長して第3u-GaN層133が形成され、それによって第3発光領域A3が構成される。   At this time, as shown in FIG. 5C, the crystal growth condition is selected so that the undoped GaN is stacked on the substrate 110 starting from the main surface of the substrate 110 which is the first crystal growth surface 121. The first u-GaN layer 131 is grown to form the first light emitting region A1. The second u-GaN layer 132 is formed by crystal growth so that undoped GaN is stacked on the substrate 110 starting from one side surface of the first concave groove 111 that is the second crystal growth surface 122. Thus, the second light emitting area A2 is configured. Further, the third u-GaN layer 133 is formed by crystal growth so that undoped GaN is stacked on the substrate 110 starting from one side surface of the second concave groove 112 which is the third crystal growth surface 123. Constitutes the third light emitting region A3.

第1〜第3u-GaN層131〜133は、それぞれ第1〜第3結晶成長面121〜123を起点として結晶成長して形成されることにより相互に異なる面方位の主面を有することとなる。   The first to third u-GaN layers 131 to 133 are formed by crystal growth starting from the first to third crystal growth surfaces 121 to 123, respectively, and thus have principal surfaces with different plane orientations. .

第1〜第3u-GaN層131〜133は、結晶成長条件の選択により、或いは、結晶成長させない部分にマスク等して、個別に結晶成長させて形成してもよく、また、結晶成長条件の選択により、第1〜第3u-GaN層131〜133のうち2つ又は全部を同時に結晶成長させて形成してもよい。   The first to third u-GaN layers 131 to 133 may be formed by individually growing a crystal by selecting a crystal growth condition or by masking a portion where the crystal is not grown. Depending on selection, two or all of the first to third u-GaN layers 131 to 133 may be formed by crystal growth at the same time.

なお、第1〜第3u-GaN層131〜133を形成する前に低温バッファ層を形成する場合には、ウエハ110’の温度を400〜500℃としてGaNを結晶成長させればよい。また、ウエハ110’における第1〜第3発光領域A1〜A3以外の部分にはマスクを設けておいてもよい。   In the case where the low temperature buffer layer is formed before the first to third u-GaN layers 131 to 133 are formed, the temperature of the wafer 110 ′ may be set to 400 to 500 ° C. and GaN may be grown. Further, a mask may be provided in a portion other than the first to third light emitting areas A1 to A3 in the wafer 110 '.

−n型GaN層形成工程−
反応容器内の圧力を10k〜100kPaとし、また、反応容器内にキャリアガスH2を5〜15L/min(以下、ガス流量は基準状態(0℃、1気圧)での値とする)の流量で流通させながら、そこに反応ガスとして、V族元素供給源(NH3)、III族元素供給源1(TMG)、及びn型ドーピング元素供給源(SiH4)を、それぞれの供給流量が0.1〜5L/min、50〜150μmol/min、及び1〜5×10-3μmol/minとなるように流す。
-N-type GaN layer formation process-
The pressure in the reaction vessel is 10 to 100 kPa, and the carrier gas H 2 is in the reaction vessel at a flow rate of 5 to 15 L / min (hereinafter, the gas flow rate is a value in a standard state (0 ° C., 1 atm)). As a reaction gas, a group V element supply source (NH 3 ), a group III element supply source 1 (TMG), and an n-type doping element supply source (SiH 4 ) are supplied as 0, respectively. . 1-5 L / min, 50-150 μmol / min, and 1-5 × 10 −3 μmol / min.

このとき、図5(d)に示すように、結晶成長条件の選択により、第1〜第3u-GaN層131〜133の主面を起点として、n型ドーパントであるSiがドープされたGaNが第1〜第3u-GaN層131〜133上に積層するようにエピタキシャル結晶成長して第1〜第3n型GaN層141〜143が形成される。従って、第1〜第3n型GaN層141〜143もまた、第1〜第3u-GaN層131〜133と同様、相互に異なる面方位の主面を有することとなる。   At this time, as shown in FIG. 5D, GaN doped with Si, which is an n-type dopant, starts from the main surface of the first to third u-GaN layers 131 to 133 by selecting crystal growth conditions. The first to third n-type GaN layers 141 to 143 are formed by epitaxial crystal growth so as to be stacked on the first to third u-GaN layers 131 to 133. Accordingly, the first to third n-type GaN layers 141 to 143 also have principal surfaces with different plane orientations, like the first to third u-GaN layers 131 to 133.

第1〜第3n型GaN層141〜143は、結晶成長条件の選択により、或いは、結晶成長させない部分にマスク等して、個別に結晶成長させて形成してもよく、また、結晶成長条件の選択により、第1〜第3n型GaN層141〜143のうち2つ又は全部を同時に結晶成長させて形成してもよい。   The first to third n-type GaN layers 141 to 143 may be formed by crystal growth individually by selecting crystal growth conditions or by masking a portion where crystal growth is not performed. Depending on selection, two or all of the first to third n-type GaN layers 141 to 143 may be formed by crystal growth at the same time.

−発光層形成工程−
ウエハ110’の温度を800℃程度とすると共に反応容器内の圧力を10k〜100kPaとし、また、反応容器内にキャリアガスN2を5〜15L/minの流量で流通させながら、そこに反応ガスとして、V族元素供給源(NH3)、III族元素供給源1(TMG)、及びIII族元素供給源2(TMI)を、それぞれの供給流量が0.1〜5L/min、5〜15μmol/min、及び2〜30μmol/min流す。
-Light emitting layer formation process-
The temperature of the wafer 110 ′ is set to about 800 ° C., the pressure in the reaction vessel is set to 10 k to 100 kPa, and the carrier gas N 2 is circulated at a flow rate of 5 to 15 L / min in the reaction vessel while the reaction gas is supplied there. As a group V element supply source (NH 3 ), a group III element supply source 1 (TMG), and a group III element supply source 2 (TMI), the respective supply flow rates are 0.1 to 5 L / min, 5 to 15 μmol. / Min, and 2 to 30 μmol / min.

このとき、結晶成長条件の選択により、第1〜第3n型GaN層141〜143の主面を起点として、InGaNが第1〜第3n型GaN層141〜143に積層するようにエピタキシャル結晶成長して第1〜第3井戸層151a〜153aが同時に形成される。   At this time, by selecting the crystal growth conditions, epitaxial crystal growth is performed so that InGaN is stacked on the first to third n-type GaN layers 141 to 143 starting from the main surfaces of the first to third n-type GaN layers 141 to 143. Thus, the first to third well layers 151a to 153a are formed simultaneously.

次いで、V族元素供給源(NH3 )、及びIII族元素供給源(TMG)を、それぞれの供給流量が0.1〜5L/min、及び5〜15μmol/minとなるように流す。 Next, the group V element supply source (NH 3 ) and the group III element supply source (TMG) are flowed so that the respective supply flow rates are 0.1 to 5 L / min and 5 to 15 μmol / min.

このとき、結晶成長条件の選択により、第1〜第3井戸層151a〜153aの主面を起点として、GaNが第1〜第3井戸層151a〜153aに積層するようにエピタキシャル結晶成長して第1〜第3障壁層151b〜153bが同時に形成される。   At this time, by selecting the crystal growth conditions, epitaxial crystals are grown so that GaN is stacked on the first to third well layers 151a to 153a starting from the main surfaces of the first to third well layers 151a to 153a. The first to third barrier layers 151b to 153b are formed at the same time.

そして、上記と同様の操作を交互に繰り返すことにより、図5(e)に示すように、第1〜第3井戸層151a〜153aと第1〜第3障壁層151b〜153bとが交互に積層された多重量子井戸層の第1〜第3発光層151〜153を形成する。   Then, by repeating the same operation as described above, the first to third well layers 151a to 153a and the first to third barrier layers 151b to 153b are alternately stacked as shown in FIG. First to third light emitting layers 151 to 153 of the formed multiple quantum well layer are formed.

ここで、第1〜第3発光層151〜153が相互に異なる結晶面を主面とする第1〜第3n型半導体層141〜143、従って、第1〜第3u-半導体層131〜133の主面と同一の結晶面を主面とするので、第1〜第3発光層151〜153における第1〜第3井戸層151a〜153a内へのInNの取り込まれ効率が相異し、そのため、元素組成比が相互に異なる、及び/又は、層厚が相互に異なることとなる。その結果、第1〜第3発光層151〜153は相互に異なる波長の光を発光するように構成されることとなる。なお、第1〜第3発光層151〜153の発光波長は、第1〜第3井戸層151a〜153aの井戸幅(厚み)及びInN混晶比に依存するが、InN混晶比が高いほど発光波長は長波長となる。InN混晶比はTMIのモル流量/(TMGのモル流量+TMIのモル流量)と成長温度によって決定される。   Here, the first to third n-type semiconductor layers 141 to 143 whose main surfaces are different crystal planes of the first to third light emitting layers 151 to 153, and accordingly, the first to third u− semiconductor layers 131 to 133. Since the same crystal plane as the main surface is used as the main surface, the efficiency of incorporation of InN into the first to third well layers 151a to 153a in the first to third light emitting layers 151 to 153 is different. The elemental composition ratios are different from each other and / or the layer thicknesses are different from each other. As a result, the first to third light emitting layers 151 to 153 are configured to emit light having different wavelengths. The emission wavelengths of the first to third light emitting layers 151 to 153 depend on the well width (thickness) and the InN mixed crystal ratio of the first to third well layers 151a to 153a, but the higher the InN mixed crystal ratio, the higher the InN mixed crystal ratio. The emission wavelength is a long wavelength. The InN mixed crystal ratio is determined by the TMI molar flow rate / (TMG molar flow rate + TMI molar flow rate) and the growth temperature.

以上のように、本実施形態に係る多波長発光素子100の製造方法によれば、面方位が相互に異なる第1〜第3結晶成長面121〜123から半導体が結晶成長して形成された、主面の結晶面が相互に異なる第1〜第3u-GaN層131〜133上には、同一の構成元素で且つ元素組成比が異なる半導体が結晶成長しても、及び/又は、同一の構成元素の半導体が層厚が異なって結晶成長しても、発光波長が異なる第1〜第3井戸層151a〜153aが形成され得ることから、第1〜第3半導体発光層151〜153を同一工程で形成することができ、従って、多波長発光素子100の効率的な製造が可能となる。   As described above, according to the method for manufacturing the multi-wavelength light emitting device 100 according to the present embodiment, the semiconductor is formed by crystal growth from the first to third crystal growth surfaces 121 to 123 having different plane orientations. Even if semiconductors having the same constituent elements and different element composition ratios grow on the first to third u-GaN layers 131 to 133 whose main surface crystal planes are different from each other, and / or have the same configuration Since the first to third well layers 151a to 153a having different emission wavelengths can be formed even if the elemental semiconductor has different crystal thickness and crystal growth, the first to third semiconductor light emitting layers 151 to 153 are formed in the same process. Therefore, the multi-wavelength light emitting device 100 can be efficiently manufactured.

−p型GaN層の形成−
ウエハ110’の温度を1000〜1100℃とすると共に反応容器内の圧力を10k〜100kPaとし、また、反応容器内にキャリアガスのH2を5〜15L/minの流量で流通させながら、そこに反応ガスとして、V族元素供給源(NH3)、III族元素供給源1(TMG)、III族元素供給源3(TMA)、及びp型ドーピング元素供給源(Cp2Mg)を、それぞれの供給流量0.1〜5L/min、50〜150μmol/min、2〜80μmol/min、及び0.03〜30μmol/min流す。
-Formation of p-type GaN layer-
The temperature of the wafer 110 ′ is 1000 to 1100 ° C., the pressure in the reaction vessel is 10 k to 100 kPa, and the carrier gas H 2 is circulated at a flow rate of 5 to 15 L / min in the reaction vessel. As a reaction gas, a group V element supply source (NH 3 ), a group III element supply source 1 (TMG), a group III element supply source 3 (TMA), and a p-type doping element supply source (Cp 2 Mg) are respectively used. Supply flow rate is 0.1 to 5 L / min, 50 to 150 μmol / min, 2 to 80 μmol / min, and 0.03 to 30 μmol / min.

このとき、図5(f)に示すように、結晶成長条件の選択により、第1〜第3発光層151〜153の主面を起点として、p型ドーパントであるMgがドープされたGaNが第1〜第3発光層151〜153上に積層するように結晶成長して第1〜第3p型GaN層161〜163が形成される。   At this time, as shown in FIG. 5 (f), by selecting the crystal growth conditions, GaN doped with Mg, which is a p-type dopant, starts from the main surfaces of the first to third light emitting layers 151 to 153. The first to third p-type GaN layers 161 to 163 are formed by crystal growth so as to be stacked on the first to third light emitting layers 151 to 153.

<n型電極及びp型電極形成工程>
ウエハ110’上に積層形成した半導体層を部分的に反応性イオンエッチングすることにより第1〜第3n型GaN層141〜143を露出させた後、真空蒸着、スパッタリング、CVD(Chemical Vapor Deposition)等の方法により第1〜第3n型GaN層141〜143上に第1〜第3n型電極171〜173及び第1〜第3p型GaN層161〜163上に第1〜第3p型電極181〜183をそれぞれ形成する。
<N-type electrode and p-type electrode formation step>
After the first to third n-type GaN layers 141 to 143 are exposed by partially reactive ion etching of the semiconductor layer formed on the wafer 110 ′, vacuum deposition, sputtering, CVD (Chemical Vapor Deposition), etc. The first to third n-type electrodes 171 to 173 on the first to third n-type GaN layers 141 to 143 and the first to third p-type electrodes 181 to 183 on the first to third p-type GaN layers 161 to 163 by the above method. Respectively.

そして、ウエハ110’を劈開することにより個々に分断し、本実施形態に係る多波長発光素子100が製造される。   Then, the wafer 110 ′ is cleaved individually to produce the multi-wavelength light emitting device 100 according to this embodiment.

本発明は多波長発光素子及びその製造方法について有用である。   The present invention is useful for a multi-wavelength light emitting device and a method for manufacturing the same.

100 多波長発光素子
110 基板
110’ ウエハ
111 第1凹溝
112 第2凹溝
121〜123 第1〜第3結晶成長面
131〜133 第1〜第3u-半導体層(第1〜第3u-GaN層)
141〜143 第1〜第3n型半導体層(第1〜第3n型GaN層)
151〜153 第1〜第3発光層
151a〜153a 第1〜第3井戸層(第1〜第3半導体発光層)
151b〜153b 第1〜第3障壁層
161〜163 第1〜第3p型半導体層(第1〜第3p型GaN層)
171〜173 第1〜第3n型電極
181〜183 第1〜第3p型電極
200 フォトレジスト
A1〜A3 第1〜第3発光領域
100 Multi-wavelength light emitting device 110 Substrate 110 ′ Wafer 111 First concave groove 112 Second concave groove 121-123 First to third crystal growth surfaces 131-133 First to third u-semiconductor layers (first to third u-GaN layer)
141-143 First to third n-type semiconductor layers (first to third n-type GaN layers)
151-153 1st-3rd light emitting layer 151a-153a 1st-3rd well layer (1st-3rd semiconductor light emitting layer)
151b to 153b First to third barrier layers 161 to 163 First to third p-type semiconductor layers (first to third p-type GaN layers)
171 to 173 First to third n-type electrodes 181 to 183 First to third p-type electrodes 200 Photoresist A1 to A3 First to third light emitting regions

Claims (7)

表面に面方位が相互に異なる第1及び第2結晶成長面を有すると共に該第1及び第2結晶成長面に対応する第1及び第2発光領域が構成された基板と、
上記基板上の上記第1発光領域に積層されるように設けられ上記第1結晶成長面を起点として半導体が結晶成長して形成された第1半導体層と、
上記第1半導体層上に積層されるように設けられ半導体が結晶成長して形成された所定の波長の光を発光する第1半導体発光層と、
上記基板上の上記第2発光領域に積層されるように設けられ上記第2結晶成長面を起点として半導体が結晶成長して形成された、上記第1半導体層の主面とは異なる結晶面を主面とする第2半導体層と、
上記第2半導体層上に積層されるように設けられ、上記第1半導体発光層を形成する半導体と同一の構成元素で且つ元素組成比が異なる半導体が結晶成長して形成された、及び/又は、上記第1半導体発光層を形成する半導体と同一の構成元素の半導体が結晶成長して形成され且つ上記第1半導体発光層とは層厚が異なる、上記第1半導体発光層が発光する光の波長と異なる波長の光を発光する第2半導体発光層と、
を備えた多波長発光素子。
A substrate having first and second crystal growth planes having different plane orientations on the surface, and first and second light emitting regions corresponding to the first and second crystal growth planes;
A first semiconductor layer provided to be stacked on the first light emitting region on the substrate and formed by crystal growth of a semiconductor from the first crystal growth surface;
A first semiconductor light emitting layer configured to be laminated on the first semiconductor layer and emitting light of a predetermined wavelength formed by crystal growth of a semiconductor;
A crystal plane different from the main surface of the first semiconductor layer, which is provided so as to be stacked on the second light emitting region on the substrate and is formed by crystal growth of a semiconductor starting from the second crystal growth plane. A second semiconductor layer as a main surface;
A semiconductor which is provided so as to be stacked on the second semiconductor layer and has the same constituent element as the semiconductor forming the first semiconductor light emitting layer and has a different element composition ratio is formed by crystal growth; and / or The light of the light emitted by the first semiconductor light-emitting layer is formed by crystal growth of a semiconductor having the same constituent element as the semiconductor forming the first semiconductor light-emitting layer and having a layer thickness different from that of the first semiconductor light-emitting layer. A second semiconductor light emitting layer that emits light of a wavelength different from the wavelength;
A multi-wavelength light emitting device comprising:
請求項1に記載された多波長発光素子において、
上記第1及び第2結晶成長面のうち一方が上記基板の表面に形成された凹溝の側面である多波長発光素子。
The multi-wavelength light emitting device according to claim 1,
One of the said 1st and 2nd crystal growth surfaces is a multiwavelength light emitting element which is a side surface of the ditch | groove formed in the surface of the said board | substrate.
請求項2に記載された多波長発光素子において、
上記第1及び第2結晶成長面のうち他方が上記基板の主面である多波長発光素子。
The multi-wavelength light emitting device according to claim 2,
The multi-wavelength light emitting device, wherein the other of the first and second crystal growth surfaces is the main surface of the substrate.
請求項1乃至3のいずれかに記載された多波長発光素子において、
上記第1及び第2半導体層を形成する半導体がGaNであると共に、上記第1及び第2半導体発光層を形成する半導体がInGaNである多波長発光素子。
The multi-wavelength light emitting device according to any one of claims 1 to 3,
A multi-wavelength light emitting device in which the semiconductor forming the first and second semiconductor layers is GaN, and the semiconductor forming the first and second semiconductor light emitting layers is InGaN.
請求項1乃至4のいずれかに記載された多波長発光素子において、
上記基板がサファイア基板である多波長発光素子。
The multi-wavelength light emitting device according to any one of claims 1 to 4,
A multi-wavelength light emitting device in which the substrate is a sapphire substrate.
請求項1乃至5のいずれかに記載された多波長発光素子において、
上記基板は、表面に、上記第1及び第2結晶成長面とは面方位が異なる第3結晶成長面を有すると共に該第3結晶成長面に対応する第3発光領域が構成されており、
上記基板上の上記第3発光領域に積層されるように設けられ上記第3結晶成長面を起点として半導体が結晶成長して形成された、上記第1及び第2半導体層の主面とは異なる結晶面を主面とする第3半導体層と、
上記第3半導体層上に積層されるように設けられ、上記第1及び第2半導体発光層を形成する半導体と同一の構成元素で且つ元素組成比が異なる半導体が結晶成長して形成された、及び/又は、上記第1及び第2半導体発光層を形成する半導体と同一の構成元素の半導体が結晶成長して形成され且つ上記第1及び第2半導体発光層とは層厚が異なる、上記第1及び第2半導体発光層が発光する光の波長と異なる波長の光を発光する第3半導体発光層と、
をさらに備えた多波長発光素子。
The multi-wavelength light emitting device according to any one of claims 1 to 5,
The substrate has a third crystal growth surface having a surface orientation different from that of the first and second crystal growth surfaces on the surface, and a third light emitting region corresponding to the third crystal growth surface is formed.
Different from the main surfaces of the first and second semiconductor layers provided to be stacked on the third light emitting region on the substrate and formed by crystal growth of the semiconductor starting from the third crystal growth surface. A third semiconductor layer having a crystal plane as a main surface;
A semiconductor that is provided so as to be stacked on the third semiconductor layer and that has the same constituent element as the semiconductor forming the first and second semiconductor light emitting layers and has a different element composition ratio is formed by crystal growth; And / or a semiconductor having the same constituent element as that of the semiconductor forming the first and second semiconductor light emitting layers is formed by crystal growth and has a layer thickness different from that of the first and second semiconductor light emitting layers. A third semiconductor light emitting layer that emits light having a wavelength different from that of light emitted by the first and second semiconductor light emitting layers;
A multi-wavelength light emitting device further comprising:
表面に面方位が相互に異なる第1及び第2結晶成長面を有する基板を準備する準備工程と、
上記準備工程で準備した基板の第1結晶成長面を起点として半導体を結晶成長させることにより、基板上に第1発光領域を構成して積層するように第1半導体層を形成する第1半導体層形成工程と、
上記準備工程で準備した基板の第2結晶成長面を起点として半導体を結晶成長させることにより、基板上に第2発光領域を構成して積層するように、第1半導体層の主面とは異なる結晶面を主面とする第2半導体層を形成する第2半導体層形成工程と、
上記第1半導体層形成工程で形成した第1半導体層上に積層するように半導体を結晶成長させて所定の波長の光を発光する第1半導体発光層を形成すると同時に、上記第2半導体層形成工程で形成した第2半導体層上に積層するように、上記第1半導体発光層を形成する半導体と同一の構成元素で且つ元素組成比が異なる半導体を結晶成長させて、及び/又は、上記第1半導体発光層を形成する半導体と同一の構成元素の半導体を、上記第1半導体発光層とは層厚が異なるように結晶成長させて、上記第1半導体発光層が発光する光の波長と異なる波長の光を発光する第2半導体発光層を形成する第1及び第2半導体発光層形成工程と、
を備えた多波長発光素子の製造方法。
Preparing a substrate having first and second crystal growth surfaces having different plane orientations on the surface;
A first semiconductor layer that forms a first light emitting region on the substrate to form a first semiconductor layer by crystal growth of the semiconductor starting from the first crystal growth surface of the substrate prepared in the preparation step Forming process;
Different from the main surface of the first semiconductor layer so that the second light emitting region is formed and stacked on the substrate by crystal growth of the semiconductor starting from the second crystal growth surface of the substrate prepared in the preparation step. A second semiconductor layer forming step of forming a second semiconductor layer having a crystal plane as a main surface;
At the same time as forming the first semiconductor light emitting layer for emitting light of a predetermined wavelength by crystal growth of the semiconductor so as to be laminated on the first semiconductor layer formed in the first semiconductor layer forming step, the second semiconductor layer formation is performed. A semiconductor having the same constituent element as that of the semiconductor forming the first semiconductor light emitting layer and having a different element composition ratio is crystal-grown so as to be stacked on the second semiconductor layer formed in the process and / or the first semiconductor layer is formed. A semiconductor having the same constituent elements as the semiconductor forming the semiconductor light emitting layer is crystal-grown so as to have a layer thickness different from that of the first semiconductor light emitting layer, so that the wavelength of light emitted by the first semiconductor light emitting layer is different. First and second semiconductor light emitting layer forming steps for forming a second semiconductor light emitting layer that emits light of a wavelength;
The manufacturing method of the multiwavelength light emitting element provided with.
JP2011053393A 2011-03-10 2011-03-10 Multi-wavelength light emitting device and manufacturing method thereof Expired - Fee Related JP5822190B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011053393A JP5822190B2 (en) 2011-03-10 2011-03-10 Multi-wavelength light emitting device and manufacturing method thereof
PCT/JP2012/001607 WO2012120891A1 (en) 2011-03-10 2012-03-08 Multi-wavelength light-emitting element and method of manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011053393A JP5822190B2 (en) 2011-03-10 2011-03-10 Multi-wavelength light emitting device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2012191013A true JP2012191013A (en) 2012-10-04
JP5822190B2 JP5822190B2 (en) 2015-11-24

Family

ID=46797862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011053393A Expired - Fee Related JP5822190B2 (en) 2011-03-10 2011-03-10 Multi-wavelength light emitting device and manufacturing method thereof

Country Status (2)

Country Link
JP (1) JP5822190B2 (en)
WO (1) WO2012120891A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018148074A (en) * 2017-03-07 2018-09-20 信越半導体株式会社 Light-emitting element and method for manufacturing the same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107894679B (en) * 2017-12-29 2023-01-10 苏州九骏电子科技有限公司 Backlight module and liquid crystal display device
CN110689814B (en) * 2018-07-05 2022-04-01 江西兆驰半导体有限公司 Multicolor micro LED array and manufacturing method thereof
WO2021140910A1 (en) * 2020-01-07 2021-07-15 ソニーグループ株式会社 Multi-wavelength light source, method of producing multi-wavelength light source, and display device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002026387A (en) * 2000-07-03 2002-01-25 Nobuhiko Sawaki Semiconductor element and its manufacturing method
JP2002185040A (en) * 2000-12-15 2002-06-28 Sony Corp Semiconductor light emitting element and manufacturing method therefor
JP2002335016A (en) * 2001-03-06 2002-11-22 Sony Corp Display unit and semiconductor light emitting element
WO2003010831A1 (en) * 2001-07-24 2003-02-06 Nichia Corporation Semiconductor light emitting device comprising uneven substrate
JP2003101156A (en) * 2001-09-26 2003-04-04 Toshiba Corp Semiconductor light-emitting device and manufacturing method therefor
JP2005129905A (en) * 2003-10-20 2005-05-19 Nichia Chem Ind Ltd Nitride semiconductor device and method of manufacturing the same
JP2009170610A (en) * 2008-01-15 2009-07-30 Mitsubishi Chemicals Corp GaN-BASED LED DEVICE AND ITS FABRICATION PROCESS
JP2010109147A (en) * 2008-10-30 2010-05-13 Sanyo Electric Co Ltd Light emitting element and method of manufacturing the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002026387A (en) * 2000-07-03 2002-01-25 Nobuhiko Sawaki Semiconductor element and its manufacturing method
JP2002185040A (en) * 2000-12-15 2002-06-28 Sony Corp Semiconductor light emitting element and manufacturing method therefor
JP2002335016A (en) * 2001-03-06 2002-11-22 Sony Corp Display unit and semiconductor light emitting element
WO2003010831A1 (en) * 2001-07-24 2003-02-06 Nichia Corporation Semiconductor light emitting device comprising uneven substrate
JP2003101156A (en) * 2001-09-26 2003-04-04 Toshiba Corp Semiconductor light-emitting device and manufacturing method therefor
JP2005129905A (en) * 2003-10-20 2005-05-19 Nichia Chem Ind Ltd Nitride semiconductor device and method of manufacturing the same
JP2009170610A (en) * 2008-01-15 2009-07-30 Mitsubishi Chemicals Corp GaN-BASED LED DEVICE AND ITS FABRICATION PROCESS
JP2010109147A (en) * 2008-10-30 2010-05-13 Sanyo Electric Co Ltd Light emitting element and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018148074A (en) * 2017-03-07 2018-09-20 信越半導体株式会社 Light-emitting element and method for manufacturing the same

Also Published As

Publication number Publication date
WO2012120891A1 (en) 2012-09-13
JP5822190B2 (en) 2015-11-24

Similar Documents

Publication Publication Date Title
JP5854419B2 (en) Multi-wavelength light emitting device and manufacturing method thereof
JP4140606B2 (en) GaN-based semiconductor light emitting device manufacturing method
US7695991B2 (en) Method for manufacturing GaN semiconductor light-emitting element
JP2001313259A (en) Method for producing iii nitride based compound semiconductor substrate and semiconductor element
JP2006114829A (en) Semiconductor device, its manufacturing method and substrate therefor
WO2003072856A1 (en) Process for producing group iii nitride compound semiconductor
TWI707482B (en) Nitride semiconductor light emitting element
KR20080110498A (en) Gan substrate, substrate with an epitaxial layer, semiconductor device, and gan substrate manufacturing method
JP6019541B2 (en) Semiconductor light emitting device
JP5060732B2 (en) LIGHT EMITTING ELEMENT AND METHOD FOR PRODUCING THE LIGHT EMITTING ELEMENT
JP5822190B2 (en) Multi-wavelength light emitting device and manufacturing method thereof
JP2007036174A (en) Gallium nitride-based light emitting diode
WO2014136393A1 (en) Processed substrate and semiconductor device using same
JP5557180B2 (en) Manufacturing method of semiconductor light emitting device
JP2011051863A (en) GaN SINGLE CRYSTAL SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, GaN-BASED SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE
JP2009141085A (en) Nitride semiconductor device
JP4523097B2 (en) Group III nitride compound semiconductor laser diode
JP2001345281A (en) Method of manufacturing nitride-based iii group compound semiconductor and nitride-based iii group compound semiconductor element
JP2008118048A (en) GaN-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE
JP4140595B2 (en) Gallium nitride compound semiconductor
JP4698053B2 (en) Method for producing group III nitride compound semiconductor
JP2007324421A (en) Nitride semiconductor element
JP5549158B2 (en) GaN single crystal substrate and manufacturing method thereof, and GaN-based semiconductor device and manufacturing method thereof
JP4172444B2 (en) Method for producing gallium nitride compound semiconductor
JP4055763B2 (en) Gallium nitride compound semiconductor and semiconductor substrate

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140307

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20141111

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150113

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150609

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150722

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150908

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150928

R150 Certificate of patent or registration of utility model

Ref document number: 5822190

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees