JP6019541B2 - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device Download PDF

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JP6019541B2
JP6019541B2 JP2014502031A JP2014502031A JP6019541B2 JP 6019541 B2 JP6019541 B2 JP 6019541B2 JP 2014502031 A JP2014502031 A JP 2014502031A JP 2014502031 A JP2014502031 A JP 2014502031A JP 6019541 B2 JP6019541 B2 JP 6019541B2
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semiconductor light
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JPWO2013128894A1 (en
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只友 一行
一行 只友
成仁 岡田
成仁 岡田
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NATIONAL UNIVERSITY CORPORATION YAMAGUCHI UNIVERSITY
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Description

本発明は半導体発光素子に関する。   The present invention relates to a semiconductor light emitting device.

半導体発光素子として、サファイア基板上にn型GaN層が設けられ、さらにその上にGaNとInGaNとが交互に積層されて構成された多重量子井戸層が設けられた構造は公知である。   As a semiconductor light emitting device, a structure in which an n-type GaN layer is provided on a sapphire substrate and a multiple quantum well layer formed by alternately stacking GaN and InGaN on the sapphire substrate is known.

また、特許文献1には、サファイア基板上にバッファ層を介してn型GaN層が設けられ、そして、その上にノンドープのInGa1−aN(0.01≦a≦0.05)で形成された厚さ180nmの歪み緩和層が設けられ、さらにその上にGaNとInGaNとが交互に積層されて構成された多重量子井戸層が設けられ、サファイア基板と多重量子井戸層との熱膨張係数の差異により発生する歪みによる応力を歪み緩和層により緩和した半導体発光素子が開示されている。In Patent Document 1, an n-type GaN layer is provided on a sapphire substrate via a buffer layer, and non-doped In a Ga 1-a N (0.01 ≦ a ≦ 0.05) is formed thereon. A strain relaxation layer having a thickness of 180 nm formed in step (b) is provided, and a multiple quantum well layer formed by alternately stacking GaN and InGaN is provided on the strain relaxation layer, and the heat of the sapphire substrate and the multiple quantum well layer is provided. A semiconductor light emitting device is disclosed in which stress due to strain generated by a difference in expansion coefficient is relaxed by a strain relaxation layer.

特開平11−233824号公報Japanese Patent Laid-Open No. 11-233824

本発明は、主面が非極性面又は半極性面のGaN層と、
上記GaN層の直上にInGa1−xN(0<x<0.1)がエピタキシャル成長して形成され、n型ドーパントを含有した厚さ0.2μm以上のInGaN層と、
上記InGaN層の直上にエピタキシャル成長して形成され、InGaNで形成された井戸層を含む多重量子井戸層と、
を備え、
上記InGaN層は、上記GaN層との間の格子不整合による歪みが完全に又は部分的に緩和している半導体発光素子である。
The present invention comprises a GaN layer whose main surface is a nonpolar or semipolar surface,
In x Ga 1-x N (0 <x <0.1) is formed by epitaxial growth directly on the GaN layer, and includes an n-type dopant-containing InGaN layer having a thickness of 0.2 μm or more,
A multiple quantum well layer formed by epitaxial growth directly on the InGaN layer and including a well layer formed of InGaN;
With
The InGaN layer is a semiconductor light emitting device in which strain due to lattice mismatch with the GaN layer is completely or partially relaxed.

実施形態に係る半導体発光素子の断面図である。It is sectional drawing of the semiconductor light-emitting device concerning embodiment. (a)〜(e)は実施形態に係る半導体発光素子の製造方法の説明図である。(A)-(e) is explanatory drawing of the manufacturing method of the semiconductor light-emitting device based on embodiment. InGaN層のInの含有割合xとリファレンスを基準としたPL発光強度の倍率との関係を示すグラフである。It is a graph which shows the relationship between the content rate x of In of an InGaN layer, and the magnification of PL emitted light intensity on the basis of a reference. n型InGaN層の厚さと発光強度分布の半値全幅との関係を示すグラフである。It is a graph which shows the relationship between the thickness of an n-type InGaN layer, and the full width at half maximum of light emission intensity distribution.

以下、実施形態について図面に基づいて詳細に説明する。   Hereinafter, embodiments will be described in detail based on the drawings.

(半導体発光素子)
図1は実施形態に係る半導体発光素子10を示す。本実施形態に係る半導体発光素子10は、例えば半導体レーザや発光ダイオードとして好適に用いられるものである。
(Semiconductor light emitting device)
FIG. 1 shows a semiconductor light emitting device 10 according to an embodiment. The semiconductor light emitting device 10 according to the present embodiment is suitably used, for example, as a semiconductor laser or a light emitting diode.

本実施形態に係る半導体発光素子10は、基板11上に、u-GaN層12、n型GaN層13、n型InGaN層14、多重量子井戸層15、p型AlGaN層16、及びp型GaN層17が順に積層され、そして、エッチングにより露出したn型InGaN層14上にn型電極18及びp型GaN層17上にp型電極19がそれぞれ設けられた構成を有する。   The semiconductor light emitting device 10 according to this embodiment includes a u-GaN layer 12, an n-type GaN layer 13, an n-type InGaN layer 14, a multiple quantum well layer 15, a p-type AlGaN layer 16, and a p-type GaN on a substrate 11. The layer 17 is sequentially stacked, and the n-type electrode 18 and the p-type electrode 19 are respectively provided on the n-type InGaN layer 14 exposed by etching and the p-type GaN layer 17.

ここで、基板11としては、例えば、典型的にはサファイア基板(Alのコランダム構造の単結晶基板)が挙げられ、その他、ZnO基板、SiC基板等が挙げられる。また、基板11は、基板表面にエッチング等により微細凹凸を形成した加工基板であってもよく、また、基板表面に酸化窒化ケイ素(SiO)或いは窒化アルミニウム(AlN)等を部分的に設けて微細凹凸を形成した加工基板であってもよい。基板11は、例えば、発光素子の状態では矩形板状に形成されており、縦及び横のそれぞれが200〜1000μm、並びに厚さが50〜300μmである。Here, as the substrate 11, for example, a sapphire substrate (single crystal substrate having a corundum structure of Al 2 O 3 ) is typically exemplified, and other examples include a ZnO substrate and a SiC substrate. The substrate 11 may be a processed substrate in which fine irregularities are formed on the substrate surface by etching or the like, and silicon oxynitride (SiO x N y ) or aluminum nitride (AlN) or the like is partially formed on the substrate surface. It may be a processed substrate provided with fine irregularities. For example, the substrate 11 is formed in a rectangular plate shape in the state of the light emitting element, and has a vertical and horizontal length of 200 to 1000 μm and a thickness of 50 to 300 μm.

基板11の主面は、a面<{11−20}面>、c面<{0001}面>、m面<{1−100}面>、n面<{1−123}面>及びr面<{1−102}面>のいずれであってもよく、また、他の面方位の結晶面であってもよい。   The main surface of the substrate 11 is a plane <{11-20} plane>, c plane <{0001} plane>, m plane <{1-100} plane>, n plane <{1-123} plane> and r. Any of the planes <{1-102} plane>, or a crystal plane with another plane orientation may be used.

基板11の結晶成長面は、主面であってもよく、また、加工基板の凹凸の側面であってもよい。基板11の結晶成長面は、a面<{11−20}面>、c面<{0001}面>、m面<{1−100}面>、n面<{1−123}面>及びr面<{1−102}面>のいずれであってもよく、また、他の面方位の結晶面であってもよい。   The crystal growth surface of the substrate 11 may be a main surface, or may be an uneven side surface of a processed substrate. Crystal growth planes of the substrate 11 are a plane <{11-20} plane>, c plane <{0001} plane>, m plane <{1-100} plane>, n plane <{1-123} plane> and It may be any of the r-plane <{1-102} plane>, or may be a crystal plane with another plane orientation.

u-GaN層12は、基板11の結晶成長面からGaNがドーパントを含まずにエピタキシャル結晶成長して形成されている。u-GaN層12の厚さは例えば2〜20μmである。   The u-GaN layer 12 is formed by epitaxially growing GaN from the crystal growth surface of the substrate 11 without containing a dopant. The thickness of the u-GaN layer 12 is, for example, 2 to 20 μm.

u-GaN層12の主面は、非極性面又は半極性面であり、{11−22}面であってもよく、また、{10−11}面等の他の面方位の結晶面であってもよい。   The main surface of the u-GaN layer 12 is a nonpolar plane or a semipolar plane, and may be a {11-22} plane, or a crystal plane with another plane orientation such as a {10-11} plane. There may be.

n型GaN層13はあっても無くてもよい。n型GaN層13は、u-GaN層12の直上に、GaNがn型のドーパントを含んでu-GaN層12と同一面方位にエピタキシャル結晶成長して形成されており、従って、主面が非極性面又は半極性面である。n型ドーパントとしては、例えば、Si、Ge等が挙げられる。n型ドーパントの濃度は例えば1.0×1017〜1.0×1020/cmである。n型GaN層13の厚さは例えば2〜10μmである。The n-type GaN layer 13 may or may not be present. The n-type GaN layer 13 is formed by epitaxially growing GaN in the same plane direction as the u-GaN layer 12 including an n-type dopant immediately above the u-GaN layer 12. Nonpolar or semipolar surface. Examples of the n-type dopant include Si and Ge. The concentration of the n-type dopant is, for example, 1.0 × 10 17 to 1.0 × 10 20 / cm 3 . The thickness of the n-type GaN layer 13 is, for example, 2 to 10 μm.

n型InGaN層14は、n型GaN層13がある場合はその直上に、無い場合はGaN層12の直上に、InGa1−xNがn型のドーパントを含んでn型GaN層13と同一面方位にエピタキシャル結晶成長して形成されており、従って、主面が非極性面又は半極性面である。The n-type InGaN layer 14 is formed immediately above the n-type GaN layer 13 when there is the n-type GaN layer 13, and when not present, the n-type GaN layer 13 includes In x Ga 1-x N containing an n-type dopant. Therefore, the main surface is a nonpolar surface or a semipolar surface.

n型InGaN層14を形成するInGa1−xNは、Inの含有割合が0<x<0.1であり、好ましくは0<x<0.05であり、より好ましくは0.01<x<0.05である。n型ドーパントとしては、n型GaN層13の場合と同様、例えば、Si、Ge等が挙げられる。n型ドーパントの濃度は例えば1.0×1017〜1.0×1020/cmである。n型InGaN層14は、単一層で構成されていてもよく、また、n型ドーパントの種類や濃度の異なる複数の層で構成されていてもよい。In x Ga 1-x N forming the n-type InGaN layer 14 has an In content ratio of 0 <x <0.1, preferably 0 <x <0.05, and more preferably 0.01. <X <0.05. Examples of the n-type dopant include Si and Ge as in the case of the n-type GaN layer 13. The concentration of the n-type dopant is, for example, 1.0 × 10 17 to 1.0 × 10 20 / cm 3 . The n-type InGaN layer 14 may be composed of a single layer, or may be composed of a plurality of layers having different n-type dopant types and concentrations.

n型InGaN層14の厚さは0.2μm以上であるが、好ましくは0.2〜10μmであり、より好ましくは0.5〜5μmである。   The thickness of the n-type InGaN layer 14 is 0.2 μm or more, preferably 0.2 to 10 μm, and more preferably 0.5 to 5 μm.

そして、以上の構成のn型InGaN層14は、n型GaN層13との間の格子不整合による歪みが完全に又は部分的に緩和している。ここで、本出願において、「完全緩和」とは、InGaN層が下地のGaN層に対して100%緩和していることを意味し、「部分緩和」とは、緩和率>0であると定義する。   In the n-type InGaN layer 14 having the above-described configuration, strain due to lattice mismatch with the n-type GaN layer 13 is completely or partially relaxed. Here, in this application, “complete relaxation” means that the InGaN layer is 100% relaxed with respect to the underlying GaN layer, and “partial relaxation” is defined as a relaxation rate> 0. To do.

多重量子井戸層15は、n型InGaN層14の直上に、n型InGaN層14と同一面方位に半導体がエピタキシャル結晶成長して形成され、従って、主面が非極性面又は半極性面であり、そして、障壁層15aと井戸層15bの交互積層構造を有する。障壁層15a及び井戸層15bの層数は例えば3〜15層である。多重量子井戸層15は発光層を構成し、その発光波長は、可視領域の波長であって、具体的にはInGaNの発光領域の360〜640nmである。多重量子井戸層15は、紫色、青色、又は緑色に発光するように構成されていることが好ましく、紫色に発光するように構成されていることがより好ましい。ここで、紫色の発光波長域は380〜450nm、青色の発光波長域は450〜495nm、緑色の発光波長域は495〜570nmである。   The multiple quantum well layer 15 is formed by epitaxially growing a semiconductor in the same plane orientation as the n-type InGaN layer 14 immediately above the n-type InGaN layer 14, and thus the main surface is a nonpolar or semipolar surface. And it has the alternately laminated structure of the barrier layer 15a and the well layer 15b. The number of barrier layers 15a and well layers 15b is, for example, 3 to 15. The multiple quantum well layer 15 constitutes a light emitting layer, and its light emission wavelength is a wavelength in the visible region, specifically, 360 to 640 nm in the light emitting region of InGaN. The multiple quantum well layer 15 is preferably configured to emit purple, blue, or green light, and more preferably configured to emit purple light. Here, the purple emission wavelength range is 380 to 450 nm, the blue emission wavelength range is 450 to 495 nm, and the green emission wavelength range is 495 to 570 nm.

井戸層15bはInGa1−yNで形成されており、yはxよりも大きいことが好ましい。井戸層15bの厚さは例えば1〜20nmである。The well layer 15b is made of In y Ga 1-y N, and y is preferably larger than x. The thickness of the well layer 15b is, for example, 1 to 20 nm.

障壁層15aを形成する半導体は、例えばバンドギャップが井戸層15bよりも大きいGaN等が挙げられる。障壁層15aの厚さは例えば5〜20nmである。   Examples of the semiconductor forming the barrier layer 15a include GaN having a band gap larger than that of the well layer 15b. The thickness of the barrier layer 15a is, for example, 5 to 20 nm.

p型AlGaN層16は、多重量子井戸層15の直上に、AlGa1−zNがp型のドーパントを含んで多重量子井戸層15と同一面方位にエピタキシャル結晶成長して形成されており、従って、主面が非極性面又は半極性面である。p型AlGaN層16を形成するAlGa1−zNは、Alの含有割合が例えば0.05<z<0.3である。p型ドーパントとしては、例えば、Mg、C等が挙げられる。p型ドーパントの場合、アクセプタ準位が深く、ドーパント濃度と自由正孔濃度とが大きく異なることから、ホール効果で測定される自由正孔濃度を含有量評価指標とするが、その自由正孔濃度は例えば1.0×1017〜5×1018/cmである。p型AlGaN層16は、単一層で構成されていてもよく、また、p型ドーパントの種類や濃度の異なる複数の層で構成されていてもよい。p型AlGaN層16の厚さは例えば10〜30nmである。The p-type AlGaN layer 16 is formed immediately above the multiple quantum well layer 15 by epitaxially growing Al z Ga 1-z N containing a p-type dopant in the same plane orientation as the multiple quantum well layer 15. Therefore, the main surface is a nonpolar surface or a semipolar surface. Al z Ga 1-z N forming the p-type AlGaN layer 16 has an Al content ratio of, for example, 0.05 <z <0.3. Examples of the p-type dopant include Mg and C. In the case of a p-type dopant, since the acceptor level is deep and the dopant concentration and the free hole concentration differ greatly, the free hole concentration measured by the Hall effect is used as the content evaluation index. Is, for example, 1.0 × 10 17 to 5 × 10 18 / cm 3 . The p-type AlGaN layer 16 may be composed of a single layer, or may be composed of a plurality of layers having different types and concentrations of p-type dopants. The thickness of the p-type AlGaN layer 16 is, for example, 10 to 30 nm.

p型GaN層17は、p型AlGaN層16の直上に、GaNがp型のドーパントを含んでp型AlGaN層16と同一面方位にエピタキシャル結晶成長して形成されており、従って、主面が非極性面又は半極性面である。p型ドーパントとしては、p型AlGaN層16の場合と同様、例えば、Mg、C等が挙げられる。ホール効果測定で測定される自由正孔濃度は例えば2.0×1017〜10×1017/cmである。p型GaN層17は、単一層で構成されていてもよく、また、p型ドーパントの種類や濃度の異なる複数の層で構成されていてもよい。p型GaN層17の厚さは例えば50〜200nmである。The p-type GaN layer 17 is formed directly on the p-type AlGaN layer 16 by epitaxially growing GaN in the same plane orientation as that of the p-type AlGaN layer 16 including the p-type dopant. Nonpolar or semipolar surface. Examples of the p-type dopant include Mg and C as in the case of the p-type AlGaN layer 16. The free hole concentration measured by the Hall effect measurement is, for example, 2.0 × 10 17 to 10 × 10 17 / cm 3 . The p-type GaN layer 17 may be composed of a single layer, or may be composed of a plurality of layers having different types and concentrations of the p-type dopant. The thickness of the p-type GaN layer 17 is, for example, 50 to 200 nm.

なお、p型層については、これらのp型AlGaN層16及びp型GaN層17に限定されるものではなく、InGaN/GaNの超格子構造等の特殊な構造であってもよい。   The p-type layer is not limited to the p-type AlGaN layer 16 and the p-type GaN layer 17, and may be a special structure such as an InGaN / GaN superlattice structure.

n型電極18の構成電極材料としては、例えば、Cr/Au,Ti/Al、Ti/Al/Mo/Au、Hf/Au等の積層構造、或いは合金等が挙げられる。n型電極18の厚さは例えばTi/Al(10nm/500nm)である。   Examples of the constituent electrode material of the n-type electrode 18 include a laminated structure such as Cr / Au, Ti / Al, Ti / Al / Mo / Au, Hf / Au, or an alloy. The thickness of the n-type electrode 18 is, for example, Ti / Al (10 nm / 500 nm).

p型電極19としては、例えば、Pd/Pt/Au、Ni/Au、Pd/Mo/Au等の積層構造、或いは合金等、又はITO(酸化インジウム錫)などの酸化物系透明導電材料が挙げられる。p型電極19の厚さは例えばITOの場合10〜200nmである。p型電極19の上にはワイヤーボンディング用のパッド電極が必要であり、多くの場合はn型電極18と同じ材料系で作製される。   Examples of the p-type electrode 19 include a laminated structure such as Pd / Pt / Au, Ni / Au, and Pd / Mo / Au, an alloy, or an oxide-based transparent conductive material such as ITO (indium tin oxide). It is done. The thickness of the p-type electrode 19 is, for example, 10 to 200 nm for ITO. A pad electrode for wire bonding is necessary on the p-type electrode 19, and in many cases, it is made of the same material system as that of the n-type electrode 18.

ところで、主面が非極性面であるIII族窒化物半導体を用いた半導体発光素子では、その物性の利点から高い発光効率が期待されているが、実際には、多重量子井戸層に含まれるInGaNで形成された井戸層に欠陥が入りやすいといった構造的な欠点を有し、その物性の利点を十分に生かしきれていないという問題がある。   By the way, a semiconductor light emitting device using a group III nitride semiconductor whose main surface is a nonpolar surface is expected to have high luminous efficiency because of its physical properties, but actually, InGaN contained in a multiple quantum well layer. There is a problem that the well layer formed in (1) has a structural defect such that defects are likely to enter, and the advantages of the physical properties are not fully utilized.

これに対し、上記構成の本実施形態に係る半導体発光素子10では、n型GaN層13と多重量子井戸層15との間にInGaNの層が介設されており、そのため発光層での転位の発生が抑制される。また、n型ドーパントを含有する主面が非極性面又は半極性面のn型GaN層13と多重量子井戸層15との間に、InGa1−xN(0<x<0.1)がエピタキシャル成長して形成された、n型GaN層13と同型のn型ドーパントを含有した厚さ0.2μm以上のn型InGaN層14が介設され、しかも、そのn型InGaN層14がn型GaN層13との間の格子不整合による歪みが完全又は部分的に緩和し、そのため欠陥は貫通転位とならないため、n型InGaN層14の欠陥密度が下地のn型GaN層13と同等となることにより高い発光効率を得ることができる。具体的には、多重量子井戸層15の発光波長に対する発光強度分布の半値全幅が40nm以下であることが好ましく、35nm以下であることがより好ましい。なお、n型GaN層13が無く、u-GaN層12と多重量子井戸層15との間にn型InGaN層14が介設された構成であっても同様の作用効果を得ることができる。On the other hand, in the semiconductor light emitting device 10 according to this embodiment having the above-described configuration, an InGaN layer is interposed between the n-type GaN layer 13 and the multiple quantum well layer 15, and therefore, dislocations in the light emitting layer are eliminated. Occurrence is suppressed. Further, In x Ga 1-x N (0 <x <0.1) is provided between the n-type GaN layer 13 whose main surface containing the n-type dopant is a nonpolar plane or a semipolar plane and the multiple quantum well layer 15. ) Is formed by epitaxial growth, and an n-type InGaN layer 14 having a thickness of 0.2 μm or more containing an n-type dopant of the same type as that of the n-type GaN layer 13 is interposed, and the n-type InGaN layer 14 is n The strain due to lattice mismatch with the n-type GaN layer 13 is completely or partially relaxed, so that the defects do not become threading dislocations. Therefore, the defect density of the n-type InGaN layer 14 is equal to that of the underlying n-type GaN layer 13. Thus, high luminous efficiency can be obtained. Specifically, the full width at half maximum of the emission intensity distribution with respect to the emission wavelength of the multiple quantum well layer 15 is preferably 40 nm or less, and more preferably 35 nm or less. Even if the n-type GaN layer 13 is not provided and the n-type InGaN layer 14 is interposed between the u-GaN layer 12 and the multiple quantum well layer 15, the same effect can be obtained.

(半導体発光素子の製造方法)
次に、本実施形態に係る半導体発光素子10の製造方法について図2(a)〜(e)に基づいて説明する。
(Manufacturing method of semiconductor light emitting device)
Next, a method for manufacturing the semiconductor light emitting device 10 according to this embodiment will be described with reference to FIGS.

本実施形態に係る半導体発光素子10の製造方法では、ウエハ11’上にu-GaN層12、n型GaN層13(Siドープ)、n型InGaN層14(Siドープ)、発光層である多重量子井戸層15(障壁層15a:GaN、井戸層15b:InGaN)、p型AlGaN層16(Mgドープ)、及びp型GaN層17(Mgドープ)の各半導体層を順に形成した後、エッチングによりn型GaN層13を露出させ、そして、n型InGaN層14及びp型GaN層17の上にそれぞれn型電極18及びp型電極19を形成する。   In the method for manufacturing the semiconductor light emitting device 10 according to the present embodiment, the u-GaN layer 12, the n-type GaN layer 13 (Si-doped), the n-type InGaN layer 14 (Si-doped), and the light emitting layer on the wafer 11 ′. Each semiconductor layer of the quantum well layer 15 (barrier layer 15a: GaN, well layer 15b: InGaN), p-type AlGaN layer 16 (Mg-doped), and p-type GaN layer 17 (Mg-doped) is sequentially formed, and then etched. The n-type GaN layer 13 is exposed, and an n-type electrode 18 and a p-type electrode 19 are formed on the n-type InGaN layer 14 and the p-type GaN layer 17, respectively.

<ウエハの準備>
ウエハ11’を準備する。ウエハ11’は、その直径によっても変わるが厚さが0.3〜3.0mm、及び直径が50〜300mmである。なお、直径50mmのウエハ11’の場合では、1枚の上に5000〜12000個の半導体発光素子10を作り込むことができる。
<Wafer preparation>
A wafer 11 ′ is prepared. The wafer 11 ′ has a thickness of 0.3 to 3.0 mm and a diameter of 50 to 300 mm, although it varies depending on the diameter. In the case of the wafer 11 ′ having a diameter of 50 mm, 5000 to 12000 semiconductor light emitting elements 10 can be formed on one wafer.

ウエハ11’の表面には、必要に応じて、エッチング、或いは、酸化窒化ケイ素(SiOxNy)の堆積により、サブミクロンオーダーの多数の微細凹凸を形成加工する。   On the surface of the wafer 11 ′, a number of fine irregularities on the order of submicron are formed and processed by etching or deposition of silicon oxynitride (SiOxNy) as necessary.

<半導体層の形成>
以下の各半導体層の形成方法としては、有機金属気相成長法(MOVPE法)、ハロゲン気相成長法(VPE法)、分子線エピタキシ法(MBE法)、ハイドライド気相成長法(HVPE法)等が挙げられ、これらのうち有機金属気相成長法が最も一般的である。以下では、有機金属気相成長法を利用した各半導体層の形成方法について説明する。
<Formation of semiconductor layer>
The following semiconductor layers can be formed by metalorganic vapor phase epitaxy (MOVPE), halogen vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE). Of these, metal organic vapor phase epitaxy is the most common. Below, the formation method of each semiconductor layer using a metal organic chemical vapor deposition method is demonstrated.

各半導体層の形成に用いるMOVPE装置は、各々、電子制御される、ウエハ搬送系、ウエハ加熱系、ガス供給系、及びガス排気系で構成されている。ウエハ加熱系は、熱電対及び抵抗加熱ヒータ、その上に設けられた炭素製或いはSiC製のサセプタで構成されている。そして、MOVPE装置は、ウエハ加熱系において、搬送される石英トレイのサセプタの上にセットされたウエハ11’上に反応ガスにより半導体層を結晶成長させるように構成されている。   The MOVPE apparatus used for forming each semiconductor layer includes a wafer transfer system, a wafer heating system, a gas supply system, and a gas exhaust system, which are electronically controlled. The wafer heating system is composed of a thermocouple, a resistance heater, and a carbon or SiC susceptor provided thereon. In the wafer heating system, the MOVPE apparatus is configured to grow a semiconductor layer with a reactive gas on a wafer 11 'set on a susceptor of a quartz tray to be conveyed.

−u-GaN層−
上記MOVPE装置を用いて、ウエハ11’を石英トレイ上にセットした後、ウエハ11’を1050〜1150℃に加熱すると共に反応容器内の圧力を10k〜100kPaとし、また、反応容器内に設置したフローチャネル内にキャリアガスとしてHを流通させ、その状態を数分間保持することによりウエハ11’をサーマルクリーニングする。
-U-GaN layer-
After the wafer 11 ′ was set on the quartz tray using the MOVPE apparatus, the wafer 11 ′ was heated to 1050 to 1150 ° C. and the pressure in the reaction vessel was set to 10 to 100 kPa, and was set in the reaction vessel. H 2 is circulated as a carrier gas in the flow channel, and this state is maintained for several minutes to thermally clean the wafer 11 ′.

次いで、ウエハ11’の温度を1050〜1150℃とすると共に反応容器内の圧力を10k〜100kPaとし、また、反応容器内にキャリアガスHを10L/min程度の流量(以下、ガス流量は基準状態(0℃、1気圧)での値とする。)で流通させながら、そこに反応ガスとして、V族元素供給源(NH)、及びIII族元素供給源(TMG)を、それぞれの供給流量が0.1〜5L/min、及び50〜150μmol/minとなるように流す。Next, the temperature of the wafer 11 ′ is set to 1050 to 1150 ° C., the pressure in the reaction vessel is set to 10 to 100 kPa, and the carrier gas H 2 is flowed into the reaction vessel at a flow rate of about 10 L / min (hereinafter, the gas flow rate is a reference). In this state, the V group element supply source (NH 3 ) and the Group III element supply source (TMG) are supplied as reaction gases. The flow rate is 0.1-5 L / min and 50-150 μmol / min.

このとき、ウエハ11’の結晶成長面を起点として、その上にアンドープのGaNがエピタキシャル結晶成長し、図2(a)に示すように、ウエハ11’上にu-GaN層12が構成される。   At this time, starting from the crystal growth surface of the wafer 11 ′, undoped GaN is epitaxially grown thereon, and as shown in FIG. 2A, the u-GaN layer 12 is formed on the wafer 11 ′. .

なお、u-GaN層12を形成する前に低温バッファ層を形成する場合には、ウエハ11’の温度を400〜500℃としてGaNを結晶成長させる。   In the case where the low temperature buffer layer is formed before the u-GaN layer 12 is formed, the temperature of the wafer 11 ′ is set to 400 to 500 ° C., and GaN is crystal-grown.

−n型GaN層−
反応容器内の圧力を10k〜100kPaとし、また、反応容器内にキャリアガスHを5〜15L/minの流量で流通させながら、そこに反応ガスとして、V族元素供給源(NH)、III族元素供給源1(TMG)、及びn型ドーパント供給源(SiH)を、それぞれの供給流量が0.1〜5L/min、50〜150μmol/min、及び1〜5×10−3μmol/minとなるように流す。
-N-type GaN layer-
The pressure in the reaction vessel is set to 10 to 100 kPa, and the carrier gas H 2 is circulated in the reaction vessel at a flow rate of 5 to 15 L / min, and as a reaction gas, a group V element supply source (NH 3 ), Group III element supply source 1 (TMG) and n-type dopant supply source (SiH 4 ) are supplied at flow rates of 0.1 to 5 L / min, 50 to 150 μmol / min, and 1 to 5 × 10 −3 μmol, respectively. / Min.

このとき、図2(b)に示すように、u-GaN層12の直上にn型GaNがエピタキシャル結晶成長してn型GaN層13が形成される。   At this time, as shown in FIG. 2B, n-type GaN is epitaxially grown immediately above the u-GaN layer 12 to form an n-type GaN layer 13.

−n型InGaN層−
ウエハ11’の温度を600〜850℃程度とすると共に反応容器内の圧力を10k〜100kPaとし、また、反応容器内にキャリアガスNを流通させながら、そこに反応ガスとして、V族元素供給源(NH)、III族元素供給源1(TMG)、III族元素供給源2(TMI)、及びn型ドーパント供給源(SiH)を供給する。
-N-type InGaN layer-
The temperature of the wafer 11 ′ is set to about 600 to 850 ° C., the pressure in the reaction vessel is set to 10 to 100 kPa, and a carrier gas N 2 is circulated in the reaction vessel, while supplying a group V element as a reaction gas. A source (NH 3 ), a group III element source 1 (TMG), a group III element source 2 (TMI), and an n-type dopant source (SiH 4 ) are supplied.

このとき、図2(c)に示すように、n型GaN層13の直上にn型InGaNがエピタキシャル結晶成長してn型InGaN層14が形成される。   At this time, as shown in FIG. 2C, n-type InGaN is epitaxially grown immediately above the n-type GaN layer 13 to form the n-type InGaN layer 14.

−多重量子井戸層−
ウエハ11’の温度を600〜850℃程度とすると共に反応容器内の圧力を10k〜100kPaとし、また、反応容器内にキャリアガスN2を流通させながら、そこに反応ガスとして、V族元素供給源(NH)、及びIII族元素供給源(TMG)を、それぞれの供給流量を流す。このとき、n型InGaN層14の直上にGaNがエピタキシャル結晶成長して障壁層15aが形成される。
-Multiple quantum well layer-
The temperature of the wafer 11 ′ is set to about 600 to 850 ° C., the pressure in the reaction vessel is set to 10 to 100 kPa, and a carrier gas N 2 is circulated in the reaction vessel, and as a reaction gas, a group V element supply source is provided. (NH 3 ) and a group III element supply source (TMG) are supplied at respective supply flow rates. At this time, GaN epitaxially grows immediately above the n-type InGaN layer 14 to form the barrier layer 15a.

次いで、V族元素供給源(NH)、III族元素供給源1(TMG)、及びIII族元素供給源2(TMI)を流す。このとき、GaNの障壁層15aの直上にInGaNがエピタキシャル結晶成長して井戸層15bが形成される。Next, a Group V element supply source (NH 3 ), a Group III element supply source 1 (TMG), and a Group III element supply source 2 (TMI) are flowed. At this time, InGaN is epitaxially grown immediately above the GaN barrier layer 15a to form the well layer 15b.

そして、上記と同様の操作を交互に繰り返し、図2(d)に示すように、障壁層15aと井戸層15bとを交互に形成することにより多重量子井戸層15を構成する。なお、多重量子井戸層15の発光波長は井戸層15bの井戸幅(井戸層15bの厚み)とInN混晶比に依存し、InN混晶比が高いほど発光波長は長波長となる。InN混晶比はTMIのモル流量/(TMGのモル流量+TMIのモル流量)、V/III比と成長温度によって決定される。   Then, the same operation as described above is repeated alternately to form the multiple quantum well layer 15 by alternately forming the barrier layer 15a and the well layer 15b as shown in FIG. 2 (d). The emission wavelength of the multiple quantum well layer 15 depends on the well width of the well layer 15b (the thickness of the well layer 15b) and the InN mixed crystal ratio, and the higher the InN mixed crystal ratio, the longer the emission wavelength. The InN mixed crystal ratio is determined by the TMI molar flow rate / (TMG molar flow rate + TMI molar flow rate), the V / III ratio, and the growth temperature.

−p型AlGaN層及びp型GaN層−
ウエハ11’の温度を800〜1100℃とすると共に反応容器内の圧力を10k〜100kPaとし、また、反応容器内にキャリアガスのHを流通させながら、そこに反応ガスとして、V族元素供給源(NH)、III族元素供給源1(TMG)、III族元素供給源3(TMA)、及びp型ドーパント供給源(CpMg)を流す。
-P-type AlGaN layer and p-type GaN layer-
The temperature of the wafer 11 ′ is set to 800 to 1100 ° C., the pressure in the reaction vessel is set to 10 to 100 kPa, and the carrier gas H 2 is circulated in the reaction vessel, while supplying a group V element as a reaction gas. A source (NH 3 ), a group III element supply source 1 (TMG), a group III element supply source 3 (TMA), and a p-type dopant supply source (Cp 2 Mg) are flowed.

このとき、図2(e)に示すように、多重量子井戸層15の直上にp型AlGaNがエピタキシャル結晶成長してp型AlGaN層16が形成される。   At this time, as shown in FIG. 2 (e), p-type AlGaN is epitaxially grown immediately above the multiple quantum well layer 15 to form a p-type AlGaN layer 16.

引き続き、反応ガスとして、V族元素供給源(NH)、III族元素供給源1(TMG)、及びp型ドーパント供給源(CpMg)を流す。Subsequently, a group V element supply source (NH 3 ), a group III element supply source 1 (TMG), and a p-type dopant supply source (Cp 2 Mg) are flowed as reaction gases.

このとき、図2(e)に示すように、p型AlGaN層16の直上にp型GaNがエピタキシャル結晶成長してp型GaN層17が形成される。   At this time, as shown in FIG. 2E, the p-type GaN is epitaxially grown immediately above the p-type AlGaN layer 16 to form the p-type GaN layer 17.

<電極の形成>
半導体層を積層形成したウエハ11’を部分的に反応性イオンエッチングすることによりn型GaN層13を露出させ、真空蒸着、スパッタリング、CVD(Chemical Vapor Deposition)等の方法によりn型InGaN層14上にn型電極18を形成する。また、p型GaN層17上にp型電極19を形成する。なお、p型GaN層17とp型電極19との間にはITO等の透明導電膜を介設させてもよい。
<Formation of electrode>
The n-type GaN layer 13 is exposed by partially reactive ion etching of the wafer 11 ′ on which the semiconductor layer is formed, and the n-type InGaN layer 14 is exposed by a method such as vacuum deposition, sputtering, or CVD (Chemical Vapor Deposition). An n-type electrode 18 is formed on the substrate. A p-type electrode 19 is formed on the p-type GaN layer 17. A transparent conductive film such as ITO may be interposed between the p-type GaN layer 17 and the p-type electrode 19.

最後に、ウエハ11’を劈開することにより個々の半導体発光素子10に分断する。   Finally, the wafer 11 ′ is cleaved to be divided into individual semiconductor light emitting elements 10.

(試験評価1)
上記実施形態と同様の構成の半導体発光素子を作製した。
(Test evaluation 1)
A semiconductor light emitting device having the same configuration as that of the above embodiment was manufactured.

基板には、表面に微細凹凸を形成した主面がr面であるサファイア基板の加工基板を用いた。そして、サファイア基板上に、低温バッファ層を介して主面が{11−22}面であるu-GaN層を結晶成長させ、その上に、半導体をエピタキシャル結晶成長させてn型GaN層、n型InGaN層、多重量子井戸層、p型AlGaN層、及びp型GaN層を順に積層形成した。従って、いずれの層も主面が{11−22}面である。   As the substrate, a processed substrate of a sapphire substrate whose main surface having fine irregularities formed on the surface was an r-plane was used. Then, on the sapphire substrate, a u-GaN layer whose principal surface is a {11-22} plane is grown through a low-temperature buffer layer, and a semiconductor is epitaxially grown thereon to form an n-type GaN layer, n A type InGaN layer, a multiple quantum well layer, a p-type AlGaN layer, and a p-type GaN layer were sequentially stacked. Accordingly, the main surface of each layer is the {11-22} plane.

半導体発光素子として、多重量子井戸層の発光波長が420nm(紫色)であるものについて、n型InGaN層におけるInの含有割合xを変量した複数種を作製した。同様に、発光波長が450nm(青色)であるもの及び発光波長が520nm(緑色)であるもののそれぞれについても、n型InGaN層におけるInの含有割合xを変量した複数種を作製した。なお、リファレンス用のn型InGaN層を設けていない半導体発光素子も作製した。   As the semiconductor light emitting device, a plurality of types in which the light emission wavelength of the multiple quantum well layer was 420 nm (purple) and the In content ratio x in the n-type InGaN layer was varied were produced. Similarly, for each of the light emission wavelength of 450 nm (blue) and the light emission wavelength of 520 nm (green), a plurality of types in which the In content ratio x in the n-type InGaN layer was varied were produced. A semiconductor light emitting device without a reference n-type InGaN layer was also produced.

そして、各半導体発光素子について、PL発光強度を測定し、リファレンスを基準としたPL発光強度の倍率を求めた。   And about each semiconductor light emitting element, PL emitted light intensity was measured and the magnification of PL emitted light intensity on the basis of a reference was calculated.

図3は、InGaN層のInの含有割合xとリファレンスを基準としたPL発光強度の倍率との関係を示す。   FIG. 3 shows the relationship between the In content ratio x in the InGaN layer and the PL emission intensity magnification with reference to the reference.

これによれば、n型InGaN層におけるInの含有割合xが0<x<0.1の範囲において、PL発光強度の倍率は1よりも大きく、従って、高い発光効率を得ることができることが分かる。特に、0.01<x<0.05の範囲において、また、紫色の発光をするものにおいて、顕著に高い発光効率が得られることが分かる。   According to this, in the range where the In content ratio x in the n-type InGaN layer is in the range of 0 <x <0.1, it is understood that the PL emission intensity magnification is larger than 1, and thus high luminous efficiency can be obtained. . In particular, it can be seen that remarkably high luminous efficiency can be obtained in the range of 0.01 <x <0.05 and those that emit purple light.

また、各半導体発光素子について逆格子空間マッピング測定を行ったところ、少なくともn型InGaN層におけるInの含有割合xが0<x<0.15の範囲にあるものについて、n型InGaN層は、n型GaN層との間の格子不整合による歪みが完全に又は部分的に緩和していることが確認された。   Further, when reciprocal lattice space mapping measurement was performed for each semiconductor light emitting element, at least the In content ratio x in the n-type InGaN layer is in the range of 0 <x <0.15, the n-type InGaN layer is n It was confirmed that the strain due to lattice mismatch with the type GaN layer was completely or partially relaxed.

(試験評価2)
試験評価1と同様にして、n型InGaN層の厚さを変量した青緑色を発光する同種の半導体発光素子を作製した。なお、Inの含有割合x=0.02とした。また、リファレンス用のn型InGaN層を設けていない半導体発光素子も作製した。そして、各半導体発光素子について、20mAの電流注入時における多重量子井戸層の発光波長に対する発光強度分布の半値全幅を求めた。
(Test evaluation 2)
In the same manner as in Test Evaluation 1, a semiconductor light-emitting element of the same kind that emits blue-green light with a variable thickness of the n-type InGaN layer was produced. The In content ratio x was set to 0.02. In addition, a semiconductor light emitting device without a reference n-type InGaN layer was also produced. For each semiconductor light emitting device, the full width at half maximum of the emission intensity distribution with respect to the emission wavelength of the multiple quantum well layer at the time of current injection of 20 mA was obtained.

図4は、n型InGaN層の厚さと発光強度分布の半値全幅との関係を示す。   FIG. 4 shows the relationship between the thickness of the n-type InGaN layer and the full width at half maximum of the emission intensity distribution.

図4によれば、リファレンス用の半導体発光素子では、発光強度分布の半値全幅が40nm強であるのに対し(図4の白丸)、n型InGaN層の厚さが0.2μm以上では、発光強度分布の半値全幅が40nm以下であり、0.3μm以上では、発光強度分布の半値全幅が35nm以下、1.0μmでは約30nmであることが分かる。つまり、これは、n型InGaN層の厚さが0.2μm以上であることにより、半導体発光素子の高い発光効率を得ることができることを示すものである。   According to FIG. 4, in the reference semiconductor light emitting device, the full width at half maximum of the light emission intensity distribution is a little over 40 nm (white circle in FIG. 4), but when the thickness of the n-type InGaN layer is 0.2 μm or more, light emission It can be seen that the full width at half maximum of the intensity distribution is 40 nm or less, and at 0.3 μm or more, the full width at half maximum of the emission intensity distribution is 35 nm or less, and about 1.0 nm at 1.0 μm. That is, this indicates that the high light emission efficiency of the semiconductor light emitting device can be obtained when the thickness of the n-type InGaN layer is 0.2 μm or more.

本発明は半導体発光素子について有用である。   The present invention is useful for semiconductor light emitting devices.

10 半導体発光素子
11 基板
11’ ウエハ
12 u-GaN層
13 n型GaN層
14 n型InGaN層
15 多重量子井戸層
15a 障壁層
15b 井戸層
16 p型AlGaN層
17 p型GaN層
18 n型電極
19 p型電極
DESCRIPTION OF SYMBOLS 10 Semiconductor light-emitting device 11 Substrate 11 ′ Wafer 12 u-GaN layer 13 n-type GaN layer 14 n-type InGaN layer 15 Multiple quantum well layer 15a Barrier layer 15b Well layer 16 p-type AlGaN layer 17 p-type GaN layer 18 n-type electrode 19 p-type electrode

Claims (3)

主面が{11−22}面のGaN層と、
上記GaN層の直上にInGa1−xN(0.01<x<0.05)がエピタキシャル成長して形成され、n型ドーパントを含有した厚さ0.2μm以上のInGaN層と、
上記InGaN層の直上にエピタキシャル成長して形成され、InGaNで形成された井戸層を含む紫色に発光するように構成された多重量子井戸層と、
を備え、
上記InGaN層は、上記GaN層との間の格子不整合による歪みが完全に又は部分的に緩和しており、
上記多重量子井戸層の発光波長に対する発光強度分布の半値全幅が40nm以下である半導体発光素子。
A GaN layer whose principal surface is a {11-22} plane;
In x Ga 1-x N (0.01 <x <0.05) is formed by epitaxial growth directly on the GaN layer, and includes an n-type dopant-containing InGaN layer having a thickness of 0.2 μm or more,
A multiple quantum well layer formed by epitaxial growth directly on the InGaN layer and configured to emit purple light including a well layer formed of InGaN;
With
In the InGaN layer, distortion due to lattice mismatch with the GaN layer is completely or partially relaxed,
A semiconductor light emitting device wherein the full width at half maximum of the emission intensity distribution with respect to the emission wavelength of the multiple quantum well layer is 40 nm or less.
請求項1に記載された半導体発光素子において、
上記GaN層が設けられた基板をさらに備えた半導体発光素子。
The semiconductor light emitting device according to claim 1,
A semiconductor light-emitting device further comprising a substrate provided with the GaN layer.
請求項7に記載された半導体発光素子において、
上記基板がサファイア基板である半導体発光素子。
The semiconductor light emitting device according to claim 7,
A semiconductor light emitting device wherein the substrate is a sapphire substrate.
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