JP2012186715A - Signal converter and signal conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve SNR of ADC and minimize degradation in overall distortion characteristic of microphone IC.SOLUTION: The signal converter includes: a preamplifier circuit for amplifying an input analog signal for output; an A-D converter for converting an analog signal based on an output from the preamplifier into a digital signal according to a cycle of an input clock; and an adjustment control circuit for controlling the adjustment of a pre-conversion analog signal that is an analog signal before conversion into a digital signal according to a frequency of an input clock.

Description

  The present invention relates to a signal conversion device and a signal conversion method, and more particularly to a signal conversion device and a signal conversion method for converting an analog signal into a digital signal.

  In a digital microphone incorporating an ADC (Analogue / Digital Converter), an analog preamplifier and an ADC are connected in the chip. Therefore, compared with the conventional analog output microphone, there is an advantage that it is resistant to external interference noise. In addition, a single-bit delta-sigma ADC is usually used as the ADC. However, when a delta-sigma ADC is used, an unnecessary tone may be generated in the signal band. For this reason, a measure for adding a DC (Direct Current) offset (or DC dither) to the ADC input is generally used.

  FIG. 19 is a block diagram showing a circuit configuration of a digital microphone IC (Integrated Circuit) 900 according to the related art. The digital microphone IC 900 includes an LDO (Low Drop out, power supply circuit) 91, a preamplifier circuit 92, and an ADC 93. The preamplifier circuit 92 amplifies the input analog signal from the microphone. The ADC 93 is connected to the next stage of the preamplifier circuit 92. The ADC 93 converts the input analog signal amplified by the preamplifier circuit 92 into a digital signal. Here, a single-bit delta-sigma ADC is usually used as the ADC 93. By using a single-bit delta-sigma ADC, quantization noise is shifted out of the voice band due to the noise shaping effect. Therefore, a low noise design is possible. Since the power supply voltage range is wide depending on the use of the microphone, the LDO 91 provides a constant voltage to the preamplifier circuit 92 and the ADC 93.

  Further, it is desirable that the delta-sigma type ADC used as the ADC 93 has a high SFDR (Spurious Free Dynamic Range). However, the delta sigma type ADC may be distorted by a non-linearity of the transfer function of the ADC encoder unit. As a main influence, a tone (low frequency noise called an idle tone) may be generated in the signal band. This is because the audio analog signal input to the ADC is at a level near the operating point where the density of “1” and “0” in the 1-bit output digital signal (PDM (Pulse Density Modulation) signal) is equal (no input) Occurs at the time of input and weak signal). In this case, tone-like noise due to a specific frequency or its harmonic component is generated in the output digital signal due to a minute offset such as the relative accuracy of the differential pair transistor in the delta-sigma modulation unit. Further, the smaller the fine offset, the lower the appearing frequency.

  As these countermeasures, intentionally adding a large DC offset (or DC dither) to the output signal (= ADC input signal) of the preamplifier circuit 92 shifts the tone out of the signal band, and the SNR caused by the tone. Can be eliminated. Note that the DC offset may be generated in advance by another circuit, or may be generated by a circuit preceding the ADC.

Here, in the microphone ADC, an estimation formula for the frequency at which a tone is generated is shown in Equation (1).

  DC_Offset is the DC bias difference of the differential output of the preamplifier. Freqs is a sampling clock signal frequency of the microphone IC. FS is a full scaler voltage of the delta sigma type ADC.

  If the DC offset value is large, the frequency at which the tone is generated increases. Thus, if a DC offset value is applied to the ADC input, the tone can be shifted out of the voice band.

  Here, Patent Document 1 discloses a technique related to a mode detector that supplies a control signal configured to control an analog circuit of a digital microphone and thereby reduce power consumption. In Patent Document 2, the extracted clock frequency detection circuit directly refers to the extracted clock, and the detected value is converted into a voltage amount by the voltage conversion circuit, thereby observing the voltage amount more faithful to the extracted clock frequency. A technique relating to a PLL circuit that enables the above-described is disclosed.

  Patent Document 3 discloses a technique related to a direct conversion wireless communication apparatus. In the technique according to Patent Document 3, the converted digital signal is subjected to arithmetic processing in a logic unit, and a DC offset component is extracted. Then, a code corresponding to the amount of the extracted DC offset component is generated in the logic unit. The code is input to the DA converter and converted from a digital signal to an analog signal (DC offset current). The DC offset current is fed back to the differential input terminals RXIN and RXINB of the reception side differential amplifier AMP1. Then, when the DC offset current flows through the resistors R1 and R2, DC offset correction (DC offset voltage correction) is performed.

  Patent Document 4 discloses a technique related to a DC offset cancel circuit. When the gain of the PGA is changed, the control unit according to Patent Document 4 refers to the DC offset value table stored in the memory and outputs a DC offset value (stored value) corresponding to the changed gain to the adder. .

Special table 2009-502062 JP 2005-109551 A JP 2008-016920 A Japanese Patent Laying-Open No. 2005-072895

  However, the above-described digital microphone IC 900 has a problem that the distortion characteristics of the preamplifier may be deteriorated when the DC offset value added to the output signal of the preamplifier circuit 92 is large. The reason is that in the related art described above, it is necessary to add a margin several times the amount originally necessary for the DC offset in consideration of the effects of process variation, clock signal frequency range, temperature fluctuation, and the like.

  As shown in Equation (1), the tone frequency is affected not only by the DC offset value but also by the clock frequency. The clock frequency of a general-purpose microphone IC is generally in the range of 1 MHz to several MHz. If the clock frequency is low, the tone frequency is shifted to the low frequency side. In the related art, even when the DC offset value is the lowest clock frequency, it is necessary to shift the tone frequency to the voice band (˜20 kHz) or more. Furthermore, when the influence of process variations and temperature fluctuations is taken into consideration, it can be seen that a DC offset value of 50 mV to several tens of mV is required.

For example, when Freqs is 1 MHz and FS is 2.4 Vpp, the minimum value of the DC offset value is expressed by the following equation (2).

Then, assuming that the effects of process variation and temperature fluctuation are ± 100% fluctuation, it is necessary to design the DC offset value to the following expression (3).

  On the other hand, for example, assuming that Freqs is 2.4 MHz and there is no variation effect, if the DC offset value is 20 mV, there is no SNR (Signal-to-Noise Ratio) degradation in the signal band caused by the tone.

  Further, even if the techniques disclosed in Patent Documents 1 to 4 described above are used, it is necessary to add a margin several times the amount originally necessary for the DC offset. I can't.

The signal conversion device according to the first aspect of the present invention includes:
A preamplifier circuit that amplifies and outputs an input analog signal;
An AD converter that converts an analog signal based on an output from the preamplifier circuit into a digital signal according to a cycle of an input clock; and
An adjustment control circuit that controls adjustment of the analog signal before conversion, which is an analog signal before being converted into the digital signal, according to the frequency of the input clock;
Is provided.

The signal conversion method according to the second aspect of the present invention includes:
Amplifies the input analog signal,
According to the frequency of an input clock that operates an AD converter that converts the amplified analog signal to a digital signal, an analog signal before conversion that is an analog signal before being converted to the digital signal is adjusted,
The amplified and adjusted analog signal is converted into a digital signal in accordance with the cycle of the input clock.

  As described above, when an amplified and unadjusted analog signal is converted into a digital signal as it is, a tone may be generated within a predetermined frequency band. Therefore, in the first and second aspects of the present invention described above, at least the analog signal before AD conversion is subjected to predetermined adjustment, so that the tone can be shifted out of the predetermined frequency band. Therefore, the generation of noise in the digital signal after AD conversion can be suppressed.

  According to the present invention, it is possible to provide a signal conversion apparatus and a signal conversion method for improving the SNR of an ADC and minimizing the deterioration of distortion characteristics of the entire microphone IC.

It is a block diagram which shows the circuit structure of IC for microphones concerning Embodiment 1 of this invention. It is a block diagram which shows the structure of the DC offset control block concerning Embodiment 1 of this invention. 1 is a block diagram showing a configuration of a clock frequency detection circuit according to a first exemplary embodiment of the present invention. 1 is a block diagram showing a configuration of a delay circuit according to a first exemplary embodiment of the present invention. It is a block diagram which shows the structure of the Schmitt trigger circuit concerning Embodiment 1 of this invention. It is a figure which shows the example of the data stored in the register concerning Embodiment 1 of this invention. It is a flowchart which shows the flow of the adjustment control process concerning Embodiment 1 of this invention. 1 is a block diagram showing a configuration of a preamplifier circuit according to a first exemplary embodiment of the present invention. It is a block diagram which shows the circuit structure of IC for microphones concerning Embodiment 2 of this invention. It is a block diagram which shows the structure of the DC offset control block concerning Embodiment 2 of this invention. It is a figure which shows the example of the data stored in the register concerning Embodiment 2 of this invention. It is a block diagram which shows the structure of the feedback control circuit concerning Embodiment 2 of this invention. It is a flowchart which shows the flow of a process of the adjustment control process concerning Embodiment 2 of this invention. It is a block diagram which shows the circuit structure of IC for microphones concerning Embodiment 3 of this invention. It is a block diagram which shows the circuit structure of IC for microphones concerning Embodiment 4 of this invention. It is a block diagram which shows the circuit structure of IC for microphones concerning Embodiment 5 of this invention. It is a block diagram which shows the circuit structure of ADC concerning Embodiment 5 of this invention. It is a block diagram which shows the circuit structure of IC for microphones concerning Embodiment 6 of this invention. It is a block diagram which shows the circuit structure of IC for digital microphones concerning related technology.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted as necessary for the sake of clarity.

<Embodiment 1 of the Invention>
FIG. 1 is a block diagram showing a circuit configuration of a microphone IC 100 according to the first embodiment of the present invention. The microphone IC 100 is operated by the power supply voltage VDD and the clock signal CLK applied from the outside. The microphone IC 100 receives an input signal IN that is an input analog signal, performs amplification, adjustment, and conversion into a digital signal, and then outputs the signal as an output signal OUT that is an output digital signal. The microphone IC 100 includes an LDO 11, a preamplifier circuit 12, an ADC 13, and a DC offset control block 14.

  The LDO 11 supplies the power supply voltage VDD applied from the outside to the preamplifier circuit 12 and the ADC 13. The LDO 11 can use the same configuration as the LDO 91 of FIG.

  The preamplifier circuit 12 operates with the power supply voltage VDD supplied from the LDO 11, amplifies the input signal IN that is an input analog signal, and outputs the output signal OUTA and the output signal OUTB to the ADC 13. Here, the preamplifier circuit 12 outputs an output signal obtained by amplifying the output signal OUTA and the output signal OUTB as a differential signal. The output signal OUTA and the output signal OUTB can be said to be a first signal and a second signal that constitute a differential signal. The preamplifier circuit 12 adjusts the input signal IN according to a control signal from a DC offset control block 14 described later. That is, the output signal OUTA and the output signal OUTB are signals amplified and adjusted from the input signal IN by the preamplifier circuit 12. Note that the order of amplification and adjustment of the input signal IN performed by the preamplifier circuit 12 may be any first. The preamplifier circuit 12 amplifies the audio analog signal output from the microphone, but is not limited thereto.

  The ADC 13 is an AD converter that operates with the power supply voltage VDD supplied from the LDO 11 and converts an analog signal based on the output from the preamplifier circuit 12 into a digital signal according to the cycle of the clock signal CLK that is an input clock. Specifically, the ADC 13 converts the output signal OUTA and the output signal OUTB, which are analog signals after amplification and adjustment, into digital signals as the output from the preamplifier circuit 12, and outputs the output signal OUT to the outside as the output signal OUT. Output. The ADC 13 is desirably a delta sigma AD converter, but is not limited thereto. The ADC 13 can use a configuration equivalent to the ADC 93 of FIG.

  The DC offset control block 14 is an adjustment control circuit that controls adjustment of a pre-conversion analog signal that is an analog signal before being converted into a digital signal by the ADC 13 according to the frequency of the clock signal CLK that operates the ADC 13. Here, the DC offset control block 14 determines the DC offset amount according to the frequency of the clock signal CLK, and controls the adjustment of the pre-conversion analog signal using the determined DC offset amount. Here, the DC offset amount is a difference between the DC bias voltages of the first signal and the second signal constituting the differential signal. Further, the DC offset control block 14 outputs a control signal SC for adjusting the pre-conversion analog signal based on the determined DC offset amount to the preamplifier circuit 12. Thereby, the DC offset control block 14 can control the adjustment of the analog signal before conversion by the preamplifier circuit 12.

  FIG. 2 is a block diagram showing a configuration of the DC offset control block 14 according to the first exemplary embodiment of the present invention. The DC offset control block 14 includes a clock frequency detection circuit 141 and a register 142. The clock frequency detection circuit 141 detects the frequency in the received clock signal CLK, and outputs the detected frequency to the register 142 as frequency information FI. For example, the clock frequency detection circuit 141 determines whether or not the clock signal CLK exceeds a predetermined frequency (hereinafter referred to as a determination frequency), and outputs the determination result to the register 142 as a High or Low signal.

  FIG. 3 is a block diagram showing a configuration of the clock frequency detection circuit 141 according to the first exemplary embodiment of the present invention. The clock frequency detection circuit 141 includes a delay circuit 1411, a Schmitt trigger circuit 1412, an inverter 1413, and a flip-flop 1414. The clock frequency detection circuit 141 supplies the received clock signal CLK to the delay circuit 1411 and the inverter 1413, and a Schmitt trigger circuit 1412 is connected to the subsequent stage of the delay circuit 1411. The clock frequency detection circuit 141 connects the output of the Schmitt trigger circuit 1412 to the data input terminal D of the flip-flop 1414, connects the output of the inverter 1413 to the clock terminal of the flip-flop 1414, and outputs the output signal OUT.

  An example of the delay circuit 1411 is shown in FIG. The delay time Tr of the rise of the output signal OUT in the delay circuit 1411 can be determined by the ratio of the current flowing from the current source Id and the load capacitance Cd (Tr = Cd / Id). An example of the Schmitt trigger circuit 1412 is shown in FIG.

  Here, the operation of detecting the frequency in the clock frequency detection circuit 141 will be described. First, when the frequency of the clock signal CLK is sufficiently smaller than the determination frequency (clock frequency << determination frequency), the clock frequency detection circuit 141 always outputs Low. On the other hand, when the frequency of the clock signal CLK is higher than the determination frequency (clock frequency> determination frequency), the clock frequency detection circuit 141 outputs the clock signal CLK as it is.

  Specifically, when the frequency of the clock signal CLK is sufficiently lower than the determination frequency (clock frequency << determination frequency), the period of the clock signal CLK is sufficiently slow with respect to the rise of the output signal from the delay circuit 1411. It is. In this case, the rising voltage of the output signal from the delay circuit 1411 exceeds the threshold value of the Schmitt trigger circuit 1412. Therefore, the Schmitt trigger circuit 1412 inverts High and outputs Low when the threshold value is exceeded. Since the signal input via the data input terminal D of the flip-flop 1414 is always delayed as compared with the clock signal CLK, the output of the flip-flop 1414 is always low.

  On the other hand, the case where the frequency of the clock signal CLK is higher than the determination frequency (clock frequency> determination frequency) is a case where the input clock is faster than the rise of the output signal from the delay circuit 1411. In this case, the rising voltage of the output signal from the delay circuit 1411 does not exceed the threshold value of the Schmitt trigger circuit 1412. Therefore, the Schmitt trigger circuit 1412 outputs a signal fixed to Low. Thereafter, the flip-flop 1414 outputs a High or Low signal in synchronization with the clock signal CLK.

  For this reason, the determination frequency serving as a threshold value for switching the DC offset can be set by the output current of the delay circuit 1411, the load capacitance, and the trigger threshold value of the Schmitt trigger circuit 1412 (voltage value when reversing from High to Low). It becomes.

  Returning to FIG. The register 142 stores a value of the control signal SC in advance in association with the detected frequency. The control signal SC is a signal for causing the preamplifier circuit 12 to control the DC offset amount. Therefore, the DC offset control block 14 selects the value of the control signal SC stored in the register 142 in accordance with the frequency information FI detected by the clock frequency detection circuit 141, and sends the selected control signal SC to the preamplifier circuit 12. Output. At this time, the DC offset control block 14 determines the DC offset amount so that when the frequency of the input clock is larger than a predetermined value, the frequency becomes smaller than that when the frequency is lower than the predetermined value.

  FIG. 6 is a diagram illustrating an example of data stored in the register 142 according to the first embodiment of the present invention. FIG. 6 shows that the control signal SCA is associated with the frequency FA, and the control signal SCB is associated with the frequency FB. For example, when the frequency FA is greater than the frequency FB, the control signal SCA includes a control instruction that causes a DC offset amount to be smaller than that of the control signal SCB. Note that the control signal SCA and the control signal SCB can also be referred to as DC offset switching signal values of the preamplifier circuit 12 in accordance with the frequency information FI. That is, the DC offset control block 14 controls the adjustment of the DC offset amount of the preamplifier circuit 12 according to the switching signal value.

  FIG. 7 is a flowchart showing the flow of the adjustment control process according to the first embodiment of the present invention. First, the DC offset control block 14 detects the clock frequency in the clock signal CLK in the clock frequency detection circuit 141 (S11). Next, the DC offset control block 14 refers to the register 142 and selects a control signal from the detected frequency (S12). Then, the DC offset control block 14 outputs the selected control signal to the preamplifier circuit 12 (S13).

  FIG. 8 is a block diagram showing an example of the configuration of the preamplifier circuit 12 according to the first exemplary embodiment of the present invention. Here, an example in the case of a two-stage amplifier configuration is shown. In FIG. 8, by adjusting the value of the current source on one side of the first stage amplifier, the difference in the DC bias of the first stage output can be changed. Then, the DC offset changed by the first stage amplifier is amplified via the next stage buffer amplifier (AMP) to generate a DC offset amount necessary for the ADC 13.

  That is, the preamplifier circuit 12 adjusts the input signal IN, which is an input analog signal, in accordance with the control signal SC from the DC offset control block 14, and amplifies the input analog signal by the AMP and outputs it to the ADC 13. Here, the preamplifier circuit 12 includes a variable current source VId that changes the current in accordance with the control signal SC in order to adjust the input signal IN. That is, the preamplifier circuit 12 generates a signal obtained by adding a DC offset amount to the input signal IN according to an instruction based on the control signal SC, and amplifies the signal by AMP. Although FIG. 8 shows an example in which the number of variable current sources VId is two, the present invention is not limited to this. Further, the means for adjusting the input signal IN is not limited to this.

  The DC offset control block 14 detects the clock signal CLK of the microphone IC 100 in the clock frequency detection circuit 141, specifies the set value of the DC offset corresponding to the clock frequency stored in the register 142, and sets the specified set value. It is determined as the DC offset amount used for adjustment. Therefore, it is assumed that the register 142 stores the frequency and the set value in association with each other in advance.

  Although the method for determining the DC offset amount using the register 142 has been described above, the set value may be obtained by calculation based on the frequency detected sequentially in the DC offset control block 14. When the frequency of the clock signal CLK is high, the required DC offset amount may be set to a low value according to the equation (1). On the other hand, when the frequency of the clock signal CLK is low, the DC offset amount may be set higher by the equation (1).

  As described above, according to the first embodiment of the present invention, the distortion characteristic caused by the margin of the excessive DC offset amount is adjusted by adjusting the ADC to the minimum DC offset amount necessary for shifting the tone out of the voice band. Degradation such as can be suppressed.

<Embodiment 2 of the Invention>
The preamplifier circuit 12 according to the first embodiment of the present invention described above adjusts and amplifies the input signal IN using the DC offset amount determined by the control signal SC from the DC offset control block 14 and outputs the output signals OUTA and OUTB. Is output. However, the input signal IN is not always adjusted accurately only by the DC offset amount determined by the DC offset control block 14 according to the first embodiment of the invention. The reason for this is that the DC offset amount to be adjusted is not only determined by the control signal SC, but also may vary due to temperature fluctuations and process variations.

  Therefore, the microphone IC 200 according to the second embodiment of the present invention is an improvement of the above-described microphone IC 100 in consideration of fluctuations in the DC offset due to temperature fluctuations and process variations.

  FIG. 9 is a block diagram showing a circuit configuration of the microphone IC 200 according to the second embodiment of the present invention. As a difference from FIG. 1, specifically, output signals OUTA and OUTB output from the preamplifier circuit 22 are connected to the DC offset control block 24, and the DC offset control block 14 is replaced with the DC offset control block 24. is there. The LDO 21, the preamplifier circuit 22, and the ADC 23 have the same configuration as the LDO 11, the preamplifier circuit 12, and the ADC 13 in FIG.

  The DC offset control block 24 detects the DC offset amount of the output of the preamplifier circuit 22. Then, the DC offset control block 24 determines the DC offset amount based on the frequency information in the same manner as the DC offset control block 14. The DC offset control block 24 compares the determined DC offset amount with the detected DC offset amount, and applies feedback to the preamplifier circuit 22. When the detected DC offset amount is small, the DC offset control block 24 outputs a control signal SC to the preamplifier circuit 22 so as to increase the DC offset amount. Conversely, when the detected DC offset amount is large, the DC offset control block 24 outputs a control signal SC to the preamplifier circuit 22 so as to reduce the DC offset amount. That is, the DC offset control block 24 detects the DC offset amount based on the output signals OUTA and OUTB, which are analog signals output from the preamplifier circuit 22, and depends on the frequency of the clock signal CLK and the detected DC offset amount. The DC offset amount used for adjustment is determined. As a result, the DC offset amount can be adjusted more accurately in consideration of variations in the DC offset amount due to temperature variations and process variations.

  FIG. 10 is a block diagram showing a configuration of the DC offset control block 24 according to the second exemplary embodiment of the present invention. The DC offset control block 24 includes a clock frequency detection circuit 241, a register 242, and a feedback control circuit 243. Note that the clock frequency detection circuit 241 has the same configuration as the clock frequency detection circuit 141 described above, and thus detailed description thereof is omitted.

  The register 242 stores a value of the set value SV in advance in association with the detected frequency. The set value SV is a value of a DC offset amount adjusted by the preamplifier circuit 12, that is, a DC offset value. FIG. 11 is a diagram illustrating an example of data stored in the register 242 according to the second embodiment of the present invention. FIG. 11 shows that the DC offset SVA is associated with the frequency FA, and the DC offset SVB is associated with the frequency FB. For example, when the frequency FA is greater than the frequency FB, the DC offset SVA is assumed to be smaller than the DC offset SVB.

  Returning to FIG. The feedback control circuit 243 receives the set value SV from the register 242, receives the output signals OUTA and OUTB from the preamplifier circuit 22, and outputs the control signal SC to the preamplifier circuit 22. The feedback control circuit 243 includes a determination circuit 2431 and an output DC offset detection circuit 2432. First, the clock frequency detection circuit 241 and the register 242 determine a necessary DC offset amount as shown in Expression (1). The output DC offset detection circuit 2432 detects an actual DC offset amount from the output signals OUTA and OUTB. Thereafter, the determination circuit 2431 determines the optimum DC offset amount by comparing the detected actual DC offset amount with the determined DC offset amount, and outputs the control signal SC. Thereby, the preamplifier circuit 22 can adjust the DC offset amount to an optimum value.

  FIG. 12 is a block diagram illustrating an exemplary configuration of the feedback control circuit 243 according to the second embodiment of the present invention. The feedback control circuit 243 detects and determines the DC offset amount in the preamplifier circuit 22. The feedback control circuit 243 converts the fluctuation of the DC offset amount due to the received output signals OUTA and OUTB into a current through a resistor. Then, after being amplified by the current mirror circuit, it is converted into a voltage.

  The determination circuit 2431 is, for example, a comparator. The determination circuit 2431 compares the converted voltage with the reference voltage. For example, when the converted voltage is higher than the reference voltage, the output of the determination circuit 2431 becomes a high potential. On the other hand, when the converted voltage is lower than the reference voltage, the output of the determination circuit 2431 becomes a low potential.

  Further, the value of the setting value SV selected in the register 242 is used as the reference voltage (the threshold value for DC offset determination, Vref in FIG. 12). Thereby, the frequency information FI of the clock signal CLK can be reflected in the determination circuit 2431. That is, the setting of the reference voltage is changed according to the frequency information FI. For example, when the frequency of the clock signal CLK is high, the DC offset set value SV is set low. Accordingly, the reference voltage in the determination circuit 2431 is also set low.

  The preamplifier circuit 22 receives the control signal SC that is the output of the determination circuit 2431 in FIG. 12, and adjusts the DC offset amount. For example, the preamplifier circuit 12 shown in FIG. 8 can be used.

  FIG. 13 is a flowchart showing the flow of the adjustment control process according to the second embodiment of the present invention. First, the DC offset control block 24 detects the clock frequency in the clock signal CLK in the clock frequency detection circuit 241 as in step S11 (S21). Next, the DC offset control block 24 refers to the register 242 and selects the set value SV from the frequency of the clock signal CLK (S22). In parallel with steps S21 and S22, the DC offset control block 24 detects the DC offset amount from the output signals OUTA and OUTB in the output DC offset detection circuit 2432 (S23).

  Thereafter, the DC offset control block 24 determines whether or not the detected DC offset amount is larger than the set value SV in the determination circuit 2431 (S24). When it is determined that the detected DC offset amount is larger than the set value SV, the DC offset control block 24 outputs a control signal for decreasing the DC offset amount to the preamplifier circuit 22 (S25). If it is determined in step S24 that the detected DC offset amount is equal to or less than the set value SV, the DC offset control block 24 outputs a control signal for increasing the DC offset amount to the preamplifier circuit 22 (S26).

  As described above, the microphone IC 200 according to the second embodiment of the present invention sets the DC offset amount to the optimum value according to the clock frequency actually used, and is further caused by the influence of process variation, temperature fluctuation, and the like. When the DC offset amount deviates from the set value, the DC offset amount is compensated. In the related art described above, since there is no compensation for the DC offset amount, it is necessary to design the DC offset so that no tone is generated in the voice band under all conditions. If the DC offset margin is too large, the distortion characteristics of the preamplifier deteriorate. In contrast, the second embodiment of the present invention sets the DC offset to an optimum value according to the clock frequency, and further implements DC offset compensation measures, so that only the minimum necessary DC offset amount is generated. It is possible to suppress the deterioration of distortion characteristics of the preamplifier. In particular, with the progress of lower voltage in the future, it becomes important to reduce the voltage margin and to suppress the DC offset amount.

<Third Embodiment of the Invention>
FIG. 14 is a block diagram showing a circuit configuration of a microphone IC 300 according to the third embodiment of the present invention. The microphone IC 300 includes an LDO 31, a preamplifier circuit 32, an ADC 33, a DC offset control block 34, and an adder 35. The LDO 31 and the ADC 33 have the same configuration as the LDO 11 and the ADC 13 in FIG. Further, since the preamplifier circuit 32 can use the same configuration as the preamplifier circuit 92 of FIG. 19, detailed description thereof is omitted.

  Similar to the DC offset control block 14 of FIG. 1, the DC offset control block 34 is an analog signal before conversion that is an analog signal before being converted into a digital signal by the ADC 33 according to the frequency of the clock signal CLK that operates the ADC 33. It is the adjustment control circuit which controls the adjustment of. Here, the DC offset control block 34 determines the DC offset amount according to the frequency of the clock signal CLK. Then, the DC offset control block 34 generates an analog signal SA based on the determined DC offset amount. Thereafter, the DC offset control block 34 outputs the generated analog signal SA to the adder 35.

  The adder 35 adds the analog signal SA generated by the DC offset control block 34 to the analog signal output from the preamplifier circuit 32 and outputs the result to the ADC 33. Here, the adder 35 adds the analog signal SA to the output signal OUTA. However, it is not limited to this. For example, when two analog signals are generated based on the DC offset amount determined by the DC offset control block 34, an adder that performs addition on the output signal OUTB is added to realize adjustment of the analog signal before conversion. It doesn't matter.

  From the above, in the third embodiment of the present invention, first, the same effect as in the first embodiment described above can be obtained. Furthermore, the microphone IC 300 according to the third embodiment of the present invention can be realized by adding a DC offset control block 34 and an adder 35 to a microphone IC having a known LDO, preamplifier circuit, and ADC. . Therefore, the existing configuration can be used and efficient development becomes possible.

<Embodiment 4 of the Invention>
FIG. 15 is a block diagram showing a circuit configuration of a microphone IC 400 according to the fourth embodiment of the present invention. As a difference from FIG. 14, specifically, output signals OUTA and OUTB output from the preamplifier circuit 42 are connected to the DC offset control block 44, and the DC offset control block 34 is replaced with the DC offset control block 44. is there. The LDO 41, the preamplifier circuit 42, the ADC 43, and the adder 45 have the same configuration as the LDO 31, the preamplifier circuit 32, the ADC 33, and the adder 35 in FIG.

  The DC offset control block 44 detects the frequency of the clock signal CLK that operates the ADC 43, similarly to the DC offset control block 34 of FIG. The DC offset control block 44 detects the DC offset amount in the output signals OUTA and OUTB of the preamplifier circuit 42. However, regarding the output signal OUTA, it is assumed that the DC offset amount has already been added by the adder 45.

  Then, the DC offset control block 44 determines the DC offset amount based on the frequency information and the detected DC offset amount, similarly to the DC offset control block 24 of FIG. Then, similarly to the DC offset control block 34 of FIG. 14, the DC offset control block 44 generates an analog signal SA based on the determined DC offset amount, and outputs the generated analog signal SA to the adder 45.

  From the above, in the fourth embodiment of the present invention, first, the same effect as in the second embodiment described above can be obtained. Further, the microphone IC 400 according to the fourth embodiment of the present invention more accurately adjusts the DC offset amount in consideration of the variation in the DC offset amount due to the temperature variation and the process variation as compared with the third embodiment described above. be able to.

<Embodiment 5 of the Invention>
FIG. 16 is a block diagram showing a circuit configuration of a microphone IC 500 according to the fifth embodiment of the present invention. The microphone IC 500 includes an LDO 51, a preamplifier circuit 52, an ADC 53, and a DC offset control block 54. The LDO 51 has the same configuration as the LDO 11 in FIG. Further, since the preamplifier circuit 52 can use a configuration equivalent to that of the preamplifier circuit 92 of FIG. 19, detailed description thereof is omitted.

  The DC offset control block 54 determines the DC offset amount according to the frequency of the clock signal CLK, similarly to the DC offset control block 14 of FIG. Then, the DC offset control block 54 outputs to the ADC 53 a control signal SC for adjusting the pre-conversion analog signal based on the determined DC offset amount. The ADC 53 adjusts the output signals OUTA and OUTB that are analog signals output from the preamplifier circuit 52 in accordance with the control signal SC, and converts the adjusted analog signals into digital signals.

  FIG. 17 is a block diagram showing an example of a circuit configuration of the ADC 53 according to the fifth embodiment of the present invention. The ADC 53 includes an integrator 531, a comparator 532, and a DAC (Digital to Analog Converter) 533. The integrator 531, the comparator 532, and the DAC 533 are an example of a general configuration for converting the output signals OUTA and OUTB, which are analog signals, into digital signals. Since these are publicly known ones, detailed description thereof is omitted.

  The ADC 53 receives the control signal SC from the DC offset control block 54. The ADC 53 includes a variable current source VId that changes the current according to the control signal SC for adjusting the output signal OUTA. Thereby, the integrator 531, the comparator 532, and the DAC 533 convert the output signal OUTB output from the preamplifier circuit 52 and the output signal OUTA whose DC offset amount is adjusted by the variable current source VId to the digital signal. Conversion can be performed.

  From the above, the microphone IC 500 according to the fifth embodiment of the present invention is obtained by adding the DC offset control block 54 to the microphone IC having the known LDO and preamplifier circuit and improving the known ADC. Is feasible. That is, the same effect as that of the first embodiment described above can be obtained by diverting the preamplifier circuit.

<Sixth Embodiment of the Invention>
FIG. 18 is a block diagram showing a circuit configuration of a microphone IC 600 according to the sixth embodiment of the present invention. As a difference from FIG. 16, specifically, output signals OUTA and OUTB output from the preamplifier circuit 62 are connected to the DC offset control block 64, and the DC offset control block 54 is replaced with the DC offset control block 64. is there. The LDO 61, the preamplifier circuit 62, and the ADC 63 have the same configuration as the LDO 51, the preamplifier circuit 52, and the ADC 53 in FIG.

  Similar to the DC offset control block 24 of FIG. 16, the DC offset control block 64 detects the frequency of the clock signal CLK for operating the ADC 53, as with the DC offset control block 54 of FIG. The DC offset control block 64 detects the DC offset amount in the output signals OUTA and OUTB of the preamplifier circuit 62.

  Then, the DC offset control block 64 determines the DC offset amount based on the frequency information and the detected DC offset amount, similarly to the DC offset control block 24 of FIG. Then, the DC offset control block 64 outputs a control signal SC to the ADC 63, similarly to the DC offset control block 24 of FIG.

  From the above, in the sixth embodiment of the present invention, first, the same effects as in the second embodiment described above can be obtained. Furthermore, the microphone IC 600 according to the sixth embodiment of the present invention more accurately adjusts the DC offset amount in consideration of the variation in the DC offset amount due to the temperature variation and process variation, as compared with the fifth embodiment described above. be able to.

<Other embodiments of the invention>
Embodiments 1 to 6 of the present invention can be applied to a technique for providing an optimum DC offset for a digital microphone incorporating an ADC in the field of a microphone and a capacitive signal source.

  Note that the microphone ICs 100 to 600 according to the first to sixth embodiments of the present invention are digital microphone ICs with a DC offset control function, and perform signal conversion on audio analog signals. The subject is not limited to this. That is, in Embodiments 1 to 6 of the present invention, any adjustment may be made so that the tone is shifted out of a predetermined frequency band before the input analog signal is converted into a digital signal.

  The microphone ICs 100, 300, and 500 according to the first, third, and fifth embodiments described above are output signals from the preamplifier circuit as compared with the microphone ICs 200, 400, and 600 according to the second, fourth, and sixth embodiments. This eliminates the function of detecting the DC offset amount, and thus has the effect of reducing the circuit scale.

  In the first to sixth embodiments of the present invention, the DC offset amount is always determined regardless of the frequency of the clock signal CLK. However, the present invention is not limited to this. For example, when the frequency of the clock signal CLK is less than the determination frequency, a fixed value such as a DC offset value according to related technology is used. When the frequency of the clock signal CLK is equal to or higher than the determination frequency, the fixed value is used. A difference value with respect to a typical value may be used. Thereby, the processing load which determines DC offset amount can be reduced.

  Furthermore, in the clock frequency detection circuit 141 of FIG. 3, the detected frequency of the clock signal CLK is compared with one determination frequency, but the present invention is not limited to this. For example, the frequency of the clock signal CLK may be detected in more detail using a plurality of determination frequencies. In that case, for example, the clock frequency detection circuit 141 may be improved, and the configurations of the delay circuit 1411, the Schmitt trigger circuit 1412, the inverter 1413, and the flip-flop 1414 may be provided in parallel for each determination frequency.

  In the first embodiment of the present invention, the DC offset control block 14 performs control according to at least the clock signal CLK and applies feedback to the preamplifier circuit 12. Therefore, there is an effect of improving distortion characteristics as compared with a microphone IC without related art DC offset control.

  In the related art described above, it is necessary to add a margin several times as much as the originally required amount to the DC offset in consideration of the process variation and the clock signal frequency range. If the DC offset is too large, distortion may easily occur in the output of the preamplifier. In addition, other characteristics may be affected by the configuration of the preamplifier. For example, noise characteristics and PSRR (Power Supply Rejection Ratio power supply voltage fluctuation rejection ratio) characteristics may be deteriorated.

  Therefore, each embodiment of the present invention adjusts the optimum DC offset amount according to the clock signal of the microphone IC. Furthermore, even when there are manufacturing processes, temperature fluctuations, audio signal fluctuations, etc., it is possible to adjust to an optimum DC offset amount. By providing the delta-sigma ADC with only the DC offset necessary to shift the tone out of the voice band, it is possible to minimize degradation of distortion characteristics and the like due to the DC offset.

  A part or all of the above embodiments can be described as in the following supplementary notes, but is not limited thereto.

(Supplementary note 1) An IC for a digital microphone for processing an audio signal including a preamplifier circuit and an A / D converter for converting an analog signal into a digital signal,
The digital microphone IC circuit is:
An IC circuit for a digital microphone, which is configured to detect a clock signal frequency and to generate and adjust a DC offset for shifting the tone of the A / D conversion circuit according to the clock frequency. .

(Supplementary note 2) A digital microphone IC for processing an audio signal including a preamplifier circuit and an A / D converter for converting an analog signal into a digital signal,
The digital microphone IC circuit is:
The function of detecting the clock signal frequency, the function of detecting the DC offset value of the input of the A / D conversion circuit, and the A / D conversion circuit according to the detected clock frequency and the input DC offset of the A / D conversion circuit An IC circuit for a digital microphone, characterized in that a DC offset for shifting a tone can be generated and adjusted.

  (Supplementary Note 3) The A / D conversion circuit is a single-bit delta-sigma ADC, and has a built-in function capable of generating and controlling a DC offset that shifts the idle tone out of the signal band. The digital microphone IC circuit according to 1 or 2

  (Supplementary note 4) The digital microphone IC circuit according to Supplementary note 1 or 2, wherein the preamplifier circuit is capable of generating and adjusting a DC offset.

  (Supplementary note 5) The digital microphone IC circuit according to supplementary note 1 or 2, wherein a circuit capable of generating and adjusting a DC offset is provided in advance and added to the output of the preamplifier circuit.

  Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention described above.

100 Microphone IC
11 LDO
12 Preamplifier circuit 13 ADC
14 DC offset control block 141 Clock frequency detection circuit 142 Register 1411 Delay circuit 1412 Schmitt trigger circuit 1413 Inverter 1414 Flip flop Id Current source Cd Capacitor D Data input terminal VId Variable current source FI Frequency information FA Frequency FB Frequency SC Control signal SCA Control signal SCB control signal SV set value SVA DC offset SVB DC offset IN input signal VDD power supply voltage CLK clock signal OUTA output signal OUTB output signal OUT output signal 200 IC for microphone
21 LDO
22 Preamplifier circuit 23 ADC
24 DC offset control block 241 Clock frequency detection circuit 242 Register 243 Feedback control circuit 2431 Judgment circuit 2432 Output DC offset detection circuit 300 IC for microphone
31 LDO
32 Preamplifier circuit 33 ADC
34 DC offset control block 35 Adder SA Analog signal 400 Microphone IC
41 LDO
42 Preamplifier circuit 43 ADC
44 DC offset control block 45 Adder 500 Microphone IC
51 LDO
52 Preamplifier circuit 53 ADC
54 DC offset control block 531 Integrator 532 Comparator 533 DAC
600 Microphone IC
61 LDO
62 Preamplifier circuit 63 ADC
64 DC offset control block 900 Digital microphone IC
91 LDO
92 Preamplifier circuit 93 ADC

Claims (18)

A preamplifier circuit that amplifies and outputs an input analog signal;
An AD converter that converts an analog signal based on an output from the preamplifier circuit into a digital signal according to a cycle of an input clock; and
An adjustment control circuit that controls adjustment of the analog signal before conversion, which is an analog signal before being converted into the digital signal, according to the frequency of the input clock;
A signal conversion device comprising: The adjustment control circuit includes:
In accordance with the frequency of the input clock, a DC offset amount that is a difference between the DC bias voltages of the first signal and the second signal constituting the differential signal is determined,
The signal conversion apparatus according to claim 1, wherein adjustment of the pre-conversion analog signal is controlled using the determined DC offset amount. The adjustment control circuit outputs a control signal for adjusting the pre-conversion analog signal based on the determined DC offset amount to the preamplifier circuit,
The signal converter according to claim 2, wherein the preamplifier circuit adjusts the input analog signal according to the control signal, amplifies the input analog signal, and outputs the amplified analog signal to the AD converter. . The adjustment control circuit outputs a control signal for adjusting the pre-conversion analog signal based on the determined DC offset amount to the AD converter,
3. The signal conversion according to claim 2, wherein the AD converter adjusts an analog signal output from the preamplifier circuit according to the control signal, and converts the analog signal after the adjustment into a digital signal. apparatus. The adjustment control circuit includes:
Generating an analog signal based on the determined DC offset amount;
The signal conversion apparatus according to claim 2, wherein the generated analog signal is added to the analog signal output from the preamplifier circuit and output to the AD converter. The adjustment control circuit includes:
Detecting the DC offset amount based on the analog signal output from the preamplifier circuit;
6. The signal conversion apparatus according to claim 2, wherein a DC offset amount used for the adjustment is determined in accordance with a frequency of the input clock and the detected DC offset amount. The adjustment control circuit includes:
7. The DC offset amount is determined such that when the frequency of the input clock is greater than a predetermined value, the DC offset amount is smaller than when the frequency is less than a predetermined value. The signal converter described in 1.   8. The signal conversion apparatus according to claim 1, wherein the preamplifier circuit amplifies an audio analog signal output from a microphone.   The signal converter according to claim 1, wherein the AD converter is a delta-sigma AD converter. Amplifies the input analog signal,
According to the frequency of an input clock that operates an AD converter that converts the amplified analog signal to a digital signal, an analog signal before conversion that is an analog signal before being converted to the digital signal is adjusted,
The signal conversion method, wherein the amplified and adjusted analog signal is converted into a digital signal in accordance with a cycle of the input clock. In accordance with the frequency of the input clock, a DC offset amount that is a difference between the DC bias voltages of the first signal and the second signal constituting the differential signal is determined,
The signal conversion method according to claim 10, wherein the pre-conversion analog signal is adjusted using the determined DC offset amount. A control signal for adjusting the pre-conversion analog signal based on the determined DC offset amount is output to a preamplifier circuit,
12. The signal conversion method according to claim 11, wherein the preamplifier circuit adjusts the input analog signal according to the control signal, amplifies the input analog signal, and outputs the amplified analog signal to the AD converter. . A control signal for adjusting the pre-conversion analog signal based on the determined DC offset amount is output to the AD converter,
The signal conversion method according to claim 11, wherein the AD converter adjusts the amplified analog signal in accordance with the control signal, and converts the adjusted analog signal into a digital signal. Generating an analog signal based on the determined DC offset amount;
The signal conversion method according to claim 11, wherein the generated analog signal is added to the amplified analog signal and output to the AD converter. Detecting the DC offset amount based on the amplified analog signal;
The signal conversion method according to any one of claims 10 to 14, wherein a DC offset amount used for the adjustment is determined in accordance with a frequency of the input clock and the detected DC offset amount. Detecting the frequency of the input clock;
The DC offset amount is determined such that when the frequency of the input clock is higher than a predetermined value, the DC offset amount is reduced as compared with a case where the frequency is lower than a predetermined value. The signal conversion method described in 1.   The signal conversion method according to claim 10, wherein the input analog signal is an audio analog signal output from a microphone.   The signal conversion method according to claim 10, wherein the AD converter is a delta-sigma AD converter.

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