JP2012179472A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine appropriately specifying an operation content including various internal winning states without immoderately consuming the storage area of a memory and without excessively increasing a control load on a CPU.SOLUTION: The game machine determines whether or not a game state advantageous to a player is generated by performing lottery processing to compare a random number value RND acquired at a prescribed timing in a game with a lottery value stored in a lottery value table DATi. The game machine includes: a main control section 50 for controlling a game operation in block; and a sub-control section 51 for performing a presentation operation, on the basis of a control command received from the main control section. Bit data are partially shared between the control command for specifying the lottery result of the lottery processing and a test signal to be output to a tester of a test machine after specifying the lottery result of the lottery processing.

Description

  The present invention relates to an electronic game machine incorporating a computer device, and is particularly suitably applied to a ball game machine and a spinning game machine.

  In a spinning machine such as a slot machine, when a player inserts a medal into a medal slot and operates a start lever, the rotation of the rotating reel is started accordingly. When the player presses the stop button to stop the rotating reel, when the symbols are aligned on an effective stop line (hereinafter referred to as an effective line), a payout medal corresponding to the symbol is paid out. However, in reality, the success / failure state of each game is determined in advance by an internal lottery process before the player starts the stop operation. Dividend medals will be paid out.

  Of the winning symbols, the Big Bonus (BB) symbol is particularly valuable. When the BB symbol is won internally and the player aligns the BB symbol on the active line, a big bonus game is started. After that, the winning probability of the small role symbol is maintained at a very high level. The number of dividend medals can be expected.

  However, since the big bonus game has a high game value, the winning probability has to be set lower accordingly. Therefore, other winning states are also prepared so that players other than the big bonus game can fully enjoy themselves. For example, a winning state called replay time (RT) is provided, and in the game during this replay time, the winning probability of the replay symbol is increased from the normal time, so that the medal consumption is suppressed and the game proceeds.

  In addition, a winning state called an assist time (AT) is provided, and in the game during the assist time, the player is assisted to ensure that a specific small role symbol that has been won internally is aligned on the active line. . Specifically, for example, if the player is notified of the stop order of the three rotating reels, and the rotating reels are stopped in that order, the small winning symbols that have been internally won can always be aligned.

  In addition, during the assist time (AT), a winning state called an assist replay time (AR) for increasing the winning probability of the replay symbol may be provided. In addition, a plurality of types of replay times RT1 to RTi may be provided, a plurality of big bonus games BB1 to BBi having different values, and various small role winning states may be provided.

  And in order to smoothly execute gaming operations including such various winning states, in recent slot machines, based on a main control unit that comprehensively controls gaming operations and control commands received from the main control unit The sub-control unit that performs the rendering operation is operating in cooperation. In addition, by sequentially outputting game contents that change in real time from the main control unit to the outside of the gaming machine, it is possible to grasp the operating state of each gaming machine at the hall computer and to perform type testing of each gaming machine at the testing institution. To make it easier.

JP 2009-89789 A

  However, in this type of gaming machine where the storage capacity of the memory that can be arranged in the main control unit is legally limited, in order to appropriately identify various internal winning states, etc., further improved program configuration and data structure Is required. However, there is no known configuration that can appropriately specify and output game contents in the modern and sophisticated slot machines including Patent Document 1.

  The present invention has been made in view of the above problems, and does not consume the storage area of the memory and does not overload the control load of the CPU, and includes various internal winning states. An object is to provide a gaming machine capable of appropriately specifying the contents.

  In order to achieve the above object, the present invention is advantageous to a player by executing a lottery process for comparing a random value acquired at a predetermined timing during a game with a lottery value stored in a lottery value table. A gaming machine that determines whether or not to generate a gaming state, a main control unit that comprehensively controls gaming operations, and a sub-control unit that executes rendering operations based on control commands received from the main control unit; The control command for specifying the lottery result of the lottery process and the test signal for specifying the lottery result of the lottery process and outputting the result to the testing machine of the test organization are part of the bit data. Is common.

  Preferably, the control command for specifying the lottery result of the lottery process is configured with a 4-byte length, while the test signal for specifying the lottery result of the lottery process should be configured with a 2-byte length. . In addition, the winning state of the lottery process is roughly divided into a bonus winning state in which the winning probability of the lottery process in the subsequent game is increased, and other small role winning states, and the bonus winning state and the small role winning state Is preferably numbered according to each rule to form part of the control command and the test signal.

  In the embodiment, the numbered information is processed according to the respective rules to create transmission data for control commands and test signals (see SS52, SS57, SS60, SS62).

  Further, it is preferable that the control command and / or the test signal is managed by a timer variable and output every byte at a predetermined time interval. A main process that is started when the power is turned on, and a timer interrupt process that is periodically started by interrupting the process of the main process, and the control command is generated each time the timer interrupt process is started. While the test signals are sequentially output in units of 1 byte, it is preferable that the test signal is output while maintaining the same value in a plurality of timer interrupt processes.

  The control command is composed of a plurality of bytes, and 1 byte specifies the lottery result of the lottery process, while the other 1 byte specifies the type of the command and the gaming state at that time. It is preferable to be configured.

  Also, the present invention executes a lottery process for comparing a random value acquired at a predetermined timing during a game with a lottery value stored in a lottery value table to generate a gaming state advantageous to the player. In the lottery value table, the number of processes of a series of lottery processes continuously executed using the lottery value table and the same lottery value in the series of lottery processes are duplicated. The identification data for specifying whether or not to use is stored, and the number of times of processing or the number of lottery values corresponding to the processing mode is stored. During the lottery process, lottery values are stored. The lottery process is executed up to the number of times specified by the specifying means based on the specifying means for specifying the processing count and the processing mode from the identification data of the table and the lottery mode specified by the specifying means. And 択抽 selection means, preferably further provided.

  Alternatively, the lottery process of the present invention is configured to compare the random value acquired at a predetermined timing with the lottery values stored in the lottery value table, and provide a plurality of lottery value tables, and each lottery value The table is configured to store a lottery value having a plurality of bit lengths and identification data for specifying the bit length and the number of data of the lottery values, and the plurality of lottery value tables corresponding to the gaming state of the gaming machine. The table selection means for selecting the required number of lottery value tables from the table, referring to the selected arbitrary number of lottery value tables in order, the magnitude relationship between the lottery value stored in each lottery value table and the random number value The same lottery value table is used until the winning state is reached, while all the comparison processes in the lottery value table are completed in the non-winning state. A continuous drawing means repeating the same comparison processing by referring to the following lottery value table that, even for further provided is suitable.

In addition, the lottery process of the present invention is configured to compare the random value acquired at a predetermined timing with the lottery values stored in the lottery value table, and a total of N types of winning states (H _{1 to} H _N ). Are grouped into L groups of M groups (H _{11 to} H _1M / H _{21 to} H _2M /... / H _{L1 to} H _LM ), and whether or not one of the N types of winning states is met. The predetermined lottery value table for determining the M lottery values for determining the presence / absence of the M winning states is stored, and the address table for storing the address information of the predetermined lottery value table has the same Preferably, L pieces of address information are stored.

  Furthermore, the lottery process of the present invention is configured to compare the random value acquired at a predetermined timing with the lottery value stored in the lottery value table, and after the internal lottery state in the lottery process, By arranging the symbols specified in the lottery process on the active line of the gaming machine, the internal winning state is configured to be effective, and among the internal winning states, the value for the player is the highest level. If there is no small role winning state, the first flag that roughly specifies the symbol to be aligned on the active line and the symbol that should be aligned on the active line are specifically specified in order to make the small role winning state effective. It is also preferable that the second flag is specified.

  According to the present invention described above, it is possible to appropriately specify operation contents including various internal winning states without consuming the storage area of the memory indiscriminately and without increasing the control burden of the CPU. .

It is a front view of the slot machine which concerns on an Example. FIG. 2 is a right side view (a) and a plan view (b) of the slot machine of FIG. 1. It is the figure which illustrated the front panel of the slot machine from the back. It is an internal front view of the main body case of the slot machine. FIG. 2 is a block diagram showing a circuit configuration of the slot machine of FIG. 1. It is a block diagram which shows the circuit structure of a main control board. It is a circuit diagram which shows a counter circuit. It is a block diagram which shows the circuit structure of a power supply board. It is a flowchart explaining the main process in a main control part, and a timer interruption process. It is a flowchart explaining an internal lottery process. It is drawing which shows the content of the lottery process of a maximum of 83 times performed during a general game. It is drawing which shows the data structure of an address table. It is drawing which shows the data structure of an address table. It illustrates a lottery value table. It illustrates a lottery value table. It illustrates a lottery value table. It is drawing which illustrated the internal winning state, the symbol arrangement | sequence of a rotating reel, and an effective line. It is a flowchart which shows a flag setting process. It is drawing explaining a small role flag, an FR flag, a bonus flag, and a replay flag. It is drawing explaining a small role flag, an FR flag, a bonus flag, and a replay flag. It is a flowchart explaining the production | generation procedure of a type test signal. It is drawing explaining a part of the game start command for the accessory and the game start command for the small part. It is drawing explaining the production | generation process of a game start command. It is a figure explaining a part of timer interruption processing in detail.

  Hereinafter, the present invention will be described in more detail based on examples. 1 to 4 illustrate a slot machine SL according to an embodiment. In this slot machine SL, a rectangular box-shaped main body case 1 and a front panel 2 fitted with various game members are connected via a hinge 3 so that the front panel 2 can be opened and closed with respect to the main body case 1. (FIG. 2). 1 is a front view of the front panel 2, FIG. 2 is a right side view (a) and a plan view (b) of the slot machine SL, FIG. 3 is a rear view of the front panel 2, and FIG. A front view is shown.

  As shown in FIG. 4, a symbol rotating unit 4 including three rotating reels 4 a to 4 c is disposed in the approximate center of the main body case 1, and a medal payout device 5 is disposed below the symbol rotating unit 4. On each of the rotating reels 4a to 4c, a BB symbol, an RB symbol, various fruit symbols, a replay symbol, and the like are drawn. The medal payout device 5 is provided with a medal hopper 5a for storing medals, a payout motor M, a medal payout control board 55, a payout relay board 63, a payout sensor (not shown), and the like. Here, the medal is derived from the payout opening 5b toward the front of the drawing based on the rotation of the payout motor M. Note that medals stored exceeding the limit amount are configured to fall into the auxiliary tank 6 through the overflow portion 5c.

  A power supply board 62 is arranged adjacent to the medal payout device 5, a main control board 50 is arranged above the symbol rotation unit 4, and a rotating drum setting board 54 is arranged adjacent to the main control board 50. ing. In addition, inside the symbol rotating unit 4, a rotating LED relay substrate 58 and a rotating relay substrate 57 are provided, and an external concentrated terminal plate 56 is disposed adjacent to the symbol rotating unit 4.

  As shown in FIG. 1, a liquid crystal display unit 7 is disposed on the upper portion of the front panel 2, and three display windows 8a to 8c corresponding to the rotating reels 4a to 4c are disposed on the lower portion thereof. Through the display windows 8a to 8c, about 3 symbols can be seen in the rotational direction of each of the rotating reels 4a to 4c, and a total of 9 symbols in the horizontal direction and 2 in the diagonal direction. Becomes a virtual stop line. However, in this embodiment, there are four effective lines as shown in FIG.

  On the left side of the display window 8a, an LED group 9 indicating a gaming state is provided. Below that, a payout display unit 10 for displaying the number of medals to be paid out as a gaming result, and the number of medals in a credit state are displayed. The storage number display part 11 to display is provided.

  In the center of the front panel 2 in the vertical direction, a medal insertion slot 12 for inserting medals is provided, and adjacent thereto, a return button 13 for returning medals filled in the medal insertion slot 12 is provided. Also, a credit check button 14 for paying out a credit medal, an insertion button 15 for artificially inserting one credit medal in place of inserting a medal into the medal slot 12, and a credit medal in a pseudo manner A maximum loading button 16 for loading three sheets is provided.

  Below these game members, a start lever 17 for starting the rotation of the rotating reels 4a to 4c and stop buttons 18a to 18c for stopping the rotating reels 4a to 4c are provided. In addition, below the front panel 2, a horizontally long tray 19 for storing medals and a medal outlet 20 communicating with the payout port 5b of the payout device 5 are provided. Speakers SP are arranged on the left and right sides of the medal outlet 20.

  As shown in FIG. 3, on the back side of the front panel 3, a medal sorting device 21 that sorts medals inserted into the medal slot 12, and medals that are determined to be inappropriate by the medal sorting device 21 A return passage 22 that guides the vehicle 20 is provided. A substrate case 23 that houses the effect control board 51, the effect interface board 52, the liquid crystal control board 61, and the like is disposed on the upper back side of the front panel 3. A game relay board 53 that relays signals between the various game members shown in FIG. 1 and the main control board 50 is provided on the medal sorting device 21.

  FIG. 5 is a block diagram illustrating a circuit configuration of the slot machine SL according to the embodiment. As shown in the figure, this slot machine SL realizes an effect operation based on a main control board 50 that controls the operation of various game members including the rotating reels 4a to 4c and a control command received from the main control board 50. The control board 51 and a power supply board 62 that converts an alternating voltage (24V) into a direct voltage (5V, 12V, 24V) and supplies them to each part of the apparatus are mainly configured.

  The main control board 50 outputs, to the effect control board 51, control commands for realizing the sound effect by the speaker SP, the lamp effect by the LED lamp or the cold cathode ray tube discharge tube, and the symbol effect by the liquid crystal display unit 7. is doing. The effect control board 51 is connected to the liquid crystal control board 61 through the effect interface board 52, and the liquid crystal control board 61 realizes a design effect in the liquid crystal display (LCD) unit 7.

  The effect control board 51 realizes lamp effects in various LEDs and cold cathode ray tube discharge tubes via the LED board 59, the inverter board 60, and the rotary LED drive board 58 together with the effect interface board 52. In addition, the effect control board 51 drives the speaker SP through the effect interface board 52 to realize an audio effect.

  The main control board 50 is connected to various game members of the slot machine through the game relay board 53. Specifically, the start switch of the start lever 17, the stop switch of the stop buttons 18a to 18c, the input switch of the input buttons 15 and 16, the liquidation switch of the checkout button 14, and the photointerrupters PH1 and PH2 constituting the input number determination unit 21d The blocker solenoid 31 constituting the inserted medal return unit 21c and the various LED elements 9 to 11 are connected.

  Further, the main control board 50 is connected to the three stepping motors for rotating the rotating reels 4a to 4c and the index sensor for detecting the reference position of the rotating reels 4a to 4c via the rotating relay board 57. Has been. Then, by rotating or stopping the stepping motor, the rotating operation of the rotating reels 4a to 4c and the stopping operation at the target position are realized.

  The main control board 50 is also connected to the medal payout device 5 through the payout relay board 63. The medal payout device 5 is provided with a medal payout control board 55, a medal payout sensor, and a payout motor M. The medal payout control board 55 is based on a control command from the main control board 50. Is rotated to pay out a predetermined amount of medals.

  In addition, the main control board 50 is also connected to the external concentration terminal board 56 and the rotary setting board 54. The rotating drum setting board 54 outputs a setting key signal indicating the setting value set by the staff using the setting key. Here, the set value defines the winning probability of the lottery process executed on the gaming machine in six stages from setting 1 to setting 6, and is appropriately set based on the sales strategy of the gaming hall. . For example, a gaming machine set to the highest rank is most advantageous to the player because the expected value of the number of medals to be paid out is the highest level.

  The external concentration terminal board 56 is connected to the hall computer HC, and the main control board 50 outputs the number of medals inserted and the number of medals paid out through the external concentration terminal board 56.

  In addition, a type test signal for specifying a game operation in real time is output from the main control board 50 in response to a type test performed by TOKYO. Even if the gaming machine has passed the type test and is installed in the gaming hall, the change of the control program is not permitted, so that the type test signal is repeatedly output. However, the gaming machine installed in the gaming hall is not equipped with a connector corresponding to the type test signal.

  FIG. 6 illustrates the circuit configuration of the main control board 50. As shown in the figure, the main control board 50 includes a one-chip microcomputer 64, an I / O port circuit 65 for inputting / outputting 8-bit parallel data, a counter circuit 66 for generating random numbers in hardware, an effect control board 51, and the like. The interface circuit with the external board is mainly configured. Here, the one-chip microcomputer 64 incorporates a CTC (Counter / Timer Circuit) 64b, an interrupt controller 64c, and the like in addition to a Z80 equivalent CPU core 64a, ROM, RAM, and the like.

  The CTC 64b is a circuit in which an 8-bit counter and a timer are integrated, and adds a periodic interrupt, a pulse output creation function (bit rate generator) and a time measurement function to the Z80 system. Therefore, in this embodiment, a timer interrupt (FIG. 13A) is applied to the Z80 CPU 64a at a time interval τ of about 1.5 mS using the CTC 64b.

  As an interface circuit, an interface circuit 67 with a power supply circuit, an interface circuit 68 with a game relay board 53, a rotary motor driving circuit 69, an effect control board and an interface circuit 70 with 51 are provided. Yes. When the power is shut off, a voltage drop interrupt is applied to the Z80 CPU 64a through the interface circuit 67. Note that the rotating motor driving circuit 69 is a circuit that generates a driving signal for the stepping motors of the rotating reels 4 a to 4 c, and the interface circuit 70 is an 8-bit parallel port for outputting a control command to the effect control board 51. It is.

  FIG. 7 is a circuit diagram illustrating the counter circuit 66 in more detail. The counter circuit 66 shown in the figure includes an input unit 24 that receives a start switch signal SG indicating ON operation of the start lever 17, a signal acquisition unit 25 by two D-type flip-flops 25a and 25b, and the lower 8 bits of hardware random numbers ( LOW) and an IC counter 26H that generates upper 8 bits (HI) of hardware random numbers. The output terminals (QA to QH) of the IC counters 26H and 26L are connected to the one-chip microcomputer 64 (CPU core 64a) through a data bus.

  The input unit 24 includes a low-pass filter including a resistor and a capacitor, and a Schmitt trigger type inverter. Therefore, the negative logic start switch signal SG is logically converted and supplied to the signal acquisition unit 25.

  The signal acquisition unit 25 includes two D-type flip-flops 25a and 25b connected in series. A reference pulse Φ is supplied to each clock terminal CLK, and data at the D input terminal is acquired and output to the Q output terminal at the rising edge timing of the reference pulse Φ. Therefore, after the start switch signal SG changes to L level, the lock terminal RCLK of each IC counter 26L, 26H rises to H level at the rising edge of the second reference pulse Φ.

  The reference pulse Φ is preferably oscillated separately from the system clock by a dedicated oscillation circuit, but for simplicity, a system clock for operating the one-chip microcomputer 64 may be substituted for the reference pulse Φ.

  Each of the two IC counters 26 includes an 8-bit binary counter and an 8-bit output register. When the clock signal supplied to the clock terminal CCLK is binary counted, when the holding signal is received at the lock terminal RCLK, the counter value of the binary counter at that moment is stored in the built-in output register. Yes. The counter value stored in the output register is output to the external output terminals (QA to QH) on condition that the output enable terminal OE is at the L level.

  As illustrated, in the counter circuit 66, as long as the power supply voltage value (DC5V) is a normal value, the reference pulse Φ is supplied to the clock terminal CCLK of the lower IC counter 26L via the NAND gate. On the other hand, the carry signal RCO of the lower IC counter 26L is supplied to the upper IC counter 26H. Therefore, the two IC counters 26 function as a 16-bit counter as a whole, and the two internal counters circulate between 0000H to FFFFH (decimal number 65535) counter values. The subscript H means a hexadecimal number including the following cases.

  As described above, when the start switch signal SG changes to L level, the lock terminal RCLK of each IC counter 26L, 26H rises to H level correspondingly, and the value of the internal binary counter is held in the output register. Is done. On the other hand, chip select signals CS0 and CS1 are supplied from the one-chip microcomputer 64 to the output enable terminals OE of the IC counters 26L and 26H. Therefore, the one-chip microcomputer 64 can acquire the data QA to QH held in the output registers built in the IC counters 26L and 26H by changing the chip select signals CS0 and CS1 to L level when necessary.

  FIG. 8 is a block diagram showing a circuit configuration of the power supply board 62. The power supply board 62 includes a rectifying unit 80 that receives AC 24V and converts it into a pulsating voltage, a first voltage converting unit 81 that converts the pulsating voltage into DC 5V, and a second that converts the pulsating voltage into DC 12V. A voltage conversion unit 82; a third voltage conversion unit 83 that converts the pulsating voltage into 24V DC; a power storage unit 84 that stores the output voltage of the first voltage conversion unit 81; And a power supply monitoring unit 85 that outputs

  The power storage unit 84 includes a capacitor C having a large capacity (about 1 Farad), limiting resistors r1 and r2 for overcurrent, and a diode D that blocks reverse current. The limiting resistance r1 is about 75Ω, and the limiting resistance r2 is about 10Ω. The voltage across the capacitor C is supplied to the one-chip microcomputer 64 as a backup power source.

  This backup power is supplied to an SRAM (static ram) built in the one-chip microcomputer 64, and even if the power supply voltage is cut off, the stored contents of the RAM (Random Access Memory) are usually held for 7 to 8 days. I have to. In this embodiment, the storage capacity of the RAM is about 512 bytes used as a work area for the gaming machine.

  The power supply monitoring unit 85 monitors the voltage level of the AC input voltage 24V and the voltage level of the DC power supply voltage 5V. Then, when any one level falls below a predetermined value, the detection signal RES changes to the L level. When an abnormality such as a momentary power failure or a power failure occurs, first, the detection signal RES is quickly output in response to the voltage drop of the AC input voltage.

  This detection signal RES is supplied to the interface circuit 67 (FIG. 6) of the main control board 50, and becomes a positive logic abnormality signal ALM and a negative logic abnormality signal ALM bar. A positive logic abnormality signal ALM is supplied to the I / O port circuit 65, while a negative logic abnormality signal ALM bar is supplied to an interrupt terminal INT (maskable Interrupt) of the one-chip microcomputer 64. Therefore, at this time, if the CPU core 64a is in the interrupt enabled state, the voltage drop interrupt process is started based on the negative logic abnormality signal ALM bar.

  The interface circuit 67 in FIG. 6 also includes a power reset circuit. When the power is turned on, the reset signal generated by the interface circuit 67 is supplied to the reset terminal RST0 of the one-chip microcomputer 64. As a result, the CPU core 64a is reset, and execution of the control program after the head address of the ROM is started.

  Next, the control operation realized by the one-chip microcomputer 64 (hereinafter referred to as the main control unit 50) of the main control board 50 will be described. 9 to 11 are flowcharts for explaining a control program executed by the main control unit 50. The control program of the main control unit 50 includes an infinite loop main process (FIG. 9 (a)) started when the power is turned on, a timer interrupt process (FIG. 9 (b)) started by a scheduled interrupt from the CTC, , And a voltage drop interrupt process (not shown) that is activated by a detection signal RES from the power supply board 62 when the power is shut off. Here, the timer interrupt and the voltage drop interrupt are both maskable interrupts, and the interrupt period τ of the timer interrupt is about 1.5 mS.

  First, the main process of FIG. 9A will be described. When the power is turned on, after the initial process (ST1), the CPU is set in the interrupt enabled state and the work area of the RAM is cleared (ST2).

  When the process of step ST2 is completed, the medal insertion process for the medal actually inserted from the medal insertion slot 12 and the medal actually inserted by pressing the insertion buttons 15 and 16 is performed (ST3). . In the medal insertion process (ST3), a medal inserted or pseudo inserted by the player is detected, the number of inserted medals is determined, and when the start lever 17 is turned on, the subroutine process is terminated. As described with reference to FIG. 7, when the start lever 17 is turned ON, the start switch signal SG changes to the L level, and the counter value at that moment is stored in the output register built in each IC counter 26H, 26L. It is retained and stored (see FIG. 7).

  Therefore, the random number acquisition process (ST4) is executed following the medal insertion process (ST3). Specifically, the one-chip microcomputer 64 changes the chip select signals CS0 and CS1 to the L level, acquires the counter value held in the counter circuit 66, and obtains the random value RND (numerical range: 0). ~ 65535) is stored in the corresponding address of the RAM.

<Lottery value table DATi used in internal lottery processing>
Next, an internal lottery process is executed based on the stored random number value RND (ST5). In this embodiment, 18 kinds of lottery value tables DAT1 to DAT18 (FIGS. 14 to 16) are prepared for the internal lottery process (ST5), and these are combined in a complex manner to provide a variety of unique internal lotteries. Processing (ST5) is executed.

  As shown in FIGS. 14 to 16, each lottery value table DAT <b> 1 to DAT <b> 18 sequentially stores 1-byte or 2-byte long lottery values WD <b> 1 to WDn following the first 1-byte data identifier. Yes.

  Each lottery value WDi means a numerical range for determining whether or not a winning state is obtained in a lottery process corresponding to the lottery value WDi. Specifically, the n lottery values WD1 to WDn are compared with the random number value RND in this order. First, if WD1> RND, the first lottery process is in the winning state, and at this stage the internal lottery The process (ST5) is completed. On the other hand, if the first lottery process is in a lost state, then RND-WD1 is compared with the second lottery value WD2, and if WD2> RND-WD1 (ie, WD1 + WD2> RND), The second lottery process is in a winning state, and the internal lottery process (ST5) is completed at this stage.

  Thereafter, the same process is repeated, so that if WD1 + WD2 +... + WDi> RND, the i-th lottery process is in a winning state. Therefore, in the case of WD1 + WD2 +... + WDn ≦ RND, all the lottery processes n times result in a losing state. As is clear from the above processing, each lottery value WDi means a winning numerical value range (winning width), and the larger the value, the higher the winning probability in the lottery processing.

  As described above, a 1-byte data identifier is stored at the head of each of the lottery value tables DAT1 to DAT18. Here, the most significant bit (bit 7) of the data identifier defines whether or not the lottery process using the lottery value table DATi is executed for each set value set in the gaming machine. The setting values are divided into six categories from setting 1 to setting 6 and are appropriately set in advance for each gaming machine. When bit7 = 1, a lottery process corresponding to the setting value of the gaming machine is executed. Is done. Conversely, if bit7 = 0, a common lottery process is executed regardless of the difference in the setting value of the gaming machine.

  Data identifier bit 6 defines whether the lottery value stored in the lottery value table DATi is 1 byte or 2 bytes long. The larger the lottery value WDi, the higher the winning probability in the lottery process. Therefore, when the winning probability is high, the lottery value needs to be 2 bytes long. Conversely, the bonus symbols (BB1 to BB3, BG1 to BG2) If the winning probability is low as shown in FIG. For example, the lottery value table DAT12 is used for the winning lottery of the bonus symbols (BB1 to BB3, BG1 to BG2), but the lottery values are all 1 byte long, and corresponding to this, bit 6 of the data identifier (20H) Is 0. In addition, in the lottery value table DAT12, even if all the lottery values WD1 to WD32 are added, the result is only 139. Therefore, the winning probability of winning one of the bonus symbols (BB1 to BB3, BG1 to BG2) is 0.2. % (139/65536).

  By the way, the data identifiers bit5 to Bit0 mean the number of lottery values WD (1 byte length or 2 byte length) stored in each lottery value table DATi following the data identifier (1 byte). Since the lottery value WD is a numerical value that uniquely defines the result of acceptance in each lottery process, the data identifiers bit5 to Bit0 mean the number of lotteries when the lottery value table DATi is used. In the right column of the lottery value tables DAT1 to DAT18 in FIG. 14 to FIG. 16, the data identifiers expressed in binary numbers and the meanings of the binary numbers are described for reference.

<Address table ADR used in internal lottery processing>
Although the lottery value tables DAT1 to DAT18 are configured as described above, at the time of each lottery process, it is necessary to specify one or a plurality of lottery value tables DATi used in the lottery process. Therefore, in this embodiment, an address table ADR (FIGS. 12 to 13) is provided, and the start address (2 bytes length) of the lottery value table DATi is stored therein.

  Specifically, the address table ADR (FIGS. 12 to 13) is roughly divided into, for example, an index area INDX having a length of 6 bytes and address areas AD1 to AD6 divided into six sections. Each of the six divided address areas AD1 to AD6 is divided into a leading 1-byte area and a remaining multiple-byte area, and the remaining multiple-byte area has one leading address (2-byte length) of the lottery value table DATi. Or, a plurality is stored. On the other hand, the first 1-byte area means the number of a series of address information (2-byte length) stored subsequent thereto, and therefore the number of address information is determined by a lottery value referenced in each gaming state. This means the number of tables DATi.

  The index area INDX of the address table ADR is divided according to the gaming state. Specifically, (1) RB1 is operating, (2) Bonus internal winning, (3) Non-RT, (4) The game is divided into six game states during RT1 operation, (5) RT2 operation, and (6) RB2 operation.

  The index area INDX stores a relative address (1 byte length) that specifies the address areas AD1 to AD6 to be referred to corresponding to each gaming state. For example, if the gaming state at that time is “Non-RT”, the address area AD3 secured after address 1356H (= 1338H + 1EH) should be referred to from the stored data (1EH) at the corresponding address in the index area INDX. Is identified.

  Of the six game states defined in the index area INDX, “RB1 in operation” and “RB2 in operation” mean a so-called big bonus state, which is based on the difference in expected value of the number of paid-out medals. (RB1, RB2). The RB1 bonus game (when RB1 is active) starts when the “BB symbol” is aligned with the active line, and the RB2 bonus game (when RB2 is active) is started when the “BG symbol” is aligned with the active line. .

  In this embodiment, multiple types of BB symbols and BG symbols are prepared. The BB symbols are BB1 symbol (red 7, red 7, red 7) and BB2 symbol (green 7, green 7, green). 7) and BB3 symbols (BAR, BAR, BAR) correspond to this. In addition, the BG symbol corresponds to two types of BG1 symbol (BAR, BAR, red 7) and BG2 symbol (BAR, BAR, green 7).

  Then, in the bonus game after the BB symbols are aligned (RB1 is in operation), the lottery values in the lottery value table DAT1 (after address 13AAH) specified in the address area AD1 are used, and within the uppermost frame in FIG. One of the 13 types of small role winning states defined in the above is won with extremely high probability (FFFFH / 10000H).

  In addition, in the bonus game after the RB symbols are arranged (RB2 is operating), the lottery values in the lottery value table DAT18 (after address 14C4H) specified in the address area AD6 are used, and within the bottom frame of FIG. One of the five types of small roles specified in the above will be elected with a probability of 100%.

  By the way, in this embodiment, “cherry”, “bell”, “red circle”, “green circle”, and “blue circle” are prepared as small role symbols. “Full circle” means “red circle”, “green circle”, or “blue circle”. Therefore, for example, when “Zenmaru” defined in the lottery value table DAT1 is internally won, and after three “Circle Designs” are arranged on the active line, regardless of the color difference of each “Circle Design”, For example, nine payout medals are paid out. Therefore, when “Zenmaru” is won internally, there are 3 × 3 × 3 = 27 combinations of “round symbols” that can be stopped on the active line.

  When aligned with "Bell Bell Bell" on the active line, 8 dividend medals are paid out, and when aligned with "Cherry ANY ANY", 4 dividend medals are paid out. Is done. Here, ANY means an arbitrary symbol.

  Further, BFR1 to BFR9 each mean a state in which a plurality of types of small roles are duplicated and won internally. For example, when BFR1 is elected internally, “Full circle, full circle, full circle”, “Blue circle, bell, full circle”, “Green circle, bell, full circle”, “Blue circle” are displayed on the active line.・ Nine dividend medals will be paid out when any combination of “Marumaru / Bell” and “Green Circle / Zenmaru / Bell” is available.

  The same applies to FR1 to FR27 defined in the lottery value table DAT2 and GFR1 to GFR3 defined in the lottery value table DAT18. For example, when FR1 of the lottery value table DAT2 is won internally, any of “Full circle / Full circle / Full circle”, “Red circle / Bell / Red circle”, “Red circle / Red circle / Bell” on the active line Nine payout medals will be paid out when the symbols of the combination are aligned. On the other hand, when GFR1 of the lottery value table DAT18 is won internally, “Full circle / Full circle / Full circle”, “Full circle / Bell / Full circle”, “Full circle / Full circle / Bell” When the symbols of any combination of "" are prepared, nine payout medals are paid out.

  By the way, the state that is not the bonus game (“RB1 in operation” or “RB2 in operation”) is collectively referred to as “general game”. During this general game, as shown in the index area INDX of the address table ADR in FIG. 12, in this embodiment, “bonus internal winning”, “non-RT”, “RT1 in operation”, “RT2 It is classified as “in operation”. Here, RT (replay time) means a game state in which the winning probability of replay winning is increased, and is classified into RT1 and RT2 according to the difference in winning probability. In the replay winning state, it is possible to shift to the next game without newly inserting medals, so that medal consumption is suppressed.

  In the present embodiment, a plurality of types of symbol combinations that enable such a replay winning state are prepared. For example, when “Replay / Replay / Replay” is aligned with the original symbol on the active line In addition, the replay winning state is also set when an irregular pattern such as “Replay / Replay / Zenmaru”, “Green 7 / Cherry / Replay” or “BAR / Cherry / Replay” is aligned on the active line.

  In the lottery value tables DAT1 to DAT18, replay A, replay B, replay C, and replay D are represented, and these mean overlapping replay winning states. For example, replay A means a single winning state of replay 1, but in other cases, replay B = replay 1 & replay 2 & replay 4, replay C = replay 1 & replay 2, replay D = Replay 1 & Replay 2 & Replay 3 are duplicated winning states. Replay 1, Replay 2, Replay 3, and Replay 4 are “Replay / Replay / Replay”, “Replay / Replay / Zenmaru”, “Green 7 / Cherry Replay”, and “BAR • "Cherry Replay" symbol means that when they are aligned on the active line, the corresponding replay i is in the replay winning state.

  “RT1” and “RT21” mean a game state in which the winning probability of such replay winning is increased, but if “RT1 is in operation”, 13 lotteries specified in the address area AD4 The lottery process is executed using the value tables in that order. If “RT2 is in operation”, the lottery process is executed using the 13 lottery value tables specified in the address area AD5 in that order. Is done.

  In this embodiment, as apparent from comparison between the data stored in the two address areas AD4 and AD5, in this embodiment, the first two columns ([1] column and [[ The lottery value tables specified in the remaining 11 columns ([3] column to [13] column) are common except for the lottery value table specified in (2) column). Therefore, in this embodiment, there is no difference in the winning probability between “RT1 in operation” and “RT2 in operation” except for the replay symbol winning probability.

  Next, “non-RT” means a game state that is neither “RT1 in operation” nor “RT2 in operation”, and a normal game in which the winning probability of the replay symbol is a normal value. In such a gaming state (during non-RT), the lottery process is executed using the 13 lottery value tables specified in the address area AD3 in that order.

  On the other hand, the game state of “Bonus Internal Winning” means a game state in which the winning symbol has been internally won for either the BB symbol or the RB symbol which is a bonus symbol, but the corresponding winning symbol has not been aligned with the active line yet. To do. Note that the bonus winning state once won internally is not lost until the bonus game is actually started and is carried over over a plurality of games. Then, in the bonus winning game that has been carried over the bonus winning state, the lottery process is executed using the 13 lottery value tables specified in the address area AD2 in that order.

  It is clear when the address values in the [2] to [11] fields of the address area AD2 (address 133FH and later) are compared with the address values in the [3] to [12] fields of the address area AD3 (address 1356H and later). As described above, the ten lottery value tables used for “in bonus winning” are common to the ten lottery value tables used for “non-RT”. Therefore, in this embodiment, there is an advantage that the lottery value table can be simplified and consumption of the ROM area can be suppressed. However, as a result, there is a possibility that a bonus symbol (BB1 to BB3, etc.) will be won again during “Bonus Internal Winning”. Valid.

  In the right column of the address areas AD1 to AD6 in FIGS. 12 to 13, the number of lotteries and the total number of lotteries when each lottery value table DATi is selected are described for reference. In the right column of the index area INDX, the absolute address value calculated from the relative address value is described for reference.

<Grouping of small roles selected>
By the way, paying attention to the lottery table DAT2, the data identifier is 49H, and it is specified that the lottery using the lottery value of 2 bytes length is repeated nine times. On the other hand, three start addresses (13C5H) of the lottery value table DAT2 are continuously stored in the address areas AD2, AD3, AD4, and AD5 of the address table ADR. Therefore, the same lottery process is executed three times in succession, and in each lottery process, the comparison process of nine lottery values and random values is executed. This is repeated 3 × 9 = 27 times continuously.

  This configuration means that a total of 27 winning states FR1 to FR27 are grouped into three groups for every nine winning states. The specific contents of each winning state are as shown in FIG. The internal winning state of the first group of FR1 to FR9 is configured such that the internal winning state can be surely effected and nine payout medals can be acquired when the left rotating reel is first stopped during the stop operation. Therefore, when the number of payout medals is evaluated, all the winning states FR1 to FR27 have the same value.

  On the other hand, the internal winning state of the second group of FR10 to FR18 is configured so that the internal winning state can be surely realized when the central rotating reel is first stopped during the stop operation, and nine payout medals can be obtained. The payout medals are all the same.

  Further, the internal winning state of the third group of FR19 to FR27 is configured so that the internal winning state can be surely realized when the right rotating reel is first stopped during the stop operation, and nine payout medals can be obtained. The payout medals are all the same.

  In this embodiment, a total of 27 winning states having similar values for the player are grouped into L groups for each of the nine winning states having a common value for the player. Therefore, various winning states can be provided without complicating the lottery processing program and without wasting storage capacity.

<Contents of internal lottery process (ST5)>
Next, the internal lottery process (ST5) executed using the address table ADR and the lottery value tables DAT1 to DAT18 will be specifically described with reference to FIGS. 10 (a) and 10 (b).

  In the internal lottery process (ST5), the CPU first specifies the gaming state at that time (ST31). Specifically, the gaming machine at that time is “RB1 in operation”, “Bonus internal winning”, “Non-RT”, “RT1 in operation”, “RT2 in operation”, or “RB2 in operation” ”Is specified.

  Next, based on the relative address value (1 byte length) stored in the index area INDX of the address table ADR, the head address (2 bytes length) of the address area ADi corresponding to the current gaming state is specified (ST32). ). Then, the table reference count stored in the first byte of the identified address area ADi is stored as the first loop count at the corresponding address in the RAM work area (ST33).

  Next, the address value Xa specifying the address area ADi is incremented (+1) and updated (ST34). Then, the updated address value Xa is stored in the memory, and the 2-byte address value Ya specified by the updated address value Xa is stored in the memory (ST35), and the lottery shown in FIG. The determination process (ST36) is executed. Note that the address value Ya is a stored value of the address area ADi, and in short, means the head address value of the selected lottery value table DATi.

  In the lottery determination process (ST36) started in this way, first, the data identifier stored in the leading address (Ya) of the lottery value table DATi is acquired (ST51). Then, the numerical values of bit 0 to bit 5 of the data identifier are stored in the corresponding addresses in the RAM work area as the second loop processing count and the offset value OFF, and the address value Ya is incremented (ST52).

  Next, it is determined whether or not the lottery process for each set value is executed based on the bit 7 of the data identifier. If bit7 = 0, the next process is skipped to step ST57. On the other hand, when bit7 = 1 and the lottery process for each set value is executed, it is determined whether the lottery value WDi is 1 byte length or 2 byte length based on bit6 of the data identifier (ST54). If the lottery value WDi is 2 bytes long, the offset value OFF in the initial state is updated to a double value by the calculation of OFF ← OFF * 2 (ST55). By this processing, the offset value OFF becomes a value twice the number of lotteries. On the other hand, if the lottery value WDi is 1 byte long, the initially set offset value OFF is used as it is.

  Then, the address value Ya is updated based on the initial state or the updated offset value OFF and the set value Si of the gaming machine (ST56). Since the set value Si is any one of 1 to 6, specifically, the address value Ya is updated by the calculation of Ya ← Ya + (Si−1) * OFF. The address value Ya before update is the value of the top address + 1 of the currently selected lottery value table DATi (see ST52), and the lottery value WDi for each set value is stored as the updated address value Ya. This is the start address value.

  Next, the lottery number NUM is updated (ST57). Here, the lottery number NUM specifies the order of a series of lottery processes. For example, if the game state is non-RT, the lottery process is executed in the order shown in FIG. The NUM is specified by a numerical value from 1 to 83.

  Subsequently, the lower 1 byte of the lottery value WDi specified by the updated address value Ya is acquired and stored in the E register of the Z80 CPU (ST58). Further, the address value Ya is incremented (ST59). Next, based on the bit 6 of the data identifier, it is determined whether the lottery value WDi is 1 byte length or 2 bytes long. If the lottery value WDi is 1 byte length, the next process is skipped to step ST63. On the other hand, if the lottery value WDi is 2 bytes long, the higher 1 byte of the lottery value specified by the incremented address value Ya is acquired and stored in the D register of the Z80 CPU (ST61). Further, the address value Ya is incremented (ST62). Note that the value of the D register remains at the initial value 0 unless the process of step ST61 is executed.

  Next, the random number value RND stored in the process of step ST4 (FIG. 9A) is read and stored in the HL register of the Z80 CPU (ST63). Then, the calculation process of HL ← HL-DE is executed in relation to the DE register that combines the D register and the E register (ST64). This subtraction process is nothing other than a lottery process based on a comparison between the random value RND and the lottery value WDi. If RND <WDi, it means that the lottery process is won.

  Regardless of whether the lottery process is successful or not, the value of the HL register after the subtraction process (lottery process) is rewritten to the random value RND. However, if it is in the winning state, the carry flag CY of the Z80 CPU is CY = 1. Therefore, the result of the success / failure is determined based on the value of the carry flag CY (ST65), and if it is in the winning state, the subroutine processing (ST51 to ST65) is completed.

  On the other hand, if carry flag CY is CY = 0 and is in a lost state, the first loop count is decremented (−1), and the processes of steps ST57 to ST65 are repeated unless the value after decrement is 0.

  For example, if the lottery value table DAT1 is selected, a maximum of 13 lottery values WDi (BA52H · 071CH · 071CH · 071CH · 071CH · 071CH · 071CH · 071CH, 071CH, 071CH, 028FH, 0258H, and 00C8) are repeated in this order. Since the sum ΣWDi of the lottery values WDi is FFFDH, the probability of winning any combination is almost 100% (= FFFDH / 10000H), and this point is as described above.

  Further, for example, when the lottery value table DAT13 is selected and the set value Si of the gaming machine is 4 (Si = 4), a maximum of four lotteries are executed while executing the calculation of RND ← RND-WDi. The comparison processing with the value WDi (28H · 0FH · 01H · 05H) is repeated in order.

  By such lottery determination processing (ST36), a series of lottery processing using the specific lottery value table DATi is executed, and the result is stored in the carry flag CY of the Z80 CPU, and the subroutine processing (ST36) is completed. . The lottery number NUM in the winning state (CY = 1) is stored at the corresponding address in the RAM work area (see ST57).

  When the lottery determination process (ST36) is completed, the address value Xa specifying the address area ADi of the address table ADR is updated by +2 (ST37), and whether or not the lottery determination process (ST36) is determined based on the carry flag CY. The result is determined (ST38). If it is a loss state, the first loop count is decremented, and the processes of steps ST35 to ST39 are repeated unless the value after decrement is 0.

  For example, if the gaming state is “Non-RT”, the address area AD3 of the address table ADR is selected, and therefore, in the lottery determination process (ST36), the calculation of RND ← RND-WDi is repeated and a maximum of 13 The lottery value tables (DAT6, DAT7, DAT2, DAT2, DAT2, DAT3, DAT4, DAT12, DAT13, DAT14, DAT15, DAT16, and DAT17) are selected in this order.

  As shown in the right column of FIG. 12, in these 13 lottery value tables DATi, 1 time, 3 times, 9 times, 9 times, 9 times, 2 times, 1 time, 32 times, 4 times, 4 times, respectively. Since the lottery process (subtraction process in ST64) is performed twice, twice, twice, and five times, if all the lottery processes are in a lost state, a total of 83 lotteries are executed. FIG. 11 illustrates the contents of the 83 lottery processes. In such a case, data indicating the lost state is stored in the first address PT1 of the RAM (ST40).

  On the other hand, if a winning state is achieved during a series of lottery determination processes (ST36), the process proceeds from step ST38 to step ST41, the lottery number NUM is stored in the second address PT2 of the RAM, and the first address PT1. And an internal winning flag is set based on the data of the second address PT2 (ST42). Note that the internal winning flag set here is referred to in the turning stop processing (ST8) and the winning determination processing (ST9).

  Corresponding to the type test in the BTS, a 2-byte type test signal is set in the work areas BUF1 and BUF2 (see FIG. 21 (d)) (ST43). The data structure of this type test signal is twice the data structure (1 byte length) in conventional gaming machines. As described above, in this embodiment, since the type test signal having a length of 2 bytes is used, the winning mode in the bonus winning state or the small role winning state can be greatly increased, and even if the winning mode is greatly increased. The increase in the burden of the control program is suppressed, and the type test is not hindered.

  When the process of step ST43 is finished, a game start command is set in the work areas COM1 and COM2 (ST44), and the internal lottery process is finished. As explained earlier, (1) game machines installed in game halls are not equipped with connection connectors for transmitting type test signals, but (2) changes in control programs are prohibited. The type test signal setting process (ST43) is repeatedly executed. Note that the processing of steps ST43 to ST44 will be further described later with reference to FIGS.

<Details of Flag Setting Process (ST42)>
Next, the game state at that time, the success / failure result of a series of lottery processes (ST36), and the winning flag specified by the lottery number NUM in the winning state will be described. As shown in FIGS. 19 (a) to 19 (d), in this embodiment, in order to realize smooth turning stop processing (ST8) and winning determination processing (ST9) corresponding to various winning states. In addition, a small role flag, an FR flag, a bonus flag, and a replay flag are provided. Since each flag has a length of 1 byte, 4 bytes of RAM are used as a whole.

[Bonus Flag FIG. 19 (c)]
First, as shown in FIG. 19 (c), the bonus flag has a 5-bit length of bit0 to bit4 and specifies an internal winning state for a bonus symbol (BB symbol or BG symbol) in this embodiment. As explained above, there are three types of BB symbols: BB1 symbol (red 7, red 7, red 7), BB2 symbol (green 7, green 7, green 7), and BB3 symbol (BAR, BAR, BAR). There are two types of BG designs: a BG1 design (BAR, BAR, red 7) and a BG2 design (BAR, BAR, green 7).

  Since these bonus symbols can only be elected as an alternative, the bonus flag is set to one of 01H, 02H, 04H, 08H, and 10H in the internal winning state for the bonus symbol, and in the non-winning state. 00H. The bonus flag is carried over over a plurality of games until the bonus symbols are aligned and stopped.

[Re-play flag FIG. 19 (d)]
The replay flag specifies the internal winning state for the replay symbol, and in this embodiment, the replay winning states of the replay A, the replay B, the regame C, and the replay D are provided. ing. As described above, in this embodiment, in order to facilitate the stop control of the gaming machine and the stop operation of the player, a plurality of types of symbol arrays for effecting the winning states of the replay A to the replay D are provided. Provided.

  Specifically, “Replay / Replay / Replay” = Replay 1, “Replay / Replay / Zenmaru” = Replay 2, “Green 7 Cherry Replay” = Replay 3, “BAR Cherry Replay” = Replay 4; Replay A = Replay 1; Replay B = Replay 1 & Replay 2 & Replay 4; Replay C = Replay 1 & Replay 2; Replay D = Replay 1 & Replay 2 & Replay 3 Therefore, the re-game flag bits 0 to 3 indicating the winning status of re-game 1 to re-game 4 are combined in multiple layers, for example, to re-game B (re-game 1 & re-game 2 & re-game 4). In the internal winning state, the replay flag is set to 00001011.

  Note that the replay flag disappears if the above-mentioned symbols cannot be aligned in the game and the replay winning state cannot be activated. This also applies to the small combination flag and FR flag described below.

[Small part flag (FIG. 19 (a)) and FR flag (FIG. 19 (b))]
By the way, in this embodiment, in order to enrich the variation of the winning state, a large number of small part winning states in which nine payout medals are paid out are provided. Specifically, three kinds of colored circle patterns (“red circle”, “green circle”, “blue circle”) are prepared, and if any combination of these is aligned on the effective line, nine sheets are displayed. A dividend medal is paid out. There are 3 × 3 × 3 = 27 ways of arranging the round symbols corresponding to the three colors. Nine payout medals are paid out even in an alignment mode in which bell symbols are mixed at the left, middle or right position of the active line, and the rest is a round symbol. In total, there are 3 × 3 × 3 = 27 ways.

  In addition, in the present embodiment, in each of the small role winnings FR1 to FR27, 27 + 27 = 54 as described above are set as internal winning states appropriately mixed, and in short, extremely various small role winning states are set. (See FIG. 17A). For this reason, if the configuration of the flags for identifying such various small role winning states is not devised considerably, the storage area of the memory is wasted and the rotation stopping process (ST8) and the winning determination process (ST9) are performed. Significantly complicated. For example, by specifying the internal winning state by a circle design of three colors (red, green, and blue) that does not include a bell design, in the case of a normal configuration, a total of 3 × 3 × 3 = 27 bit length small role flags It becomes necessary.

  Therefore, in order to eliminate such waste, in this embodiment, the winning combination winning state is specified by 16 bits by combining the winning combination flag and the FR flag each having an 8-bit length. Specifically, the small role flag does not matter the color of the circle design at all, and “Zenmaru / Zenmaru / Zenmaru”, “Bell / Zenmaru / Zenmaru”, “Zenmaru / Bell / Zenmaru” It is roughly specified whether the winning state is “maru”, “full circle / full circle / bell”, “bell / bell / bell”, or “cherry / ANY / ANY”. “Full circle” is a concept including all of “red circle”, “green circle”, and “blue circle”.

  As shown in FIG. 19 (a), the small role flag bit0 = 1 means the winning state of “full circle / full circle / full circle” that does not include the bell symbol, and bit1 = 1 means the active line On the left side, it means the winning status of “Bell / Marumaru / Marumaru” where the bell symbol is located. In addition, bit2 = 1 means that a small part winning state of “full circle / bell / full circle” in which “bell” is located in the center of the effective line, and bit3 = 1 means that “bell” is on the right side of the effective line. It means the small role winning status of “Marumaru / Marumaru / Bell”. In addition, bit4 = 1 and bit5 = 1 mean the small role winning state by “Bell / Bell / Bell” and “Cherry / ANY / ANY”. ANY means an arbitrary symbol.

  On the other hand, the FR flag shown in FIG. 19 (b) indicates the winning status roughly specified by the above-mentioned small role flag as “Bell ••••” “•• bell ••” “•••• bell”. This is a flag for specifying the color of the ○ symbol (round symbol). When FR1 to FR27 are selected, an assist function for notifying a correct stop operation may be performed together. Bit 0 and bit 1 of the FR flag indicate the position of the rotating reel to be stopped first.

  As shown in FIG. 19B, for example, in the internal winning state in which the lower 2 bits of the FR flag are binary numbers 01, the internal winning state is surely realized when the stop operation is started from the left rotating reel. The symbols of the rotating reel are arranged and the effective line is defined (see FIGS. 17C and 17C).

  Further, the internal winning state in which the lower 2 bits of the FR flag are binary number 10 can be effectively realized when the stop operation is started from the central rotating reel, and the internal winning state in which the lower 2 bits are binary number 11. In the winning state, when the stop operation is started from the right rotating reel, the internal winning state can be realized. Note that the internal winning state in which the lower two bits of the FR flag are binary 00 can make the internal winning state effective even if the stop operation is started from any rotating reel.

  The FR flag bits 5 to 7 specify the color of a round symbol to be aligned with the rotating reel specified by the FR flag bits 0 to 1. Further, bits 2 to 4 of the FR flag specify the colors of the round symbols to be aligned with the remaining rotating reels. Note that the 3 bits (bit 5 to bit 7 or bit 2 to bit 4) for specifying the color indicate that the least significant bit is red, the most significant bit is green, and the middle bit is blue.

  By the way, the FR flag is set only at the time of internal winning of FR1 to FR27, BFR1 to BFR9, and GFR1 to GFR3, and these internal winnings include one or two bell symbols. Since the FR flag bits 2 to 4 specify the color of the circular symbol of the rotating reel other than the rotating reel to which the “bell” is to be aligned, if a plurality of colors are allowed, each corresponding bit is 1 It becomes. In addition, in the internal winning states of FR1 to FR27, BFR1 to BFR9, and GFR1 to GFR3, a stop mode of “full circle / full circle / full circle” is always included, and the rotation stop processing (ST8) or winning Since the determination process (ST9) is executed on the assumption that the internal winning state of “full circle / full circle / full circle” is established, the FR flag is not “full circle / full circle / full circle”. The color of the round symbol is specified for the winning state.

  Based on the above, the flag setting process (ST42) in FIG. As shown in FIG. 18 (a), in the flag setting process, first, a conversion table corresponding to the gaming state is selected, a small role winning number HIT is specified from the lottery number NUM, and the work area HIT (FIG. 21 (d)). (ST70). FIG. 18B shows a conversion table that is selected during non-RT (during a normal general game). By referring to the conversion table provided for each gaming state, a lottery number is displayed. NUM is converted to small role winning number HIT. The lottery process executed during non-RT is a maximum of 83 times, but the small winning number HIT is determined based on the small winning combination without the bonus winning.

  As a result of such conversion processing, it is determined whether or not the current winning state is FR winning (ST71). In addition to FR1 to FR27 during non-RT, the FR winning is also provided for BFR1 to BFR9 (RB1 in operation) and GFR1 to GFR3 (RB2 in operation) during a bonus game (FIGS. 12 to FIG. 12). 16).

  If it is not FR winning, the small role flag and the replay flag are set with reference to the small role flag setting table, and the FR flag is cleared (ST72). Note that the rules for setting the small combination flag and the replay flag are as shown in FIGS. 19 (a) and 19 (d).

  On the other hand, in the case of FR winning, the small flag and FR flag are set with reference to the FR flag setting table, and the replay flag is cleared (ST73). Note that the rules for setting the small combination flag and the FR flag are as shown in FIG. For example, if FR1 is in the internal winning state, “red circle / bell / red circle”, “red circle / red circle / bell”, or “full circle / full circle / full circle” is the winning combination. Is a binary number 00001101 (= 0DH) that specifies “full circle / full circle / full circle”, “full circle / bell / full circle”, and “full circle / full circle / full circle”. In addition, when the stop operation is started from the left side, the internal winning state can be activated, and “red circle” becomes a problem as a circle symbol corresponding to “bell”, so the FR flag is red circle (3 bits is 001) + red circle (3 bits) Is 001) + binary number 00100101 (= 25H) indicating the start left position (2 bits is 01). FR10 to FR27 are set according to the same rule.

  When the FR flag, the replay flag, and the small combination flag are set in this manner, it is next determined from the small combination winning number whether the bonus symbol is in the internal winning state (ST74). Then, on condition that the bonus internal winning state is not carried over (ST75), the bonus flag is set and the subroutine processing is ended (ST76). The bonus flag is set based on the rule of FIG. Note that the bonus winning status may overlap with the small role winning status, replay winning status, etc. (see lottery numbers 36 to 52 in FIG. 18B). In such a case, a bonus flag and others Are duplicated.

<Details of Model Test Signal Set Processing (ST43)>
The flag setting process (ST42 in FIG. 10) has been described above. Next, the type test signal setting process (ST43 in FIG. 10) will be described in detail with reference to FIG.

  As shown in FIG. 21A, first, bit information of the bonus flag is numbered to generate bonus information (SS50). As shown in FIG. 19C, the establishment of the bonus flag is specified by the fact that any bit of bit0 to bit4 is 1. In this embodiment, in particular, the bonus flag is numbered to display bonus information. I have identified. The correspondence relationship between the bonus flag and the bonus information is as shown in FIG. 21C, and the lower 6 bits (D0 to D5) of 1 byte are secured as the bonus information. However, in this embodiment, since there are five types of internal winning states of the bonus game (BB1, BB2, BB3, BG1, BG2), only the lower 3 bits of 1 byte are actually used.

However, in this embodiment, the bonus flag is numbered and used as 6-bit bonus information, so the bonus mode can be enriched to a maximum of 2 ⁶ -1 = 63 types without changing the program specifications and data structure. be able to.

  The method of numbering the bit information of the bonus flag is as shown in FIG. 21B. First, the B register of the Z80 CPU is cleared to zero (SS70), and the value of the bonus flag is stored in the accumulator ACC of the Z80 CPU (SS71). ). If the bonus game is not won and the ACC value is zero, the subroutine process is terminated.

  On the other hand, if ACC ≠ 0, the B register is incremented (SS73), the ACC value is shifted right by 1 bit (SS74), and the value of the carry flag CY that receives the least significant bit of ACC is 1 or not. Is determined (SS75). If CY = 0, the processing of SS73 to SS75 is repeated. If CY = 1, the value of the B register at that time is stored in ACC, and the subroutine processing is completed (SS76). As is apparent from the above processing, bonus information is generated in the lower 6 bits (D0 to D5) of ACC when the processing of step SS50 is completed.

  Therefore, the bonus information generated in the ACC is stored in a predetermined work area IMF (SS51), and the high-order 2 bits of the ACC are set to 10 to generate 1 byte-long bonus data. The generated accessory data is a part of the type test signal. If it is a type test, it is output to a testing machine of Hotsukyo.

  Subsequently, the CPU is set to the interrupt disabled state (SS53), and the 1-byte length accessory data generated in the process of step SS52 is stored in the first buffer BUF1 of the work area (SS54). Also, the output management timer TM2 for managing the output operation of the type test signal is initialized (SS55). According to the specifications of the testing machine of Hotsukyo, it is necessary to output the model test signal at an interval of 25 mS per byte, so in this embodiment where the timer interrupt period is 1.5 mS, the initial value of the output management timer TM2 34.

  As shown in FIG. 24 (a), the value of the output management timer TM2 is decremented every timer interrupt, so the initial value 34 means a time width of 51 mS (= 34 * 1.5). Here, the reason why the time twice as long as the output interval (25 mS) of the type test signal is secured is that in this embodiment, the type test signal is particularly 2 bytes long.

  Next, the small role winning number HIT stored in the flag setting process (ST70 in FIG. 18) is read (SS56). As described with reference to FIG. 18, the small role winning number HIT is determined with reference to a conversion table (for example, FIG. 18B) corresponding to the gaming state. FIG. 22A shows a list of small role winning numbers HIT. The small role winning numbers 01H to 24H are assigned to the winning numbers described in the right column of the conversion table of FIG. 18B. Correspond. On the other hand, the small role winning numbers 25H to 31H mean the small role winning state when the gaming state is “RB1 in operation” or “RB2 in operation”.

  In any case, since the winning combination state of the present embodiment can be specified by the lower 6 bits of 1 byte, by setting 01 to the upper 2 bits of 1 byte, the 1 byte long small role data is obtained. Generate (SS57). Then, the small combination data is stored in the second buffer BUF2 of the work area (SS58).

  When the above processing is completed, the CPU is set to the interrupt permitting state and the subroutine processing is completed (SS59). As described above, in this embodiment, the CPU is set to the interrupt disabled state and the processing of steps SS54 to SS58 is executed, so that no timer interrupt is generated during the execution, and unreasonable accessory data and small combination data are tested. There is no risk of output to the machine.

<Details of Game Start Command Set Processing (ST44 in FIG. 10)>
Next, the contents of the game start command setting process (ST44 in FIG. 10) will be described in detail with reference to FIG.

  First, the bonus information stored in the work area IMF is read, and other information is added thereto to generate a 2-byte long game start command. Here, the game start command for a bonus item indicates whether or not the bonus game has been won internally in the internal lottery process (ST5 in FIG. 9 and FIG. 10A) executed at the start of each game. This is a control command for transmission from 50 to the effect control unit 51.

  As described with reference to FIG. 21, the bonus information is a numbered bonus flag (see SS50), and is composed of a 6-bit length (D0 to D5) re-displayed in FIG. Then, by adding the upper 2 bits (D6 to D7 = 00) to the bonus information of 6-bit length, the first byte of the accessory game start command is generated (SS60).

  Next, the command type (D8 to D11) of 4 bits length, the status information (D12 to D14) of 3 bytes length, and the most significant bit (D15 = 1) are concatenated, The second byte is generated (SS60). In this embodiment, 16 types illustrated in FIG. 23D are prepared as command types. However, since a game start command for an accessory is generated at the execution timing of step SS60, the command type is D11. ~ D8 = 0011 (= 03H).

  Also, the 3-byte length state information (D12 to D14) is information for specifying the gaming state at that time. Specifically, “RB1 in operation”, “RB2 in operation”, “RT1 in operation”, “ The gaming state of “RT2 in operation” or “non-RT” is specified by 3 bits D12 to D14.

  Then, the 2-byte long game game start command having the above data structure is stored in the command first buffer COM1 in the work area (SS61).

  Next, the small role winning number HIT stored in the process of step ST70 of FIG. 18 is read, and the first byte of the small role game start command is generated (SS62). The small role winning number HIT has a 6-bit length shown in FIG. 22 (a), and the upper 2 bits (00) are added to this to be the first byte of the small role game start command.

  In addition, a combination of a 4-bit command type (D8 to D11), a 3-byte status information (D12 to D14), and a most significant bit (D15 = 1), 2 bytes of a small-combination game start command An eye is generated (SS62). As described above, the command types are 16 types as shown in FIG. 23 (d). However, in Step SS62, since the small-item game start command is generated, the command types are D11 to D8 = 1100 (= 0DH).

  The small-combination game start command generated in this way is stored in the command second buffer COM2 in the work area (SS63), and finally, a command timer TM1 for controlling the output operation of the control command. Is initialized and the subroutine processing is completed (SS64). Note that the command timer TM1 is set to an initial value of 5, and a control command (game start command for an accessory and a small role) is output 4 times at 1 byte intervals at an interrupt timing interval of 1.5 ms. (See FIG. 24C).

<After internal lottery process (ST5)>
The internal lottery process (ST5) has been described in detail above with reference to FIGS. 10, 18, 21, and 23. Returning to FIG. 9, the subsequent process will be described. When the internal lottery process (ST5) with the random number value RND is completed, next, preparation work for rotating the rotating reels 4a to 4c is performed, and the rotation control of the rotating reels 4a to 4c by the timer interruption is enabled (ST6 to ST8). Thereafter, when the stop buttons 18a to 18c are pressed, a rotating cylinder stop process for stopping the corresponding rotating reels 4a to 4c is performed (ST8).

  In this spinning cylinder stop process, stop control is executed so as to follow the result of the internal lottery process (ST5). That is, as a result of the internal lottery process (ST5), if there is any internal winning state, the symbols of the rotating reels 4a to 4c are aligned so as to match the winning result on condition that the player performs an appropriate stop operation. However, if the timing at which the player presses the stop button or the order of the stop operation is inappropriate, the player is stopped in a lost state pattern. As a result, the small winning combination at the corner is wasted, but the bonus winning is carried over after the next game.

  Thus, when all the rotating reels 4a to 4c are stopped, it is determined whether or not the winning symbols are aligned on the active line (ST9), and the necessary number of medals are paid out (ST10).

  Then, a necessary process is executed by managing the game digest number of RT (replay time) (ST11). Next, it is determined whether or not the player is in the replay winning state (ST12). If the player is in the replay winning state, a re-game operation start process (ST15) is executed, and then the process proceeds to step ST2. Note that, as described above, there are multiple types of symbol combinations that are in the replay winning state.

  If it is not in the replay winning state, it is determined whether or not the bonus game is currently in progress (RB1 is in operation or RB2 is in operation). If the bonus game is in progress, the corresponding processing is executed and the process proceeds to step ST2.

  On the other hand, if the determination in step ST13 is NO, it is determined whether or not the bonus symbol is aligned (ST14). If the bonus symbol is aligned, the bonus game start process (ST17) is executed. The process proceeds to step ST2. There are many types of combinations of bonus symbols.

<Timer interrupt processing>
Next, the timer interrupt process shown in FIG. 9B will be described. This timer interrupt process is started at a constant time interval τ (= 1.5 mS) based on a maskable interrupt signal (timer signal) from the CTC inside the one-chip microcomputer 64.

  When a timer interruption occurs, the CPU register is saved (ST21), and then port input processing is performed (ST22). In the port input process, signals from all switches arranged in the slot machine, such as a start switch, a stop switch, a stored medal switch, a clearing switch, and a door switch, are input through the I / O port circuit 65. In the port input process, the detection signals S1 and S2 from the photo interrupters PH1 and PH2 are also input through the I / O port circuit 65. The detection signals S1 and S2 are signals indicating that medals have been detected on the upstream side and the downstream side of the passage.

  Next, in order to keep track of the current positions of the three rotary reels 4a to 4c, a rotating rotation control process is executed (ST23). The main control unit 50 can grasp the current position of each of the rotating reels 4a to 4c based on the input timing of the input signal from the index sensor and the number of drive pulses supplied to the stepping motor thereafter. Note that in the rotation rotation control process (ST23), the start-up process and stop process of the rotating reels 4a to 4c are also performed. Is generated.

  When the rotation rotation control process (ST23) is completed, the periodic update process is executed (ST24). In the scheduled update process, various software timer values for managing game operations are updated by the decrement process (-1) (ST55). By this update process, the output management timer TM2 initialized in the process of step SS55 and the command timer initialized in the process of step SS64 are decremented to zero (see FIG. 24A). The command timer TM1 manages the output timing of a 4-byte control command, and the output management timer TM2 manages the output timing of a 2-byte model test signal.

  Subsequently, one byte of the control command is output to the effect control unit 51 (ST25). Note that various command types shown in FIG. 23D exist in the control command, and the control command to be output is prepared in the i-th buffer COMi reserved for each command type i.

  However, here, for convenience, only the game start commands for the accessory and the small role that are output at the start of the game will be described. As shown again in FIG. 24 (d), the game start command (2 bytes length) for the bonus item is prepared in the first buffer COM1, and the game start command (2 bytes length) for the small role is stored in the second buffer. COM2 is prepared. At the timing at which these game start commands are to be output, the command timer TM1 is initialized and TM1 ≠ 0 (see SS64 in FIG. 23).

  Therefore, the command output process (ST25) for the game start command operates as shown in FIG. 24 (c) based on the value of the command timer TM1. Specifically, if the command timer TM1 = 4, the upper 1 byte of the first buffer COM1 is output together with the interrupt signal. If the command timer TM1 = 3, the lower 1 of the first buffer COM1 is output together with the interrupt signal. If the command timer TM1 = 2 is output, the upper 1 byte of the second buffer COM1 is output together with the interrupt signal. If the command timer TM1 = 1, the lower 1 of the second buffer COM1 is output together with the interrupt signal. Output bytes.

  In other words, in this embodiment, a game start command for an accessory and a game start command for a small role are continuously output at a time interval of an interrupt cycle of 1.5 mS, and the corresponding interrupt signal is output. In the production control unit 51, the interrupt processing program is activated and a game start command is acquired. If the command timer TM1 = 0, the command output process is skipped and the previous output state is maintained.

  By the way, since the other control commands excluding the game start command are 2 bytes long, one control command is transmitted by two successive timer interrupts. In any case, since the various control commands illustrated in FIG. 23D are transmitted from the main control unit 50 to the effect control unit 51, the effect control unit 51 recognizes the internal winning state grasped and the start lever 17. Corresponding to the operation of the stop buttons 18a to 18c, etc., it is possible to execute an image effect on a liquid crystal display, a lamp effect of an LED lamp, and a sound effect using sound effects.

  Next, a medal information output process is executed, and for example, a medal insertion signal and a medal payout signal, each of which is a 1-bit signal, are output to the external concentration terminal board 56 (ST26). From this medal insertion signal and payout signal, the hall computer HC can grasp the number of medals inserted into each slot machine SL and the number of medals paid out from each slot machine SL.

  In addition, the main control unit 50 outputs drive data for driving each LED lamp group to the game relay board 53 and the rotary relay board 57, and executes the output process of the type test signal (ST27). . The output processing of the type test signal does not exhibit any significance in the game hall, but a control program that passes the type test is used as it is based on a legal request.

  FIG. 24B is a flowchart showing the output processing of the type test signal. Based on the value of the output management timer TM2, if the output management timer TM2 is TM2 ≧ 17, the accessory data of the work area BUF1 is output. If 17> TM2> 0, the small combination data of the work area BUF2 is output, and if TM2 = 0, zero data is output. As is clear from the above processing, the accessory data is continuously output for about 25 mS (= 17 * 1.5 mS), and subsequently, the small role data is continuously output for about 25 mS. Is done.

  When the processing of step ST27 is completed in this way, after determining whether or not there is an abnormality such as a medal payout sensor or a door opening sensor (ST28), the saved register is restored and the interrupt processing is completed (ST29).

  As described above, in the present embodiment, the game start command is divided into a combination of an accessory and a small role, and the total length is 4 bytes. Since it is divided into a total length of 2 bytes, even if the winning mode is greatly increased, no significant design change is required.

  In addition, the first byte of the accessory game start command is substantially the same as the accessory data, and the first byte of the accessory game start command is substantially the same as the accessory data. Even if the command length increases, the increase in control burden is suppressed.

  Although the embodiments of the present invention have been specifically described above, the specific description is not particularly intended to limit the present invention and can be appropriately changed.

DATi lottery value table WD lottery value RND random value 50 main control unit 51 sub control unit

In order to achieve the above object, the present invention determines whether or not the player is in a winning state by sequentially comparing a random value acquired at a predetermined timing during a game with a plurality of lottery values stored in a lottery value table. It is a gaming machine that executes a lottery process to be determined, and the winning state of the lottery process includes a bonus winning state in which the winning state is carried over to the next game until it is activated, and other small role winning states both are roughly classified into, by providing a plurality of types of game status, by using the lottery value table corresponding to each gaming state, the specific contents of the lottery process is configured to vary gaming state, the Realized with main processing including lottery processing, and timer interrupt processing including output processing that outputs the test signal to the testing machine of the test organization that is started on a regular basis by interrupting the processing of the main processing And said The test signal that specifies the lottery result of the selection process is configured with a 2-byte length that specifies the bonus winning state and the small role winning state. In the main process, the test signal is generated while generating the 2-byte length test signal. While initializing the timer variable that defines the output duration of the signal, in the timer interrupt processing, the timer variable is updated and the 2-byte test signal is repeated one byte at a time for the specified output duration. It is configured to output .

Claims (10)

A game for determining whether or not to generate a gaming state advantageous to a player by executing a lottery process for comparing a random value acquired at a predetermined timing during a game with a lottery value stored in a lottery value table Machine,
A main control unit that generally controls gaming operations, and a sub-control unit that executes rendering operations based on control commands received from the main control unit,
The control command that specifies the lottery result of the lottery process and the test signal that specifies the lottery result of the lottery process and that is output to the testing machine of the test organization share a part of bit data. A gaming machine characterized by   The control command for specifying the lottery result of the lottery process is configured with a 4-byte length, while the test signal for specifying the lottery result of the lottery process is configured with a 2-byte length. Game machines. The winning state of the lottery process is roughly divided into a bonus winning state in which the winning probability of the lottery process in the subsequent game increases, and other small role winning states,
The gaming machine according to claim 1 or 2, wherein the bonus winning state and the small role winning state are numbered according to respective rules and constitute a part of the control command and the test signal.   The gaming machine according to claim 1, wherein the control command and / or the test signal is managed by a timer variable and configured to be output for each byte at a predetermined time interval. A main process that is started when the power is turned on, and a timer interrupt process that is periodically started by interrupting the process of the main process,
The control command is sequentially output in units of 1 byte each time the timer interrupt process is started,
The gaming machine according to claim 1, wherein the test signal is output while maintaining the same value in a plurality of timer interruption processes. The control command is composed of a plurality of bytes,
The 1 byte specifies the lottery result of the lottery process,
The gaming machine according to any one of claims 1 to 5, wherein the other 1 byte is configured by specifying a type of the command and a gaming state at that time. A lottery process for comparing a random value acquired at a predetermined timing during a game with a lottery value stored in a lottery value table is executed to determine whether or not a game state advantageous to the player is generated. Configured,
The lottery value table includes a processing number of a series of lottery processes that are continuously executed using the lottery value table, and a processing mode for determining whether or not the same lottery value is used in a series of lottery processes. , And identification data for specifying the number of lottery values corresponding to the number of processing times or the processing mode are stored,
At the time of the lottery process, specifying means for specifying the number of times of processing and the processing mode from identification data of a lottery value table;
Selection lottery means for executing lottery processing up to the number of times specified by the specifying means based on the lottery aspect specified by the specifying means;
The gaming machine according to claim 1, wherein The lottery process is configured to compare a random value acquired at a predetermined timing with a lottery value stored in a lottery value table,
A plurality of lottery value tables are provided, and each lottery value table is configured to store a lottery value having a plurality of bit lengths, and identification data for specifying the bit length and the number of data of the lottery values,
Table selection means for selecting a required number of lottery value tables from the plurality of lottery value tables in correspondence with the gaming state of the gaming machine;
Referring to the arbitrary number of selected lottery value tables in order, the lottery values stored in each lottery value table and the random number values are compared in order of addresses, and the same lottery is performed until the winning state is achieved. While using the value table, when all the contrast processing in the lottery value table is completed in a non-winning state, continuous lottery means that repeats the same contrast processing with reference to the next selected lottery value table;
The gaming machine according to claim 1, further comprising: The lottery process is configured to compare a random value acquired at a predetermined timing with a lottery value stored in a lottery value table,
A total of N types of winning states (H _{1 to} H _N ) are grouped into M groups of L groups (H _{11 to} H _1M / H _{21 to} H _2M /... / H _{L1 to} H _LM ),
In a predetermined lottery value table that determines whether or not one of the N types of winning states is met, M lottery values that determine the presence or absence of the M winning states are stored.
The gaming machine according to claim 1, wherein L pieces of the same address information are stored in an address table that stores address information of the predetermined lottery value table. The lottery process is configured to compare a random value acquired at a predetermined timing with a lottery value stored in a lottery value table,
After becoming the internal winning state in the lottery process, the internal winning state is configured to be effective by aligning the symbols defined in the lottery process on the effective line of the gaming machine,
Among the internal winning states, for a small role winning state whose value to the player is not at the highest level, a symbol that is to be aligned on an active line in order to make the small role winning state effective is roughly specified. The gaming machine according to claim 1, wherein the gaming machine is configured to be specified by a flag and a second flag that specifically specifies a symbol to be aligned on the active line.

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