JP2012174907A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving reliability in operation characteristics.SOLUTION: A semiconductor device 1 comprises a substrate 7 containing silicon and a stacked body 6 provided on the substrate 7. The stacked body 6 includes a suppress region 13 containing fluorine at least on the side of the substrate of a sidewall of the stacked body 6. The suppress region 13 is provided on the side of the sidewall of the insulating film 2 provided on the substrate 7, and has a fluorine concentration greater than that of a channel region 11.

Description

  Embodiments described below generally relate to semiconductor devices.

In the manufacture of nonvolatile semiconductor memory devices, a technique for introducing fluorine into dangling bonds generated in a channel region has been proposed.
Here, in the manufacture of a semiconductor device such as a nonvolatile semiconductor memory device, an etching process using an RIE (Reactive Ion Etching) method is performed.
In the etching process using this RIE method, a laminated body having a desired shape is formed from the laminated film by causing accelerated ions to collide with the laminated film laminated on the substrate. Therefore, a damage layer or an etching residue is likely to be generated on the substrate side of the side wall of the formed laminate. A damaged layer or etching residue generated in such a portion becomes an insulator having defects such as dangling bonds by being oxidized or the like, so that the insulator may serve as a trap site for trapping electrons.
When such a trap site is formed, electrons are trapped in the trap site during the operation of the semiconductor device, which may reduce the reliability of the operation characteristics. For example, in the case of a nonvolatile semiconductor memory device or the like, the behavior of electrons in the vicinity of the tunnel insulating film is affected, and the write voltage is increased, so that the reliability with respect to operation characteristics may be lowered.

JP 2010-40635 A

  A problem to be solved by an embodiment of the present invention is to provide a semiconductor device capable of improving reliability with respect to operating characteristics.

  A semiconductor device according to an embodiment is a semiconductor device including a substrate including silicon and a stacked body provided on the substrate, and the stacked body includes fluorine on at least the substrate side of the sidewall of the stacked body. The suppression area | region containing is included.

1 is a schematic partial cross-sectional view for illustrating a semiconductor device according to an embodiment. It is a schematic diagram for demonstrating a mode that an electron is trapped. It is a schematic graph for demonstrating the introduction amount distribution of the fluorine in a laminated body. It is a schematic graph for demonstrating distribution of the fluorine in the laminated body after heat processing. (A) is a case where heat treatment is performed in an oxygen atmosphere, and (b) is a case where heat treatment is performed in an argon gas atmosphere.

Hereinafter, embodiments will be illustrated with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and detailed description is abbreviate | omitted suitably.
In the following, as an example, a case where the semiconductor device according to the present embodiment is a flash memory will be described.

FIG. 1 is a schematic partial cross-sectional view for illustrating a semiconductor device according to the present embodiment.
In FIG. 1, memory cell portions are mainly shown, and known word lines, bit lines, protective films, interlayer insulating films, contacts, peripheral circuit portions, etc. provided in the flash memory are omitted.
As shown in FIG. 1, a memory cell portion of the semiconductor device 1 is provided with a stacked body 6 in which a tunnel insulating film 2, a floating gate 3, an inter-gate insulating film 4, and a control gate 5 are stacked in this order. Yes.
In addition, a suppression region 13 containing fluorine is formed on at least the side wall of the multilayer body 6 on the substrate 7 side in order to suppress trapping of electrons.

An n-type silicon region (n-well) 8 is formed in the upper layer portion of the substrate 7 containing silicon.
The stacked body 6 is provided on a p-type silicon region (p-well) 9 surrounded by an n-type silicon region (n-well) 8. If the semiconductor device 1 has such a configuration, it becomes possible to apply a voltage to the p-type silicon region 9 independently from the substrate 7, so that power consumption during data erasing can be suppressed. .

A source / drain region 10 using an n-type diffusion layer is provided on both sides of the stacked body 6. The source / drain region 10 is shared by the adjacent stacked bodies 6. Further, the channel region 11 is formed between the source / drain regions 10 below the stacked body 6.
A p-type silicon region 12 having an impurity concentration higher than that of the channel region 11 is provided below the source / drain region 10. If the p-type silicon region 12 is provided, so-called halo ion implantation or pocket ion implantation can be performed, so that the threshold voltage Vth can be lowered and variations in the threshold voltage Vth can be suppressed.

  The tunnel insulating film 2 provided in the stacked body 6 can be formed of, for example, a silicon oxide film or a silicon oxynitride film having a thickness of about 3 nm to 15 nm. Note that a silicon oxide film, a silicon oxynitride film, or the like for forming the tunnel insulating film 2 can be formed in the upper layer portion of the substrate 7 using a thermal oxidation method or the like.

The floating gate 3 can be formed of, for example, a polysilicon film having a thickness of about 10 nm to 500 nm. The polysilicon film or the like for forming the floating gate 3 can be formed using, for example, a CVD (Chemical Vapor Deposition) method. In this case, as impurities for obtaining conductivity, for example, phosphorus, arsenic, or the like is doped so as to have a concentration of about 10 ¹⁸ atoms / cm ⁻³ to 10 ²¹ atoms / cm ^−3. it can.

  The intergate insulating film 4 can be formed of an insulating film having a thickness of about 5 nm to 30 nm, for example. In this case, the inter-gate insulating film 4 can be formed of, for example, a silicon oxide film, a silicon oxynitride film, or the like. Further, the inter-gate insulating film 4 may be formed of, for example, a silicon oxide film / silicon nitride film / silicon oxide film (ONO film), or a laminated film using HfAlO, AlO, HfSiO, ZrSiO, or the like. it can. The insulating film for forming the inter-gate insulating film 4 can be formed using, for example, a CVD method.

The control gate 5 can be formed of, for example, a polysilicon film having a thickness of about 10 nm to 500 nm. Note that a polysilicon film or the like for forming the control gate 5 can be formed using, for example, a CVD method. In this case, as impurities for obtaining conductivity, for example, phosphorus, arsenic, boron, or the like is doped so as to have a concentration of about 10 ¹⁸ atoms / cm ⁻³ to 10 ²¹ atoms / cm ^−3. be able to.
Alternatively, a silicide film and a polysilicon film are laminated by forming a metal film such as W, Ni, Mo, Ti, and Co on the formed polysilicon film and then performing a heat treatment to form a silicide film. A control gate 5 having a laminated structure may be used.

Here, the laminated body 6 is formed using PEP (Photo Engraving Process) and RIE method.
For example, first, films for forming the tunnel insulating film 2, the floating gate 3, the inter-gate insulating film 4, and the control gate 5 are stacked in this order. Then, using the resist pattern formed on the film for forming the control gate 5 as a mask, the stacked body 6 having a desired shape can be formed by using the RIE method.

  According to the knowledge obtained by the present inventor, if the laminated body 6 is formed by using the RIE method, a damage layer or an etching residue is generated on the substrate 7 side of the side wall of the laminated body 6 due to ion collision. It becomes easy. A damaged layer or etching residue generated in such a portion becomes an insulator having defects such as dangling bonds by being oxidized or the like, so that the insulator may serve as a trap site for trapping electrons.

FIG. 2 is a schematic diagram for illustrating how electrons are trapped.
Since the electric field strength increases as electrons are trapped, the state in which electrons are trapped is represented by the electric field strength. In addition, the electric field strength distribution is represented by monotone shading, and is displayed so that the higher the electric field strength is, the lighter the lower the electric field strength is.
As shown in FIG. 2, the electric field strength is highest in the region A on the substrate 7 side of the side wall of the laminate 6. This means that many electrons are trapped by the trap site formed in this portion.

  In this case, since electrons are trapped at the trap site during the operation of the semiconductor device, for example, in the case of a flash memory having a memory cell having the above-described configuration, the behavior of electrons in the vicinity of the tunnel insulating film 2. May be affected, and the write voltage may increase. As a result, the reliability of the operation characteristics of the flash memory may be reduced.

Therefore, in the present embodiment, the suppression region 13 containing fluorine is provided in order to suppress trapping of electrons.
As described above, trap sites having defects such as dangling bonds are likely to occur on the substrate 7 side of the side wall of the stacked body 6. Therefore, by introducing fluorine into this portion, the fluorine is bonded to the portion that is a dangling bond so that electrons are not easily trapped.
The suppression region 13 can be formed by introducing fluorine into the stacked body 6 and performing a heat treatment for collecting the introduced fluorine in the suppression region 13. Details of this heat treatment will be described later.

In this case, the suppression region 13 can be formed at least on the side wall side of the tunnel insulating film 2.
For example, the suppression area | region 13 containing these area | regions may be formed by introduce | transducing fluorine into the surface of the board | substrate 7 between the laminated bodies 6, the side wall whole area of the laminated body 6, etc. FIG.

Further, for example, in the case where an etching residue is formed on the substrate 7 side of the side wall of the stacked body 6 or between the stacked bodies 6, fluorine is introduced into the etching residue, so that the suppression region including this is included. 13 may be formed.
That is, the suppression region 13 may be formed at least on the substrate 7 side of the side wall of the stacked body 6.

However, since the floating gate 3, the control gate 5, the source / drain region 10 and the channel region 11 are portions through which electricity flows, if too much fluorine is introduced, the resistance variation in these becomes large and the reliability with respect to the operating characteristics is increased. May decrease.
Therefore, it is preferable that the introduced fluorine is collected in a portion where trap sites are likely to be generated.

According to the knowledge obtained by the present inventor, the introduced fluorine can be collected in a portion where trap sites are likely to be generated by performing a predetermined heat treatment after the introduction of fluorine.
FIG. 3 is a schematic graph for illustrating the introduction amount distribution of fluorine in the laminate.
Note that the stacked body is formed by stacking a polysilicon film, a silicon oxide film, a polysilicon film, a silicon oxide film, and a silicon film in this order from the surface side of the stacked body. In this case, the structure from the polysilicon film on the front surface side to the silicon oxide film on the back surface side of the stacked body corresponds to the configuration of the stacked body 6 described above, and the silicon film on the back surface side corresponds to the channel region 11.
Also, the horizontal axis represents the thickness direction dimension of the laminated body, “0” is the surface of the laminated body, “0 to T1” is a polysilicon film, “T1 to T2” is a silicon oxide film, and “T2 to T3” is poly. The silicon film, “T3 to T4” is a silicon oxide film, and “T4” and subsequent are silicon films.
Fluorine was introduced from the surface side of the laminate using an ion implantation method.

  As shown in FIG. 3, even if fluorine is introduced from the surface side of the laminate, fluorine can be introduced to the back side of the laminate according to the implantation energy. This means that fluorine can be introduced not only into the laminate 6 but also into the channel region 11.

FIG. 4 is a schematic graph for illustrating the distribution of fluorine in the laminate after the heat treatment.
4A shows a case where heat treatment is performed in an oxygen atmosphere, and FIG. 4B shows a case where heat treatment is performed in an argon gas atmosphere.

As can be seen from FIGS. 4A and 4B, if a predetermined heat treatment is performed, the amount of fluorine in the polysilicon film or silicon film can be reduced.
This means that the amount of fluorine introduced into the floating gate 3, the control gate 5, the source / drain region 10, and the channel region 11 can be reduced by performing a predetermined heat treatment.
Therefore, resistance fluctuations that can be caused by introducing fluorine into these portions through which electricity flows can be suppressed, and a decrease in reliability with respect to operating characteristics can be suppressed.

As can be seen from FIGS. 4A and 4B, the amount of fluorine in the silicon oxide film can be increased by performing a predetermined heat treatment.
This means that the fluorine introduced into the tunnel insulating film 2 and the inter-gate insulating film 4 can be collected by performing a predetermined heat treatment.
In addition, the amount of fluorine in the tunnel insulating film 2 that is located on the substrate 7 side of the stacked body 6 and easily generates trap sites can be significantly increased as compared with that before the heat treatment.
It can also be seen that the difference in the atmosphere in which the heat treatment is performed has little effect on the fluorine distribution. That is, first, the fluorine introduced by the heat treatment can be diffused to bond the fluorine to dangling bonds or the like existing in the laminate 6.
Further, by continuing the heat treatment after diffusing the introduced fluorine, the fluorine diffused in the floating gate 3, the control gate 5, the source / drain region 10, the channel region 11, etc. The insulating film 4 can be collected.
If such heat treatment is performed, fluorine introduced into a portion where fluorine introduction is desired (for example, the tunnel insulating film 2) is moved from a portion where fluorine introduction is not desirable (for example, the channel region 11). Can be made.
Therefore, the reliability with respect to the operating characteristics of the semiconductor device 1 can be greatly improved.

Next, the suppression region 13 will be further illustrated.
The suppression region 13 is formed from at least one of a conductive film (for example, the floating gate 3) and the channel region 11 by fluorine introduced into the insulating film (for example, the tunnel insulating film 2) and heat treatment. And moved to fluorine.
Further, the fluorine concentration in the suppression region 13 is set higher than the fluorine concentration in the channel region 11.
According to the knowledge obtained by the present inventors, when the fluorine concentration in the suppression region 13 is set to 10 ¹⁹ atoms / cm ⁻³ or more and 10 ²¹ atoms / cm ⁻³ or less, an increase in write voltage can be suppressed. Therefore, the reliability with respect to the operating characteristics can be improved.

  In the following manner, the suppression region 13 having such a fluorine concentration can be formed, and fluorine introduced into the floating gate 3, the control gate 5, the source / drain region 10, the channel region 11 and the like. The amount of can be reduced. Further, it is possible to increase the amount of fluorine in the tunnel insulating film 2 that is located on the substrate 7 side of the stacked body 6 and easily generates trap sites.

First, the method for introducing fluorine will be exemplified.
For example, after forming the stacked body 6 using the RIE method, fluorine can be introduced by supplying a gas containing fluorine to the substrate 7 on which the stacked body 6 is formed.
In addition, fluorine can be introduced by performing plasma treatment using a gas containing fluorine.

In addition, after forming the stacked body using the RIE method, an insulating film having a thickness of about 5 to 100 mm is formed on the side wall of the stacked body, and a gas containing fluorine is supplied to the insulating film formed on the side wall of the stacked body. Fluorine can be introduced into the.
In this case, since the laminated body and the insulating film formed on the side wall are integrated, the insulating film is formed, but the laminated body corresponds to the laminated body 6 described above.
If such an insulating film is formed, it is possible to suppress the introduction of fluorine into the floating gate 3, the control gate 5, the source / drain region 10, the channel region 11, and the like.

Moreover, after forming the stacked body 6 using the RIE method, fluorine can be introduced using the ion implantation method.
As the source gas, for example, BF ₃ can be exemplified. In this case, the implanted ions are F ⁺ , BF ⁺ , and BF ²⁺ . In addition, the dose amount of fluorine ions can be set to 10 ¹¹ atoms / cm ⁻² or more and 5 × 10 ¹³ atoms / cm ⁻² or less.
After forming the stacked body 6, n-type impurities are implanted on both sides of the stacked body 6 to form the source / drain regions 10. At this time, if BF ₃ or the like is used as a source gas, the source In addition to the formation of the drain region 10, fluorine can be introduced.

Moreover, when forming the laminated body 6 using RIE method, it is possible to introduce fluorine.
For example, in the final step for forming the stacked body 6 using the RIE method, a CH _X F _Y- based gas and an oxygen gas are used so that fluorine is introduced together with the formation of the stacked body 6. be able to.
Note that the processing conditions and the like in each of these methods can be changed as appropriate according to the configuration of the semiconductor device, the material of the film, and the like. Therefore, the processing conditions in each of these methods can be obtained by conducting experiments and simulations in advance.

Next, the heat treatment will be exemplified.
This heat treatment is performed not only to diffuse the introduced fluorine, but also to increase the amount of fluorine in the portion where the trap site is likely to be generated (for example, the tunnel insulating film 2). Further, it is performed in order to reduce the amount of fluorine in a portion where it is desirable not to introduce fluorine (for example, floating gate 3, control gate 5, source / drain region 10, channel region 11 and the like).

Here, the temperature in heat processing can be 750 degreeC or more and 1000 degrees C or less, for example.
This heat treatment can be performed using, for example, a rapid heating method (RTA; Rapid Thermal Annealing). In this case, in order to make the profiles of the other dopant elements as designed, the heat treatment time is set to a short time so as to be 10 seconds or more and 30 seconds or less.
For example, the distribution state of fluorine in the stacked body 6 can be made appropriate by controlling the processing time and the like. That is, fluorine introduced into a portion where fluorine introduction is desired (for example, the tunnel insulating film 2) can be moved from a portion where fluorine introduction is not desirable (for example, the channel region 11).
Note that treatment conditions (for example, treatment temperature and treatment time) in the heat treatment can be changed as appropriate in accordance with the structure of the semiconductor device, the material of the film, the thickness of the film, the required distribution state of fluorine, and the like. Therefore, the processing conditions in the heat treatment can be obtained by conducting experiments and simulations in advance.

According to the embodiment exemplified above, it is possible to realize a semiconductor device capable of improving reliability with respect to operation characteristics.
As mentioned above, although several embodiment of this invention was illustrated, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, and the like can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.
For example, the shape, size, material, arrangement, number, and the like of each element included in the semiconductor device 1 are not limited to those illustrated, but can be changed as appropriate.
Moreover, although the case where the semiconductor device 1 was a flash memory was illustrated, it is not necessarily limited to this. For example, other non-volatile storage devices (nonvolatile memory) such as MRAM (Magnetoresistive Random Access Memory) and ReRAM (Resistance Random Access Memory) may be used, and volatile storage devices such as DRAM (Dynamic Random Access Memory). (Volatile memory). Further, not only a storage device (memory) but also a logic IC (Logic Integrated Circuit) may be used.
That is, the present invention can be widely applied to semiconductor devices in which a stacked body is formed using the RIE method.

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Tunnel insulating film, 3 Floating gate, 4 Gate insulating film, 5 Control gate, 6 Laminated body, 7 Substrate, 8 n-type silicon region, 9 p-type silicon region, 10 source-drain region, 11 channel Region, 12 p-type silicon region, 13 suppression region

Claims (5)

A semiconductor device having a substrate containing silicon and a stacked body provided on the substrate,
The stacked body includes a suppression region containing fluorine on at least the substrate side of the side wall of the stacked body. The laminate has an insulating film provided on the substrate,
The semiconductor device according to claim 1, wherein the suppression region is provided at least on the side wall side of the insulating film. The laminate is provided on the upper side of a channel region provided in the substrate,
The semiconductor device according to claim 1, wherein a fluorine concentration in the suppression region is higher than a fluorine concentration in the channel region. The laminate further includes a conductive film containing silicon provided on the opposite side of the insulating film from the substrate side,
The suppression region includes fluorine introduced into the insulating film and fluorine moved from at least one of the conductive film and the channel region to the insulating film by heat treatment. The semiconductor device according to any one of 1 to 3. 5. The semiconductor device according to claim 1, wherein a fluorine concentration in the suppression region is 10 ¹⁹ atoms / cm ⁻³ or more and 10 ²¹ atoms / cm ⁻³ or less.