JP2012174707A - Semiconductor manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a capacitor using a strontium titanate film as a capacitance insulation film, which has large capacitance and less leakage current.SOLUTION: In a semiconductor manufacturing method, after forming a lower electrode, a multilayer film in which an intermediate titanium nitride film and an amorphous strontium titanate film contacting each other are laminated on the lower electrode. Subsequently, the intermediate titanium nitride film and the amorphous strontium titanate film are converted into a crystalline strontium titanate film by performing first heat treatment. Subsequently, an upper electrode is formed on the crystalline strontium titanate film.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

In recent years, miniaturization has progressed in DRAMs, and in the generations after the design rule of 40 nm, an insulating film having a high dielectric constant is required as a dielectric film for capacitors. At present, the use of SrTiO _x (strontium titanate; x represents a positive number and may be a natural number or a decimal number, hereinafter referred to as “STO”) is being studied as one of the candidates (Patent Literature). 1).

JP 2001-111000 A

  However, it is difficult to reduce the leakage current in a capacitor using a conventional STO film, and it is difficult to use it as a dielectric film suitable for a miniaturized DRAM memory cell.

One embodiment is:
Forming a lower electrode;
Forming a laminated film in which an intermediate titanium nitride film and an amorphous strontium titanate film are in contact with each other on the lower electrode;
Converting the intermediate titanium nitride film and the amorphous strontium titanate film into a crystalline strontium titanate film by performing a first heat treatment;
Forming an upper electrode on the crystalline strontium titanate film;
The present invention relates to a method for manufacturing a semiconductor device including a capacitor.

  In a capacitor using a strontium titanate film as a capacitor insulating film, a capacitor having a large capacitance and a small leakage current can be formed.

It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 1st Example. It is a figure which shows the relationship between the crystallization temperature of an amorphous STO film, and the amorphous Sr / Ti ratio in an amorphous STO film. It is a figure which shows the cross-sectional SEM image of a crystalline STO film | membrane and a titanium nitride film. It is a figure which shows the relationship between the film thickness of an intermediate titanium nitride film, and crystalline Sr / Ti ratio of the crystalline STO film | membrane after heat processing. It is a figure which shows the relationship between the dielectric constant (epsilon) r of a STO capacitor, and the film thickness of an intermediate titanium nitride film. It is a figure which shows the relationship between the leakage current of a STO capacitor, and the film thickness of an intermediate titanium nitride film. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 2nd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 2nd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 2nd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 2nd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 2nd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 3rd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 3rd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 3rd Example. It is a graph which shows the dependence of a dielectric constant and leakage current with respect to the amount of aluminum dope. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by the modification of 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by the modification of 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by the modification of 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by the modification of 4th Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device by the modification of 4th Example.

  The manufacturing method and structure of the STO capacitor according to the first embodiment will be described with reference to FIGS. 1 to 5 are sectional views showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 6 shows the crystallization temperature of an amorphous STO film (hereinafter referred to as “amorphous STO film”) and the atomic ratio of strontium (Sr) and titanium (Ti) in the amorphous STO film. FIG. 4 is a diagram showing a relationship (hereinafter referred to as “amorphous Sr / Ti ratio”). 7A and 7B are cross-sectional SEM images of an STO film in a crystalline state (hereinafter referred to as “crystalline STO film”) and a titanium nitride film. FIG. 8 is a graph showing the relationship between the film thickness of the intermediate titanium nitride film and the atomic ratio of Sr and Ti (hereinafter referred to as “crystalline Sr / Ti ratio”) in the crystalline STO film after the heat treatment. FIG. 9 is a diagram showing the relationship between the relative dielectric constant εr of the STO capacitor and the film thickness of the intermediate titanium nitride film. FIG. 10 is a graph showing the relationship between the leakage current of the STO capacitor and the film thickness of the intermediate titanium nitride film.

As shown in FIG. 1, an interlayer film 112 made of a silicon oxide film was formed on a semiconductor substrate 111 such as silicon. Thereafter, a capacitor contact plug 113 penetrating the interlayer film 112 and connected to the semiconductor device 111 was formed. A capacitor lower electrode film was formed on the capacitor contact plug 113. A ruthenium film (Ru) was used as the material of the lower electrode film. The ALD method was used for forming the lower electrode film, and Ru (C ₇ H ₁₁ ) (C ₇ H ₉ ) was used as the source gas. The method for forming the lower electrode film is not limited to this, and an MOCVD method or the like can be used. The thickness of the lower electrode film was 10 nm. After the formation of the lower electrode film, patterning was performed using a lithography technique and a dry etching technique to form the lower electrode 114.

As shown in FIG. 2, a titanium nitride film (TiN) was formed on the lower electrode 114. Hereinafter, this titanium nitride film is referred to as “intermediate titanium nitride film 115”. The thickness of the titanium nitride film was changed to 0.5 nm, 1 nm, 1.5 nm, and 2 nm for evaluation. Hereinafter, the film thickness of the formed intermediate titanium nitride film 115 is denoted as “tTiN”. Here, as a comparison, a film having a thickness of 0 nm without forming a titanium nitride film was also formed. The titanium nitride film was formed by using the ALD method and alternately supplying TiCl ₄ and NH ₃ as source gases. The manufacturing method of the titanium nitride film is not limited to this, and an MOCVD method or the like may be used.

As shown in FIG. 3, an amorphous STO film 116 was formed. An ALD method was used to form the amorphous STO film 116. In the ALD method, a strontium (Sr) source gas was supplied for a predetermined time with the semiconductor substrate heated to about 300 ° C. (step (a)). Thereafter, O ₃ was supplied as an oxidizing raw material gas for a predetermined time to cause an oxidation reaction of strontium, and then a purge was performed (step (b)). Subsequently, after supplying the titanium raw material gas for a predetermined time, O ₃ was supplied as an oxidizing raw material gas for a predetermined time to cause an oxidation reaction of titanium (step (c)). Thereafter, purging was performed (step (d)). In the ALD method, the STO film formation cycle including steps (a) and (b) is 1 cycle or more, and the Ti material film formation cycle including steps (c) and (d) is 1 cycle or more. A cycle is constructed. Then, the amorphous Sr / Ti ratio of the amorphous STO film was adjusted by adjusting the number of cycles of the Sr raw material film forming cycle and the Ti raw material film forming cycle. Further, the film thickness of the STO film was adjusted by adjusting the number of STO film formation cycles.

In this embodiment, the material gas supply time for forming the amorphous STO film 116 is 10 seconds, the purge time is 10 seconds, and the film thickness is 10 nm. Note that bis (pentamethylcyclopentadienyl) strontium (Sr (C ₅ (CH ₃ ) ₅ ) ₂ ) was used as a strontium raw material. As other strontium raw materials, Sr (DPM) ₂ (DPM is dipivaloylmethanate), Sr (METHD) ₂ (METHD is methoxyethoxytetramethylheptanedionate), Sr (OC ₂ H ₅ ) ₂ , Sr (OC ₃ H ₇ ) ₂ , Sr (HfA) ₂ (HfA is hexafluoroacetylacetonate) or the like can be used, but is not particularly limited to these gases.

Tetrakis (isopropoxy) titanium Ti (OCH (CH ₃ ) ₂ ) ₄ was used as the titanium source gas. In addition, tetrakis (2-methoxy-1-methyl-1-propoxo) titanium (Ti (MMP) ₄ ), TiO (tmhd) ₂ (where tmhd is 2,2,6,6-tetramethylheptane-3 , 5-dione), Ti (depd) (tmhd) ₂ (where depd represents diethylpentadiol) and the like, but known titanium source gases can be used, but are not particularly limited to these gases.

  The composition ratio of the formed amorphous STO film 116 was examined by RBS (Rutherford backscattering spectroscopy) measurement or the like. In this example, the amorphous Sr / Ti ratio was 1.6. This is because, as will be described later with reference to FIG. 4, the crystallization temperature is lowered by making strontium excessive, and the STO film can be prevented from peeling off. In this embodiment, the manufacturing method of the amorphous STO film 116 is described by the ALD method. However, the manufacturing method is not limited to this, and the amorphous STO film 116 may be formed by an MOCVD method, a sputtering method, or the like.

  As shown in FIG. 4, the substrate on which the amorphous STO film 116 was formed was heat-treated to crystallize the amorphous STO film 116 to form a crystalline STO film 116a. The crystallization heat treatment was performed using an RTA (Rapid Thermal Anneal) method in a nitrogen atmosphere. The temperature was 600 ° C. for 5 minutes. This heat treatment temperature was determined based on the following experimental results.

  A titanium nitride film and a 10 nm amorphous STO film are sequentially formed on a silicon substrate, and then subjected to a heat treatment at different heat treatment temperatures, to determine whether the formed STO film has crystallinity or not. Investigated by measurement. The amorphous STO film was formed by changing the amorphous Sr / Ti ratio to 0.8, 1.0, 1.2, 1.4, and 1.6. For each, the crystallization temperature was examined. The result is shown in FIG.

  In FIG. 6, the amorphous state is indicated by □, and the crystallized state is indicated by ■. The crystallization temperature varies depending on each amorphous Sr / Ti ratio. The crystallization temperatures are 620 ° C. when the amorphous Sr / Ti ratio is 0.8 and 610 ° C. when the amorphous Sr / Ti ratio is 1. 590 ° C. when the amorphous Sr / Ti ratio was 1.2, 580 ° C. when the amorphous Sr / Ti ratio was 1.4, and 570 ° C. when the amorphous Sr / Ti ratio was 1.6. When the amorphous Sr / Ti ratio was 1.8 or 2.0, 570 ° C., and when the amorphous Sr / Ti ratio was 1.6 or more, the crystallization temperature became constant. Similarly, on the ruthenium film, when the crystallization temperature and the amorphous Sr / Ti ratio dependence were examined, the crystallization temperature and the amorphous Sr / Ti ratio dependence almost the same as those on the titanium nitride film were obtained. The dependence of the material of the lower electrode was not seen. As described above, the reason why the crystallization temperature tends to decrease as the amorphous Sr / Ti ratio increases is not clear. However, a strontium oxide is easily crystallized at a low temperature due to excessive strontium. (SrO oxide)) and the like are formed, and titanium oxide (TiO oxide) is taken into the crystal nucleus to grow the STO crystal.

  Next, after forming a titanium nitride film on the silicon substrate and forming an amorphous STO film with an amorphous Sr / Ti ratio of 1.6 nm on the titanium nitride, the heat treatment temperature is set under the above heat treatment conditions. SEM observation was performed by changing the temperature between 570 ° C. and 700 ° C. at intervals of 10 ° C. As a result, in the sample heat-treated at 650 ° C. or higher, film peeling was observed at the interface between the titanium nitride film and the crystalline STO film 116a. No peeling of the film was observed in the sample heat-treated at 640 ° C. or lower. When the same observation was performed while changing the amorphous Sr / Ti ratio to 1, peeling was observed at about 650 ° C. or higher.

  FIG. 7A shows a cross-sectional SEM photograph when the amorphous Sr / Ti ratio is 1.6 and the heat treatment temperature is 600 ° C., and FIG. 7B shows a cross-sectional SEM photograph when the heat treatment temperature is 650 ° C. In the sample performed at 650 ° C., circular spots are observed when viewed from the top, and FIG. 7B shows a cross section of the portion. In a portion that appeared as a circular spot, peeling 121 occurred between the crystalline STO film and the titanium nitride film. The STO film has poor adhesion to the lower electrode, suggesting that attention to peeling is necessary. In addition, the heat treatment time was not dependent on time and ease of peeling in the range up to 1 hour. Similarly, when the lower electrode was a ruthenium film, the heat treatment temperature and peeling were observed, but showed a tendency to peel off at substantially the same temperature.

  Thus, it has been found that the STO film is easily peeled off by a heat treatment at 650 ° C. or higher, and that the crystallization heat treatment needs to be performed at a temperature lower than 650 ° C. The temperature at which this peeling occurs was determined by SEM observation. However, in order to surely suppress peeling, it is desirable that the temperature is lowered from 650 ° C. with a margin.

  On the other hand, the crystallization temperature is 570 ° C. to 620 ° C., and there is no room for the temperature range between the crystallization temperature and the temperature at which peeling occurs. Further, it is preferable to perform the crystallization heat treatment at a temperature as high as possible higher than the crystallization temperature and to sufficiently perform the crystallization in order to increase the dielectric constant. Therefore, the crystallization temperature is in a temperature range lower than 650 ° C., and it is desirable that the temperature be as low as possible in such a temperature range. With such a crystallization temperature, the temperature difference between the heat treatment temperature and the crystallization temperature can be increased, crystallization can be sufficiently performed, and a temperature margin of 650 ° C. at which peeling occurs can be secured. As described above, it is desirable to lower the crystallization temperature. For this purpose, from the result of the relationship between the crystallization temperature and the amorphous Sr / Ti ratio, the amorphous state during the formation of the amorphous STO film 116 is reduced. It is effective to increase the Sr / Ti ratio and lower the crystallization temperature. For this reason, the amorphous Sr / Ti ratio of the amorphous STO film 116 is preferably 1.6 or more. In this embodiment, the amorphous Sr / Ti ratio of the amorphous STO film 116 is 1.6. Thereby, the crystallization temperature could be lowered to 570 ° C., and the heat treatment temperature of the crystallization heat treatment was performed at 600 ° C. which was sufficiently lower than 650 ° C. at which peeling was observed. Thereby, it becomes possible to promote crystallization while suppressing peeling.

  Subsequent to the crystallization heat treatment, an oxidizing atmosphere heat treatment is performed as necessary to sufficiently supply oxygen into the STO film. The temperature is lower than the crystallization heat treatment so that peeling does not occur. In this embodiment, the process was performed at 450 ° C. for 10 minutes in an oxygen atmosphere and a furnace.

  As shown in FIG. 5, an upper electrode film was formed. A ruthenium (Ru) film was used as the material of the upper electrode film. The upper electrode film can be formed in the same manner as the lower electrode film in the process of FIG. The film thickness of the upper electrode film was 10 nm. The upper electrode film was patterned by using a photolithography technique and an etching technique to form the upper electrode 117. Through this process, a crystalline STO film 116a was used as an insulating film, and an SIM capacitor 118 having an MIM structure including a lower electrode 114 and an upper electrode 117 was formed above and below the crystalline STO film 116a. The atomic ratio of five types of STO capacitors 118 formed by varying the film thickness tTiN was examined.

  The atomic ratio of Sr and Ti in the crystalline STO film 116a was examined by RBS measurement. This atomic number ratio is referred to as “crystalline Sr / Ti ratio” in distinction from the amorphous Sr / Ti ratio, which is the number of atoms in the amorphous STO film. FIG. 8 shows the crystalline Sr / Ti ratio with respect to each film thickness tTiN of the intermediate titanium nitride film. At tTiN = 0 nm, the same 1.6 as in the amorphous state was shown. On the other hand, at tTiN = 0.5 nm, 1 nm, 1.5 nm and 2 nm, the values are smaller than 1.6 in the amorphous state, and are 1.3, 1.0, 0.8 and 0.7, respectively. It was.

  When these are seen, the crystalline Sr / Ti ratio is smaller as the tTiN is thicker in the sample in which the intermediate titanium nitride film 115 is formed. This means that as the film thickness tTiN of the intermediate titanium nitride film 115 increases, the proportion of titanium in the crystalline STO film 116a increases. During the crystallization heat treatment, the intermediate titanium nitride film It is suggested that 115 is taken into the STO film and the crystalline Sr / Ti ratio is lowered.

  Next, dielectric constant characteristics and leakage current characteristics were evaluated for the various STO capacitors produced. FIG. 9 shows the dependence of the relative dielectric constant εr on the titanium nitride film thickness tTiN. At tTiN = 0 nm where the intermediate titanium nitride film 115 is not formed, the relative dielectric constant εr is as small as about 40. In the STO capacitor with tTiN = 0.5 nm in which the intermediate titanium nitride film was formed at 0.5 nm, the relative dielectric constant εr increased to about 90. Further, at tTiN = 1.0 nm and 1.5 nm where the thickness of the intermediate titanium nitride film 115 was increased, the relative dielectric constant εr was about 100, which was the largest value. Further, at tTiN = 2 nm where the thickness of the intermediate titanium nitride film 115 was increased, the relative dielectric constant decreased to about 50. These STO capacitors can obtain a large value compared to the relative dielectric constant of about 20 to 30 of the conventional zirconium oxide film. In particular, when TiN = 0.5 and 1.0.1.5, the relative dielectric constant is close to 100. The ratio εr was obtained, and a very good value of 3 times or more of the conventional zirconium oxide film was obtained.

Let us look at the relationship between the relative dielectric constant εr and the crystalline Sr / Ti ratio of the crystalline STO film 116a. It can be seen that when the crystalline Sr / Ti ratio is 0.8 and 1.0, that is, when tTiN = 1.5 nm and 1 nm, the relative dielectric constant εr is as large as 100. When the crystalline Sr / Ti ratio changes in a larger direction, the relative dielectric constant εr is 90 when the Sr / Ti ratio is 1.3 (when tTiN = 0.5 nm), and the Sr / Ti ratio is 1.6. At that time (when tTiN = 0 nm), the relative dielectric constant εr changed to 40, which was a small direction. When the crystalline Sr / Ti ratio was changed in a direction smaller than those, the relative dielectric constant εr was changed to a direction as small as 50 when the Sr / Ti ratio was 0.7 (when tTiN = 2 nm). That is, the relative dielectric constant εr shows a peak in the vicinity of 0.8 to 1.2 near the Sr / Ti ratio of 1, and the relative dielectric constant εr decreases as it deviates from that. This is because, when the crystalline Sr / Ti ratio is close to 1, the composition ratio is close to 1 of the stoichiometric ratio of the STO film (SrTiO ₃ ), and the STO film is dominantly formed, so that the relative dielectric constant is large. It is thought that it became. It is considered that the relative dielectric constant εr of the STO film is about 100. On the other hand, when the crystalline Sr / Ti ratio> 1, excess strontium is contained, and the strontium forms a strontium oxide film (SrO _x ) and is considered to be mixed in the STO film. This strontium oxide film has a relative dielectric constant εr of about 40, which is smaller than 100, which is the relative dielectric constant εr of the obtained STO. Therefore, the STO film mixed with the strontium oxide film is considered to have a small relative dielectric constant εr as a whole. In addition, when Sr / Ti <1, excessive titanium is contained, and this titanium is considered to form a titanium oxide film (TiO _x ) and coexist in the STO film. The titanium oxide film has an anatase structure and a relative dielectric constant of about 40, and a rutile structure of about 80, and the relative dielectric constant εr is smaller than the relative dielectric constant 100 of the STO film. Therefore, the STO film mixed with the titanium oxide film is considered to have a small relative dielectric constant εr as a whole. From these results, it is shown that it is desirable to form the crystalline Sr / Ti ratio in the vicinity of 1 in order to increase the relative dielectric constant εr.

Next, a voltage was applied between the upper and lower electrodes of the capacitor, and the leakage current flowing between the electrodes was evaluated. FIG. 10 shows the dependence of the leakage current density J on the film thickness tTiN of the intermediate titanium nitride film 115. The leakage current is shown as a leakage current density when 1.0 V is applied. In the case of using a voltage configuration in which Vdd is used as the power supply voltage in the peripheral circuit region and ½ Vdd is applied to the bit line, ½ Vdd is applied to the capacitor insulating film. In the current DRAM, about 1.5 V is used for Vdd, and about 0.75 V is applied to the capacitor insulating film. In the evaluation of the leakage current, the evaluation was performed at 1.0 V in consideration of a voltage variation margin. The leakage current needs to satisfy the data retention time of the product. In the current DRAM, for example, it is required to be about 1 × 10 ⁻¹⁵ A or less per cell, and the leakage current density is 1 × 10 ⁻⁸ (A / cm ² ) or less.

When tTiN = 0 nm where the intermediate titanium nitride film 115 was not formed and 0.5 nm and 1 nm where the intermediate titanium nitride film 115 was formed, the leakage current was as small as J = 5 × 10 ⁻⁹ (A / cm ² ). At tTiN = 1.5 nm in which the intermediate titanium nitride film 115 was further thickened, the leakage current was slightly increased to 9 × 10 ⁻⁹ (A / cm ² ). When the thickness of the intermediate titanium nitride film 115 was further increased at tTiN = 2 nm, the leakage current further increased and increased by 3 digits or more to J = 5 × 10 ⁻⁵ (A / cm ² ). At tTiN = 0 to 1.5 nm, the allowable value on the product of the leakage current density was 1 × 10 ⁻⁸ (A / cm ² ) or less. On the other hand, at t = 2 nm, it was larger than the allowable value on the product and did not satisfy the specifications. From these, it was shown that it is necessary to form at t = 1.5 nm or less in this example from the viewpoint of leakage current.

  Here, the relationship between the type of capacitor electrode material and the leakage current is considered. Since the band gap of the STO film is as narrow as 3.2 eV, depending on the electrode material, there is a problem that the band offset with respect to the crystalline STO film decreases and the leakage current due to Schottky conduction increases. As a result of examining the work function of the ruthenium film and the titanium nitride film by using the XPS method, the inventors obtained 4.99 eV and 4.85 eV, respectively. As a result, the ruthenium film has a deeper work function than the titanium nitride film, suggesting that the leakage current is suppressed. Further, the electron affinity χ of the STO film is about 4.0 eV, and the band offset is estimated from this value, and 1 eV between the ruthenium film and the STO film, and 0.85 eV between the titanium nitride film and the STO film. It is estimated that about 1 eV is secured in the ruthenium film, but it is estimated that it is smaller than 1 eV in the titanium nitride film.

From the experimental results, the sample with tTiN = 0 nm had a leakage current density as small as J = 5 × 10 ⁻⁹ (A / cm ² ). The reason is considered that the current is suppressed because the estimated value of the band offset with the conduction band of the STO film is about 1 eV because the lower electrode is a ruthenium film. On the other hand, in the sample of tTiN = 2 nm, the leakage current increases as J = 5 × 10 ⁻⁵ (A / cm ² ) because the STO film is formed on the intermediate titanium nitride film formed on the ruthenium film. Since it is formed, the estimated value of the band offset with respect to the conduction band of the STO film is about 0.85 eV, which is smaller than 1 eV of the ruthenium film, so that it is estimated that the leakage current has increased.

Here, at t = 0.5 nm, 1 nm, and 1.5 nm, although the intermediate titanium nitride film is formed, the leakage current is as small as J = 1 × 10 ⁻⁸ (A / cm ² ) or less, The leakage current characteristic of tTiN = 0 nm was almost the same value. As described above, as a result of examining the composition ratio of the crystalline STO film 116a, in the sample in which the intermediate titanium nitride film 115 is formed, the crystalline Sr / Ti ratio is amorphous when the amorphous STO film 116 is formed. The quality Sr / Ti ratio was smaller than 1.6. This suggests that the ratio of titanium in the STO film is increased by incorporating the intermediate titanium nitride film into the STO film during the crystallization heat treatment. Considering the result of the leakage current characteristics obtained here, at tTiN = 0.5 nm, 1 nm, and 1.5 nm, most of the intermediate titanium nitride film 115 is taken into the crystalline STO film 116 a, and the lower electrode 114 It is considered that the ruthenium film is in contact with the crystalline STO film 116a. On the other hand, at tTiN = 2 nm, it is considered that a part of the intermediate titanium nitride film 114 is taken into the STO film after the crystallization heat treatment, but at least a part of the intermediate titanium nitride film 114 remains. Note that, at tTiN = 0.5 nm, 1 nm, and 1.5 nm, it is considered that the intermediate titanium nitride film 115 is almost taken into the crystalline STO film 116a, but a part of the intermediate titanium nitride film 115 remains slightly and remains. There is a possibility that the intermediate titanium nitride film 115 is altered and remains as an insulating film, for example, TiO _x , TiO _x N _y or the like. Even when such an insulating film is altered and remains, the effect of suppressing Schottky conduction is sufficiently exhibited.

As described above, in this embodiment, the intermediate titanium nitride film 115 formed on the ruthenium film of the lower electrode 114 is taken into the STO film during the crystallization heat treatment of the amorphous STO film 116. Thus, it is estimated that the crystalline STO film 116a is formed. Here, in the case where the Sr / Ti ratio of the amorphous STO film 116 is made larger than 1, excess strontium is contained, and this strontium is SrTiO _{3 with} titanium taken from the intermediate titanium nitride film. It is thought to form crystals. Here, when the excess strontium and the titanium of the intermediate titanium nitride film form STO, oxygen is required. The oxygen is contained in the amorphous STO film, the ruthenium film of the lower electrode, and the silicon oxide of the base substrate. It can be supplied from oxygen contained in the membrane or the like. If oxygen deficiency in the formed crystalline STO film 116a becomes a problem even if these oxygens are supplemented, the oxygen is removed by performing an oxidizing atmosphere heat treatment after the crystallization heat treatment in the step of FIG. It is effective to supplement.

  The thickness of the intermediate titanium nitride film 115 is such that the amorphous Sr / Ti ratio of the amorphous STO film 116 to be used, the thickness of the amorphous STO film 116, and the crystalline quality required for the crystalline STO film 116a to be formed. It is determined depending on the Sr / Ti ratio. The amorphous Sr / Ti ratio of the amorphous STO film 116 used here is an amorphous Sr / Ti ratio that provides a desired crystallization temperature that can satisfy the temperature of the desired crystallization heat treatment. It is decided. When obtaining a predetermined crystalline Sr / Ti ratio, it is necessary to increase the thickness of the intermediate titanium nitride film 115 as the amorphous Sr / Ti ratio increases. The thickness of the amorphous STO film 116 is determined from the breakdown voltage, leakage current, and capacitance value required for the STO capacitor 118. In order to obtain a predetermined crystalline Sr / Ti ratio, the thicker the amorphous STO film 116, the thicker the intermediate titanium nitride film 115 needs to be. The crystalline Sr / Ti ratio required for the formed crystalline STO film 116a is determined to be about 1 in order to obtain a high capacitance value. In order to obtain a predetermined crystalline Sr / Ti ratio, it is necessary to increase the thickness of the intermediate titanium nitride film 115 as the crystalline Sr / Ti ratio decreases.

  The crystallization heat treatment performed in the step of FIG. 4 needs to be performed so that almost all of the intermediate titanium nitride film 115 can be taken into the STO film. Therefore, when the intermediate titanium nitride film 115 becomes thicker, the crystallization heat treatment time is increased accordingly. Considering the influence of the heat load of the crystallization heat treatment on the transistor, the time for the crystallization heat treatment is preferably shorter, and for this purpose, the thickness of the intermediate titanium nitride film 115 is preferably thinner.

  In the method of manufacturing a semiconductor device according to the present embodiment, a step of forming an intermediate titanium nitride film having a first thickness on the lower electrode, a step of forming an amorphous STO film on the intermediate titanium nitride film, an amorphous STO film And a step of forming a crystalline STO film so as to take in the intermediate titanium nitride film.

  The amorphous STO film is formed of amorphous Sr / Ti, which is the atomic ratio of strontium and titanium, having the first atomic ratio, and the crystalline STO film is a crystal having the atomic ratio of strontium and titanium. The quality Sr / Ti has a second atomic ratio that is smaller than the first atomic ratio.

  The first atomic ratio is preferably greater than 1 and the second atomic ratio preferably has 0.8 to 1.2. After the formation of the crystalline STO film, the titanium nitride film is formed so as not to exist between the crystalline STO film and the lower electrode.

  The amorphous STO film is formed with an amorphous Sr / Ti ratio of 1.6 and heat-treated at a temperature of 600 ° C. or lower to form a crystalline STO film with a crystalline Sr / Ti ratio of 1.0. It is preferable.

  In the manufacturing method of this example, an intermediate titanium nitride film is formed on the lower electrode, an amorphous STO film having a composition with a Sr / Ti ratio larger than 1 is formed thereon, heat treatment is performed, and intermediate nitridation is performed. It is preferable to use a method of taking a titanium film and forming a crystalline STO film having an Sr / Ti ratio of about 1. As a result, a crystalline STO capacitor having a high dielectric constant and a low leakage current can be formed at a low temperature, and can be formed while suppressing the problem of peeling.

  In this embodiment, the ruthenium film is used for the upper electrode and the lower electrode. However, the present invention is not limited to this, and a material having a deep work function, in particular, a material deeper than ruthenium can be used, such as a platinum film, an iridium film, and a nickel film. A metal such as a cobalt film or a molybdenum film, or an oxide film such as a ruthenium oxide film, an iridium oxide film, or a molybdenum oxide film can be used. Further, a laminated film composed of a plurality of films selected from these may be used.

  In this embodiment, it has been described that the intermediate titanium nitride film 115 is taken into the STO film in the crystallization heat treatment. However, the heat treatment is performed in an annealing process of the interlayer film in a process after forming the STO capacitor, a heat treatment process in growing the CVD film when forming the contact plug, etc., other than the crystallization heat treatment performed in the process of FIG. Also good. However, when these heat treatments are substituted after the STO capacitor is formed, there is a problem that stress due to the change in the structure of the STO film is applied to the STO film and the film deteriorates. Can be used.

(Second embodiment)
In the second embodiment, an STO capacitor having a smaller leakage current is provided by using the technique of the first embodiment. 11 to 15 are sectional views of the semiconductor device for explaining the second embodiment.

  As shown in FIG. 11, an interlayer film 212 made of a silicon oxide film, a capacitor contact plug 213, and a lower electrode 214 were formed on a semiconductor substrate 211 in the same manner as in the step of FIG. As the material of the lower electrode 214, a ruthenium film (Ru) was used.

  Similar to the growth of the amorphous STO film in the step of FIG. 3 of the first embodiment, the amorphous first STO film 215 was formed by the ALD method. The film thickness of the amorphous first STO film 215 was 5 nm, and the amorphous Sr / Ti ratio was 1.6.

  As shown in FIG. 12, an intermediate titanium nitride film 216 was formed on the amorphous first STO film 215 in the same manner as the formation of the intermediate titanium nitride film in the step of FIG. 4 of the first embodiment. The film thickness of the intermediate titanium nitride film was formed with tTiN = 1 nm.

  As shown in FIG. 13, an amorphous second STO film 217 was formed in an amorphous state by the ALD method in the same manner as the growth of the amorphous STO film in the step of FIG. 3 of the first embodiment. The film thickness of the amorphous second STO film 217 was set to 5 nm, and the amorphous Sr / Ti ratio was formed with the same amorphous Sr / Ti = 1.6 as that of the amorphous STO film of the first example.

As shown in FIG. 14, in the same manner as the process of FIG. 4 of the first embodiment, heat treatment for 5 minutes is performed by RTA method in an inert gas atmosphere of nitrogen (N ₂ ) at 600 ° C., paying attention to peeling. Then, the amorphous first STO film 215 and the amorphous second STO film 217 were crystallized. Thus, a crystallized first STO film 215a and a crystallized second STO film 217a were formed. Subsequent to the crystallization heat treatment, an oxidizing atmosphere heat treatment was performed as necessary to sufficiently supply oxygen into the STO film. The heat treatment temperature in an oxidizing atmosphere was lower than the crystallization heat treatment so that peeling does not occur. In this embodiment, the process was performed at 450 ° C. for 10 minutes in an oxygen atmosphere and a furnace.

  As shown in FIG. 15, an upper electrode film was formed in the same manner as in the step of FIG. 5 of the first example. A ruthenium (Ru) film was used as the material of the upper electrode film. The upper electrode 218 was formed by patterning using a photolithography technique and an etching technique.

  Through the above steps, an STO capacitor 219 having an MIM structure using the STO film as an insulating film was formed. In the completed STO capacitor 219, the intermediate titanium nitride film 216 is taken in and disappears by the first STO film and the second STO film, and the crystalline first STO film 215a and the crystalline second STO film 217a are formed on the ruthenium film of the lower electrode 214. Became the structure laminated | stacked in order. That is, the amorphous second STO film 217 formed thereon was formed as a crystallized second STO film 217a with a (200) preferential orientation. The crystalline Sr / Ti ratio of the crystallized first STO film 215a and the crystallized second STO film 217a is formed to be approximately 1, respectively, so that a high relative dielectric constant εr is obtained. Between the crystallized first STO film 215a and the crystallized second STO film 217a, the crystal continuity is divided, and a grain boundary 221 extending in a planar shape is formed, which is formed substantially parallel to the upper surface of the lower electrode 214. (FIG. 14). In this way, the crystalline STO film was formed with a grain interface that was divided into two layers in the height direction, and it was possible to suppress the formation of a grain boundary that continuously runs from the lower electrode 214 to the upper electrode 218.

When the leakage current of this STO film was measured, J = 1 × 10 ⁻⁹ (A / cm ² ) and tTiN = 0, 0.5 nm, which showed the smallest leakage current obtained in the first example, Compared with J = 5 × 10 ⁻⁹ (A / cm ² ) at 1.0 nm, an even lower current could be obtained. The reason for this is considered to be that the formation of a grain boundary that continuously runs from the lower electrode to the upper electrode is suppressed.

  Next, the relative dielectric constant εr was measured. As a result, a result equal to 100 and the result obtained in the first example was obtained. When this embodiment is used, a high dielectric constant film having a smaller leakage current than that of the first embodiment can be obtained. This is effective when it is desired to reduce the leakage current.

(Third embodiment)
The crystalline STO film formed by crystallization after the formation of the amorphous STO film may have a defect level due to the loss of oxygen in the film, leading to an increase in leakage current. The present embodiment relates to an example for countering such a problem.

  The manufacturing method and structure of the STO capacitor according to the third embodiment will be described with reference to FIGS. 16 to 18 are cross-sectional views showing a method of manufacturing a semiconductor device according to the third embodiment. FIG. 19 is a graph showing the dependence of the relative permittivity and leakage current on the aluminum doping amount.

  As shown in FIG. 16, a semiconductor substrate 311, an interlayer film 312 made of a silicon oxide film, a capacitor contact plug 313, and a capacitor lower electrode 314 were formed in the same manner as in the process of FIG. As the material of the lower electrode 314, a ruthenium film (Ru) was used. The film thickness of the lower electrode 314 was 10 nm. An intermediate titanium nitride film 315 was formed in the same manner as in the process of FIG. The film thickness of the intermediate titanium nitride film 315 was formed with tTiN = 1 nm.

  An amorphous Al-containing STO film containing aluminum (Al) was formed on the intermediate titanium nitride film 315 by ALD. Hereinafter, this is referred to as “amorphous Al-containing STO film 316”. This amorphous Al-containing STO film 316 was formed with an atomic ratio Sr / Ti ratio of strontium and titanium of 1.6, as in the first example.

An ALD method was used to form the amorphous Al-containing STO film 316. A strontium (Sr) source gas was supplied for a predetermined time while the semiconductor substrate was heated to about 300 ° C., and then O ₃ was supplied as an oxidizing source gas for a predetermined time to cause an oxidation reaction of strontium. Subsequently, after supplying the titanium raw material gas for a predetermined time, an oxidation reaction of titanium is caused by supplying O ₃ as an oxidizing raw material gas for a predetermined time. This was defined as one cycle of the ALD method, and a plurality of cycles were repeated to form an STO film so as to have a desired film thickness. Furthermore, in this embodiment, after supplying the aluminum (Al) source gas for a predetermined time, the step of causing the oxidation reaction of aluminum by supplying O ₃ as the oxidizing source gas for a predetermined time is performed in the plurality of cycles. Of these, they were added to a predetermined number of cycles. The aluminum source gas supply time in the step for causing the oxidation reaction of aluminum and the number of cycles in which the step for causing the oxidation reaction of aluminum were added were adjusted so that aluminum was contained at a desired concentration in the completed STO film. . As the strontium source gas and titanium source gas, the gases shown in the first embodiment can be used. Although trimethylaluminum (TMA) was used as the aluminum source gas, it is not limited to this.

  In this embodiment, the total film thickness is 10 nm. STO films containing different aluminum concentrations were formed by changing the number of steps for causing an oxidation reaction of aluminum to be added to the cycle. Note that the film formation method is not limited to the ALD method, and an MOCVD method, a sputtering method, or the like can be used.

As in FIG. 4 of the first embodiment, paying attention to peeling, heat treatment for 5 minutes in an inert gas atmosphere of nitrogen (N ₂ ) at about 600 ° C. is performed for 5 minutes, and crystallized Al content An STO film was formed. Hereinafter, this film is referred to as “crystallized Al-containing STO film 316a”. In addition, although it is thought that crystallization temperature changes by performing aluminum dope, the influence on crystallization temperature was small at 2 at% or less used in this experiment. Subsequent to the crystallization heat treatment, an oxidizing atmosphere heat treatment was performed as necessary to sufficiently supply oxygen into the STO film. The heat treatment temperature in an oxidizing atmosphere was lower than the crystallization heat treatment so that peeling does not occur. In this embodiment, the process was performed at 450 ° C. for 10 minutes in an oxygen atmosphere and a furnace.

  As shown in FIG. 18, an upper electrode 317 was formed in the same manner as in the step of FIG. 5 of the first example. As the material of the upper electrode 317, a ruthenium (Ru) film was used. Through this process, the STO capacitor 318 having the MIM structure using the STO film as an insulating film was formed. For the crystallized Al-containing STO film 317 formed by changing the aluminum concentration, the atomic ratio Al / (Sr + Ti + Al + O) of aluminum was examined by the RBS method, and the atomic concentration varied between 0 at% and 2 at%. A sample was formed. Further, the Sr / Ti ratio was formed to be about 1.

  For these samples, the dependence of the relative permittivity (●) and the leakage current (◯) on the aluminum doping amount was examined. The results are shown in FIG. At 0 at% not containing aluminum, the relative dielectric constant εr was 100 as in the first example. In the right vertical axis indicating the relative dielectric constant εr in FIG. 19, the relative dielectric constant εr at 0 at% is normalized to 1 and indicated by a relative dielectric constant ratio. As can be seen from the graph, the relative permittivity ratio is 1 at 0 at%, and the relative permittivity ratio gradually decreases as the aluminum atom number concentration increases. In the range of 0.3 to 1 at%, the relative dielectric constant ratio is about 0.7 and the relative dielectric constant εr is about 70. In this range, a substantially constant value was shown regardless of the aluminum atom number concentration. It decreased again at 1 at% or more, and a relative dielectric constant ratio of 0.3 was shown at 2 at%. From this result, when the ratio of the number of aluminum atoms to be doped is in the range of 0.3 to 1 at%, the dielectric constant is about 70% to 80% smaller than that of the STO film not containing aluminum, but it is currently used. A sufficiently large value is obtained as compared with 20 to 30 or the like of the relative dielectric constant εr of zirconium. Moreover, the change of the relative dielectric constant εr with respect to the concentration of aluminum atoms was small and stable, and the result of suppressing the problem of variation in manufacturing was shown.

The leakage current density J = 5 × 10 ⁻⁹ (A / cm ² ) under the conditions of the first example of 0 at% not containing aluminum is shown. In the left vertical axis showing the leakage current in FIG. 19, the leakage current at 0 at% is shown as a leakage current ratio normalized to 1. When aluminum was doped at 0.1 at%, the leakage current ratio decreased sharply to 1/200 and showed a small leakage current value of J = 2 × 10 ⁻¹¹ (A / cm ² ). When doping at 0.1 at% or more, the doping amount increases and decreases gradually. From this, it was found that the leakage current can be reduced by two orders of magnitude by doping aluminum at 0.1 at% or more. This is because the STO film not containing aluminum easily causes oxygen vacancies, and a defect level is formed at a location where oxygen is released, causing leakage. Since the ion radius of aluminum is close to that of titanium (Ti), it is considered that when aluminum is doped, it is replaced with titanium (Ti) in the STO film. Aluminum is a trivalent element with little change in valence. Doping aluminum is considered to reduce the amount of oxygen vacancies and suppress leakage current. Aluminum is an element with almost no change in valence, and does not form an unstable level. As an element that can obtain the same effect as aluminum, any of gallium (Ga), indium (In), and lutetium (Lu), which are the same trivalent elements and have an atomic radius close to that of titanium, can be used.

(Fourth embodiment)
The present embodiment discloses a method of applying the capacitor of the first embodiment to a DRAM. 20 to 28 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the fourth embodiment. 29 to 33 are cross-sectional views of a semiconductor device for explaining a modification of the fourth embodiment.

  As shown in FIG. 20, the element isolation region 12 was formed on the semiconductor substrate 11. An element formation region 13 was defined by being partitioned by the element isolation region 12. After forming the gate insulating film 14, the gate conductive film 15, and the gate protective film 16, the gate electrode 17 was formed by sequentially etching using a resist mask. Using the gate electrode 17 as a mask, a source / drain region 18 was formed on the semiconductor substrate 11 by ion implantation. Sidewalls 19 were formed on the side walls of the gate electrode 17. A gate interlayer film 20 was formed so as to embed between the gate electrodes 17. A cell contact plug 21 connected to the source / drain region 18 between the gate electrodes 17 was formed. A cell contact plug interlayer 22 was formed. A bit line contact plug 23 that penetrates the cell contact plug interlayer 22 and is connected to the cell contact plug 21 on the side to which the bit line is connected was formed. A bit line 24 connected to the bit line contact plug 23 was formed. A bit line interlayer film 25 was formed. A capacitor contact plug 26 that penetrates the bit line interlayer 25 and is connected to the cell contact plug 21 on the side to which the capacitor is connected was formed.

  A capacitor interlayer 27 is formed. The material used was a silicon oxide film. In this example, a capacitor having a concave structure in which holes are formed in the interlayer film and electrodes are formed on the inner walls of the holes is used. The capacitor structure is not limited to this, and a box structure obtained by patterning a conductive film may be used.

  As shown in FIG. 21, a resist mask 411 having an opening in the capacitor hole formation region was formed by using a photolithography technique. Using the resist mask 411, etching was performed to penetrate the capacitor interlayer 27 and open the capacitor contact plug 26, thereby forming a capacitor hole 412.

As shown in FIG. 22, the lower electrode film 413 was formed from the capacitor hole 412 to the capacitor interlayer film 27. A ruthenium film (Ru) was used as the material of the lower electrode film 413. The ALD method was used for forming the lower electrode film 413, and Ru (C ₇ H ₁₁ ) (C ₇ H ₉ ) was used as the source gas. The method for forming the lower electrode film 413 is not limited to this, and an MOCVD method or the like can be used. The film thickness of the lower electrode film 413 is 10 nm, but the material is not limited to the ruthenium film, and a material having a deep work function, particularly a material deeper than ruthenium can be used. A platinum film, an iridium film, a nickel film A metal such as a cobalt film or a molybdenum film, or an oxide film such as a ruthenium oxide film, an iridium oxide film, or a molybdenum oxide film can be used. Further, a laminated film composed of a plurality of films selected from these may be used.

  As shown in FIG. 23, the lower electrode film 413 on the capacitor interlayer 27 was selectively removed, and the lower electrode 413 was formed so as to remain on the bottom surface from the side surface in the capacitor hole 412. The lower electrode 413 is connected to the capacitor contact plug 26 at the bottom. Although the CMP method is used to form the lower electrode 413, the method for forming the lower electrode 413 is not limited to this, and an etch back method may be used. In forming the lower electrode 413, a protective film such as a resist film is embedded in the recess of the lower electrode film 413 in the capacitor hole 412 in order to prevent the lower electrode film 413 in the capacitor hole 412 from being etched away. It can also be done. In that case, after removing the lower electrode film 413 on the capacitor interlayer film 27, the protective film is removed.

As shown in FIG. 24, an intermediate titanium nitride film 414 was formed in the same manner as in the step of FIG. 2 of the first example. The intermediate titanium nitride film 414 was formed by using an ALD method, and using TiCl ₄ and NH ₃ as source gases alternately. The manufacturing method of the intermediate titanium nitride film 414 is not limited to this, and an MOCVD method or the like may be used. In this embodiment, it is preferable to use a manufacturing method having excellent step coverage such as ALD method and MOCVD method. In this embodiment, the thickness of the intermediate titanium nitride film 414 is tTiN = 1 nm. The film thickness of the intermediate titanium nitride film 414 is the same as the amorphous Sr / Ti ratio used in the amorphous STO film, the film thickness, and the crystallinity after crystallization as described in the first embodiment. It is determined according to the demand for the crystalline Sr / Ti ratio of the STO film.

As shown in FIG. 25, the STO film was grown in an amorphous state as a capacitor insulating film in the same manner as in the step of FIG. 3 of the first example to obtain an amorphous STO film 415. In this embodiment, the amorphous Sr / Ti ratio of the amorphous STO film 415 is 1.6. The amorphous STO film 415 was formed using an ALD method having excellent step coverage. That is, after supplying a strontium (Sr) source gas for a predetermined time while the semiconductor substrate is heated to about 300 ° C., O ₃ is supplied as an oxidizing source gas for a predetermined time to cause an oxidation reaction of strontium, Was purged. Subsequently, after supplying the titanium raw material gas for a predetermined time, an oxidation reaction of titanium was caused by supplying O ₃ as an oxidizing raw material gas for a predetermined time, and then purge was performed. This was defined as one cycle of the ALD method, and a plurality of cycles were repeated to form an STO film so as to have a desired film thickness. In this example, the raw material gas was supplied for 10 seconds, the purge time was 10 seconds, and the film thickness was 10 nm.

Note that bis (pentamethylcyclopentadienyl) strontium (Sr (C ₅ (CH ₃ ) ₅ ) ₂ ) was used as a strontium raw material. In addition, Sr (DPM) ₂ (DPM is dipivaloylmethanate), Sr (METHD) ₂ (METHD is methoxyethoxytetramethylheptanedionate), Sr (OC ₂ H ₅ ) ₂ , Sr (OC ₃ H ₇ ) ₂ , Sr (HfA) ₂ (HfA is hexafluoroacetylacetonato) or the like can be used, but is not particularly limited to these gases. Tetrakis (isopropoxy) titanium Ti (OCH (CH ₃ ) ₂ ) ₄ was used as the titanium source gas. In addition, tetrakis (2-methoxy-1-methyl-1-propoxo) titanium (Ti (MMP) ₄ ), TiO (tmhd) ₂ (where tmhd is 2,2,6,6-tetramethylheptane-3 , 5-dione), Ti (depd) (tmhd) ₂ (where depd represents diethylpentadiol) and the like, but known titanium source gases can be used, but are not particularly limited to these gases.

  The amorphous Sr / Ti ratio, which is the composition ratio of strontium (Sr) and titanium (Ti), of the amorphous STO film 413 to be formed is the number of cycles of the Sr source film formation cycle, the number of cycles of the Ti source film formation cycle And was formed at a predetermined composition ratio. The amorphous Sr / Ti ratio of 1.6 is used here, but as described in the first embodiment, the crystallization temperature can be lowered by increasing the Sr / Ti ratio. A desired crystallization temperature that satisfies the temperature is determined so as to obtain an amorphous Sr / Ti ratio.

  In this embodiment, the amorphous STO film 415 is formed with a thickness of 10 nm. The film thickness is determined from the breakdown voltage, leakage current, and capacitance value required for the STO capacitor 462 as described in the first embodiment.

  Regarding the thickness of the intermediate titanium nitride film 414, the amorphous Sr / Ti ratio of the amorphous STO film 415 to be used, the thickness of the amorphous STO film 415, and the crystal required for the crystalline STO film 415a to be formed. Depending on the quality Sr / Ti ratio, the thickness is determined. The amorphous Sr / Ti ratio of the amorphous STO film 415 used here is an amorphous Sr / Ti ratio that provides a desired crystallization temperature that can satisfy the temperature of the desired crystallization heat treatment. It is decided. When obtaining a predetermined crystalline Sr / Ti ratio, it is necessary to increase the thickness of the intermediate titanium nitride film 414 as the amorphous Sr / Ti ratio increases. The thickness of the amorphous STO film 415 is determined from the breakdown voltage, leakage current, and capacitance value required for the STO capacitor 417 to be completed later. In order to obtain a predetermined crystalline Sr / Ti ratio, it is necessary to make the intermediate titanium nitride film 414 thicker as the amorphous STO film 415 is thicker. The crystalline Sr / Ti ratio required for the formed crystalline STO film 415a is determined to be about 1 in order to obtain a high capacitance value. It is necessary to increase the thickness of the intermediate titanium nitride film 414 as the crystalline Sr / Ti ratio decreases.

As shown in FIG. 26, the crystallization heat treatment was performed under the conditions of 600 ° C. for 5 minutes and N ₂ atmosphere for 5 minutes in the same manner as in the step of FIG. 4 of the first example. This heat treatment temperature is determined to be higher than the crystallization temperature and as low as possible with respect to 650 ° C. As described in the first embodiment, the heat treatment time is determined so that the intermediate titanium nitride film 414 can be almost completely taken in by the STO film.

  Subsequent to the crystallization heat treatment, an oxidizing atmosphere heat treatment was performed as necessary to sufficiently supply oxygen into the STO film. The heat treatment temperature in an oxidizing atmosphere was lower than the crystallization heat treatment so that peeling does not occur. In this embodiment, the process was performed at 450 ° C. for 10 minutes in an oxygen atmosphere and a furnace.

  A crystalline STO film 415a was formed as described above. In the crystallization heat treatment, the intermediate titanium nitride film 414 was taken into the STO film, and the lower surface of the crystalline STO film 415a was in contact with the ruthenium film of the lower electrode 414. The crystalline STO film 415a was formed so that the crystalline Sr / Ti ratio was approximately 1.

As shown in FIG. 27, an upper electrode film 416 was formed in the same manner as in the process of FIG. 5 of the first embodiment. As the material of the upper electrode film 416, a ruthenium film (Ru) film was used, and the ALD method having excellent step coverage was used for the film formation. Ru (C ₇ H ₁₁ ) (C ₇ H ₉ ) was used as a source gas for the upper electrode film 416. The method for forming the upper electrode is not limited to this, and an MOCVD method or the like can be used. The film thickness of the upper electrode was 10 nm. The material of the upper electrode is not limited to the ruthenium film, but a material having a deep work function, particularly a material deeper than ruthenium, can be used, such as platinum film, iridium film, nickel film, cobalt film, molybdenum film, ruthenium oxide An oxide film such as a film, an iridium oxide film, or a molybdenum oxide film can be used. Further, a laminated film composed of a plurality of films selected from these may be used.

  As shown in FIG. 28, the upper electrode film 416 was formed by patterning the upper electrode film using a photolithography technique and an etching technique. Thus, an STO capacitor 417 including a crystalline STO film 415a and a lower electrode 413 and an upper electrode 416 formed above and below the crystalline STO film 415a was formed. An interlayer film 418 on the capacitor was formed. In the peripheral circuit region, a peripheral contact connected to the bit line 24 from the interlayer film 418 on the capacitor was formed (not shown). A wiring 419 connected to the peripheral contact was formed. Thereafter, an interlayer film, a via hole, a wiring, a cap film, an interlayer film, a pad electrode, and a passivation film were formed as necessary to complete the device.

Through the above steps, a DRAM having an MIM capacitor using a crystalline STO film as an insulating film could be formed. The relative permittivity of the formed capacitor was as large as about 100, and the leak current density when 1 V was applied was as small as J = 5 × 10 ⁻⁵ (A / cm ² ). This makes it possible to manufacture a highly reliable DRAM element having excellent data retention characteristics (refresh characteristics) even when miniaturized. Although the formation method of the first embodiment is applied here, the methods of the second and third embodiments can be applied.

(Modification)
FIGS. 29-33 is a figure for demonstrating the modification of 4th Example. In the fourth embodiment described above, after forming the lower electrode film, the lower electrode is formed so as to cover the inside of the capacitor hole, and an intermediate titanium nitride film and an amorphous STO film are formed thereon to form an intermediate titanium nitride film. The method of taking in the STO film was used. In this method, an intermediate titanium nitride film 414 was formed so as to cover the capacitor interlayer 27 (FIG. 24). In the process of FIG. 26, when the intermediate titanium nitride film 414 is taken into the STO film, if the intermediate titanium nitride film remains as a residue on the capacitor interlayer film, a short circuit occurs between adjacent lower electrodes, resulting in a product defect. cause. Therefore, it is necessary to form the intermediate titanium nitride film 414 so as to be taken into the STO film so as not to remain on the capacitor interlayer film 27. In the modification, a method that does not cause such a problem is disclosed.

  As shown in FIG. 29, the same processes as in the fourth embodiment are performed until the lower electrode film 414 in FIG. 22 is formed. An intermediate titanium nitride film 511 was stacked on the lower electrode film 414. The method for forming the lower electrode film 414 is performed in the same manner as in FIG. 24 of the fourth embodiment.

  As shown in FIG. 30, the intermediate titanium nitride film 511 and the lower electrode film 413 on the capacitor interlayer film 27 are selectively removed by the same method as in FIG. A lower electrode 413 and an intermediate titanium nitride film 511 were formed so as to remain on the bottom surface. The lower electrode 413 was connected to the capacitor contact plug 26 at the bottom. Although the CMP method is used to form the lower electrode 413, the method for forming the lower electrode 413 is not limited to this, and an etch back method may be used. Moreover, you may protect the inside of a recessed part with a protective film.

  As shown in FIG. 31, an amorphous STO film 512 was formed in the same manner as in the step of FIG. 25 of the fourth embodiment.

  As shown in FIG. 32, crystallization heat treatment was performed in the same manner as in the step of FIG. 26 of the fourth example. The intermediate titanium nitride film 511 formed in the capacitor hole 412 was taken into the STO film. At this time, the amorphous STO film 512 was crystallized to form a crystalline STO film 512a. The crystalline STO film 512 a is thicker than the portion formed on the capacitor interlayer 27 because the intermediate titanium nitride film 511 is taken in the portion formed in the capacitor hole 412. Incidentally, since the intermediate titanium nitride film 511 is not formed on the annular upper surface of the lower electrode 413, the thickness of the crystalline STO film 512a becomes substantially equal to the thickness on the capacitor interlayer film 27 in that portion. It was formed thinner than the thickness of the crystalline STO film 512a in the hole 412.

  As shown in FIG. 33, an upper electrode film 513 was formed in the same manner as in the step of FIG. 27 of the fourth embodiment. The upper electrode 513 was formed by patterning using a photolithography technique and an etching technique. As a result, an STO capacitor 514 was formed. Subsequent steps were completed through the same steps as in FIG. 28 of the fourth embodiment. If this modification is used, the intermediate titanium nitride film 511 is selectively formed on the sidewall in the capacitor hole 412 in the step of FIG. Removed by. As a result, the problem of a short circuit between the adjacent lower electrodes via the intermediate titanium nitride film 511 can be prevented.

  In the STO capacitor 514 of this modified example, the film thickness of the crystalline STO film 512 a on the annular upper surface of the lower electrode 413 is formed smaller than the thickness of the crystalline STO film 512 a in the capacitor hole 412. The Therefore, the lower electrode 413 is formed in such a thickness that the leakage current and breakdown voltage in the portion on the annular upper surface satisfy the product specifications. Further, since the Sr / Ti ratio of the crystalline STO film 512a on the annular upper surface of the lower electrode 413 has an amorphous Sr / Ti ratio, the relative dielectric constant εr in this part is Although it is smaller than the relative dielectric constant εr of the portion in the capacitor hole 412, the influence as capacitance is small and can be at a level with no problem.

11 Semiconductor substrate 12 Element isolation region 13 Element formation region 14 Gate insulating film 15 Gate conductive film 16 Gate protective film 17 Gate electrode 18 Source / drain region 19 Side wall 20 Gate interlayer 21 Cell contact plug 22 Cell contact plug interlayer 23 Bit Line contact plug 24 Bit line 25 Bit line interlayer 26 Capacitor contact plug 27 Capacitor interlayer 111, 211, 311 Semiconductor substrate 112, 212, 312 Interlayer 113, 213, 313 Capacitor contact plug 114, 214, 314 Lower electrode 115, 216, 315 Intermediate titanium nitride film 116 Amorphous STO film 116a Crystalline STO film 117, 218, 317 Upper electrode 118, 219, 318 STO capacitor 121 Peeling 215 Amorphous first STO film 215a Crystallized first STO film 217 Amorphous second STO film 217a Crystallized second STO film 221 Grain boundary 316 Amorphous Al-containing STO film 316a Crystallized Al-containing STO film 317 Crystallized Al-containing STO film 411 Resist mask 412 Capacitor hole 413 Lower electrode film 414 Intermediate titanium nitride film 415 Amorphous STO film 415a Crystalline STO film 416 Upper electrode film 417, 462 STO capacitor 418 Capacitor interlayer film 419 Wiring 511 Intermediate titanium nitride film 512 Amorphous STO film 512a Crystalline STO film 513 Upper electrode film 514 STO capacitor

Claims (14)

Forming a lower electrode;
Forming a laminated film in which an intermediate titanium nitride film and an amorphous strontium titanate film are in contact with each other on the lower electrode;
Converting the intermediate titanium nitride film and the amorphous strontium titanate film into a crystalline strontium titanate film by performing a first heat treatment;
Forming an upper electrode on the crystalline strontium titanate film;
A method for manufacturing a semiconductor device including a capacitor.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the laminated film is composed of an intermediate titanium nitride film and an amorphous strontium titanate film laminated in order from the lower electrode side to the upper electrode side.   2. The semiconductor according to claim 1, wherein the stacked film is composed of an amorphous strontium titanate film, an intermediate titanium nitride film, and an amorphous strontium titanate film stacked in order from the lower electrode side to the upper electrode side. Device manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, wherein the amorphous strontium titanate film contains aluminum.   5. The method of manufacturing a semiconductor device according to claim 4, wherein an atomic ratio Al / (Sr + Ti + Al + O) in the amorphous strontium titanate film is 0.1 to 1.0 at%.   The atomic number ratio Sr / Ti in the amorphous strontium titanate film is larger than the atomic ratio Sr / Ti in the crystalline strontium titanate film according to any one of claims 1 to 5. A method for manufacturing a semiconductor device. The atomic ratio Sr / Ti in the amorphous strontium titanate film is 1 or more,
The method for manufacturing a semiconductor device according to claim 6, wherein an atomic ratio Sr / Ti in the crystalline strontium titanate film is 0.8 to 1.2.   The method for manufacturing a semiconductor device according to claim 7, wherein an atomic ratio Sr / Ti in the amorphous strontium titanate film is 1.6 or less.   The method for manufacturing a semiconductor device according to claim 1, wherein the first heat treatment is performed at a temperature lower than 650 ° C. 9.   The method for manufacturing a semiconductor device according to claim 9, wherein the first heat treatment is performed at a temperature of 600 ° C. or less. Before the step of forming the lower electrode,
Forming a MOS transistor;
Forming a bit line to be connected to the first impurity diffusion region of the MOS transistor;
Forming a capacitor contact pad to be connected to the second impurity diffusion region of the MOS transistor;
Have
In the step of forming the lower electrode,
The method for manufacturing a semiconductor device according to claim 1, wherein the lower electrode is formed so as to be connected to the capacitor contact pad. After the step of forming the capacitive contact pad,
Forming an interlayer insulating film so as to cover the capacitive contact pad;
Forming a capacitor hole in the interlayer insulating film so as to expose the capacitor contact pad;
Have
In the step of forming the lower electrode,
Forming a lower electrode in the capacitor hole;
The step of forming the laminated film includes
Forming the intermediate titanium nitride film on the lower electrode in the capacitor hole and on the interlayer insulating film;
Removing the intermediate titanium nitride film on the interlayer insulating film;
Forming the amorphous strontium titanate film on the intermediate titanium nitride film in the capacitor hole;
The method for manufacturing a semiconductor device according to claim 11, comprising:   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing a second heat treatment in an oxidizing atmosphere after the step of converting to the crystalline strontium titanate film.   The method for manufacturing a semiconductor device according to claim 13, wherein a temperature of the first heat treatment is higher than a temperature of the second heat treatment.