JP2012174498A - Plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma display panel that reduces sustained discharge voltage.SOLUTION: A first electrode 100 comprises: a first transparent electrode 101; and a first bus electrode 110 that is laminated on the first transparent electrode 101. A second electrode 200 comprises: a second transparent electrode 201; a third transparent electrode 202; and a second bus electrode 210 that is arranged between the second transparent electrode 201 and the third transparent electrode 202 and that is electrically connected to each of the second transparent electrode 201 and the third transparent electrode 202. The third electrode 300 comprises: a fourth transparent electrode 301; and a third bus electrode 310 that is laminated on the fourth transparent electrode 301. Width of the second transparent electrode 201 is equal to or larger than width of the first transparent electrode 101 but smaller than 1.3 times the width of the first transparent electrode 101. Width of the second bus electrode 210 is larger than 1.1 times width of the first bus electrode 110 but smaller than 2.6 times the width of the first bus electrode 110.

Description

  The technology disclosed herein relates to a plasma display panel used for a display device or the like.

  A plasma display panel (hereinafter referred to as PDP) has a configuration in which a front plate and a back plate are arranged to face each other. A display electrode disposed on the front plate for supplying a driving waveform is composed of a scan electrode and a sustain electrode. A sustain discharge for causing the PDP to emit light is generated between the scan electrode and the sustain electrode. The scan electrodes and the sustain electrodes are provided with bus electrodes. In order to improve the light extraction efficiency of the PDP, a technique for applying a sustain waveform to two discharge cells adjacent in the vertical direction using one bus electrode as a common electrode is disclosed. That is, one bus electrode (common bus electrode) supplies a sustain waveform to two adjacent sustain electrodes (see, for example, Patent Document 1).

JP 2009-283160 A

  However, if the bus electrode to which the sustain waveform is applied is a common bus electrode, the sustain discharge may spread to the vicinity of the common bus electrode. When the sustain discharge spreads to the vicinity of the common bus electrode, the discharge distance becomes longer. Therefore, the voltage required for the sustain discharge rises. Furthermore, depending on the viewing distance, there is a problem that a dark part is visually recognized in a specific cycle in the horizontal direction, and pixels appear rough.

  The technology disclosed herein has been made to solve the above-described problems. That is, the sustain discharge is prevented from spreading to the vicinity of the common bus electrode. Furthermore, it is possible to reduce that the dark part is visually recognized at a specific cycle in the horizontal direction, and to prevent the pixel from appearing rough. That is, an object is to provide a PDP that can suppress an increase in voltage required for the sustain discharge and that has a good appearance.

  The above object is achieved by the following PDP. The PDP includes a front plate and a back plate disposed to face the front plate. The front plate includes a plurality of display electrodes and a dielectric layer covering the display electrodes. The display electrode is configured by sequentially arranging a first electrode, a second electrode, and a third electrode. The first electrode includes a strip-shaped first transparent electrode and a first bus electrode provided to overlap the first transparent electrode. The second electrode includes a strip-shaped second transparent electrode disposed on the first electrode side, a strip-shaped third transparent electrode disposed on the third electrode side, a second transparent electrode, And a second bus electrode disposed between the third transparent electrode and electrically connected to each of the second transparent electrode and the third transparent electrode. The third electrode includes a strip-shaped fourth transparent electrode and a third bus electrode provided so as to overlap the fourth transparent electrode. The width of the second transparent electrode is not less than the width of the first transparent electrode and less than 1.3 times the width of the first transparent electrode. The width of the second bus electrode is greater than 1.1 times the width of the first bus electrode and less than 2.6 times the width of the first bus electrode.

  According to said structure, it can suppress that a sustain discharge spreads to the common bus electrode vicinity. Furthermore, it is possible to reduce that the dark part is visually recognized at a specific cycle in the horizontal direction, and to prevent the pixel from appearing rough. Therefore, it is possible to suppress an increase in the voltage necessary for the sustain discharge, and it is possible to provide a PDP having a better appearance.

It is a perspective view which shows schematic structure of PDP concerning this Embodiment. It is a figure which shows electrode arrangement | positioning of the PDP. It is a figure which shows the drive waveform of the PDP. It is a figure which shows a part of front plate concerning this Embodiment. It is a figure which shows the cross section of the front plate. It is a figure which shows the accumulation state of the wall charge in the front plate.

(Embodiment)
The PDP 1 of the present embodiment is an AC surface discharge type PDP. In the present embodiment, as shown in FIG. 1, a three-dimensional orthogonal coordinate system including an X axis, a Y axis, and a Z axis is defined. Hereinafter, in each drawing, description will be made with reference to the XYZ coordinate system as appropriate. As shown in FIG. 1, the PDP 1 has a structure in which a front plate 2 including a front glass substrate 5 and the like and a back plate 3 including a back glass substrate 11 and the like face each other. The outer peripheral portions of the front plate 2 and the back plate 3 are hermetically sealed with a sealing material made of glass frit or the like. A discharge gas such as Ne (neon) and Xe (xenon) is sealed at a pressure of 55 kPa to 80 kPa in the discharge space inside the sealed PDP 1. Note that light emission of the PDP 1 is extracted from the positive direction of the Z axis.

  The front plate 2 has display electrodes 8 formed on the front glass substrate 5. The display electrode 8 extends in the Y-axis direction. The display electrode 8 includes a first electrode 100, a second electrode 200, and a third electrode 300. The first electrode 100 includes a first transparent electrode 101 and a first bus electrode 110. The first electrode 100 is a scan electrode that provides a scan voltage waveform. The second electrode 200 includes a second transparent electrode 201, a second bus electrode 210, and a third transparent electrode 202. The second transparent electrode 201 and the second bus electrode 210 constitute a sustain electrode that gives a sustain waveform. Further, the third transparent electrode 202 and the second bus electrode 210 constitute a sustain electrode that gives a sustain waveform. That is, the second bus electrode 210 is a common bus electrode for the second transparent electrode 201 and the third transparent electrode 202. The third electrode 300 includes a fourth transparent electrode 301 and a third bus electrode 310. The third electrode 300 is a scan electrode that gives a scan voltage waveform.

  Further, the front plate 2 includes a dielectric layer 9 that covers the display electrode 8 and a protective layer 10 that covers the dielectric layer 9. In addition, in order to improve the contrast of the display image, the front plate 2 may include a black stripe or a black matrix.

  The back plate 3 has a plurality of address electrodes 12 formed on the back glass substrate 11. The address electrode extends in the X-axis direction. That is, the address electrode 12 is arranged in a direction orthogonal to the display electrode 8. Further, the back plate 3 has a base dielectric layer 13 that covers the address electrodes 12. On the base dielectric layer 13, a partition 4 composed of a horizontal partition 4 a and a vertical partition 4 b is disposed. The horizontal partition 4a extends in the Y-axis direction. The vertical partition 4b extends in the X-axis direction. The vertical barrier rib 4 b is formed at a position corresponding to between the two address electrodes 12. Further, the back plate 3 has a phosphor layer 14 formed between adjacent barrier ribs 4. For example, the phosphor layer 14 includes a phosphor that emits red light, a phosphor that emits green light, and a phosphor that emits blue light.

  As shown in FIG. 2, the PDP 1 has n scan electrodes SC1, SC2, SC3,... SCn arranged extending in the Y-axis direction. The PDP 1 has n sustain electrodes SU1, SU2, SU3,... SUn arranged extending in the Y-axis direction. The PDP 1 has m address electrodes A1... Am that are arranged extending in the X-axis direction. A discharge cell is formed at a portion where scan electrode SC1 and sustain electrode SU1 intersect address electrode A1. M × n discharge cells are formed in the discharge space. An area where the discharge cells are formed is an image display area. The scan electrode and the sustain electrode are connected to a connection terminal provided at a peripheral end portion outside the image display area of the front plate. The address electrode is connected to a connection terminal provided at a peripheral end portion outside the image display area of the back plate.

  As shown in FIG. 3, the PDP 1 is driven by a subfield driving method. One field is composed of a plurality of subfields. One subfield has an initialization period, an address period, and a sustain period. The initialization period is a period in which the initialization discharge is generated in the discharge cell. The address period is a period for generating an address discharge for selecting a discharge cell to emit light after the initialization period. The sustain period is a period in which a sustain discharge is generated in the discharge cell selected in the address period.

  In the initializing period of the first subfield, the address electrodes A1 to Am and the sustain electrodes SU1 to SUn are held at 0 (V). In addition, a ramp voltage that gradually rises from voltage Vi1 (V) that is equal to or lower than the discharge start voltage to voltage Vi2 (V) that exceeds the discharge start voltage is applied to scan electrodes SC1 to SCn. Then, the first weak setup discharge occurs in all the discharge cells. Due to the initialization discharge, negative wall voltage is stored on scan electrodes SC1 to SCn. Positive wall voltage is stored on sustain electrodes SU1 to SUn and address electrodes A1 to Am. The wall voltage is a voltage generated by wall charges accumulated on the protective layer 10 and the phosphor layer 14.

  Thereafter, sustain electrodes SU1 to SUn are maintained at positive voltage Vh (V). A ramp voltage that gently falls from voltage Vi3 (V) toward voltage Vi4 (V) is applied to scan electrodes SC1 to SCn. Then, the second weak setup discharge is generated in all the discharge cells. The wall voltage between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is weakened. The wall voltage on the address electrodes A1 to Am is adjusted to a value suitable for the write operation.

  In the subsequent address period, scan electrodes SC1 to SCn are temporarily held at Vr (V). Next, negative scan pulse voltage Va (V) is applied to scan electrode SC1 in the first row. Further, a positive address pulse voltage Vd (V) is applied to the address electrode Ak (k = 1 to m) of the discharge cell to be displayed in the first row among the address electrodes A1 to Am. At this time, the voltage at the intersection between the address electrode Ak and the scan electrode SC1 is obtained by adding the wall voltage on the address electrode Ak and the wall voltage on the scan electrode SC1 to the externally applied voltage (Vd−Va) (V). It becomes. That is, the voltage at the intersection between the address electrode Ak and the scan electrode SC1 exceeds the discharge start voltage. Address discharge occurs between address electrode Ak and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1. A positive wall voltage is accumulated on scan electrode SC1 of the discharge cell in which the address discharge has occurred. A negative wall voltage is accumulated on sustain electrode SU1 of the discharge cell in which the address discharge has occurred. A negative wall voltage is accumulated on the address electrode Ak of the discharge cell in which the address discharge has occurred.

  On the other hand, the voltage at the intersection of the address electrodes A1 to Am to which the address pulse voltage Vd (V) is not applied and the scan electrode SC1 does not exceed the discharge start voltage. Accordingly, no address discharge occurs. The above address operation is sequentially performed until the discharge cell in the nth row. The address period ends when the address operation of the discharge cell in the n-th row ends.

  In the subsequent sustain period, positive sustain pulse voltage Vs (V) is applied to scan electrodes SC1 to SCn as the first voltage. A ground potential, that is, 0 (V) is applied as a second voltage to sustain electrodes SU1 to SUn. In the discharge cell in which the address discharge has occurred at this time, the voltage between scan electrode SCi and sustain electrode SUi is the sustain pulse voltage Vs (V), the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Is added and exceeds the discharge start voltage. Then, sustain discharge occurs between scan electrode SCi and sustain electrode SUi. The phosphor layer is excited by the ultraviolet rays generated by the sustain discharge and emits light. A negative wall voltage is accumulated on scan electrode SCi. A positive wall voltage is accumulated on sustain electrode SUi. A positive wall voltage is accumulated on the address electrode Ak.

  In the discharge cells where no address discharge has occurred during the address period, no sustain discharge occurs. Therefore, the wall voltage at the end of the initialization period is maintained. Subsequently, 0 (V) as the second voltage is applied to scan electrodes SC1 to SCn. Sustain pulse voltage Vs (V), which is the first voltage, is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage between sustain electrode SUi and scan electrode SCi exceeds the discharge start voltage. Therefore, a sustain discharge occurs again between sustain electrode SUi and scan electrode SCi. That is, a negative wall voltage is accumulated on sustain electrode SUi. A positive wall voltage is accumulated on scan electrode SCi.

  Thereafter, similarly, the discharge cells in which the address discharge is generated in the address period when the sustain pulse voltages Vs (V) corresponding to the luminance weight are alternately applied to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn. Sustain discharge occurs continuously. When the application of the predetermined number of sustain pulse voltages Vs (V) is completed, the sustain operation in the sustain period ends.

  The operations in the initialization period, the writing period, and the sustain period after the subsequent second subfield are substantially the same as the operations in the first subfield. Therefore, detailed description is omitted. In the second and subsequent subfields, a selective initializing operation may be performed in which an initializing discharge is selectively generated only in the discharge cells that have generated a sustain discharge in the previous subfield. In the present embodiment, the all-cell initializing operation and the selective initializing operation are selectively used between the first subfield and the other subfields. However, the all-cell initialization operation may be performed in an initialization period in a subfield other than the first subfield. Further, the all-cell initialization operation may be performed once every several fields.

  The operations in the writing period and the sustain period are the same as those in the first subfield described above. However, the operation in the sustain period is not necessarily the same as the operation in the first subfield described above. The number of sustain discharge pulses Vs (V) changes in order to generate a sustain discharge that can provide luminance corresponding to the image signal sig. In other words, the sustain period is driven to control the luminance for each subfield.

  Next, a method for manufacturing the PDP 1 will be described in detail. First, a method for manufacturing the front plate 2 will be described. Display electrodes 8 are formed on front glass substrate 5 by photolithography. Specifically, first, the first transparent electrode 101, the second transparent electrode 201, the third transparent electrode 202, and the fourth transparent electrode 301 are formed on the front glass substrate 5. In the following description, the first transparent electrode 101, the second transparent electrode 201, the third transparent electrode 202, and the fourth transparent electrode 301 are simply referred to as “transparent electrodes”.

  As an example, the transparent electrode is formed by patterning a thin film of a material transparent to visible light, such as an ITO (Indium Tin Oxide) film.

  Next, the first bus electrode 110, the second bus electrode 210, and the third bus electrode 310 are formed. In the following description, the first bus electrode 110, the second bus electrode 210, and the third bus electrode 310 are simply referred to as “bus electrodes”.

  As a material for the bus electrode, an electrode paste containing silver (Ag), a glass frit for binding silver, a photosensitive resin, a solvent, and the like is used. First, an electrode paste is applied to the front glass substrate 5 by a screen printing method or the like. Next, the solvent in the electrode paste is removed by a drying furnace. Next, the electrode paste is exposed through a photomask having a predetermined pattern.

  Next, the electrode paste is developed to form a bus electrode pattern including a photosensitive resin. Finally, the bus electrode pattern is fired at a predetermined temperature in a firing furnace. That is, the photosensitive resin or the like in the bus electrode pattern is removed. Further, the glass frit in the bus electrode pattern is melted. The molten glass frit binds silver by vitrification again after firing. A bus electrode is formed by the above process.

  In addition to the method of screen printing the electrode paste, a sputtering method, a vapor deposition method, or the like can be used. The bus electrode may have a stacked structure of a black electrode containing a black pigment for improving the contrast of the image display surface and a metal electrode for ensuring conductivity. Details of the display electrode 8 will be described later.

  Next, the dielectric layer 9 is formed. As a material for the dielectric layer 9, a dielectric paste containing a dielectric glass frit, a resin, a solvent, and the like is used. First, a dielectric paste is applied on the front glass substrate 5 by a die coating method or the like so as to cover the display electrode 8 with a predetermined thickness. Next, the solvent in the dielectric paste is removed by a drying furnace. Finally, the dielectric paste is fired at a predetermined temperature in a firing furnace. That is, the resin in the dielectric paste is removed. Further, the dielectric glass frit is melted. The molten glass frit is vitrified again after firing. Through the above steps, the dielectric layer 9 is formed.

  In addition to the method of die coating the dielectric paste, a screen printing method, a spin coating method, or the like can be used.

  Next, a protective layer 10 made of magnesium oxide (MgO) or the like is formed on the dielectric layer 9. The protective layer 10 can be formed by a vacuum deposition method, a CVD method, a sputtering method, or the like.

  The front plate 2 is completed through the above steps.

  Next, a method for manufacturing the back plate 3 will be described. First, the address electrode 12 is formed on the rear glass substrate 11 by photolithography. As an address electrode material, silver (Ag) for securing conductivity, glass frit for binding silver, a photosensitive resin, a solvent, and the like are used. First, the address electrode paste is applied on the rear glass substrate 11 with a predetermined thickness by screen printing or the like. Next, the solvent in the address electrode paste is removed by a drying furnace. Next, the address electrode paste is exposed through a photomask having a predetermined pattern. Next, the address electrode paste is developed to form an address electrode pattern. Finally, the address electrode pattern is fired at a predetermined temperature in a firing furnace. That is, the photosensitive resin in the address electrode pattern is removed. Further, the glass frit in the address electrode pattern is melted. The molten glass frit is vitrified again after firing. The address electrode 12 is formed by the above process.

  In addition to the method of screen printing the address electrode paste, a sputtering method, a vapor deposition method, or the like can be used.

  Next, the base dielectric layer 13 is formed. As a material for the base dielectric layer 13, a base dielectric paste containing a dielectric glass frit, a resin, a solvent, and the like is used. First, a base dielectric paste is applied by a screen printing method or the like so as to cover the address electrodes 12 on the rear glass substrate 11 on which the address electrodes 12 are formed with a predetermined thickness. Next, the solvent in the base dielectric paste is removed by a drying furnace. Finally, the base dielectric paste is fired at a predetermined temperature in a firing furnace. That is, the resin in the base dielectric paste is removed. Further, the dielectric glass frit is melted. The molten dielectric glass frit is vitrified again after firing. Through the above steps, the base dielectric layer 13 is formed.

  In addition to the method of screen printing the base dielectric paste, a die coating method, a spin coating method, or the like can be used. Further, a film to be the base dielectric layer 13 can be formed by CVD (Chemical Vapor Deposition) method or the like without using the base dielectric paste.

  Next, the partition walls 4 are formed by photolithography. As a material for the partition 4, a partition paste including a filler, a glass frit for binding the filler, a photosensitive resin, a solvent, and the like is used. First, the barrier rib paste is applied on the underlying dielectric layer 13 with a predetermined thickness by a die coating method or the like. Next, the solvent in the partition wall paste is removed by a drying furnace. Next, the barrier rib paste is exposed through a photomask having a predetermined pattern. Next, the barrier rib paste is developed to form a barrier rib pattern. Finally, the partition pattern is fired at a predetermined temperature in a firing furnace. That is, the photosensitive resin in the partition pattern is removed. Further, the glass frit in the partition wall pattern is melted. The molten glass frit is vitrified again after firing. The partition 4 is formed by the above process.

  In addition to the photolithography method, a sand blast method or the like can be used.

  Next, the phosphor layer 14 is formed. As the phosphor layer 14 material, a phosphor paste containing phosphor particles, a binder, a solvent and the like is used. First, a phosphor paste is applied on the underlying dielectric layer 13 between adjacent barrier ribs 4 and on the side surfaces of the barrier ribs 4 by a dispensing method or the like. Next, the solvent in the phosphor paste is removed by a drying furnace. Finally, the phosphor paste is fired at a predetermined temperature in a firing furnace. That is, the resin in the phosphor paste is removed. The phosphor layer 14 is formed by the above steps.

  In addition to the dispensing method, a screen printing method or the like can be used.

  The back plate 3 is completed through the above steps.

  Finally, a method for assembling the front plate 2 and the back plate 3 will be described. First, a sealing material (not shown) is formed around the back plate 3 by a dispensing method. As a material for the sealing material (not shown), a sealing paste containing glass frit, a binder, a solvent, and the like is used. Next, the solvent in the sealing paste is removed by a drying furnace. Next, the front plate 2 and the back plate 3 are arranged to face each other so that the display electrodes 8 and the address electrodes 12 are orthogonal to each other. Next, the periphery of the front plate 2 and the back plate 3 is sealed with glass frit. Finally, a discharge gas containing Ne, Xe or the like is enclosed in the discharge space 15.

  Next, details of the display electrode 8 will be described. As shown in FIG. 4, the display electrode 8 is arranged in order so that the first electrode 100, the second electrode 200, and the third electrode 300 are orthogonal to the X axis. The first electrode 100 includes a strip-shaped first transparent electrode 101 and a first bus electrode 110 provided so as to overlap the first transparent electrode 101. The second electrode 200 is disposed on the first electrode 100 side (X-axis positive direction) and the strip-shaped second transparent electrode 201, and on the third electrode side (X-axis negative direction). The band-shaped third transparent electrode 202 is disposed between the second transparent electrode 201 and the third transparent electrode 202 and is electrically connected to each of the second transparent electrode 201 and the third transparent electrode 202. The second bus electrode 210 is provided. The third electrode 300 includes a strip-shaped fourth transparent electrode 301 and a third bus electrode 310 provided so as to overlap the fourth transparent electrode 301. The width W2 of the second transparent electrode 201 is equal to or greater than the width W1 of the first transparent electrode 101 and less than 1.3 times the width W1 of the first transparent electrode 101. The width D2 of the second bus electrode 210 is greater than 1.1 times the width D1 of the first bus electrode 110 and less than 2.6 times the width D1 of the first bus electrode 110.

  The second bus electrode 210 gives a sustain voltage waveform to the second transparent electrode 201 and the third transparent electrode 202.

  In addition, a first discharge gap is formed between the first transparent electrode 101 and the second transparent electrode 201. A second discharge gap is formed between the third transparent electrode 202 and the fourth transparent electrode 301.

  That is, in the discharge cell in which the first electrode 100 and the second transparent electrode 201 are arranged, the sustain discharge starts from the first discharge gap. In the discharge cell in which the third electrode 300 and the third transparent electrode 202 are arranged, the sustain discharge starts from the second discharge gap.

  Further, an interpixel gap (IPG) is formed between the first bus electrode 110 and the third bus electrode 310 adjacent to the first bus electrode 110 in the positive X-axis direction. No discharge occurs between the electrodes sandwiching the IPG. Furthermore, an IPG is formed along the second bus electrode 210. A horizontal partition wall 4a is formed in a region facing the IPG. That is, the second bus electrode 210 is formed at a position facing the horizontal partition wall 4a.

  As shown in FIG. 5, the first electrode 100 is provided with the first bus electrode 110 overlapped in the negative Z-axis direction of the first transparent electrode 101.

  The dielectric layer 9 is formed using a dielectric paste as a material as described above. Therefore, when the dielectric paste is applied onto the front glass substrate 5, a flat dielectric paste layer is formed without depending much on the structure (such as bus electrodes) formed on the front glass substrate 5. By the drying and firing, the dielectric paste shrinks and the dielectric layer 9 is formed. However, the surface of the dielectric layer 9 remains generally flat. That is, the distance from the front glass substrate 5 to the surface of the dielectric layer 9 is substantially constant. Therefore, the thickness of the dielectric layer 9 on the bus electrode is smaller than the thickness of the dielectric layer 9 in the region where the bus electrode is not formed.

  That is, as shown in FIG. 5, since the first bus electrode 110 has a predetermined thickness, the total T1 of the thickness of the dielectric layer 9 on the first bus electrode 110 and the thickness of the protective layer 10. Is smaller than the total T2 of the thickness of the dielectric layer 9 on the second transparent electrode 201 and the thickness of the protective layer 10.

  That is, when the width of the second transparent electrode 201 is smaller than the width of the first transparent electrode 101, the capacitance accumulated on the first electrode 100 when the above driving waveform is applied to the first electrode 100. Becomes larger than the capacity accumulated on the second transparent electrode 201. That is, the wall charge accumulated on the first electrode 100 is larger than the wall charge accumulated on the second transparent electrode 201. At this time, the spread of the sustain discharge starting from the first discharge gap spreads to the vicinity of the second bus electrode 210 in order to balance the wall charges. When the sustain discharge spreads to the vicinity of the second bus electrode 210, the voltage necessary for the sustain discharge rises. Further, the second bus electrode 210 is formed in a region facing the horizontal partition 4a. When the spread of the sustain discharge approaches the horizontal barrier rib 4a, the light emission efficiency decreases.

  However, in the present embodiment, as shown in FIG. 4, the width W2 of the second transparent electrode 201 is equal to or larger than the width W1 of the first transparent electrode 101 and 1 of the width W1 of the first transparent electrode 101. It is configured to be less than 3 times. According to this configuration, the capacity accumulated on the first electrode 100 is equal to or less than the capacity accumulated on the second transparent electrode 201. That is, as shown in FIG. 6, the wall charge accumulated on the first electrode 100 becomes equal to or less than the wall charge accumulated on the second transparent electrode 201. Therefore, it is possible to suppress the sustain discharge starting from the first discharge gap from spreading to the vicinity of the second bus electrode 210. That is, by using the second bus electrode 210 that gives a sustain waveform as a common bus electrode, an increase in the sustain discharge voltage in the PDP 1 can be suppressed while enjoying the benefit of improving the light extraction efficiency of the PDP 1.

  Furthermore, depending on the viewing distance of the PDP 1, the first bus electrode 110, the third bus electrode 310, and the horizontal partition wall 4a may be visually recognized as a unit. In this case, it seems that dark portions are periodically generated in the horizontal direction (Y-axis direction) of the PDP 1. That is, the pixel is visually recognized as coarse, and the appearance of the PDP 1 is deteriorated.

  However, in the present embodiment, the width D2 of the second bus electrode 210 is larger than 1.1 times the width D1 of the first bus electrode 110 and 2.6 times the width D1 of the first bus electrode 110. Is less than. By increasing the width D2 of the second bus electrode 210, the antiphase component of the region where the first bus electrode 110, the third bus electrode 310, and the horizontal partition wall 4a are integrated can be strengthened. Therefore, it can be suppressed that a dark part appears to be periodically generated in the horizontal direction (Y-axis direction) of the PDP 1. Furthermore, the greater the magnification within the above range, the greater the suppression effect.

  The present inventors produced a plurality of PDPs 1 having a cell pitch in the X-axis direction in the range of 480 μm to 576 μm. The basic configuration of the PDP 1 is as described above. Further, a neon (Ne) -xenon (Xe) -based mixed gas having a xenon (Xe) content of 15% by volume was enclosed in PDP 1 at an internal pressure of 60 kPa. The present inventors have confirmed that an increase in the sustain discharge voltage of PDP 1 can be suppressed under the following conditions. Furthermore, the present inventors confirmed that a dark part is not periodically visible in the horizontal direction of PDP1. The thickness of the bus electrode is 4 μm to 6 μm, the thickness of the transparent electrode is 0.2 μm, W1 and W4 are 120 μm to 160 μm, W2 and W3 are 120 μm to 200 μm, the thickness of the dielectric layer 9 is 20 μm to 25 μm, and the ratio of the dielectric layers The dielectric constant is 4.5 to 7.0. Here, after W1 was first determined, W2 was determined to be equal to or greater than W1 and less than 1.3 times W1. The same applies to W4 and W3. Further, D1 and D3 are 40 μm to 80 μm, and D2 is 44 μm to 210 μm.

  As shown in FIGS. 4 and 5, the second transparent electrode 201 is arranged at a predetermined interval from the second bus electrode 210, and a part of the second transparent electrode 201 It is preferably electrically connected to the bus electrode 210. This is because the spread of the sustain discharge starting from the first discharge gap can be further suppressed.

  Furthermore, it is preferable that the second transparent electrode 201 and the second bus electrode 210 are connected at one or more locations for one discharge cell. This is because the sustain voltage waveform is more reliably applied from the second bus electrode 210 to the second transparent electrode 201.

  Further, as shown in FIG. 4, the distance L1 between the center of the first discharge gap in the X-axis direction and the first discharge gap side end portion of the first bus electrode 110 is the X-axis of the first discharge gap. The distance L2 is preferably shorter than the distance L2 between the center in the direction and the first discharge gap side end of the second bus electrode 210. This is because the sustain discharge starting from the first discharge gap can be further suppressed from spreading toward the second bus electrode 210 side.

  Further, as shown in FIGS. 4 and 5, the width W3 of the third transparent electrode 202 is equal to or larger than the width W4 of the fourth transparent electrode 301 and the width W4 of the fourth transparent electrode 301 is 1. It is preferably less than 3 times. This is because the sustain discharge starting from the second discharge gap can be prevented from spreading to the vicinity of the second bus electrode 210. Further, the width D2 of the second bus electrode 210 is preferably greater than 1.1 times the width D3 of the third bus electrode 310 and less than 2.6 times the width D3 of the third bus electrode 310. . This is because it can be suppressed that a dark part appears to be periodically generated in the horizontal direction (Y-axis direction) of the PDP 1.

  Furthermore, as shown in FIG. 4, the third transparent electrode 202 is arranged at a predetermined interval from the second bus electrode 210, and a part of the third transparent electrode 202 is part of the second bus electrode 210. Are preferably electrically connected to each other. This is because the spread of the sustain discharge starting from the second discharge gap can be further suppressed.

  Furthermore, it is preferable that the third transparent electrode 202 and the second bus electrode 210 are connected at one or more locations for one discharge cell. This is because the sustain voltage waveform is more reliably applied from the second bus electrode 210 to the third transparent electrode 202.

  Further, the distance L3 between the center of the second discharge gap in the X-axis direction and the second discharge gap side end portion of the third bus electrode 310 is the same as the distance between the center of the second discharge gap in the X-axis direction and the second discharge gap. It is preferable that the distance between the bus electrode 210 and the second discharge gap side end portion is shorter than the distance L4. This is because it is possible to further suppress the sustain discharge starting from the second discharge gap from spreading toward the second bus electrode 210 side.

  The technology disclosed herein can realize a PDP capable of reducing the sustain voltage. Therefore, it is useful for a display device with a large screen.

1 PDP
2 Front plate 3 Back plate 4 Partition 4a Horizontal partition 4b Vertical partition 5 Front glass substrate 8 Display electrode 9 Dielectric layer 10 Protective layer 11 Back glass substrate 12 Address electrode 13 Base dielectric layer 14 Phosphor layer 100 First electrode 101 1st transparent electrode 110 1st bus electrode 200 2nd electrode 201 2nd transparent electrode 202 3rd transparent electrode 300 3rd electrode 301 4th transparent electrode 310 3rd bus electrode

Claims (6)

A front plate,
A back plate disposed opposite to the front plate,
The front plate includes a plurality of display electrodes and a dielectric layer covering the display electrodes,
The display electrode is configured by sequentially arranging a first electrode, a second electrode, and a third electrode,
The first electrode includes a strip-shaped first transparent electrode and a first bus electrode provided to overlap the first transparent electrode,
The second electrode includes a strip-shaped second transparent electrode disposed on the first electrode side, a strip-shaped third transparent electrode disposed on the third electrode side, and the second electrode A second bus electrode disposed between the transparent electrode and the third transparent electrode and electrically connected to each of the second transparent electrode and the third transparent electrode,
The third electrode has a belt-like fourth transparent electrode and a third bus electrode provided to overlap the fourth transparent electrode,
The width of the second transparent electrode is equal to or greater than the width of the first transparent electrode and less than 1.3 times the width of the first transparent electrode;
The width of the second bus electrode is greater than 1.1 times the width of the first bus electrode and less than 2.6 times the width of the first bus electrode.
Plasma display panel. The second transparent electrode is disposed at a predetermined interval from the second bus electrode, and a part of the second transparent electrode is electrically connected to the second bus electrode.
The plasma display panel according to claim 1. The width of the third transparent electrode is not less than the width of the fourth transparent electrode and less than 1.3 times the width of the fourth transparent electrode,
The width of the second bus electrode is greater than 1.1 times the width of the third bus electrode and less than 2.6 times the width of the third bus electrode.
The plasma display panel according to any one of claims 1 and 2. The third transparent electrode is disposed at a predetermined interval from the second bus electrode, and a part of the third transparent electrode is electrically connected to the second bus electrode.
The plasma display panel according to claim 3. A first discharge gap is formed between the first transparent electrode and the second transparent electrode, and a first discharge gap side end of the first discharge gap and the first bus electrode. Is shorter than the distance between the center of the first discharge gap and the first discharge gap side end of the second bus electrode,
The plasma display panel according to claim 2. A second discharge gap is formed between the third transparent electrode and the fourth transparent electrode, and the second discharge gap side end portion of the center of the second discharge gap and the third bus electrode. Is shorter than the distance between the center of the second discharge gap and the second discharge gap side end of the second bus electrode,
The plasma display panel according to claim 4 or 5.

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