JP2012174087A - Power-supply device operation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power-supply device operation circuit capable of reducing a reverse current and preventing failures of a power-supply device internal circuit and the like.SOLUTION: A power-supply device operation circuit connected between a power-supply device and a device load and adapted to control power supply includes first and second ORing transistors which are connected in parallel to a current pathway for connecting the power-supply device and the device load and controlled to be in an OFF state from an ON state in accordance with first and second control signals, respectively; a monitor part for monitoring the amount of current flowing in the current pathway; and a detection circuit for changing the first ORing transistor from the ON state to the OFF state by the first control signal when the current flowing in the current pathway becomes a first value according to a monitoring result from the monitor part and for changing the second ORing transistor from the ON state to the OFF state by the second control signal when the current flowing in the current pathway becomes a second value smaller than the first value.

Description

  The present invention relates to a power supply device operation circuit, and more particularly to a power supply device operation circuit including an ORing FET.

  When a power supply operating in parallel fails, when repairing the failed power supply by hot-plugging, the output terminal of the power supply unit is usually used to prevent the occurrence of rapid charging current to the output capacitor when a new power supply is inserted. Use an ORing circuit to prevent backflow.

  Here, when a power supply device fails, the current flows back to the failed power supply device, and current may be drawn from another power supply operating in parallel. In this case, an ORING FET (power supply device operation circuit) including an ORing FET is used to control the ON / OFF of the ORING FET so that a normally operating power supply device does not stop.

  In addition, there exist patent document 1 and patent document 2 etc. as a prior art.

JP 2002-198792 A JP 2000-322132 A

  However, with the recent increase in the output current of the power supply device, it has become necessary to use a plurality of ORing FETs. When a plurality of ORing FETs are used, the total input capacity of the FETs also increases, and there is a problem that a delay occurs in the time for turning off after detecting the backflow of current. When such a problem occurs, there is a possibility that the internal circuit components of the power supply device may break down due to the reverse current due to the delay of the FET turn-off time.

  An object of the present invention is to provide a power supply operation circuit that reduces a backflow current and prevents a failure of a power supply internal circuit or the like.

  The present invention is a power supply device operation circuit that is connected between a power supply device and a device load and controls power supply from the power supply device to the device load, and is a current that connects the power supply device and the device load. The first and second ORing transistors connected in parallel to the path and controlled from the on state to the off state according to the first and second control signals, respectively, and the amount of current flowing through the current path are monitored. When the current flowing through the current path from the monitoring unit and the monitoring result from the monitoring unit becomes the first value, the first ORing transistor is turned off from the on state by the first control signal, A detection circuit that turns the second ORing transistor from an on state to an off state by the second control signal when the second value is smaller than the first value. Source device is an operation circuit.

  The present invention can reduce a backflow current and prevent a failure of a power supply device.

3 is a configuration of a power supply device operation circuit according to the first exemplary embodiment. 1 is a configuration example of a system to which a power supply device operation circuit according to a first embodiment is connected. 3 is a configuration of a detection circuit according to the first exemplary embodiment. 3 is an operation timing chart of the power supply device operation circuit according to the first exemplary embodiment; 3 is a configuration of a power supply device operation circuit according to a second exemplary embodiment.

  Embodiment 1 of the Invention

  Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the first embodiment, the present invention is applied to a power supply apparatus operation circuit.

  FIG. 1 shows a configuration of a power supply operation circuit 100 according to the present embodiment. As shown in FIG. 2, the power supply device operation circuit 100 is arranged in parallel between the plurality of power supply devices and the device load RZ, and supplies power from the plurality of power supply devices to the device load RZ. Each of power supply device operation circuit 100 and device load RZ are connected by node N1.

  As shown in FIG. 1, the power supply device operation circuit 100 includes a current detection resistor Rs, a detection circuit 10, ORing FET control circuits 11 to 13, FETs (Field Effect Transistors) Q11 to Q13, and terminals T11 to T13. Have

  The terminal T11 is connected to the output line of the power supply device. Terminal T12 is connected to a connection node (node N1 in FIG. 2) of device load RZ. The terminal T13 is connected to the ground terminal GND.

  The current detection resistor Rs has one end connected to the terminal T11 and the other end connected to the terminal T12. Here, the voltage at one end of the current detection resistor Rs is V2, and the voltage at the other end is V1. If the current I1 flows through the current detection resistor Rs, the potential difference (V2−V1) between both ends of the current detection resistor Rs is I1 × Rs. Here, when a backflow of current occurs due to a malfunction of the power supply device, I1 decreases, so the potential difference (V2−V1) between both ends of the current detection resistor Rs also decreases.

  Thus, the amount of current flowing through the current path connecting the terminals T11 and T12 can be monitored by the potential difference (V2−V1) between both ends of the current detection resistor Rs. Therefore, the current detection resistor Rs can be regarded as a monitor unit that monitors the amount of current.

  The FET Q11 has a source and a drain connected to a current path connecting the terminals T11 and T12. The gate control signal P11 from the ORing FET control circuit 11 is input to the gate. The FET Q12 has a source and a drain connected to a current path connecting the terminals T11 and T12. The gate control signal P12 from the ORing FET control circuit 12 is input to the gate. The FET Q13 has a source and a drain connected to a current path connecting the terminals T11 and T12. The gate control signal P13 from the ORing FET control circuit 13 is input to the gate.

  In response to the detection control signal S11, the ORing FET control circuit 11 outputs a gate control signal P11 so that the FET Q11 is turned off. For example, when the low-level detection control signal S11 is input, the gate control signal P11 is set to low level, and the FET Q11 is turned off.

  In response to the detection control signal S12, the ORing FET control circuit 12 outputs a gate control signal P12 so that the FET Q12 is turned off. For example, when the low-level detection control signal S12 is input, the gate control signal P12 is set to low level, and the FET Q12 is turned off.

  In response to the detection control signal S13, the ORing FET control circuit 13 outputs a gate control signal P13 so that the FET Q13 is turned off. For example, when a low level detection control signal S13 is input, the gate control signal P13 is set to low level and the FET Q13 is turned off.

  The detection circuit 10 outputs detection control signals S11 to S13 according to the potential difference between the voltages V2 and V1. FIG. 3 shows the configuration of the detection circuit 10. As shown in FIG. 3, the detection circuit 10 includes an operational amplifier Z1, comparators Z2 to Z4, resistors R1 to R7, and terminals T21 to T25.

  The terminal T21 receives the voltage V1. A voltage V2 is input to the terminal T22.

  The resistor R1 is connected between the terminal T21 and the node N21. The resistor R2 is connected between the node N21 and the node N23. The resistor R3 is connected between the terminal T22 and the node N22. The resistor R4 is connected between the node N21 and the ground terminal GND.

  The operational amplifier Z1 has an inverting input terminal connected to the node N21, a non-inverting input terminal connected to the node N22, and an output terminal connected to the node N23.

  As can be seen from the above connection configuration, the resistors R1 to R4 and the operational amplifier Z1 constitute a differential amplifier circuit. Therefore, the voltage V3 obtained by amplifying the potential difference (V1−V2) between both ends of the current detection resistor Rs is applied to the node N23.

  The comparator Z2 has a non-inverting input terminal connected to the node N23, a reference voltage Vref1 input to the inverting input terminal, and an output terminal connected to the terminal T23. The resistor R5 is connected between the power supply terminal Vcc and the terminal T23. The voltage applied to the terminal T23 is output from the detection circuit 10 to the ORing FET control circuit 11 as a detection control signal S11.

  The comparator Z2 outputs a low-level detection control signal S11 when the voltage V3 of the node N23 is lower than the reference voltage Vref1, and outputs a high-level detection control signal S11 when higher than the reference voltage Vref1.

  The comparator Z3 has a non-inverting input terminal connected to the node N23, a reference voltage Vref2 input to the inverting input terminal, and an output terminal connected to the terminal T24. The resistor R6 is connected between the power supply terminal Vcc and the terminal T24. The voltage applied to the terminal T24 is output from the detection circuit 10 to the ORing FET control circuit 12 as a detection control signal S12.

  The comparator Z3 outputs a low-level detection control signal S12 when the voltage V3 at the node N23 is lower than the reference voltage Vref2, and a high-level detection control signal S12 when it is higher than the reference voltage Vref2.

  The comparator Z4 has a non-inverting input terminal connected to the node N23, a reference voltage Vref3 input to the inverting input terminal, and an output terminal connected to the terminal T25. The resistor R6 is connected between the power supply terminal Vcc and the terminal T25. The voltage applied to the terminal T25 is output from the detection circuit 10 to the ORing FET control circuit 13 as a detection control signal S13.

  The comparator Z4 outputs a low level detection control signal S13 when the voltage V3 of the node N23 is lower than the reference voltage Vref3, and a high level detection control signal S13 when higher than the reference voltage Vref3.

  Here, the relationship between the reference voltages Vref1 to Vref3 is Vref1> Vref2> Vref3.

  Next, operation | movement of the power supply device operation circuit 100 concerning this Embodiment 1 is demonstrated using FIG. FIG. 4 shows a transition state with respect to time of the voltage of the node N23, the detection control signals S11 to S13, and the FETs Q11 to Q13 for explaining the operation of the power supply apparatus operation circuit 100.

  The detection circuit 10 detects a potential difference (V1−V2) between both ends of the current detection resistor Rs. When a backflow of current occurs due to a malfunction of the power supply device or a change in the device load RZ, the current flowing through the current detection resistor Rs also decreases. When the current flowing through the current detection resistor Rs decreases, the potential difference (V1−V2) across the current detection resistor Rs also decreases, and the voltage V3 at the node N23 also decreases as shown in FIG.

  When the voltage V3 falls below the reference voltage Vref1 at time t1, the output of the comparator Z2 becomes low level, and the detection control signal S11 of low level is output from the detection circuit 10. The ORing FET control circuit 11 changes the FET Q11 from the on state to the off state by the gate control signal P11 in response to the low level detection control signal S11.

  When the voltage V3 further decreases and becomes lower than the reference voltage Vref2 at time t2, the output of the comparator Z3 becomes low level, and the low level detection control signal S12 is output from the detection circuit 10. The ORing FET control circuit 12 changes the FET Q12 from the on state to the off state by the gate control signal P12 in response to the low level detection control signal S12.

  When the voltage V3 further decreases and becomes lower than the reference voltage Vref3 at time t3, the output of the comparator Z4 becomes low level, and the low level detection control signal S13 is output from the detection circuit 10. In response to the low level detection control signal S13, the ORing FET control circuit 13 causes the FET Q13 to transition from the on state to the off state by the gate control signal P13.

  Here, in recent years, with the increase in the output current of the power supply device, it has become necessary to use a plurality of ORing FETs. When a plurality of ORing FETs are used, the total input capacity of the FETs also increases. In the prior art, even if a reverse current flow is detected due to a malfunction of the power supply device, there is a problem that a delay occurs between the detection of the reverse current and the turning off of the OR FET when the total input capacitance of the plurality of ORing FETs is large. There was a problem that the internal circuit components of the power supply failed due to the reverse current due to this delay.

  However, in the power supply device operation circuit 100 according to the first embodiment, the plurality of ORing FETs are turned off stepwise in accordance with a decrease in the potential difference between both ends of the current detection resistor Rs accompanying an increase in the backflow current. Thus, the number of on-state ORing FETs can be controlled according to the output load. This means that the total input capacitance of the FET can be reduced in stages, and the time until the ORing FET is turned off can be shortened, preventing the failure of the power supply internal circuit components, which has been a problem in the prior art. It becomes possible.

  Embodiment 2 of the Invention

  Hereinafter, a specific second embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the second embodiment, as in the first embodiment, the present invention is applied to a power supply apparatus operation circuit.

  FIG. 5 shows a configuration of a power supply device operation circuit 200 according to the second exemplary embodiment. As shown in FIG. 5, the power supply device operation circuit 200 includes a current transformer circuit CT1, a resistor Rct, a detection circuit 10, ORing FET control circuits 11 to 13, FETs Q11 to Q13, and terminals T11 to T13. .

  In addition, the structure which attached | subjected the code | symbol same as FIG. 1 among the code | symbols shown in FIG. 5 has shown the structure similar to or similar to FIG. The second embodiment is different from the first embodiment in that a current transformer circuit CT1 and a resistor Rct are used instead of the current detection resistor Rs. Therefore, in the second embodiment, only the differences are described, and the description of the same parts as in the first embodiment is omitted.

  In the current transformer circuit CT1, one end on the primary winding side is connected to the terminal T11, the other end is connected to the terminal T12, one end on the secondary winding side is connected to the node N31, and the other end is connected to the node N32. Although this current transformer circuit CT11 performs current detection like the current detection resistor Rs of the first embodiment, the amount of current flowing to the secondary winding side can be controlled by the turn ratio M of the primary side to the secondary side. is there. For example, when a current I1 flows on the primary winding side, I1 × M flows on the secondary winding side.

  The resistor Rct has one end connected to the node N31 and the other end connected to the node N32. A current flowing through the secondary winding side of the above-described current transformer circuit CT1 flows through the resistor Rct. The voltage on one end side is V2, and the voltage on the other end side is V1. Assuming that the current I1 × M flows through the resistor Rct, the potential difference (V2−V1) between both ends of the resistor Rct is I1 × M × Rct.

  The voltages V1 and V2 are input to the detection circuit 10 as in the first embodiment. Note that, when current backflow occurs due to a failure of the power supply device or fluctuation of the device load RZ, etc., I1 decreases, so that the potential difference (V2−V1) between both ends of the resistor Rct also decreases as in the first embodiment. .

  Thus, the amount of current flowing through the current path connecting the terminals T11 and T12 can be monitored by the potential difference (V2−V1) between both ends of the resistor Rct. For this reason, the current transformer circuit CT1 and the resistor Rct can be regarded as a monitor unit.

  The operation of the detection circuit 10 due to the decrease in the potential difference (V2−V1) is the same as that described in the first embodiment. That is, the operations of the power supply device operation circuit 200 other than the current transformer circuit CT1 and the resistor Rct described above are the same as those in the first embodiment, and the diagram for explaining the operation is also the same as FIG. For this reason, explanation here is omitted.

  The power supply device operation circuit 200 according to the second embodiment uses a current transformer circuit CT1 for current detection instead of the current detection resistor Rs of the first embodiment, and has resistance Rct rather than current detection by the current detection resistor Rs. The effect of reducing the loss is obtained. Other effects are the same as those of the first embodiment.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, in the above-described embodiment, three ORing FETs are arranged in parallel, but a configuration in which a plurality of FETs are further provided may be used.

100, 200 Power supply device operation circuit Rs Current detection resistor 10 Detection circuit 11-13 ORing FET control circuit Q11-Q13 FET
T11 to T13 terminal Z1 operational amplifier Z2 to Z4 comparator R1 to R7 resistance T21 to T25 terminal CT1 current transformer circuit Rct resistance

Claims (5)

A power supply device operation circuit connected between a power supply device and a device load and controlling power supply from the power supply device to the device load,
First and second ORing transistors that are connected in parallel to a current path that connects the power supply device and the device load, and are controlled from an on state to an off state in response to first and second control signals, respectively. When,
A monitor for monitoring the amount of current flowing in the current path;
When the current flowing through the current path becomes a first value from the monitoring result from the monitoring unit, the first ORing transistor is turned off from the on state by the first control signal, and the first And a detection circuit that turns the second ORing transistor from an on state to an off state by the second control signal when the second value is smaller than the second value. The monitor unit has a current detection resistor disposed on the current path,
The power supply device operation circuit according to claim 1, wherein the detection circuit detects an amount of current flowing through the current path based on a potential difference between both ends of the current detection resistor. The monitor unit is
A current transformer in which a primary winding side is disposed on the current path;
A first resistor connected to both ends on the secondary winding side of the current transformer,
The power supply device operation circuit according to claim 1, wherein the detection circuit detects an amount of current flowing through the current path based on a potential difference between both ends of the first resistor. The detection circuit includes an amplifier that amplifies the potential difference;
A first comparator that outputs the first control signal when the output voltage of the amplifier is equal to or lower than a first reference voltage corresponding to the first value;
4. A second comparator that outputs the second control signal when an output voltage of the amplifier becomes equal to or lower than a second reference voltage corresponding to the second value. The power supply device operation circuit described in 1. A first ORing transistor control circuit connected between a control terminal of the first ORing transistor and the detection circuit;
A second ORing transistor control circuit connected between a control terminal of the second ORing transistor and the detection circuit;
The first ORing transistor control circuit drives the first ORing transistor from an OFF state to an ON state in response to the first control signal,
The power supply device operation circuit according to claim 4, wherein the second ORing transistor control circuit drives the second ORing transistor from an OFF state to an ON state in response to the second control signal.

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