JP6421707B2 - Power circuit - Google Patents

Description

  The present invention relates to a power supply circuit.

  Some power supply circuits suppress overshoot of the output voltage when the power supply input to the power supply terminal rises. However, in a power supply circuit that outputs power that is input from a path different from the power supply terminal for circuit drive, when the input rises later than the power supply or when the power supply causes an instantaneous power failure, Since this is a condition, an overshoot occurs.

  Further, even when the minimum operating voltage of the reference voltage circuit and the minimum operating voltage of the control amplifier are different, overshoot may occur at the time of recovery from the power supply voltage drop.

JP 2009-284615 A

  The present invention has been made in view of the above circumstances, and its purpose is to prevent the output from overshooting not only when the power supply is turned on, but also in various cases when the power supply voltage drops and then recovers. An object of the present invention is to provide a power supply circuit that can be suppressed.

The power supply circuit according to claim 1, an output transistor provided between an input terminal and an output terminal, a reference voltage circuit that generates a reference voltage from a power supply having a power supply voltage different from the input voltage of the input terminal, a control amplifier for outputting a predetermined voltage to the output terminal by controlling the output transistor in accordance with the difference between the output voltage generated in the reference voltage and the output terminal that is set by the reference voltage circuit, said supply voltage and An output prohibition circuit (13, 13a) that cancels the output prohibition signal when both of the input voltages reach the respective detection voltages, and when the output prohibition signal is canceled, the input voltage is applied to the input terminal. When the output transistor is operated by the control amplifier in a state, the reference voltage generated by the reference voltage circuit is lower than the control amplifier. And et started and a voltage control circuit for applying raised to the reference voltage.

  By adopting the above configuration, in the state where the input voltage is lowered, the power supply voltage is lowered, or the output prohibition signal is output due to other conditions, the drive control of the output transistor by the control amplifier is stopped. Thereafter, when the return of the input voltage and the power supply voltage or other conditions are released and the output prohibition signal is released, the input voltage is applied to the input terminal and the output transistor is operated by the control amplifier. At this time, the voltage control circuit gives the control amplifier a reference voltage generated by the reference voltage circuit starting from a voltage lower than the reference voltage and increasing it to the reference voltage. As a result, the output transistor is controlled so as to gradually output the voltage without causing an overshoot by being driven with a voltage suddenly applied.

Electrical configuration diagram showing the first embodiment Time chart showing the status of each part Electrical configuration diagram showing the second embodiment Time chart showing the status of each part Electrical configuration diagram showing the third embodiment Electrical configuration diagram showing the fourth embodiment Time chart showing the status of each part Electrical configuration diagram showing the fifth embodiment Time chart showing the status of each part Electrical configuration diagram showing the sixth embodiment

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. In the power supply circuit 1 shown in FIG. 1, the output transistor 2 is an N-channel MOSFET. The drain of the output transistor 2 is connected to the input terminal IN, the source is connected to the output terminal OUT, and is connected to the ground via the output voltage monitoring voltage dividing circuit 3. A gate drive signal is given to the gate of the output transistor 2 from the control amplifier 4. The voltage dividing circuit 3 includes two resistors 3a and 3b connected in series. The terminal voltage of the resistor 3b is output to the inverting input terminal of the control amplifier 4 as the monitor voltage Vfb of the output voltage VOUT.

  The reference voltage circuit 5 generates and outputs a reference voltage Vref based on the DC voltage supplied from the DC power supply VD. The voltage control circuit 6 outputs the reference voltage Vref given from the reference voltage circuit 5 to the non-inverting input terminal of the control amplifier 4 as the reference voltage Vrefa. The voltage control circuit 6 is provided with a change-over switch 7 on the input side, and is connected to the control amplifier 4 via a resistor 8a and is connected to the ground via a capacitor 8b. A charging circuit 9 is configured by the resistor 8a and the capacitor 8b.

  The changeover switch 7 switches between a state in which the terminal of the resistor 8a is connected to the output terminal of the reference voltage circuit 5 and a state in which the terminal of the resistor 8a is disconnected from the reference voltage circuit 5 and connected so as to short-circuit the charging circuit 9. The gate of the output transistor 2 is connected to the ground via the switch 10. The switch 10 turns on the output transistor 2 by connecting the gate of the output transistor 2 to the ground in the on state.

  The voltage of the DC power supply VD is detected by the power supply voltage monitoring circuit 11 and outputs a signal indicating whether or not the power supply drop detection voltage VDth has been reached. The voltage of the input terminal IN is detected by the input voltage monitoring circuit 12, and a signal indicating whether or not the input drop detection voltage VINth is reached is output. In the output prohibition state in which the output prohibition signal S is output, the output prohibition circuit 13 holds the charging circuit 9 in a short-circuited state with respect to the changeover switch 7, holds the switch 10 in the on state, and turns off the output transistor 2. I have to.

  The output prohibition circuit 13 outputs an output prohibition signal S in response to input signals from the power supply voltage monitoring circuit 11 and the input voltage monitoring circuit 12. In this case, the condition is that the power supply voltage monitoring circuit 11 detects that the voltage of the DC power supply VD has reached the detection voltage VDth, and the input voltage monitoring circuit 12 detects that the input voltage VIN has reached the detection voltage VINth. It is. In response to this, the output prohibition circuit 13 cancels the output prohibition state in which the output prohibition signal S is output, connects the charging circuit 9 to the output terminal of the reference voltage circuit 5 with respect to the changeover switch 7, and turns off the switch 10. Let

  Next, the operation of the above configuration will be described with reference to FIG. First, before the voltage of the DC power supply VD rises (before time t0 in FIG. 2A), the output inhibition circuit 13 outputs the output inhibition signal S as shown in FIG. The Thereby, the changeover switch 7 is held in a state where the charging circuit 9 composed of the resistor 8a and the capacitor 8b is short-circuited, and the switch 10 is turned on and the output transistor 2 is held in the off state. In this state, the input voltage VIN (FIG. 2B) to the input terminal IN is still zero, and therefore the reference voltage Vref (FIG. 2D) and the output voltage VOUT of the output terminal OUT (FIG. 2E) )) Is also zero.

  Next, when the voltage of the DC power supply VD reaches the detection voltage VDth at time t0 (FIG. 2A), the power supply voltage monitoring circuit 11 detects this and outputs a detection signal to the output inhibition circuit 13. The output prohibition circuit 13 cancels the output prohibition signal S at this time t0. In this state, the reference voltage circuit 5 is in a state capable of generating and outputting the reference voltage Vref based on the voltage of the DC power supply VD. However, since the output prohibition circuit 13 does not receive a signal indicating that the input voltage VIN has reached the detection voltage VINth from the input voltage monitoring circuit 12, the output prohibition state is maintained. Therefore, at this time t0, the changeover switch 7 is not connected to the reference voltage circuit 5 side.

  Thereafter, at time t1, when the input voltage VIN rises (FIG. 2B) and exceeds the detection voltage VINth, the input voltage monitoring circuit 12 inputs a detection signal of the input voltage VIN to the output prohibition circuit 13. As a result, the output prohibition circuit 13 stops the output prohibition signal S and cancels the output prohibition state (FIG. 2C), switches the changeover switch 7 to the reference voltage circuit 5 side, and turns off the switch 10. Switch.

  In the voltage control circuit 6, when the resistor 8a is connected to the reference voltage circuit 5 side and the short circuit state of the capacitor 8b is released, charging of the capacitor 8b is started by the reference voltage Vref via the resistor 8a of the charging circuit 9. The terminal voltage of the capacitor 8b, that is, the input voltage Vrefa to the control amplifier 4 gradually increases. At time t1, since the output transistor 2 is in the off state, the output voltage VOUT (FIG. 2 (e)) and the monitor voltage Vfb are zero.

  In the control amplifier 4, since the terminal voltage of the capacitor 8b is input to the non-inverting input terminal as the input voltage Vrefa, the voltage gradually increases from the time t1 with a time constant determined by the resistor 8a and the capacitor 8b. As a result, when the input voltage Vrefa rises, the control amplifier 4 outputs a gate drive signal to the output transistor 2 so that the difference voltage with respect to the monitor voltage Vfb increases. As a result, the drain current of the output transistor 2 gradually increases. Along with this, the monitor voltage Vfb also gradually increases.

  As a result, even when the input voltage VIN rises at time t1 with a delay from the time t0 when the voltage of the DC power supply VD rises, the output voltage VOUT is increased as the reference voltage Vref increases as shown in FIG. Gradually rising, and overshooting can be suppressed.

  Next, an operation when the input voltage VIN temporarily decreases while the voltage of the DC power supply VD is equal to or higher than the detection voltage VDth will be described. For example, it is assumed that the input voltage VIN suddenly decreases at time t2. In this case, when the input voltage monitoring circuit 12 detects that the input voltage VIN is lower than the detection voltage VINth, the detection signal is output to the output prohibition circuit 13. In response to this, the output prohibiting circuit 13 outputs an output prohibiting signal S so as to switch to the output prohibiting state and controls the selector switch 7 and the switch 10.

  The change-over switch 7 releases the connection state with the reference voltage circuit 5 according to the output of the output inhibition signal S, and further switches the series circuit of the resistor 8a and the capacitor 8b to a short-circuit state. As a result, the charge charged in the capacitor 8b is gradually discharged through the resistor 8a, and the input voltage Vrefa to the non-inverting input terminal of the control amplifier 4 decreases as shown in FIG. To go.

  The switch 10 switches the output transistor 2 to an off state in response to the output of the output prohibition signal S. As a result, the output transistor 2 is quickly turned off. Note that the output voltage VOUT of the output terminal OUT decreases at a constant rate as shown in FIG. 2E, for example, depending on the characteristics of the load connected to the output terminal OUT. Note that when the decrease period of the input voltage VIN is short, the output voltage VOUT has not reached zero, and when the decrease period is long, the output voltage VOUT has reached zero.

  Thereafter, when the reduced state of the input voltage VIN ends in a short period and rises to a predetermined level again at time t3, this is detected by the input voltage monitoring circuit 12. In response to this, the output prohibition circuit 13 cancels the output of the output prohibition signal S. As a result, the changeover switch 7 is switched, and the voltage control circuit 6 enters a state in which the reference voltage Vref is input from the reference voltage circuit 5.

  In the voltage control circuit 6, charging of the capacitor 8b is started via the resistor 8a of the charging circuit 9, and the terminal voltage of the capacitor 8b rises as shown in FIG. The input voltage Vrefa gradually increases. At this time, when the input voltage Vrefa is low, the output voltage VOUT may still be high and the monitor voltage Vfb may be higher, for example, at time t3 in FIG. The transistor 2 is not driven.

  Thereafter, at a time slightly later than time t3, the input voltage Vrefa further increases and becomes higher than the monitor voltage Vfb, and the control amplifier 4 causes the output transistor 2 to follow the input voltage Vrefa. A drive signal is output to the gate. When the input voltage Vrefa reaches a predetermined voltage, the monitor voltage Vfb also has the same level, whereby the output voltage VOUT reaches a predetermined level.

  Next, the operation when the voltage of the DC power supply VD temporarily decreases will be described. The voltage of the DC power supply VD starts to decrease at time t4. At time t5, the power supply voltage monitoring circuit 11 detects that the power supply voltage is lower than the threshold voltage VDth (FIG. 2 (a)), and the output prohibition circuit 13 detects this. Output a signal. In response to this, the output prohibition circuit 13 outputs the output prohibition signal S (FIG. 2C).

  The threshold voltage VDth for detecting the voltage drop of the DC power supply VD in the power supply voltage monitoring circuit 11 is a voltage level higher than the lowest voltage Va at which the control amplifier 4 can operate (VDth> Va). This is because the output transistor 2 is turned off before the control amplifier 4 becomes inoperable and an unstable drive signal is output from the output terminal. Further, in the reference voltage circuit 5, the minimum voltage Vb necessary for generating the reference voltage Vref is lower than the minimum operating voltage Va of the control amplifier 4 (Vb <Va), so that the voltage of the DC power supply VD is Vb. If it is above, voltage control circuit 6 is in the state where reference voltage Vref was given.

  When the power supply voltage monitoring circuit 11 detects a voltage drop of the DC power supply VD at time t5, the output prohibiting signal S is output from the output prohibiting circuit 13. Thereby, the changeover switch 7 of the voltage control circuit 6 switches the charging circuit 9 to the short circuit state, and the switch 10 switches the output transistor 2 to the off state. Since the capacitor 8b of the charging circuit 9 is discharged through the resistor 8a and the terminal voltage decreases, the input voltage Vrefa to the control amplifier 4 also decreases. At this time, the output voltage VOUT of the output terminal OUT decreases at a constant speed as described above.

  As a result, even when the voltage of the DC power supply VD further decreases and becomes lower than the minimum operating voltage Va of the control amplifier 4, the output transistor 2 is held in the off state without being affected by the operating state of the control amplifier 4. Can do.

  Thereafter, when the voltage of the DC power supply VD is restored and the voltage drop detection state is canceled by the power supply voltage monitoring circuit 11 at time t6, the output prohibition circuit 13 cancels the output of the output prohibition signal S. As a result, the output of the reference voltage circuit 5 is switched to be supplied to the voltage control circuit 6 by the changeover switch 7. At this time, the switch 10 is simultaneously turned off, so that the forced off state of the output transistor 2 is released.

  In this case as well, the terminal voltage of the capacitor 8b is gradually increased by the charging from the reference voltage circuit 5 by the charging circuit 9, and accordingly, the input voltage Vrefa to the control amplifier 4 is gradually increased. Therefore, the output transistor 2 is driven and controlled so that the output voltage VOUT also gradually increases. Thereafter, at time t7 when the voltage of the DC power supply VD reaches a predetermined level, the output voltage VOUT also reaches a substantially constant level.

  In such a first embodiment, the changeover switch 7 that is switched by the output prohibition signal S is provided, and the charge of the capacitor 8b of the charging circuit 9 is discharged. Further, an input voltage monitoring circuit 12 for detecting a decrease in the input voltage VIN is provided, and the output prohibition signal S is output by the output prohibition circuit 13 when the input voltage decreases.

  Thereby, even after the voltage of the DC power supply VD rises, when the input voltage VIN of the input terminal IN decreases or when the voltage of the DC power supply VD decreases, the charge of the capacitor 8b is discharged and the input voltage to the control amplifier 4 is discharged. The operation after power restoration can be started after Vrefa is lowered, and overshooting of the output voltage VOUT at the time of power restoration can be suppressed.

  Also in this case, since the switch 10 is provided, the output transistor 2 can be quickly switched to the OFF state after the output inhibition signal S is output in the event of an abnormality.

  Further, even when the minimum operating voltage Va of the control amplifier 4 and the minimum operating voltage Vb of the reference voltage circuit 5 are different, the occurrence of overshoot due to this difference is suppressed when returning from the voltage drop of the DC power supply VD. be able to.

(Second Embodiment)
FIG. 3 and FIG. 4 show the second embodiment, and the following description will be focused on differences from the first embodiment. This embodiment is effective when the control amplifier 4 is provided with a PNP-type bipolar transistor at the input stage. In addition to the configuration of the first embodiment, the power supply circuit 14 includes an output monitor circuit 15 that monitors the output voltage VOUT and a filter 16, and a short-circuit switch 17 that short-circuits between the terminals of the resistor 8a as the voltage control circuit 6a. It is configured.

  The output monitor circuit 15 outputs a high level detection signal until the output voltage VOUT reaches a predetermined level, and outputs a low level detection signal when the output voltage VOUT exceeds a predetermined threshold voltage VOUTth. The filter 16 has a delay function, and changes the output from the high level to the low level when a certain delay time ΔT has elapsed from the time when the detection signal of the output monitor circuit 15 changes from the high level to the low level. The short-circuit switch 17 of the voltage control circuit 6a maintains an off state when a high level detection signal is given from the output monitor circuit 15 via the filter 16, and turns on when a low level detection signal is given. Switch.

  Next, the operation of the above configuration will be described with reference to FIG. In this embodiment, the voltage of the DC power supply VD and the input voltage VIN both rise at time t1 in the first embodiment, and after a certain time from the time when the output inhibition signal S from the output inhibition circuit 13 is released (from time t2). The operation up to the previous time) will be described.

  As shown in FIG. 4A, the voltage of the DC power supply VD and the input voltage VIN rise at time t1, and a signal indicating that the power supply voltage monitoring circuit 11 and the input voltage monitoring circuit 12 have reached a predetermined level is output. Then, the output prohibition circuit 13 cancels the output prohibition signal S as shown in FIG. As a result, a voltage is applied from the reference voltage circuit 5 to the charging circuit 9 of the voltage control circuit 6a in the same manner as described above. As the capacitor 8b is charged, the input voltage Vrefa to the control amplifier 4 gradually increases (FIG. 4C). The control amplifier 4 gives a gate drive signal to the gate of the output transistor 2, and the output voltage VOUT at the output terminal OUT gradually increases (FIG. 4 (d)).

  At this time, the output monitor circuit 15 outputs a high-level detection signal while the output voltage VOUT does not reach the predetermined threshold voltage VOUTth. As a result, the short-circuit switch 17 of the voltage control circuit 6a is kept off. When the output voltage VOUT gradually rises and reaches the threshold voltage VOUTth at time t1a, the output monitor circuit 15 switches to a low level detection signal and outputs it. Since this low level detection signal is provided to the short-circuit switch 17 via the filter 16, a low-level signal is applied to the short-circuit switch 17 at a time point t1b after the delay time ΔT has elapsed from the time point t1a. , Switches to the on state.

  Since the resistor 8a of the charging circuit 9 is short-circuited by this, the reference voltage Vref of the reference voltage circuit 5 becomes the input voltage Vrefa to the control amplifier 4 as it is. As described above, in the configuration in which the input terminal of the control amplifier 4 is provided as the base of a PNP type bipolar transistor, the input voltage Vrefa is higher by the voltage drop ΔVref of the resistor 8a when the base current flows to the charging circuit 9 side. In this state, Vrefa (= Vref + ΔVref) is input. On the other hand, when the short-circuit switch 17 is turned on, the reference voltage input to the control amplifier 4 becomes equal to the reference voltage Vref excluding the voltage drop ΔVref caused by the resistor 8a.

  As a result, the input voltage Vrefa of the control amplifier 4 is input as a voltage equal to the reference voltage Vref of the reference voltage circuit 5, and the output voltage VOUT is accurately output based on the reference voltage Vref of the reference voltage circuit 5. be able to.

The configuration of the control amplifier 4 described above is as follows.
When a PNP type bipolar transistor is provided at the input stage of the control amplifier 4, the base current flows from the control amplifier 4 side to the charging circuit 9 side via the non-inverting input terminal. As a result, the input voltage Vrefa to the non-inverting input terminal is increased by the base current (ΔVref) flowing through the resistor 8a with respect to the reference voltage Vref of the reference voltage circuit 5. As described above, if the reference voltage Vrefa to the control amplifier 4 is different from the output voltage Vref of the reference voltage circuit 5, the operation as designed may not be possible. In this embodiment, such a problem is solved.

  As described above, the variation ΔVref of the input voltage Vrefa caused by the resistor 8a of the charging circuit 9 is relatively low even if the base current from the control amplifier 4 is about several tens of nanoamperes. If it is larger, the variation ΔVref of the reference voltage Vrefa increases, and the output voltage VOUT also varies greatly. In order to suppress this, it is conceivable to set the resistance value of the resistor 8a small. In this case, it is necessary to increase the capacitance of the capacitor 8b so as not to change the time constant of the charging circuit 9. There is. However, increasing the capacitance of the capacitor 8b increases the area and is difficult to adopt in design.

  In the second embodiment, the output monitor circuit 15, the filter 16, and the short-circuit switch 17 are provided. As a result, even if the control amplifier 4 has a configuration in which a PNP type bipolar transistor is provided in the input stage, the fluctuation of the output voltage VOUT due to the fluctuation ΔVref of the input voltage Vrefa due to the resistor 8a of the charging circuit 9 is eliminated, and the reference voltage The output voltage VOUT corresponding to the reference voltage Vref of the circuit 5 can be output with high accuracy.

  In the above embodiment, the filter 16 is provided so that the detection signal of the output monitor circuit 15 can be applied to the switching of the short-circuit switch 17 in a stable state, but the filter 16 is omitted. You can also In this case, it is preferable to add a hysteresis function so as to prevent the output of the output monitor circuit 15 from chattering.

(Third embodiment)
FIG. 5 shows a third embodiment. The difference from the first embodiment is that an output prohibiting circuit 13a constituting the power supply circuit 18 is used. The output prohibition circuit 13a is configured to accept the signals P1, P2 and the like assuming that the output voltage VOUT is prohibited from being output from an external ECU (electronic control unit) or the like.

  Examples of such signals P1 and P2 include abnormality detection signals such as an overcurrent detection signal and an overheat detection signal. In addition to this, the output inhibition signal S can be output in response to various abnormality detection signals and other signals.

  Thus, even when an abnormality detection signal such as the signal P1 or P2 is input, the output prohibition circuit 13a outputs the output detection signal S to stop the operation of the output transistor 2, and the abnormality detection signal P1 or When P2 is released, the output voltage VOUT can be output while gradually increasing the reference voltage Vref in the same manner as in the first embodiment. it can.

(Fourth embodiment)
FIG. 6 and FIG. 7 show the fourth embodiment. Hereinafter, parts different from the first embodiment will be described. In this embodiment, when the power supply circuit 19 is provided and the changeover switch 7 is switched to short-circuit the charging circuit 9, the charge of the capacitor 8b is not completely discharged but discharged to the state where the set voltage Vc remains. Thus, the charge / discharge time is shortened.

  In this case, if the set voltage Vc is increased, the terminal voltage of the capacitor 8b remains high, and the output voltage VOUT tends to overshoot when the power is restored. Here, by appropriately selecting the set voltage Vc, the output voltage VOUT can be recovered in a short time while suppressing the occurrence of overshoot.

  The power supply circuit 19 is provided with a setting power supply 20 as the voltage control circuit 6b. The set power source 20 has a set voltage Vc based on a DC voltage, and is provided in a discharge path formed when the charging circuit 9 is short-circuited. When the set charge Vc is discharged, the set power source 20 is discharged. Provided to stop.

  Next, the operation of the above configuration will be described with reference to FIG. In this embodiment, in the first embodiment, the voltage of the DC power supply VD and the input voltage VIN rise after the times t0 and t1, and the output voltage VOUT is predetermined after the output inhibition signal S from the output inhibition circuit 13 is released. The same is true until the level is reached. Thereafter, the operation when the input voltage VIN decreases at time t2 is different.

  That is, when the input voltage VIN decreases at time t2 (FIG. 7B) and the input voltage monitoring circuit 12 detects this, the output inhibition circuit 13 outputs the output inhibition signal S (FIG. 7C). ) The changeover switch 7 and the switch 10 are controlled. Thereby, in the voltage control circuit 6b, the electric charge of the capacitor 8b of the charging circuit 9 is discharged through the resistor 8a. At this time, the charge discharge of the capacitor 8b is stopped when it becomes equal to the set voltage Vc of the set power source 20, and the input voltage Vrefc to the control amplifier 4 becomes equal to the set voltage Vc (FIG. 7 (d)). The output voltage VOUT decreases in the same manner as described above (FIG. 7 (e)).

  Thereafter, when the state where the input voltage VIN is reduced ends in a short period and rises to a predetermined level again at time t3 (FIG. 7B), this is detected by the input voltage monitoring circuit 12, and the output prohibition circuit 13 outputs. The prohibition signal output is canceled (FIG. 7C). Thereby, the changeover switch 7 is switched, and the reference voltage Vref is applied again from the reference voltage circuit 5 to the voltage control circuit 6b.

  At this time, in the voltage control circuit 6b, charging of the capacitor 8b is started via the resistor 8a of the charging circuit 9, but since the voltage of the set voltage Vc remains before time t3, the output voltage Although the output voltage VOUT is slightly reduced, the reference voltage Vref is higher than that, so that the control amplifier 4 outputs a drive signal so as to increase the output voltage VOUT to the gate of the output transistor 2.

  As a result, when the switch 10 is switched to the OFF state, the input voltage Vrefa corresponding to the set voltage Vc is input to the gate of the output transistor 2, and immediately thereafter reaches the level equivalent to the reference voltage Vref. At this time, the output voltage VOUT may have a small overshoot (FIG. 7 (e)). However, when the difference from the output voltage VOUT is small, this overshoot has no adverse effect, so the output voltage VOUT can be secured quickly.

In the fourth embodiment, the setting power source 20 is provided in the configuration of the voltage control circuit 6b, and when the charging circuit 9 is short-circuited, the discharge amount of the capacitor 8b is limited and the terminal voltage remains only at the setting voltage Vc. It comprised so that it might become. Thereby, it is possible to quickly start up while suppressing the overshoot of the output voltage VOUT when the power is restored.
Note that the setting voltage Vc of the setting power source 20 can be set to an appropriate voltage according to the characteristics of the load connected to the output terminal OUT.

(Fifth embodiment)
FIG. 8 and FIG. 9 show the fifth embodiment, and the parts different from the first embodiment will be described below. In this embodiment, the power supply circuit 21 has a configuration in which a buffer circuit 22 that outputs a constant current is provided as a voltage control circuit 6c in place of the resistor 8a of the charging circuit 9. In this configuration, the capacitor 8b is charged with a time constant determined by the resistor 8a and the capacitor 8b, whereas the capacitor 8b is charged by a constant current of the buffer circuit 22.

  In the state where the output prohibition signal S is released, the changeover switch 7 is connected to the buffer circuit 22 side, the constant current from the buffer circuit 22 is charged in the capacitor 8b, and when the reference voltage Vref is reached, the constant current stops. The input voltage Vrefa equal to the reference voltage Vref is input to the non-inverting input terminal of the control amplifier 4. In the state where the output prohibition signal S is output, the changeover switch 7 disconnects the buffer circuit 22 and shorts the capacitor 8b, and the charge on the capacitor 8b is instantaneously discharged.

  Next, the operation of the above configuration will be described with reference to FIG. In this embodiment, the operation of each part is almost the same as that of the first embodiment, but the terminal voltage changes when the capacitor 8b is charged by the buffer circuit 22 is different. That is, in the first embodiment, the charging circuit 9 is charged according to the time constant determined by the resistor 8a and the capacitor 8b, whereas in this embodiment, the capacitor 8b is a constant current output from the buffer circuit 22. As a result of charging, the terminal voltage rises linearly.

  As a result, in this embodiment, as shown in FIG. 9D, the input voltage Vrefa to the non-inverting input terminal of the control amplifier 4 starts to rise linearly from, for example, time t1, and the reference voltage circuit 5 When the output reference voltage Vref is reached, the current of the buffer circuit 22 stops. At this time, the control amplifier 4 outputs a drive signal to the gate of the output transistor 2 along the input voltage Vrefa, and the output voltage VOUT also rises linearly as shown in FIG.

When a decrease in the input voltage VIN is detected at time t2 or when a decrease in the power supply voltage is detected at time t5, both terminals of the capacitor 8b are short-circuited by the switching operation of the changeover switch 7, and the capacitor 8b is charged. The electric charge is instantaneously discharged, and the terminal voltage becomes zero (FIG. 9 (d)).
Also according to the fifth embodiment, it is possible to obtain substantially the same operational effects as the first embodiment.

(Sixth embodiment)
FIG. 10 shows the sixth embodiment. The difference from the first embodiment is that the switch 10 is omitted. According to this configuration, the changeover switch 7 of the voltage control circuit 6 is switched by the output of the output prohibition signal S from the output prohibition circuit 13, but the output transistor 2 cannot be operated directly in the off state. Absent.

However, since the voltage control circuit 6 reduces the input voltage Vrefa to the non-inverting input terminal of the control amplifier 4 due to the discharge of the capacitor 8b, the output transistor 2 shifts to the OFF state as the terminal voltage of the capacitor 8b decreases. Therefore, substantially the same operation can be performed.
Therefore, the sixth embodiment can obtain the same effect as that of the first embodiment.

(Other embodiments)
In addition, this invention is not limited only to embodiment mentioned above, In the range which does not deviate from the summary, it is applicable to various embodiment, For example, it can deform | transform or expand as follows.

  In the first to fifth embodiments, the switch 10 is provided to shift the output transistor 2 to the OFF state by the output prohibition circuit 13 when the output prohibition signal S is output. The output of the control amplifier 4 may be stopped, or the power supply to the control amplifier 4 may be stopped.

  In the sixth embodiment, the case where the present invention is applied to the first embodiment is shown. However, the present invention is not limited to this, and the present invention can also be applied to the second, third, and fifth embodiments.

  In the drawing, 1, 14, 19, 21, and 23 are power supply circuits, 2 is an output transistor, 3 is a voltage dividing circuit, 4 is a control amplifier, 5 is a reference voltage circuit, 6, 6a, 6b, and 6c are voltage control circuits, 7 is a changeover switch, 8a is a resistor, 8b is a capacitor, 9 is a charging circuit, 10 is a switch, 11 is a power supply voltage monitoring circuit, 12 is an input voltage monitoring circuit, 13 and 13a are output inhibition circuits, 15 is an output monitoring circuit, Reference numeral 16 is a filter, 17 is a short-circuit switch, 20 is a set power source, and 22 is a buffer circuit.

Claims (7)

An output transistor (2) provided between the input terminal and the output terminal;
A reference voltage circuit (5) for generating a reference voltage from a power supply having a power supply voltage different from the input voltage of the input terminal ;
A control amplifier (4) for controlling the output transistor according to a difference between a reference voltage set by the reference voltage circuit and an output voltage generated at the output terminal, and outputting a predetermined voltage to the output terminal;
An output prohibition circuit (13, 13a) for canceling the output prohibition signal in a state where both the power supply voltage and the input voltage reach the respective detection voltages;
When the output prohibition signal is canceled, the reference voltage circuit generates the reference voltage circuit for the control amplifier when the output transistor is operated by the control amplifier in a state where an input voltage is applied to the input terminal. A power supply circuit comprising a voltage control circuit (6, 6a, 6b, 6c) for starting a reference voltage from a lower voltage and increasing the reference voltage to the reference voltage. The power supply circuit according to claim 1,
The voltage control circuit (6, 6a, 6b) has a charging circuit (9) composed of a resistor (8a) and a capacitor (8b), and charges the capacitor from the reference voltage circuit to increase the terminal voltage. A power supply circuit configured to output the terminal voltage to the control amplifier, and configured to discharge the charge of the capacitor when the output inhibition signal is input. The power supply circuit according to claim 2,
The voltage control circuit (6b) is configured to discharge the charge of the capacitor (8b) to a predetermined level that becomes a predetermined terminal voltage when the output inhibition signal is input. circuit. The power supply circuit according to claim 2 or 3,
A shorting switch (17) for short-circuiting the resistor (8a) of the voltage control circuit (6a);
A power supply circuit comprising: an output monitor circuit (15) for monitoring an output voltage of the output terminal and turning on the short-circuit switch when the monitor voltage becomes equal to or higher than a predetermined voltage. The power supply circuit according to claim 1,
The voltage control circuit (6c) includes a buffer circuit (22) and a capacitor (8b) charged by the buffer circuit, and is configured to discharge the charge of the capacitor when the output inhibition signal is input. Power supply circuit characterized by being made. In the power supply circuit according to any one of claims 1 to 5,
An input voltage monitoring circuit (12) for monitoring an input voltage applied to the input terminal;
The output inhibit circuit detects a drop in the input voltage by the input voltage monitoring circuit, the power supply circuit, wherein the benzalkonium be output to the output inhibit signal. The power supply circuit according to claim 6,
The output prohibiting circuit (13a) outputs the output prohibiting signal according to a control signal given from the outside.

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