JP2014176242A - Power unit, power supply control method and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power unit capable of fast recovering a normal power supply state in the case where a failure occurs in any one of a plurality of power sources.SOLUTION: In the power unit comprising an ORing circuit 21 at an output side of each of a plurality of power sources connected in parallel, each ORing circuit 21 includes first, second and third transistors Q1, Q2 and Q3 formed from a plurality of switch elements such as MOSFETs connected in parallel, and second and third Zener diodes ZD2 and ZD3 and second and third resistors Rz2 and Rz3 are connected to gate terminals of the second and third transistors Q2 and Q3. When resuming power supply to a side of a load 30 after a failure occurs in any power source and all the plurality of switch elements of the respective power sources are switched to OFF state, the first transistor Q1 is first recovered to ON state and the second and third transistors Q2 and Q3 are then recovered to the ON state step by step while being delayed for a predetermined time from the first transistor Q1.

Description

  The present invention relates to a power supply device, a power supply control method, and an electronic device, and in particular, a power supply device that can quickly return to a normal voltage supply state when any of a plurality of power supplies fails, a power supply control method, and The present invention relates to an electronic device.

  In the case of an electronic device consisting of multiple power supplies operating in parallel, if one of the power supplies fails, the other power supply that is operating normally can be protected and the electronic device can continue to operate For example, as described in Japanese Patent Application Laid-Open No. 2011-200016 “Power supply device” in Japanese Patent Application Laid-Open No. 2011-200016, for example, an ORing circuit (oring circuit: backflow prevention) Circuit) is incorporated into the power supply. As a switch element in a recent ORing circuit, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with less power loss than a diode is used. The driving of the MOSFET is controlled according to the state.

JP2011-200016 (page 2-3)

  However, when a MOSFET is used as a switching element in the ORing circuit of the power supply device, the number of MOSFETs connected in parallel increases with an increase in current of the power supply, and a longer time is required for driving each MOSFET. When an abnormality occurs in the power supply, not only does it take a long time to return to normal power supply operation after disconnecting from the abnormal power supply by the ORing circuit, but a voltage state lower than the normal voltage value continues. In the end, there are cases where continuous operation as an electronic device is impaired.

  That is, in the related art, when a plurality of power supplies that operate in parallel are provided in the electronic device, the power supply device for controlling the plurality of power supplies that operate in parallel includes isolation of the failed power supply and other power supplies. For the purpose of protection, as described above, an ORing circuit (an ORING circuit, a backflow prevention circuit) for disconnecting the output terminal of the failed power supply from other power supplies is provided. In addition, as a switch element constituting the switch part in the ORing circuit, a MOSFET with less power loss than a diode is usually used, and depending on each state such as when the power supply is started, at a steady state, or when a failure occurs Driven.

  When an abnormal state in which an overvoltage is output from any of the power supplies connected in parallel occurs, the power supply apparatus detects the output voltage of the abnormal state and disconnects the output terminal of the power supply. In addition to controlling the switch part of the other power supply to the OFF state (non-conducting state), in order to prevent backflow from the faulty power supply for other power supplies, the switch part of the ORing circuit of each other power supply is temporarily turned off. Control to the state (non-conducting state).

  After that, when it is detected that the faulty power supply is isolated, the abnormal state is resolved, and no abnormal voltage is generated at the output terminals connected in parallel, the normal power supply resumes the power supply operation. Therefore, control is performed so that the switch unit of the ORing circuit of each normal power supply is returned to the ON state (conducting state) from the temporarily stopped state. Here, when the switch unit of the ORing circuit is re-driven to the ON state (conducting state), the return time to the normal state depends on the driving ability for the switch unit.

  On the other hand, the switch section of the ORing circuit is often configured by connecting a plurality of switch elements in parallel instead of a single switch element according to the current capacity required on the load side in a steady state. As described above, when the switch unit of the ORing circuit is composed of a plurality of switch elements connected in parallel, in the prior art, in order to drive all of the plurality of switch elements at the same time, each switch element is in an ON state (conductive It takes a long time to return to the normal state, and the output voltage fluctuates before the normal state is restored, causing the load side operation to become unstable. There was a possibility.

(Object of the present invention)
The present invention has been made in view of such circumstances, and a power supply apparatus and power supply control capable of quickly returning to a normal power supply state when a failure occurs in any one of a plurality of power supplies It is an object to provide a method and an electronic device.

  In order to solve the above-described problems, the power supply device, the power supply control method, and the electronic device according to the present invention mainly adopt the following characteristic configuration.

  (1) A power supply apparatus according to the present invention includes a switch unit on the output side of each of a plurality of power supplies connected in parallel, and supplies power from each of the power supplies to a load in parallel via each switch unit. Each of the switch units is composed of a plurality of switch elements connected in parallel, and when a failure occurs in which an abnormal voltage is output to any one of the plurality of power sources, all of the switch units included in each power source are provided. Each of the power supplies other than the failed power supply, when resuming the power supply to the load side by each power supply other than the failed power supply among the plurality of power supplies, after setting the switch element in the non-conductive state, The switching timing for switching each of the plurality of switch elements constituting the switch unit to a conductive state is shifted in a predetermined time stepwise, And wherein the to return to the conductive state from a conductive state.

  (2) The power supply control method according to the present invention includes a switch unit on the output side of each of a plurality of power supplies connected in parallel, and supplies power from each of the power supplies to the load in parallel via each switch unit Each of the switch units is composed of a plurality of switch elements connected in parallel, and each power source is provided with a power supply when a failure occurs in which an abnormal voltage is output to any one of the plurality of power sources. After switching all the switch elements in the switch section to the non-conductive state, when restarting the power supply to the load side by each power source other than the failed power source among the plurality of power sources, other than the failed power source For each of the power supplies, the switching timing for switching each of the plurality of switch elements constituting the switch unit to the conductive state is shown stepwise. Staggered time determined order, characterized in that to return from the nonconductive state to the conductive state.

  (3) An electronic device according to the present invention includes a power supply circuit that supplies power to a load by connecting a plurality of power supplies in parallel, and the power supply circuit uses at least the power supply device described in (1). It is configured.

  According to the power supply device, the power supply control method, and the electronic device of the present invention, the following effects can be obtained.

  In other words, in a power supply device composed of a plurality of power supplies operating in parallel, each power supply has a plurality of switch elements connected in parallel in a switch unit arranged for backflow prevention and protection, and one of the power supplies fails When this occurs, by setting all of the switch elements to the OFF state (non-conducting state), the faulty power supply is isolated and disconnected, and then normal power supplies other than the faulty power supply are returned to the normal state. By adopting a circuit configuration that can drive a plurality of switch elements in the switch unit in a time-shifted manner in a stepwise manner, one of the switch elements instructed to return first is replaced with another switch element. It is possible to return to the ON state (conducting state) at a high speed with priority over the voltage fluctuation value and time until the output voltage is normalized. It is possible. Therefore, it is possible to reduce the number of installed large-capacity capacitors for suppressing voltage fluctuations, and to realize downsizing, integration, and cost reduction of the power supply device.

It is a block block diagram which shows an example of the block configuration of the power supply device of this invention. FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of an ORing circuit in the power supply device illustrated in FIG. 1. FIG. 3 is a waveform diagram showing voltage waveforms of main parts for explaining an example of the operation of the power supply device including the ORing circuit shown in FIG. 2.

  Preferred embodiments of a power supply device, a power supply control method, and an electronic device according to the present invention will be described below with reference to the accompanying drawings. In the following description, a power supply device and a power supply control method according to the present invention will be described. However, such a power supply device may be built in or externally attached to the electronic device as a power supply device in an electronic device that requires a plurality of power supplies. Needless to say, you can do it.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be described first. The present invention provides an ORing circuit (oring circuit, backflow prevention circuit) installed on the output side for each power supply for isolation and backflow prevention in a power supply device that supplies power from a plurality of power supplies connected in parallel to the load side When a plurality of switch elements are connected in parallel as a switch part of each switch, each switch element is switched from an OFF state (non-conduction state) to an ON state (conduction state) in order to return a normal power supply other than the failed power supply to a normal state. When switching to the state), it is important not to operate all the switch elements at the same time, but to operate in a stepwise manner so that one of the switch elements operates before the other switch element. It is a feature.

  Thus, when the power supply from the normal power supply is resumed, the drive circuit for driving each switch element first supplies the drive current only to the specific switch element operating in advance. It becomes possible to return the specific switch element from the OFF state (non-conduction state) to the ON state (conduction state) at high speed, and to restore the normal power supply once disconnected at the time of power failure to the steady state at high speed. Therefore, fluctuations in the output voltage supplied to the load can be suppressed.

(Embodiment of the present invention)
Next, a configuration example of an embodiment of the power supply device of the present invention will be described first with reference to the block configuration diagram of FIG. FIG. 1 is a block configuration diagram showing an example of a block configuration of a power supply device according to the present invention. As an example of a power supply device composed of a plurality of power supplies, three power supplies of a first power supply, a second power supply, and a third power supply are arranged in parallel. The case where it is connected is shown as an example.

  The power supply device shown in FIG. 1 has a backflow prevention for isolating a faulty power supply and protecting a normal power supply on the output side of each of the DC / DC converter units 11, 12, and 13 constituting the three power supplies operating in parallel. ORing circuits 21, 22 and 23 are connected. The output terminals of the three ORing circuits 21, 22, and 23 are connected in parallel and connected to the load 30. That is, three DC / DC converter units 11, 12, and 13 are connected in parallel to the load 30 via the three ORing circuits 21, 22, and 23, respectively.

  Next, an example of the circuit configuration of the ORing circuit in the power supply device shown in FIG. 1 will be described with reference to the circuit diagram of FIG. FIG. 2 is a circuit diagram showing an example of the circuit configuration of the ORing circuit 21 in the power supply device shown in FIG. 1, but the other ORing circuits 22 and 23 in FIG. 1 also have the same circuit configuration as FIG. It has become.

  In general, the switch units in the ORing circuits 21, 22 and 23 in FIG. 1 have a configuration in which a plurality of switch elements are connected in parallel according to the current capacity required on the load 30 side. In the switch section of the ORing circuit 21 shown, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used as a switch element, and three transistors (first transistor Q1, second transistor Q2, and third transistor Q3) ( In this case, the MOSFET is connected in parallel.

  The source terminals S1, S2, and S3 of the first, second, and third transistors Q1, Q2, and Q3 are connected to the output side of the DC / DC converter unit 11 that constitutes a power source, and the first, second, The drain terminals D1, D2, and D3 of the third transistors Q1, Q2, and Q3 are connected to each other and to the load 30.

  The first, second, and third body diodes are provided between the source terminals S1, S2, and S3 of the first, second, and third transistors Q1, Q2, and Q3 and the drain terminals D1, D2, and D3, respectively. Parasitic diodes, that is, built-in diodes are formed as Dq1, Dq2, and Dq3, and the anode sides of the first, second, and third body diodes Dq1, Dq2, and Dq3 are formed at the source terminals S1, S2, and S3, In addition, the drain terminals D1, D2, and D3 are formed with the respective canode sides of the first, second, and third body diodes Dq1, Dq2, and Dq3.

  In addition, the switching timing for switching the switching elements of the first, second, and third transistors Q1, Q2, and Q3 from the OFF state (non-conducting state) to the ON state (conducting state) depends on the capability of the drive IC 211. In order to make it possible to return from the OFF state (non-conducting state) to the ON state (conducting state) with a predetermined time shift, each of the first, second, and third transistors Q1, Q2, Q3 The connection states of the control terminals, that is, the gate terminals G1, G2, and G3 are set to different states.

  That is, the gate terminal G1 of the first transistor Q1 is directly connected to a drive IC (Integrated Circuit) 211 that is a drive current supply source in order to return the first transistor Q1 to the ON state (conductive state) at the earliest timing. ing. On the other hand, the gate terminals G2 and G3 of the second and third transistors Q2 and Q3 are turned on when the second and third transistors Q2 and Q3 are delayed by a predetermined time from the first transistor Q1, respectively. In order to return to the state (conductive state), the drive IC 211 is connected to the drive current supply source 211 via the second and third Zener diodes ZD2 and ZD3. Here, the gate terminals G2 and G3 of the second and third transistors Q2 and Q3 are connected to the anode sides of the second and third Zener diodes ZD2 and ZD3, respectively, and the second and third Zener diodes ZD2 and ZD3, respectively. Is connected to the drive IC 211.

  Between the gate terminals G2 and G3 of the second and third transistors Q2 and Q3 and the source terminals S2 and S3, the zener voltage values of the second and third Zener diodes ZD2 and ZD3, that is, the second The second and third resistors Rz2 and Rz3 are connected to generate the third Zener voltage values Vz2 and Vz3. Therefore, when the drive current is supplied from the drive IC 211, the gate current Ig1 is immediately input to the gate terminal G1 of the first transistor Q1 to which the Zener diode is not connected, and the gate current Ig1 is connected between the gate terminal G1 and the source terminal S1. The drive voltage is immediately applied to

  However, the second and third transistors Q2 and Q3, to which the second and third Zener diodes ZD2 and ZD3 are connected, respectively, exceed the second and third Zener voltage values Vz2 and Vz3 and are second and third. Until the zener diodes ZD2 and ZD3 reach the ON state (conductive state), the gate currents Ig2 and Ig3 do not flow into the gate terminals G2 and G3 of the second and third transistors Q2 and Q3, respectively. No driving voltage is applied between G3 and the source terminals S2, S3.

  That is, the second and third Zener voltage values Vz2 and Vz3 return the second and third transistors Q2 and Q3 to the ON state (conductive state) at a timing delayed by a predetermined time from the first transistor Q1, respectively. The voltage value is set so as to give a switching timing for the purpose. In other words, among the first, second, and third transistors Q1, Q2, and Q3 of the plurality of switch elements, the switch element to be delayed in stages, for example, the second and second switch timings for switching to the ON state (conductive state). In each of the three transistors Q2 and Q3, the second and third Zener diodes ZD2 and ZD3 and the Zener voltage generating resistors, that is, the second and third resistors Rz2 and Rz3, are gate terminals G2 which are control terminals of the respective switch elements. , G3, and the voltage value of the Zener voltage, that is, the second and third Zener voltage values Vz2 and Vz3, respectively, taking into account the capability of the drive source that drives the gate terminals G2 and G3 of the control terminal, that is, the drive IC 211, respectively. By setting, switching in each switch element, that is, the second and third transistors Q2 and Q3 Timing is set so as to slow down a predetermined time.

  Here, the switching timing for each of the second and third transistors Q2 and Q3 is a switch element to be switched to a conductive state among a plurality of switch elements such as the first to third transistors Q1 to Q3. More than the time required for the switch element, for example, the first transistor Q1 to switch to the ON state (conducting state) after the gate current Ig1 from the drive IC 211 is input to the gate terminal G1 as a switching instruction for one transistor Q1. After the time elapses, gate currents Ig2 and Ig3 are input from the drive IC 211 to the respective gate terminals G2 and G3 as switching instructions for the switching elements to be switched in the next order, for example, the second and third transistors Q2 and Q3. It is set to be.

  In the present embodiment, the timing for starting driving each of the second and third transistors Q2 and Q3 is set to the same level as the time required for the first transistor Q1 to switch to the ON state (conductive state). Therefore, the voltage values of the second and third Zener voltage values Vz2 and Vz3 are the same as the voltage value between the source terminal S1 and the gate terminal G1 at which the first transistor Q1 can be turned on, that is, the first on-voltage value V1on. Since the first transistor Q1 reaches the ON state (conducting state), the supply operation of the gate currents Ig2 and Ig3 to the gate terminals G2 and G3 of the second and third transistors Q2 and Q3 is started. Shows when to start.

  As for the first, second, and third transistors Q1, Q2, and Q3, the first steady-state current value Id1n that can be normally passed as the drain current Id1 for the first transistor Q1 is the second, third transistor Q2, Q3 is set to be smaller than the second and third steady current values Id2n and Id3n that can normally flow as drain currents Id2 and Id3, respectively, and the first transistor Q1 is set as the gate current Ig1 of the first transistor Q1. The first on-current value I1on that can be turned on (conducted) also turns on (conducts) the second and third transistors Q2 and Q3 as the gate currents Ig2 and Ig3 of the second and third transistors Q2 and Q3, respectively. To be smaller than the second and third on-current values I2on and I3on. It is constant.

  In other words, in the steady state in which all of the first, second, and third transistors Q1, Q2, and Q3 are in the ON state, the voltage between the source terminal S1 and the gate terminal G1 of the first transistor Q1, that is, the first drive voltage Vgs1. The voltage value (first steady voltage value V1n) is also set to a high value as the first on-voltage value V1on that can turn on (conduct) the first transistor Q1. On the other hand, for the second and third transistors Q2 and Q3, the voltages between the source terminals S2, S3-gate terminals G2 and G3 of the second and third transistors Q2 and Q3, that is, the second and third drive voltages Vgs2 and Vgs3, respectively. Respective voltage values (second and third steady voltage values V2n and V3n) can turn on (conduct) the second and third transistors Q2 and Q3, respectively. Second and third on-voltage values V2on and V3on Is set to the same value as.

  Further, the drive IC 211 has a switching element when a reverse current due to an increase in the output voltage of the ORing circuits 22 and 23 downstream of the other power sources connected in parallel, that is, the DC / DC converters 12 and 13 in FIG. The driving of all the first, second, and third transistors Q1, Q2, and Q3 is stopped, and the backflow current is controlled not to flow into the DC / DC converter unit 11. After that, when another power supply that outputs an abnormal voltage value is isolated, or when the other power supply returns to a normal output voltage state and the voltage rise is resolved, The drive IC 211 is controlled so as to resume driving of the first, second, and third transistors Q1, Q2, and Q3 of the switch element. Note that the drive current from the drive IC 211 is supplied in common to the first, second, and third transistors Q1, Q2, and Q3, so that when the drive IC 211 stops outputting the drive current. In addition to stopping the application state of the voltage between the source terminal S1 and the gate terminal G1 of the first transistor Q1 whose gate terminal G1 is directly connected to the drive IC 211, that is, the first drive voltage Vgs1, other second, second The voltage between the source terminals S2, S3-gate terminals G2, G3 of the three transistors Q1, that is, the application state of the second and third drive voltages Vgs2, Vgs3 is also stopped.

(Description of operation of embodiment)
Next, an example of the operation of the power supply device including the ORing circuit including the circuit as shown in the circuit diagram of FIG. 2 will be described with reference to the waveform diagram of FIG. FIG. 3 is a waveform diagram showing a voltage waveform of the main part for explaining an example of the operation of the power supply device including the ORing circuit 21 shown in FIG. 2, together with the voltage waveform of the load voltage Vo applied to the load 30. , As the drive voltage of each switch element in the ORing circuit 21, the voltage between the source terminal and the gate terminal of each of the first, second, and third transistors Q1, Q2, and Q3, that is, the first, second, and third drive voltages Vgs1, Vgs2. , Vgs3 shows voltage waveforms.

  As shown in the waveform diagram of the load voltage Vo in FIG. 3, when the time T0 is reached, for example, the output voltage of another power source connected in parallel, that is, the ORing circuit 22 other than the ORing circuit 21 in FIG. When an abnormality occurs in the output voltage from the ORing circuit 23 and the load voltage Vo rises from the normal voltage value Von in the normal operating state to the overvoltage Vov state, the ORing circuit 21 that has detected the overvoltage Vov. The drive IC 211 immediately stops the output of the first drive voltage Vgs1 common to the gate terminals G1, G2, and G3 of all the first, second, and third transistors Q1, Q2, and Q3 of the switch element, and the first The second and third transistors Q1, Q2, and Q3 are shifted to the OFF state (non-conducting state), and the backflow current does not flow into the DC / DC converter unit 11. The sea urchin control. Similarly, in the other ORing circuits 22 and 23, all the switch elements of the respective switch units are set to the OFF state (non-conductive state). As a result, the failed power supply that has generated the abnormal output voltage is isolated.

  Thereafter, as shown in the waveform diagram of the load voltage Vo in FIG. 3, the abnormality of the output voltage from the other ORing circuit 22 or the ORing circuit 23 is eliminated at the time T1, and the load voltage Vo becomes the overvoltage Vov. When the state drops from the state, the first, second, and third body diodes Dq1, Dq2, and Dq3 parasitic on the first, second, and third transistors Q1, Q2, and Q3 of the switching element in the ORing circuit 21 are changed. The current is supplied to the load 30 through the first and second body diodes Dq1, Dq2, and Dq3, and the voltage drops below the normal voltage value Von by a voltage corresponding to the conduction voltage VF of the first, second, and third body diodes Dq1, Dq2, and Dq3. Resulting in.

  However, at the time T1, at the same time, the drive IC 211 that detects that the voltage has dropped from the state of the overvoltage Vov starts to flow the drive current, and the first, second, and third transistors Q1, Q2, and Q3 of the switch elements respectively. Thus, the ORing circuit 21 starts the return operation. As a result, first, as shown in the waveform diagram of the first drive voltage Vgs1 of FIG. 3, the first drive voltage Vgs1 of the first transistor Q1 to which the drive current from the drive IC 211 is directly input as the gate current Ig1 is the first drive voltage Vgs1. The transistor Q1 increases toward the first ON voltage value V1on that can be turned on (conducted). That is, the first drive voltage Vgs1 of the first transistor Q1 gradually increases from '0' toward the first on-voltage value V1on according to a certain gradient according to the drive capability of the drive IC 211.

  On the other hand, the drive IC 211 outputs the drive current from the drive IC 211 at the second and third transistors Q2 and Q3 where the drive currents are input to the gate terminals G2 and G3 via the second and third Zener diodes ZD2 and ZD3, respectively. The drive current from the drive IC 211 is cut until the first drive voltage Vgs1 reaches the second and third Zener voltage values Vz2 and Vz3 in the second and third Zener diodes ZD2 and ZD3, and the second and third transistors. Gate currents Ig2 and Ig3 are not input to the gate terminals G2 and G3 of Q2 and Q3, respectively, and the second and third drive voltages Vgs2 and Vgs3 are not output to the second and third transistors Q2 and Q3, respectively. , '0' state continues.

  Here, in the present embodiment, the voltage values of the second and third Zener voltage values Vz2 and Vz3 are the voltage values between the source terminal S1 and the gate terminal G1 that can turn on the first transistor Q1, that is, the first on-state. It is set to the same level as the voltage value V1on. Therefore, until the first drive voltage Vgs1 reaches the second and third Zener voltage values Vz2 and Vz3, which are about the same as the first on-voltage value V1on, the drive IC 211 only has to drive the first transistor Q1. Thus, the speed until the first transistor Q1 reaches the first on-voltage value V1on that can be turned on can be improved.

  Thereafter, as shown in the waveform diagram of the first drive voltage Vgs1 in FIG. 3, the first drive voltage Vgs1 for driving the first transistor Q1 has risen, and a predetermined time has passed according to the capability of the drive IC 211. When the first transistor Q1 reaches the first ON voltage value V1on at which the first transistor Q1 can be turned on at the time T2, the first transistor Q1 is switched to the ON state, and therefore, the waveform diagram of the load voltage Vo in FIG. As described above, the load voltage Vo at the load 30 returns from the state where it has dropped by the voltage corresponding to the conduction voltage VF to the normal voltage value Von.

  Further, at time T2, the first and second drive voltages Vgs1 applied to the second and third Zener diodes ZD2 and ZD3 are set to be approximately the same as the first on-voltage value V1on. Since the zener voltage values Vz2 and Vz3 are reached, the drive current from the drive IC 211 is supplied to the second and third transistors Q2 and Q3 as gate currents Ig2 and Ig3 via the second and third zener diodes ZD2 and ZD3, respectively. A transition is made to the state of being input to the respective gate terminals G2, G3 of Q3.

  Therefore, as shown in the waveform diagrams of the second and third drive voltages Vgs2 and Vgs3 in FIG. 3, the second and third drive voltages Vgs2 and Vgs3 are supplied to the drive IC 211 for the second and third transistors Q2 and Q3, respectively. Start climbing according to a certain slope according to ability. As described above, the drive IC 211 is in a state of supplying a drive current to all of the first, second, and third transistors Q1, Q2, and Q3, and is shown in the waveform diagram of the first drive voltage Vgs1 in FIG. As described above, the first drive voltage Vgs1 for the first transistor Q1 changes to a gentler gradient than the gradient until the first ON voltage value V1on is reached according to the supply capability of the drive IC 211, and the first drive voltage Vgs1 in the steady state. While continuing to increase toward the steady voltage value V1n, the operation of supplying the load current Io from the first transistor Q1 to the load 30 is continued.

  Thereafter, as shown in the waveform diagrams of the second and third drive voltages Vgs2 and Vgs3 in FIG. 3, the second and third transistors at time T3 when a predetermined time has passed according to the capability of the drive IC 211. When the second and third drive voltages Vgs2 and Vgs3 for Q2 and Q3 respectively reach the second and third on-voltage values V2on and V3on that can turn on the second and third transistors Q2 and Q3, respectively, The third transistors Q2 and Q3 are switched to the ON state, and the second and third transistors Q2 and Q3 also start supplying the load current Io to the load 30, and together with the first transistor Q1 to the load 30 A transition is made to a normal state in which the load current Io is supplied.

  As described above, with respect to a normal power supply, the switching timing at which each of the second and third transistors Q2 and Q3 switches to the ON state (conductive state) is delayed by a predetermined time from the first transistor Q1. That is, for normal power supplies other than the failed power supply, all switch elements of the first, second, and third transistors Q1, Q2, and Q3 are simultaneously switched from the OFF state (non-conductive state) to the ON state (conductive state). Instead, the switching timing for switching the switch elements of the first, second, and third transistors Q1, Q2, and Q3 to the ON state (conducting state) is controlled to be shifted by a predetermined time.

  After the elapse of time T3, as shown in the waveform diagrams of the first, second, and third drive voltages Vgs1, Vgs2, and Vgs3 in FIG. 3, the first drive voltage Vgs1 for the first transistor Q1 is The first steady voltage value V1n higher than the first on-voltage value V1on is maintained, and the second and third drive voltages Vgs2 and Vgs3 for the second and third transistors Q2 and Q3 are the second and third on-voltage values, respectively. All the transistors (MOSFETs) of the first, second, and third transistors Q1, Q2, and Q3 are maintained at the second and third steady voltage values V2n and V3n having the same voltage values as V2on and V3on. The normal state of supplying the load current Io to 30 is restored.

  In the above description, the switch portion in the ORing circuit 21 for preventing the backflow is changed to the first, second, and third transistors Q1, Q2, and Q3 according to the current capacity required on the load 30 side. The case where a plurality of switch elements are connected in parallel has been described. However, the number of switch elements constituting the switch unit is not limited to three, and the present invention can be applied to two or more than two. Needless to say, you can.

  Further, when the normal state is restored, only the first transistor is selected as the second specific switch element among the three switch elements of the first, second, and third transistors Q1, Q2, and Q3. The second transistors and the third transistors Q2 and Q3 are turned on (conducted) at a timing earlier than that of the third transistors Q2 and Q3. The case has been described in which both are turned on (conducted) at substantially the same timing although they are slow. However, the present invention is not limited to such a case, and it is possible to drive each of the plurality of switch elements in the ORing circuit 21 in stages, and turn on each of the plurality of switch elements at different timings ( Depending on the power supply capability, a specific switch element that is turned on (conducted) earlier than other switch elements may be turned on simultaneously, not just one. May be.

  In the above description, the case where a MOSFET is used as the switch element constituting the switch unit in the ORing circuit 21 has been described. However, in some cases, a heterojunction FET or a bipolar transistor may be used. Anyway. When a heterojunction FET is used, the control terminal as a switch element is a gate terminal as in the case of MOSFET, and the conduction state and non-conduction state are controlled by applying a gate voltage to the gate terminal. On the other hand, when using a bipolar transistor, the control terminal as a switch element is a base terminal, and it goes without saying that the conduction state and the non-conduction state are controlled by applying the base to the base terminal.

(Explanation of effect of embodiment)
As described in detail above, the following effects are obtained in the present embodiment. That is, in a power supply device configured with a plurality of power supplies operating in parallel, each power supply includes a plurality of switch elements in an ORing circuit 21 (switch unit) arranged for backflow prevention and protection. When a failure occurs in the power supply, all the switch elements are set to the OFF state (non-conduction state) to isolate and disconnect the failed power supply, and then normal power supplies other than the failed power supply are normal. When returning to the state, by adopting a circuit configuration in which a plurality of switch elements in the ORing circuit 21 (switch unit) can be driven stepwise by shifting in time, any of the instructions for which the return instruction is first given This switch element can be prioritized over other switch elements and returned to the ON state (conducting state) at high speed until the output voltage becomes normal It is possible to reduce the voltage variation value and time. Therefore, it is possible to reduce the number of installed large-capacity capacitors for suppressing voltage fluctuations, and to realize downsizing, integration, and cost reduction of the power supply device.

  The configuration of the preferred embodiment of the present invention has been described above. However, it should be noted that such embodiments are merely examples of the present invention and do not limit the present invention in any way. Those skilled in the art will readily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 11 DC / DC converter part 12 DC / DC converter part 13 DC / DC converter part 21 ORing circuit 22 ORing circuit 23 ORing circuit 30 Load 211 Drive IC (Integrated Circuit)
D1 drain terminal D2 drain terminal D3 drain terminal Dq1 first body diode Dq2 second body diode Dq3 third body diode G1 gate terminal G2 gate terminal G3 gate terminal Id1 drain current Id1n first steady current value Id2 drain current Id2n second steady current Value Id3 Drain current Id3n Third steady current value I1on First on current value I2on Second on current value I3on Third on current value Ig1 Gate current Ig2 Gate current Ig3 Gate current Io Load current Q1 First transistor Q2 Second transistor Q3 First 3 transistor Rz2 second resistor Rz3 third resistor S1 source terminal S2 source terminal S3 source terminal V1n first steady voltage value V1on first on voltage value V2n second steady voltage value V2on second on voltage value V3n third steady state Voltage value V3on First on-voltage value VF Conducting voltage Vgs1 First drive voltage Vgs2 Second drive voltage Vgs3 Third drive voltage Vo Load voltage Von Normal voltage value Vov Overvoltage Vz2 Second Zener voltage value Vz3 Third Zener voltage value ZD2 First 2 Zener diode ZD3 3rd Zener diode

Claims (9)

  In a power supply apparatus that includes a switch unit on the output side of each of a plurality of power supplies connected in parallel, and supplies power in parallel to the load from each power supply via each switch unit, each of the switch units is connected in parallel When a failure that outputs an abnormal voltage to any one of the plurality of power supplies occurs, all the switch elements in the switch unit included in each power supply are set to a non-conductive state. Then, when resuming power supply to the load side by each power source other than the failed power source among the plurality of power sources, the plurality of switches constituting the switch unit for each of the power sources other than the failed power source The switching timing for switching each element to the conductive state is shifted in stages by a predetermined time to return from the non-conductive state to the conductive state. Power apparatus according to claim Rukoto.   The switching timing elapses more than the time required for the switch element to switch to the conductive state after outputting a switching instruction for a switch element to be switched to the conductive state among the plurality of switch elements. 2. The power supply device according to claim 1, wherein the power supply device is set so as to output a switching instruction for a switch element to be switched in the next order.   The switch element is composed of any one of a MOSFET, a heterojunction FET, and a bipolar transistor, and when the switch element is a MOSFET or a heterojunction FET, by applying a gate voltage to a gate terminal serving as a control terminal of the switch element, When the switch element is a bipolar transistor, the conduction state and non-conduction state of the switch element are controlled by applying a base voltage to a base terminal serving as a control terminal of the switch element. The power supply device according to claim 1, wherein the conduction state is controlled.   Of each of the plurality of switch elements, each of the switch elements whose switching timing is delayed in stages is connected with a Zener diode and a resistor for generating a Zener voltage to the control terminal of the switch element. 4. The voltage value is set in consideration of the ability of a drive source for driving the control terminal, so that the switching timing of each switch element is set to be delayed by a predetermined time. The power supply device described in 1.   A power supply control method in a power supply apparatus that includes a switch unit on the output side of each of a plurality of power supplies connected in parallel, and supplies power from each of the power supplies in parallel to a load via each switch unit, wherein the switch unit Each is composed of a plurality of switch elements connected in parallel, and when a failure occurs in which an abnormal voltage is output to any one of the plurality of power supplies, all the switch elements in the switch unit included in each power supply are connected. After restarting the power supply to the load side by each power source other than the failed power source among the plurality of power sources after setting to the non-conducting state, the switch unit for each power source other than the failed power source Non-conducting state by shifting the switching timing for switching each of the plurality of constituting switch elements to a conducting state stepwise in a stepwise manner. Power supply control method for causing return to al-conductive state.   The switching timing elapses more than the time required for the switch element to switch to the conductive state after outputting a switching instruction for a switch element to be switched to the conductive state among the plurality of switch elements. 6. The power supply control method according to claim 5, wherein the power supply control method is set so as to output a switching instruction for a switching element to be switched in the next order after the switching.   The switch element is composed of any one of a MOSFET, a heterojunction FET, and a bipolar transistor, and when the switch element is a MOSFET or a heterojunction FET, by applying a gate voltage to a gate terminal serving as a control terminal of the switch element, When the switch element is a bipolar transistor, the conduction state and non-conduction state of the switch element are controlled by applying a base voltage to a base terminal serving as a control terminal of the switch element. The power supply control method according to claim 5 or 6, wherein the conduction state is controlled.   Of each of the plurality of switch elements, each of the switch elements whose switching timing is delayed in stages is connected with a Zener diode and a resistor for generating a Zener voltage to the control terminal of the switch element. 8. The voltage value is set in consideration of the capability of a drive source that drives the control terminal, so that the switching timing of each switch element is set to be delayed by a predetermined time. The power supply control method described in 1.   An electronic apparatus comprising a power supply circuit for supplying power to a load by connecting a plurality of power supplies in parallel, wherein the power supply circuit is configured using the power supply apparatus according to any one of claims 1 to 4. An electronic device.

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