JP2012169008A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of reducing a peak current.SOLUTION: A semiconductor storage device comprises: a memory cell array in which a plurality of memory cells are arranged in rows and columns; a plurality of even-numbered bit lines arranged in the columns with even numbers; a plurality of odd-numbered bit lines arranged in the columns with odd numbers adjacent to the columns with even numbers; and a plurality of sense amplifiers 11 each of which is selectively connected to the odd-numbered bit lines and even-numbered bit lines. Each of the sense amplifiers comprises: first and second inverter circuits 68 and 69 for which a latching connection is made so as to have data held in first and second nodes; and a sensing part including first and second transistors P11 and P12, in each of which a current control signal is supplied to a gate, one end of a current path is connected to a first power supply voltage and the other end of the current path is connected to a control terminal of the corresponding first or second inverter circuit.

Description

  The present invention relates to a semiconductor memory device.

  For example, the NAND flash memory includes an SLC (Single Level Cell) capable of storing 1-bit data in a memory cell, an MLC (Multi Level Cell) capable of storing multi-bit data in a memory cell, and the like.

Japanese Patent No. 3935139

  A semiconductor memory device capable of reducing peak current is provided.

  According to the embodiment, a semiconductor memory device according to an aspect includes a memory cell array in which a plurality of memory cells are arranged in rows and columns, a plurality of even bit lines arranged in an even number of the columns, A plurality of odd bit lines arranged in odd columns adjacent to a column, and a plurality of sense amplifiers each selectively connected to the odd bit lines and even bit lines, each of the sense amplifiers The first and second inverter circuits latch-connected to hold data in the first and second nodes, a current control signal is applied to the gate, one end of the current path is connected to the first power supply voltage, A sense unit having first and second transistors connected to the control terminals of the first and second inverter circuits at the other end of the current path, respectively.

1 is a block diagram showing an example of the overall configuration of a semiconductor memory device according to a first embodiment. The figure which shows the 1st thru | or 5th voltage generation circuit in FIG. FIG. 2 is a diagram illustrating a configuration of a sense amplifier in FIG. 1. The equivalent circuit diagram which shows the sense unit which concerns on 1st Embodiment. FIG. 5 is a diagram illustrating a data read operation of the sense unit according to the first embodiment. FIG. 5 is a diagram showing a data write operation of the sense unit according to the first embodiment. FIG. 6 is a diagram showing a write verify operation of the sense unit according to the first embodiment. FIG. 6 is a diagram showing a data erase / erase verify operation of the sense unit according to the first embodiment. The figure which shows NOT operation of the sense unit which concerns on 1st Embodiment. The figure which shows the cell current monitoring operation | movement of the sense unit which concerns on 1st Embodiment. The equivalent circuit diagram which shows the sense unit which concerns on 2nd Embodiment. The figure which shows data read-out operation | movement of the sense unit which concerns on 2nd Embodiment. The figure which shows data write-in operation | movement of the sense unit which concerns on 2nd Embodiment. FIG. 10 is a diagram showing a write verify operation of the sense unit according to the second embodiment. FIG. 10 is a diagram showing a data erase / erase verify operation of the sense unit according to the second embodiment. The figure which shows NOT arithmetic operation of the sense unit which concerns on 2nd Embodiment. FIG. 10 is a timing chart showing a data transfer operation of a sense unit according to the second embodiment. The figure which shows the data transfer operation | movement of the sense unit which concerns on 2nd Embodiment. The figure which shows the effect of the sense unit which concerns on 2nd Embodiment. The figure which shows the effect of the sense unit which concerns on 2nd Embodiment.

  Here, in the sense amplifier of the NAND flash memory, for example, in a data read operation, a transistor (for example, NMOS) is forcibly turned on according to the voltage of the bit line and a latch node is discharged (forced inversion). ) There are cases. In this case, it is necessary to make the ON current i (NMOS) for turning on the transistor (NMOS) compete with the switching current i (PMOS) of the transistor (PMOS) constituting the latch node. For this reason, the values of the currents i (NMOS) and i (PMOS) increase. Similarly, the current value for charging the latch node also increases.

  As a result, the peak current increases and a power supply voltage drop occurs.

  In order to prevent the peak current from increasing and to ensure stable operation, the gate width (W) of the switching transistor (NMOS) is increased, and the gate length (L) of the transistor (PMOS) constituting the latch node is increased. It is possible. However, in the above configuration, the circuit area may increase.

  Therefore, embodiments will be described below with reference to the drawings. In the following description, a NAND flash memory is taken as an example of a semiconductor memory device. In this description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
A semiconductor memory device according to the first embodiment will be described.

<1. Configuration example>
1-1. Overall configuration example
First, an example of the overall configuration of the semiconductor memory device according to the first embodiment will be described with reference to FIG.

  As shown in the figure, the semiconductor memory device according to this embodiment includes a memory cell array 1, a row decoder 2, a driver circuit 3, a voltage generation circuit 4, an n-channel MOS transistor group 6, a data input / output circuit 7, a control unit 8, A source line SL driver 9 and a sense amplifier 11 are provided.

  The memory cell array 1 includes blocks BLK0 to BLKs including a plurality of nonvolatile memory cell transistors MT (s is a natural number). Each of the blocks BLK0 to BLKs includes a plurality of NAND strings 15 in which nonvolatile memory cell transistors MT are connected in series. Each of the NAND strings 15 includes, for example, 64 memory cell transistors MT and select transistors ST1 and ST2.

  The memory cell transistor MT can hold data of two or more values. The structure of the memory cell transistor MT includes a charge storage layer (for example, an insulating film) formed on a semiconductor substrate with a gate insulating film interposed therebetween, and an insulating layer formed on the charge storage layer and having a dielectric constant higher than that of the charge storage layer. This is a MONOS structure having a film (hereinafter referred to as a block layer) and a control gate formed on the block layer. The structure of the memory cell transistor MT may be FG type. The FG type includes a floating gate (conductive layer) formed on a p-type semiconductor substrate with a gate insulating film interposed therebetween, and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween. Structure.

  The control gate of the memory cell transistor MT is electrically connected to the word line, the drain is electrically connected to the bit line, and the source is electrically connected to the source line. Memory cell transistor MT is an n-channel MOS transistor. The number of memory cell transistors MT is not limited to 64, but may be 128, 256, 512, etc., and the number is not limited.

  The adjacent memory cell transistors MT share the source and drain. And it arrange | positions so that the current path may be connected in series between selection transistor ST1, ST2. The drain region on one end side of the memory cell transistors MT connected in series is connected to the source region of the select transistor ST1, and the source region on the other end side is connected to the drain region of the select transistor ST2.

  The control gates of the memory cell transistors MT in the same row are commonly connected to any one of the word lines WL0 to WL63, and the gate electrodes of the select transistors ST1 and ST2 of the memory cell transistors MT in the same row are select gate lines SGD1, Commonly connected to SGS1. For simplification of description, the word lines WL0 to WL63 may be simply referred to as word lines WL in the following when they are not distinguished. Further, the drains of the select transistors ST1 in the same column in the memory cell array 1 are commonly connected to any of the bit lines BL0 to BLn. Hereinafter, the bit lines BL0 to BLn are collectively referred to as a bit line BL (n: natural number) unless they are distinguished. The sources of the selection transistors ST2 are commonly connected to the source line SL.

  In addition, data is written into or read from a plurality of memory cell transistors MT connected to the same word line WL, and this unit is referred to as a page. Further, data is erased from the plurality of memory cell transistors MT in a unit of block BLK.

  The row decoder 2 includes a block decoder 20 and n-channel MOS transistors 21 to 23. The block decoder 20 decodes the block address given from the control unit 8 at the time of data write operation, read operation and erase, and selects the block BLK based on the result. That is, the control line TG connected to the MOS transistors 21 to 23 corresponding to the block BLK including the selected memory cell transistor MT is selected, and the MOS transistors 21 to 23 are turned on. At this time, the block decoder 20 outputs a block selection signal. The block selection signal is a signal for selecting one of the plurality of memory blocks BLK0 to BLKs by the row decoder 2 when data is read, written, erased, or the like. Thereby, the row decoder 2 selects the row direction of the memory cell array 1 corresponding to the selected block BLK. That is, based on the selection signal supplied from the block decoder 20, the row decoder 2 transfers the voltage supplied from the driver circuit 3 to the select gate lines SGD1 and SGS1 and the word lines WL0 to WL63, respectively.

  The driver circuit 3 includes select gate line drivers 31 and 32 provided for the select gate lines SGD1 and SGS1, and a word line driver 33 provided for each word line WL. In the present embodiment, only the word line driver 33 and select gate line drivers 31 and 32 corresponding to the block BLK0 are illustrated. However, actually, the word line driver 33 and the select gate line drivers 31 and 32 are commonly connected to, for example, 64 word lines WL and select gate lines SGD1 and SGS1 provided in the blocks BLK0 to BLKs.

  The block BLK is selected according to the decoding result of the page address given from the control unit 8. The word line driver 33 transfers a desired voltage obtained from the voltage generation circuit to the control gate of the memory cell transistor MT provided in the selected block BLK. The select gate line driver 31 transfers a desired voltage obtained from the voltage generating circuit to the gate of the select transistor ST1. At this time, the select gate line driver 31 transfers the signal sgd to the gate of the select transistor ST1. Specifically, the select gate line driver 31 transfers, for example, the signal sgd to the gate of the select transistor ST1 when data is written, read, erased, and further when data is verified. The signal sgd is set to the ground power supply voltage level VSS (for example, about 0 [V]) when the signal is at the “L” level, and the internal power supply voltage level when it is at the “H” level. VDD (for example, about 1.8 [V]).

  Similarly to the select gate line driver 31, the select gate line driver 32 transfers a desired voltage to the gate of the select transistor ST2 at the time of data writing, data reading, and data verification. At this time, the select gate line driver 32 transfers the signal sgs to the gate of the select transistor ST2. The signal sgs is set to 0 [V] when the signal is at the “L” level, and is set to the voltage VDD when the signal is at the “H” level.

  The voltage generation circuit 4 includes a first voltage generation circuit 41, a second voltage generation circuit 42, a third voltage generation circuit 43, a fourth voltage generation circuit 44, and a fifth voltage generation circuit 45. The first voltage generation circuit 41 to the fifth voltage generation circuit 45 will be described later.

The data input / output circuit 7 outputs an address and a command supplied from a host via an I / O terminal (not shown) to the control unit 8. The data input / output circuit 7 outputs write data to the sense amplifier 11 through the data line D _line . Further, when data is output to the host, the data input / output circuit 7 receives the data received from the sense amplifier 11 via the data line D _line via the I / O terminal based on the control of the control unit 8. Output to.

  The control unit 8 controls the operation of the entire NAND flash memory. That is, an operation sequence in a data write operation, a read operation, and an erase operation is executed based on the address and command given from a host (not shown) via the data input / output circuit 7. The control unit 8 generates a block selection signal / column selection signal based on the address and the operation sequence.

  The control unit 8 outputs the block selection signal described above to the row decoder 3. Further, the control unit 8 outputs a column selection signal to the sense amplifier 11. The column selection signal is a signal for selecting the column direction of the sense amplifier 11.

  The control unit 8 is given a control signal supplied from a memory controller (not shown). Based on the supplied control signal, the control unit 8 distinguishes whether the signal supplied from the host to the data input / output circuit 7 via an I / O terminal (not shown) is an address or data. .

  The source line SL driver 9 includes MOS transistors 12 and 13. One end of the current path of the MOS transistor 12 is connected to the source line SL, the other end is grounded, and a signal Clamp_S1 is applied to the gate. One end of the current path of the MOS transistor 13 is commonly connected to one end of the current path of the MOS transistor 12, the other end is supplied with the voltage VDD, and the gate is supplied with the signal Clamp_S2.

  When the MOS transistor 12 is turned on, the potential of the source line SL is set to 0 [V]. When the MOS transistor 13 is turned on, the potential of the source line SL is set to the voltage VDD. The signals Clamp_S1 and S2 given to the gates of the MOS transistors 12 and 13 are controlled by the control unit 8. Note that the MOS transistor 13 is turned on when erase verify is performed. That is, the voltage VDD is transferred from the source line SL side to the bit line BL by turning on the MOS transistor 13 during the erase verify.

1-2. About the first voltage generation circuit 41 to the fifth voltage generation circuit 45
Next, the first voltage generation circuit 41 to the fifth voltage generation circuit 45 will be described with reference to FIG.

  As illustrated, the first voltage generation circuit 41 to the fifth voltage generation circuit 45 include a limiter circuit 50 and a charge pump circuit 51. The charge pump 51 generates voltages necessary for, for example, a data write operation, an erase operation, and a read operation by the control unit 8. Each of the voltages is output from the node N1 and supplied to, for example, the row decoder 2 in the NAND flash memory via the driver circuit 3. The limiter circuit 50 controls the charge pump circuit 51 according to the potential of the node N1, while monitoring the potential of the node N1. That is, if the potential of the node N1 is higher than a predetermined value, the limit circuit 50 stops the pumping of the charge pump circuit 51 and steps down the potential of the node N1.

  On the other hand, if the potential of the node N1 is lower than a predetermined value, the charge pump circuit 51 is pumped to boost the potential of the node N1.

  The first voltage generation circuit 41 generates a voltage VPGM when writing data, and transfers the voltage VPGM to the selected word line WL. The voltage VPGM is a voltage of such a magnitude that the charge of the channel formed immediately below the memory cell transistor MT is injected into the charge storage layer, and the threshold value of the memory cell transistor MT changes to another level.

  The second voltage generation circuit 42 generates the voltage VPASS and transfers the voltage VPASS to the unselected word line WL. The voltage VPASS is a voltage at which the memory cell transistor MT is turned on.

  The third voltage generation circuit 43 generates the voltage VERA and transfers it to the well driver 7. The voltage VERA is 20 [V], for example. That is, when erasing data, a voltage of, for example, 20 [V] generated by the third voltage generating circuit 43 is applied to the well region where the memory cell transistor MT is formed.

  The fourth voltage generation circuit 44 generates a voltage VCGR and transfers this voltage VCGR to the selected word line WL. The voltage VCGR is a voltage corresponding to data to be read from the memory cell transistor MT.

  The fifth voltage generation circuit 45 generates the voltage VREAD and transfers this voltage VREAD to the non-selected word line WL when reading data. The voltage VREAD is a voltage that turns on the memory cell transistor MT without depending on the data held by the memory cell transistor MT.

1-3. About sense amplifier 11
Next, a configuration example of the sense amplifier 11 according to the first embodiment will be described with reference to FIG. As illustrated, the sense amplifier 11 includes, for example, sense blocks SB _{1 to} SB ₁₆ . These sense blocks SB _{1 to} SB ₁₆ can hold, for example, 2 kbytes of data. That is, the sense amplifier 11 can exchange (read and write) 2 kbytes of data per page with the memory cell array 1 via the bit line BL. In the case where the sense blocks SB ₁ to SB ₁₆ are not distinguished, they are simply referred to as sense blocks SB. Note that the number of divisions of the sense amplifier 11 is not limited to 16 and may be any number.

Each of sense blocks SB sense unit _{SU 1-1 ~SU 1-M, SU} 2-1 ~SU 2-M, ..., includes a _{SU 16-1 ~SU 16-M.} These sense units SU _{1-1 to} SU _{1 -M} , SU _{2-1 to} SU _{2 -M} ,..., SU _{16-1 to} SU _16-M each hold data of the corresponding memory cell transistor MT. Incidentally, the sense unit _{SU 1-1 ~SU 1-M, SU} 2-1 ~SU 2-M, ..., if there is no need to distinguish between _{SU 16-1 ~SU 16-M,} simply referred to as a sense unit SU.

  The sense unit SU can hold 1-bit data. Further, two bit lines BL are connected to one sense unit SU. That is, data reading and writing are performed one by one of the two adjacent bit lines BL. This configuration will be described using an enlarged view of the sense block SB.

  As shown in the figure, in the sense units SU1-1 to SU8-1, a pair of two adjacent bit lines BL is a pair of bit lines BL0 and BL1, a pair of bit lines BL2, a bit line BL3, and a bit line BL4, respectively. , A set of bit lines BL5, and so on. That is, reading and writing are collectively performed on n / 2 bit lines BL among n bit lines BL. Hereinafter, the bit line BL to be read or written in the set of bit lines BL is referred to as a selected bit line BL, and the non-target bit line BL is referred to as a non-selected bit line BL.

  These sense units SU sense and amplify data read from the memory cell transistor MT to the bit line BL when reading data. More specifically, the sense unit SU precharges the voltage VDD to the bit line BL and senses the voltage (or current) of the bit line BL.

Further, the sense units SU _{1-1 to} SU _8-1 are connected to a common signal line COM. The data held by the sense units SU _{1-1 to} SU _8-1 is detected by the fail bit detection circuit 11-1. Thereafter, the result detected by the fail bit detection circuit 11-1 is transferred to the control unit 8.

1-4. About Sense Unit SU
Next, a configuration example of the sense unit SU according to the first embodiment will be described with reference to FIG. The sense unit SU according to the present embodiment is a sense unit capable of sensing binary data stored in the memory cell transistor MT.

  As shown in the figure, the sense unit SU includes a primary data cache (PDC, PDCn), a dynamic data cache (DDC), a temporary data cache (TDC), a MOS transistor group 6, and the like.

  The primary data cache (PDC, PDCn) includes inverters 68 and 69 and PMOS transistors P11 and P12. Inverters 68 and 69 are constituted by PMOS transistors and NMOS transistors (not shown). The input and output of the inverter circuit 68 are latch-connected by being connected to the output and input of the inverter 69, respectively. The source of the PMOS transistor P11 is connected to the internal power supply voltage VDD, the drain is connected to the control terminal of the inverter 68 (the source of the PMOS transistor constituting the inverter 68), and the current potential signal SAPG is applied to the gate. The source of the PMOS transistor P12 is connected to the internal power supply voltage VDD, the drain is connected to the control terminal of the inverter 69 (the source of the PMOS transistor constituting the inverter 69), and the current potential signal SAPG is applied to the gate.

  The current potential signal SAPG is used to suppress the Ids of the PMOS transistor P11 to Ido_P11 / n (1 / n) where the saturation current (drain = VDD, gate = VSS, source = VSS) of the PMOS transistor P11 is Ido_P11. A gate potential signal generated by the current copy means. For example, in this example, Ido_P11 is about several tens of μA. With this current potential signal SAPG, the peak current can be suppressed to about 1/5. Details will be described later.

  The dynamic data cache (DDC) includes a PMOS transistor P75 and an NMOS transistor N75. One end of the current path of the PMOS transistor P75 is connected in common with one end of the current path of the transistor N75. One end of the current path of the PMOS transistor P75 is connected to the internal power supply voltage VDD. The other end of the current path of transistor N75 is connected, and the gate is connected to node N1a. Transistor N75 has its gate connected to node LAT1.

  In the temporary data cache (TDC), data of the bit line BL at the time of data reading or the like is held, and one end of the transistor 81, one end of the capacitor C1, and one end of the transistors 74 and 79 are connected. The other end of the current path of the transistor 81 is connected to the transistor group 6 and a signal BLCCLAMP is given to the gate. A boost signal Boost is supplied to the other end of the electrode of the capacitor C1. The other end of the current path of the transistor 74 is connected to a dynamic data cache (DDC), and a signal REG is given to the gate. One end of the current path of the transistor 79 is connected to the dynamic data cache (DDC), the other end is connected to the current path of the transistor 80, and the gate is connected to the temporary data cache (TDC).

  The MOS transistor group 6 includes NMOS transistors 6a to 6b, and functions as a bit line selection circuit that can connect the node N12 (TDC) of the sense unit SU to either the odd or even bit line BL.

  The current paths of MOS transistors 6a and 6b are connected in series between internal power supply voltage VDD and node N12 (TDC) of sense unit SU, and signals BLS (i + 1) and BIAS (i + 1) are applied to the gates, respectively. The connection nodes of the current paths of the MOS transistors 6a and 6b are connected to the odd bit line BL (i + 1) (i is an even number, i = 0, 2, 4,..., N). The current paths of MOS transistors 6c and 6d are connected in series between internal power supply voltage VDD and node N12 (TDC) of sense unit SU, and signals BLSi and BIASi are applied to the gates, respectively. The connection nodes of the current paths of the MOS transistors 6c and 6d are connected to the even bit line BLi.

  The MOS transistors 6b and 6d are turned on complementarily to the MOS transistors 6a and 6c in response to the signal BlAS (i + 1) and the signal BlASi, and supply the voltage VDD to the non-selected bit line BL.

  When MOS transistors 6b and 6c and MOS transistor 84 are turned on, sense unit SU is electrically connected to even bit line BLi (selected bit line BL), and odd bit line BL (i + 1) is a non-selected bit. Line BL.

  In contrast, when the MOS transistors 6a and 6d and the MOS transistor 84 are turned on, the sense unit SU is connected to the odd bit line BL (i + 1) (selected bit line BL) and the even bit line BLi is not selected. The bit line BL is used. At this time, the potential of the even-numbered or odd-numbered bit line BL set as the non-selected bit line BL is fixed at, for example, the voltage VDD. That is, the MOS transistor 84 functions as a non-selection circuit that charges the bit line BL to a non-selection potential.

  When the voltage (VDD + Vth) corresponding to the 'H' level is supplied to the gates of the MOS transistors 6a to 6d as the signal BLSi, the signal BLS (i + 1), the signal BIASi, and the signal BIAS (i + 1). MOS transistors 6a-6d are turned on. Here, the voltage Vth is a threshold voltage of the MOS transistors 6a to 6d.

  On the other hand, when a signal corresponding to 'L' level, for example, zero potential, is transferred to the gate of the MOS transistor group 6 as the signal BLSi, signal BLS (i + 1), signal BIASi, and signal BIAS (i + 1), the MOS transistors 6a to 6d. Is turned off.

  In addition, the other end of the current path of the transistor 80 is connected to the ground power supply voltage VSS, and a signal SEN1 is applied to the gate. One end of the current path of the transistor 72 is connected to the primary data cache, the other end is connected to the node N12 (TDC), and a signal BLC1 is applied to the gate.

  Transistors 78 and 82 are connected in series between the signal line COM and the ground power supply voltage VSS. One end of the current path of the transistor 78 is grounded, and the signal CHK1 is supplied to the gate. One end of the current path of the transistor 82 is connected to the other end of the current path of the transistor 78, the other end of the current path is connected to the signal line COM, and the gate is connected to the node N1b.

The signal line COM outputs a fail signal indicating whether, for example, write verify, erase verify, or the like has been completed in the sense unit SU. The signal line COM is commonly connected along the column direction in the sense block (for example, between the sense blocks SB _{1 to} SB ₈ ). Therefore, a signal inverted from, for example, the “L” level to the “H” level is detected on the signal line COM in accordance with how many bit sense units SU have failed to write data in the write verify.

One end of the current path of the column selection MOS transistor 65 is connected to the node N1b, and the other end is connected to the input / output data line D _line (signal line I / O). An “L” or “H” level signal is input / output to / from the PDC via the MOS transistor 65 from the input / output data line D _line .

One end of the current path of the column selection transistor 66 is connected to the node N1a, and the other end is connected to the input / output data line D _line (signal line I / On). An “L” or “H” level signal is input / output to / from the PDC via the MOS transistor 66 from the input / output data line D _line . Note that complementary signals are inputted to and outputted from the signal line I / O and the signal line I / On.

A column selection signal CSL is supplied to the gates of the MOS transistors 65 and 66. When the MOS transistors 65 and 66 are turned on by the signal CSL, the sense unit SU inputs / outputs data to / from the data input / output circuit 8 via the input / output data line D _line .

<2. Operation of sense unit SU>
<2-1. Data read operation (Read)>
Next, the data read operation of the sense unit SU according to the first embodiment will be described with reference to FIG. Here, a case where the even bit line BLi is the selected bit line BL will be described as an example. At this time, the voltage of the odd-numbered bit line BL (i + 1) is charged to the non-selection voltage (voltage VDD) during the read operation.

Step S11- (1) (BL charge)
First, the gates of the transistors 76 and 81 are selected, the current paths of the transistors 76 and 81 are made conductive, and the potential of the bit line BL is charged by the current current I (1) in the drawing. Here, the transistor 71 is turned on, and the potential of the latch node 1Nb becomes the “H” level.

Step S11- (2) (BL transition wait)
Subsequently, the potential of the gate signal BLCCAMP of the transistor 81 is not selected (VSS), the transistor 81 is turned off, and the process waits until the potential of the bit line BL transitions.

Step S11- (3) (Charge share sense)
Subsequently, the potential of the gate signal BLPRE of the transistor 76 is not selected (VSS), and the potential of the gate signal BLCCAMP of the transistor 81 is selected (Vsen), so that the node N12 (TDC) and the bit line BL are made conductive.

  This causes charge transfer. That is, when the NAND string 15 is in a conductive state, the charge of the even bit line BLi is discharged toward the source line SL. As a result, the node N12 (TDC) transits from the voltage VDD to, for example, zero potential ('L'). In this case, the charge at the node N12 moves to the even bit line BLi. This is because the even bit line BLi capacity is larger than the wiring capacity of the node N12.

  On the other hand, when the NAND string 15 is in a non-conduction state, the potential of the even bit line BLi maintains the voltage VDD, and therefore no charge transfer occurs. That is, the potential of the node N12 is maintained at the voltage VDD ('H').

Step S11- (4) (PRST)
Subsequently, the gate of the transistor 71 is selected, the current path of the transistor 71 is made conductive, the current I (4) in the figure is generated, and the dynamic data cache (DDC) is charged. At this time, if the power supply voltage VDD is high, the PMOS transistor P75 in the dynamic data cache (DDC) is unnecessary.

Step S11- (5) (TDC => PDC)
Subsequently, a sensing operation is performed. This sense operation is an operation in which the gate signal SEN1 of the transistor 80 is set to the “H” level and the potential of the bit line BL (TDC) is taken into the primary data cache PDC.

  As a result of the conduction of the NAND string 15, the MOS transistor 79 is turned off when the potential of the node N12 (TDC) transits to, for example, zero potential. For this reason, the signal SEN1 is set to the “H” level, and the node N1b of the PDC (hereinafter referred to as PDC (node N1b)) holds the “H” level.

  On the other hand, when the NAND string 15 is turned off and the potential of the node N12 (TDC) maintains the voltage VDD, the MOS transistor 79 is turned on. In this state, when the signal SEN1 is set to the “H” level and the MOS transistor 80 is turned on, the ground power supply potential (for example, “L” level = zero potential) is conducted from the node N1b, and the current (5 in FIG. ) Flows. Therefore, the node N1b of the PDC is inverted from the “H” level to the “L” level. In this way, the PDC takes in and latches data at either the ‘L’ level or the ‘H’ level corresponding to the potential of the even bit line BLi.

  At this time, the current potential signal SAPG is given to the gates of the PMOS transistors P11 and P12 that are AND-connected to the latch circuits 68 and 69, and the switching current i (PMOS) of the PMOS transistors constituting the inverters 69 and 68 is controlled. it can. As a result, the switching current i (PMOS) and the on-current i (NMOS) of the NMOS transistor 79 constituting the current (5) in step S11- (5) are reduced. Therefore, the peak current during charging of the latch node N1b can be reduced, and the power drop can be reduced.

Step S11- (6) (IO transfer)
Subsequently, when the signal CSL becomes “H” level, the data held in the PDC is transferred to the signal line I / O and the signal line I / On via the transistors 65 and 66.

<2-2. Data write operation (Program)>
Next, the data write operation of the sense unit SU according to the first embodiment will be described with reference to FIG. Here, similarly, a case where the even bit line BLi is the selected bit line BL will be described as an example.

Step S12- (1) (80hrst)
First, the gate of the transistor 71 is selected, the current path of the transistor 71 is made conductive, and the current I (1) in the figure is generated. At this time, it is assumed that the potential of the latch node 1Nb is at the “H” level.

Step S12- (2) (Program data load)
Subsequently, the write data is loaded into the primary cache PDC.
As shown as current (2) in the figure, when a command (for example, CMD1) is given from the host to the control unit 8, it is transferred from the signal lines I / O and I / On via the MOS transistors 65 and 66. The write data ('H' or 'L' level) is stored in the PDC.

Step S12- (3) (NOT)
Subsequently, the data held in the PDC (nodes N1b and N1a) is inverted. That is, a NOT operation is performed on the PDC data. At this time, the gate signal CSL of the transistors 65 and 66 is set to the “L” level.

Step S12- (4) (Program bias)
Subsequently, when writing data to the memory cell transistor MT, the signal BLC1 is set to the “H” level, and the MOS transistor 72 is turned on. Further, the signal BLCCLAMP (and the signal BLSi) is set to the “H” level, and the MOS transistor 81 (and the MOS transistor 6 c) are turned on. As a result, the current (5) in the figure flows, the data held by the PDC is transferred to the even bit line BLi, and desired data writing is performed.

<2-3. Write Verify Operation (PVFY)>
Next, the write verify operation of the sense unit SU according to the first embodiment will be described with reference to FIG. In the write verify operation, it is determined whether or not the writing is completed according to the data held in the PDC. Specifically, when the data held in the PDC is at the “L” level, it is determined that the data writing is complete, and when it is at the “H” level, it is determined that the data writing operation is not complete, and is determined to be complete. The data write operation and write verify operation are repeated until the data is written.

  Here, similarly, a case where the even bit line BLi is the selected bit line BL will be described as an example.

Step S13- (1) (BL charge)
First, the gates of the transistors 76 and 81 are selected, the current paths of the transistors 76 and 81 are made conductive, the current current I (1) in the figure is generated, and the potential of the bit line BL is charged. At this time, the potential of the latch node 1Nb is assumed to be 'L' level, and the potential of the latch node 1Na is assumed to be 'H' level.

Step S13- (2) (BL transition wait)
Subsequently, the potential of the gate signal BLCCAMP of the transistor 81 is not selected (VSS), the transistor 81 is turned off, and the process waits until the potential of the bit line BL transitions.

Step S13- (3) (Charge share sense)
Subsequently, the potential of the gate signal BLPRE of the transistor 76 is not selected (VSS), and the potential of the gate signal BLCCAMP of the transistor 81 is selected (Vsen), so that the node N12 (TDC) and the bit line BL are made conductive. This causes the charge transfer.

The node N12 (TDC) when writing and verifying the “1” data is charged with the “L” level potential.
When the potential of the “L” level is charged to the node N12 (TDC) when the “0” data is written and verified, the above “0” data writing is determined to be a failure. Therefore, it is a target of reprogramming in step S13- (5) described later.
If the node N12 (TDC) at the time of writing and verifying the “0” data is charged with the “H” level potential, it is determined that the “0” data writing is successful (pass). Therefore, reprogramming in step S13- (5) described later is not performed.

Step S13- (4) (TDC => PDC)
Subsequently, similarly, a sensing operation is performed in which the gate signal SEN1 of the transistor 80 is set to the “H” level and the potential of the bit line BL (TDC) is taken into the primary data cache PDC. The data charged in the node N12 (TDC) by the above step S13- (3) has the following relationship, respectively.

When the node N12 (TDC) is charged with the “L” level when the “1” data is written and verified, the transistor 79 is not turned on and the data is not taken into the PDC. Therefore, the data latched at the node N1b is not inverted.
When the node N12 (TDC) is charged with the “L” level when the “0” data is written and verified, the transistor 79 is not turned on and the data is not taken into the PDC. Therefore, since the data latched at the node N1b is not inverted and remains at the “H” level, the “0” data write is determined to be a failure.
When the “0” data is written and verified, the transistor 79 becomes conductive when the node N12 (TDC) is charged with the “H” level. Therefore, when the gate signal SEN1 of the transistor 80 becomes the “H” level, the current (5) in the figure flows, and the data of the “L” level of the node N12 (TDC) is taken into the PDC. Therefore, the data “H” level latched at the node N1b is inverted to the “L” level, and the “0” data write is determined to be successful (pass).
Step S13- (5) (Re-Program)
Subsequently, when it is determined that the writing has failed (fail), the signal BLC1 is set to the “H” level and the MOS transistor 72 is turned on by the same voltage relationship as in step S12- (4). Further, the signal BLCCLAMP is set to the H ′ level, and the MOS transistor 81 is turned on. As a result, the current (5) in the figure flows, the data held by the PDC is transferred to the even bit line BLi, and desired data writing is performed. These operations are continued until it is determined that the data writing is successful (pass).

<2-4. Data Erase / Erase Verify Operation (ERASE / EVFY)>
Next, a data erase / erase verify operation of the sense unit SU according to the first embodiment will be described with reference to FIG.

Step S14- (1) (SABL = VDD)
First, the gate signals BLPRE and the signal BLCCLAMP of the transistors 76 and 81 are set to the “H” level, the current (1) is supplied, and the potential of the source terminal of the MOS transistor 81 is set to the voltage VDD.

Step S14- (2) (TDC = VDD)
Subsequently, the signal BLCCLAMP and the signal BLPRE are set to the “H” level, the MOS transistors 76 and 81 are turned on, and the current (2) in the drawing is supplied, whereby the potential of the node N12 (TDC) is set to the internal power supply voltage VDD. To do.

Step S14- (3) (TDC => PDC)
Subsequently, the potential of the node N12 (TDC) is taken into the primary data cache PDC. The signal SEN1 is set to the “H” level, the current (3) in the figure is passed, and the data for setting the node N1b to the “L” level and the node N1a to the “H” level is latched.

<Erase verification (even)>
Next, the erase verify operation in the above configuration will be described. The erase verify operation was alternately performed on the even bit line BLi and the odd bit line BL (i + 1), and the write data of the memory cell transistor MT could be erased on both the even bit line BLi and the odd bit line BL (i + 1). When confirming the above, the erase verify operation is completed. Specifically, when the data held in the PDC after the erase verify is at the “L” level, the control unit 8 determines that the erase verify has been completed based on information from the fail bit detection circuit 11-1.

  First, the erase verify operation of the even bit line BLi (even) will be described.

Step S14- (4) (SABL charge)
When the signal BLCCLAMP and the signal BLPRE are set to the “H” level and the MOS transistors 76 and 81 are turned on, the current (4) is supplied and the bit line is charged.

Step S14- (5) (BL transition wait & TDC charge)
Subsequently, the potential of the gate signal BLCCAMP is deselected (VSS), the transistor 81 is turned off, the process waits until the potential of the bit line BL transitions, the signal BLPRE is selected (Vsg), the transistor 76 is turned on, and the node N12 (TDC) and the internal power supply voltage are made conductive to charge node N12 (TDC).

Step S14- (6) (Charge share sense (even))
Subsequently, the potential of the bit line BL is transferred to the node N12 (TDC). The signal BLPRE is not selected (VSS), and the transistor 76 is turned off. The signal BLCCLAMP is selected (Vsenev), and the even bit line BLi and the node N12 (TDC) are electrically connected. If all the memory cell transistors MT connected to the even bit line BLi are in the erased state, the potential of the even bit line BLi is set to the voltage VDD corresponding to the “H” level even after charge sharing ( Erase verify pass (pass)). On the other hand, if not all in the erased state, even after charge sharing, the potential of the even-numbered bit line BLi corresponds to the “L” level (erase verify fail (fail)).

Step S14- (7) (REG = H)
Subsequently, the signal REG is selected to turn off the DDC. At this time, it is assumed that the node N1b of the PDC is at the “L” level and the node N1a is at the “H” level.

Step S14- (8) (PDC Reset)
Subsequently, the node N1b is set to the “H” level, the node N1a is set to the “L” level, the latch data is inverted, and the latch data of the PDC is reset.

Step S14- (9) (Sense)
Subsequently, a sensing operation for capturing the potential of the node N12 (TDC) into the PDC is performed.

  At this time, when the node N12 (TDC) is set to the “H” level and the erase verify pass is performed, the MOS transistor 79 is turned on and the signal REG is selected (the “H” level), thereby holding the PDC. The data transitions from the “H” level to the “L” level.

  On the other hand, when the node N12 (TDC) is set to the 'L' level and the erase verify fails (fail), the MOS transistor 79 is turned off. Therefore, even if the signal REG is selected ('H' level), the data held in the PDC remains at the 'H' level.

  The erase verify operation of the odd-numbered bit line BLi (odd) can be performed in the same manner as described above, and thus detailed description thereof is omitted.

<Erase verify operation>
Next, calculation for erase verify of even and odd bit lines will be described.

Step S14- (13) (EVFY even & odd operation)
First, the signal BLCCLAMP and the signal BLPRE are not selected (VSS), and the transistors 76 and 81 are turned off. By selecting the signal REG (VDD) and setting it to the internal power supply voltage (VSS), the current (13) in the figure is passed through the DDC, and the potential of the node N12 (TDC) is discharged.

  At this time, the calculation can be performed as follows according to the potential relationship of the node N12 (TDC).

  When the TDC potential is at the “H” level, the erase verify of the even bit line (even) is passed (“H” level) and the erase verify of the odd bit line (odd) is passed ( 'H' level).

  When the TDC potential is at the 'L' level, at least one of the even bit line (even) and the odd bit line (odd) is failed.

Step S14- (14) (PDC Reset)
Subsequently, PRST is selected (H), the transistor 71 is turned on and a current (14) is supplied, the node N1b is set to the “H” level, the node N1a is set to the “L” level, the latch data is inverted, and the latch data of the PDC To reset.

Step S14- (15) (Sense)
Subsequently, SEN1 is selected (H), the transistor 80 is turned on, a current (15) is supplied, and the potential of the PDC is sensed.

  At this time, the PDC potential relationship is opposite to the TDC potential relationship.

Step S14- (0) (Batch detection (serial mode))
Subsequently, collective detection (serial mode) for making the above determination will be described. The batch detection is an operation for batch detection that determines whether or not an erased state is set.

  First, the signal CSL is not selected ('L' level), and the MOS transistors 65 and 66 are turned off.

  Subsequently, the signal CHK1 is selected to turn on the transistor 78, and a current (0) in the drawing is supplied. Based on the voltage relationship of the terminal COM at this time, it is determined whether or not the memory cell transistor MT is in the erased state. . In this example, it is assumed that when the PDC (node N1b) is at the “H” level, the erase verify is failed (fail).

  At this time, if the terminal COM is kept at the “H” level, an erase verify pass is made. On the other hand, if the terminal COM changes from the “H” level to the “L” level, an erase verify failure (fail) occurs.

Next, the NOT calculation operation of the sense unit SU according to the first embodiment will be described with reference to FIG. The NOT operation is performed by inverting the data held in the PDC (node N1b). Step S15- (1) (TDC => VSS)
First, the signal BLPRE is selected ('H' level), the MOS transistor 76 is turned on, and the current (1) in the figure is generated between the node N12 (TDC) and the internal power supply voltage (VSS). By this step, the node N12 (TDC) is set to the ground power supply voltage VSS level.

Step S15- (2) (PDC => TDC)
Subsequently, the signal REG is selected (Vsg), the transistor 74 is turned on, the current (2) in the figure is generated, and the data “0” or “1” stored in the PDC is supplied to the node N12 (TDC). Let it be transferred.

Step S15- (3) (PDC reset (PRST ON))
Subsequently, in order to perform the PDC reset operation, the signal PRST is selected ('H' level), the MOS transistor 71 is turned on, the current (3) in the figure is generated, and the node N1b of the PDC is set to the power supply potential (ie, 'H' level).

Step S15- (4) (Sense (PDC confirmation))
Subsequently, the signal SEN1 is selected ('H' level) to turn on the MOS transistor 80.

  At this time, if the data transferred from the node N12 (TDC) is '0' data, the potential of the node N1b maintains the 'H' level.

  On the other hand, when the data transferred from the node N12 (TDC) is '1' data, the potential of the node N1b changes from 'H' level to 'L' level.

<2-6. Cell current measurement (I cell Monitor)>
Next, a cell current measurement operation (I cell monitor) of the sense unit SU according to the first embodiment will be described with reference to FIG.

Step S16- (1) (set)
First, the current (1) shown in the figure is supplied, the current Icell is supplied to the bit line BL through the signal terminal COM, and all are selected.

Step S16- (2) (Icell (off))
Subsequently, the transistor 75 is not selected, the transistor P75 is selected, and the current (2) which is the cell current Icell (Ioff) is supplied, so that all are not selected.

Step S16- (3) (Serial write data 1)
Subsequently, the signal CSL is selected and the transistors 65 and 66 are turned on to transfer the write data 'H' and 'L' from the data lines I / O and I / On to the PDC, and the node N1b is set to the 'H' level. The node N1a is set to the “L” level state.

Step S16- (4) (Icell Monitor)
Subsequently, the latch data is transferred from the PDC to the node N12 (TDC), and the cell current is detected.

  First, in the case of the measurement target bit, with the transistor P75 turned on and the transistor 76 turned off, the signal REG is selected to turn on the transistor 74, and the current (4) in the figure is generated. At this time, the node N1b of the PDC is at the 'H' level, and the node N1a is at the 'L' level.

  On the other hand, in the case of a bit not to be measured, the current (4) is not generated because the signal REG is selected and the transistor 74 is turned on with the transistors P75 and 76 turned off. At this time, the node N1b of the PDC is at the 'L' level, and the node N1a is at the 'H' level.

Step S16- (5) (Serial write data 0)
Subsequently, the signal CSL is selected, the transistors 65 and 66 are turned on, the write data 'L' and 'H' are transferred from the data lines I / O and I / On to the PDC, and the node N1b is set to the 'L' level. The node N1a is set to the “H” level state.

  Thereafter, even when the write data is '1' data, the cell current can be detected in the same manner as described above.

<3. Effect>
According to the semiconductor memory device and the operation thereof according to the first embodiment, at least the following effect (1) can be obtained.

(1) The peak current can be reduced.
As described above, the PMOS transistors P11 and P12 are AND-connected to the latch circuits 68 and 69 of the semiconductor memory device according to the first embodiment, and the current potential signal SAPG is supplied to the gate.

  Therefore, during the data read operation, the switching current i (PMOS) of the PMOS transistor constituting the inverters 69 and 68 is controlled to reduce the switching current i (PMOS) and the on-current i (NMOS) of the NMOS transistor 79. it can. As a result, the peak current at the time of charging the latch node N1b can be reduced. For example, the current potential signal SAPG can suppress the peak current to about 1/5. Furthermore, power drop can be reduced.

  For example, as shown in FIG. 5, when the current (5) is generated, the node N1b of the PDC is inverted from the ‘H’ level to the ‘L’ level. In this way, the PDC takes in and latches data at either the ‘L’ level or the ‘H’ level corresponding to the potential of the even bit line BLi. At this time, the current potential signal SAPG is given to the gates of the PMOS transistors P11 and P12 that are AND-connected to the latch circuits 68 and 69, and the switching current i (PMOS) of the PMOS transistors constituting the inverters 69 and 68 is controlled. it can.

(2) The occupied area can be reduced, which is advantageous for miniaturization.
In addition, since the switching current i (PMOS) can be reduced by the current control by the PMOS transistors P11 and P12, the gate length (L) of the PMOS transistors P11 and P12 and the gate width (W) of the NMOS transistor 79 are set. It is also possible to make it thinner.

  Therefore, the occupied area can be reduced, which is advantageous for miniaturization.

[Second Embodiment (an example further including a cache unit)]
Next, a semiconductor memory device according to the second embodiment will be described. The second embodiment relates to an example further including a cache unit. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example>
First, a configuration example of the sense unit SU according to the second embodiment will be described with reference to FIG.

  As shown in the figure, the sense unit SU according to the second embodiment is different from the first embodiment in that it further includes a cache unit 11B in addition to the sense unit 11A.

  The cache unit 11B includes a data cache (SDC, SDCn) and transistors 71-2, 72-2, and N22.

  The data cache (SDC, SDCn) includes inverters 68-2 and 69-2 and PMOS transistors P21 and P22. Inverters 68-2 and 69-2 are constituted by PMOS transistors and NMOS transistors not shown. The input and output of the inverter circuit 68-2 are latch-connected by being connected to the output and input of the inverter 69-2, respectively. The source of the PMOS transistor P21 is connected to the internal power supply voltage VDD, the drain is connected to the control terminal of the inverter 68-2 (the source of the PMOS transistor constituting the inverter 68-2), and the current potential signal LAT2n is applied to the gate. . The source of the PMOS transistor P22 is connected to the internal power supply voltage VDD, the drain is connected to the control terminal of the inverter 69-2 (the source of the PMOS transistor constituting the inverter 69-2), and the current potential signal SEN2n is applied to the gate. .

  One end of the current path of the transistor 71-2 is connected to the ground power supply voltage, the other end of the current path is connected to the node N2a of the data cache, and a signal PRST2 is applied to the gate.

  One end of the current path of the transistor 72-2 is connected to the node N2b of the data cache, the other end of the current path is connected to the node N12 (TDC), and the signal BLC2 is supplied to the gate.

  One end of the current path of the transistor N22 is connected to the PDC of the sense unit 11A, the other end is connected to the SDC of the cache unit 11B, and the sense unit 11A and the cache unit 11B are switched and connected according to the signal P2S applied to the gate. To do.

<Operation of Sense Unit SU>
Next, each operation of the sense unit SU according to the second embodiment will be described. In this example, the cache unit 11A is further provided as described above. Therefore, the description of the overlapping operation in the sense unit 11A is omitted.

<Data read operation (Read)>
First, the data read operation of the sense unit SU according to the second embodiment will be described with reference to FIG. Here, a case where the even bit line BLi is the selected bit line BL will be described as an example. At this time, the voltage of the odd-numbered bit line BL (i + 1) is charged to the non-selection voltage (voltage VDD) during the read operation.

Step S21- (1) (BL charge)
First, similarly, a current I (1) in the figure is generated to charge the potential of the bit line BL. At this time, it is assumed that the potential of the latch node 1Nb is at the “H” level.

Step S21- (2) (BL transition wait)
Subsequently, similarly, the potential of the gate signal BLCCAMP of the transistor 81 is not selected (VSS), the transistor 81 is turned off, and the process waits until the potential of the bit line BL transitions.

Step S21- (3) (Charge share sense)
Subsequently, similarly, the node N12 (TDC) and the bit line BL are brought into conduction to cause charge transfer.

  That is, when the NAND string 15 is conductive, the node N12 (TDC) transitions from the voltage VDD to, for example, zero potential ('L'). On the other hand, when the NAND string 15 is non-conductive, the potential of the node N12 maintains the voltage VDD ('H').

Step S21- (4) (SDCn HiZ)
Subsequently, the gate of the transistor 71-2 is selected, the current path of the transistor 71-2 is made conductive, and the current current I (4) in the figure is generated.

  At this time, the gate signals of the PMOS transistors P11, P12, P21, and P22 in the PDC and SDC are controlled, and the current i (PMOS) in the PDC and SDC is controlled. Further, the gate signals of the PMOS transistors P21 and P22 in the SDC are selected, and the node N2b of the SDC is set to the H level.

Step S21- (5) (PRST)
Subsequently, similarly, the current I (5) in the figure is generated to charge the dynamic data cache (DDC). In this case, similarly, the gate signals of the PMOS transistors P11, P12, P21, and P22 in the PDC and SDC are controlled, and the current i (PMOS) in the PDC and SDC is controlled.

Step S21- (6) (TDC => PDC)
Subsequently, a similar sensing operation is performed, and the potential of the node N12 (TDC) is taken into the PDC. In this case as well, the gate signals of the PMOS transistors P11, P12, P21, and P22 in the PDC and SDC are controlled, and the current i (PMOS) in the PDC and SDC is controlled.

Step S21- (7) (P2S gate open)
Subsequently, the signal P2S is selected (VSG) to select the transistor N22, the current (7) is generated, and the latch data of the PDC is transferred to the SDC. At this time, the gate signals of the PMOS transistors P11, P12, P21, and P22 in the PDC and SDC are controlled, and the current i (PMOS) in the PDC and SDC is controlled.

  As a result, for example, 'H' level latched at the node N1b of the PDC and 'L' level latch data latched at the node N1a become 'H' level at the node N2b and 'L' level at the node N2a. Transferred as latch data.

Step S21- (8) (SDC, SDCn determination)
Subsequently, the gate signals LAT2n, SEN2n, and PRST2 are not selected (L level), while the gate signal SAPG is selected (H level) and the current i (PMOS) in the PDC is controlled, thereby latching the SDC latch data. To confirm.

Step S21- (9) (IO transfer)
Subsequently, when the signal CSL is selected, a current (9) is generated, and data held in the PDC is transferred to the signal line I / O and the signal line I / On via the transistors 65 and 66.

<Data write operation (Program)>
Next, the data write operation of the sense unit SU according to the second embodiment will be described with reference to FIG. Here, similarly, a case where the even bit line BLi is the selected bit line BL will be described as an example.

Step S22- (1) (80hrst)
First, the gate of the transistor 71-2 is selected, the current path of the transistor 71-2 is made conductive, and the current I (1) in the figure is generated. At this time, it is assumed that the potential of the latch node 1Nb is at the “H” level.

Step S22- (2) (Program data load)
Subsequently, write data is loaded into the cache SDC from the data lines I / O and I / On.
As shown as current (2) in the drawing, when a command (for example, CMD85h) is given from the host to the control unit 9, the gate signal CSL is selected and the signal lines I / O, Write data ('H' or 'L' level) transferred from the I / On is stored in the SDC.

Step S22- (3) (Program data TDS set / PDC reset)
Subsequently, the data held in the PDC is set in the node 12 (TDC). As shown in the figure, the gate signals PRST1 and BLC2 are selected to turn on the transistors 72-1 and 71-2, generate a current (3), and set write data to the node 12 (TDC).

  At this time, the gate signal SAPG of the PMOS transistors P11 and P12 in the PDC is controlled, and the current i (PMOS) in the PDC is controlled.

Step S22- (4) (Program data PDC set)
Subsequently, the gate signal SEN1 is selected (H level), the current (4) is generated, and the write data of the node 12 (TDC) is set in the PDC.

<Write verify operation (PVFY)>
Next, a write verify operation of the sense unit SU according to the second embodiment will be described with reference to FIG. In the write verify operation, it is determined whether or not the writing is completed according to the data held in the PDC. Specifically, when the data held in the PDC is at the “L” level, it is determined that the data writing is complete, and when it is at the “H” level, it is determined that the data writing operation is not complete, and is determined to be complete. The data write operation and write verify operation are repeated until the data is written.

  Here, similarly, a case where the even bit line BLi is the selected bit line BL will be described as an example.

Step S23- (1) (Program bias)
First, when writing data to the memory cell transistor MT, the signals BLC1 and BLCCLAMP are selected ('H' level) to turn on the transistors 72-1 and 81. As a result, the current (1) in the drawing flows, the data held in the PDC is transferred to the even bit line BLi, and desired data writing is performed.

Step S23- (2) (BL charge)
First, similarly, the current (2) in the figure is generated to charge the potential of the bit line BL. At this time, the potential of the latch node 1Nb is assumed to be 'L' level, and the potential of the latch node 1Na is assumed to be 'H' level.

Step S23- (3) (BL transition wait)
Subsequently, the potential of the gate signal BLCCAMP of the transistor 81 is not selected (VSS), the transistor 81 is turned off, and the process waits until the potential of the bit line BL transitions.

Step S23- (4) (Charge share sense)
Subsequently, the potential of the gate signal BLPRE of the transistor 76 is not selected (VSS), and the potential of the gate signal BLCCAMP of the transistor 81 is selected (Vsen), so that the node N12 (TDC) and the bit line BL are made conductive. This causes the charge transfer.

The node N12 (TDC) when writing and verifying the “1” data is charged with the “L” level potential.
When the potential of the “L” level is charged to the node N12 (TDC) when the “0” data is written and verified, the above “0” data writing is determined to be a failure. Therefore, the reprogramming in step S21- (1) is performed again.
If the node N12 (TDC) at the time of writing and verifying the “0” data is charged with the “H” level potential, it is determined that the “0” data writing is successful (pass). Therefore, the reprogramming in step S21- (1) is not performed.
Step S23- (4) (TDC => PDC)
Subsequently, similarly, the gate signal SEN1 of the transistor 80 is set to the “H” level, and a sensing operation for capturing the potential of the bit line BL (TDC) into the primary data cache PDC is performed. Similarly, the data charged in the node N12 (TDC) by the above step S23- (3) has the following relationship, respectively.

When the node N12 (TDC) is charged with the “L” level when the “1” data is written and verified, the transistor 79 is not turned on and the data is not taken into the PDC. Therefore, the data latched at the node N1b is not inverted.
When the node N12 (TDC) is charged with the “L” level when the “0” data is written and verified, the transistor 79 is not turned on and the data is not taken into the PDC. Therefore, since the data latched at the node N1b is not inverted and remains at the “H” level, the “0” data write is determined to be a failure. Therefore, it is subject to reprogramming.
When the “0” data is written and verified, if the “L” level is charged in the node N12 (TDC), the transistor 79 becomes conductive. Therefore, when the gate signal SEN1 of the transistor 80 is selected, the current (4) in the figure flows, and the data at the “L” level of the node N12 (TDC) is taken into the PDC. Therefore, the data “H” level latched at the node N1b is inverted to the “L” level, and the “0” data write is determined to be successful (pass). In this case, rewriting is not performed.
These operations are continued until it is determined that the data writing is successful (pass).

<Data erase / erase verify operation (ERASE / EVFY)>
Next, a data erase / erase verify operation of the sense unit SU according to the second embodiment will be described with reference to FIG.

Step S24- (1) (SABL = VDD)
First, similarly, in order to improve the cut-off characteristics of the MOS transistors 6a and 6c so that the high voltage of 20V related to the data erasure is not transmitted to the sense unit SU, the gate signals BLPRE and the signals BLCCLAMP of the transistors 76 and 81 are improved. Is set to the “H” level, a current (1) is supplied, and the potential at the source end of the MOS transistor 81 is set to the voltage VDD.

Step S24- (2) (TDC = VDD)
Subsequently, the signal BLCCLAMP and the signal BLPRE are selected ('H' level), the MOS transistors 76 and 81 are turned on, and the current (2) in the figure is passed, whereby the potential of the node N12 (TDC) is set to the internal power supply. The voltage is VDD.

Step S24- (3) (TDC => PDC)
Subsequently, the potential of the node N12 (TDC) is taken into the primary data cache PDC. The signal SEN1 is set to the “H” level, the current (3) in the figure is supplied, and the data for setting the node N1b to the “H” level and the node N1a to the “L” level is latched.

<Erase verification (even)>
Next, the erase verify operation in the above configuration will be described. The erase verify operation was alternately performed on the even bit line BLi and the odd bit line BL (i + 1), and the write data of the memory cell transistor MT could be erased on both the even bit line BLi and the odd bit line BL (i + 1). When confirming the above, the erase verify operation is completed. Specifically, when the data held in the PDC after the erase verify is at the “L” level, the control unit 8 determines that the erase verify has been completed based on information from the fail bit detection circuit 11-1.

  First, the erase verify operation of the even bit line BLi (even) will be described.

Step S24- (4) (SABL charge)
When the signal BLCCLAMP and the signal BLPRE are selected ('H' level) and the MOS transistors 76 and 81 are turned on, the current (4) flows, and the potential of the node N12 (TDC) is set to the voltage VDD.

Step S24- (5) (BL transition wait & TDC charge)
Subsequently, the potential of the gate signal BLCCAMP is deselected (VSS), the transistor 81 is turned off, the process waits until the potential of the bit line BL transitions, the signal BLPRE is selected (Vsg), the transistor 76 is turned on, and the node N12 (TDC) and the internal power supply voltage are made conductive to charge node N12 (TDC).

Step S24- (6) (Charge share sense (even))
Subsequently, the potential of the bit line BL is transferred to the node N12 (TDC). The signal BLPRE is not selected (VSS), and the transistor 76 is turned off. The signal BLCCLAMP is selected (Vsenev), and the even bit line BLi and the node N12 (TDC) are electrically connected. If all the memory cell transistors MT connected to the even bit line BLi are in the erased state, the potential of the even bit line BLi is set to the voltage VDD corresponding to the “H” level even after charge sharing ( Erase verify pass (pass)). On the other hand, if not all in the erased state, even after charge sharing, the potential of the even-numbered bit line BLi corresponds to the “L” level (erase verify fail (fail)).

Step S24- (7) (REG = H)
Subsequently, the signal REG is selected to turn off the DDC. At this time, it is assumed that the node N1b of the PDC is at the “L” level and the node N1a is at the “H” level.

Step S24- (8) (PDC Reset)
Subsequently, the signal PRST1 is selected to generate a current (8), the node N1b is set to the “H” level, the node N1a is set to the “L” level, the latch data is inverted, and the latch data of the PDC is reset.

Step S24- (9) (SEN = H (Sense))
Subsequently, the signal SEN1 is selected (H level), the transistor 80 is turned on, and a sensing operation for capturing the potential of the node N12 (TDC) into the PDC is performed.

  At this time, when the node N12 (TDC) is set to the “H” level and the erase verify pass is performed, the MOS transistor 79 is turned on and the signal REG is selected (the “H” level), thereby holding the PDC. The data transitions from the “H” level to the “L” level.

  On the other hand, when the node N12 (TDC) is set to the 'L' level and the erase verify fails (fail), the MOS transistor 79 is turned off. Therefore, even if the signal REG is selected ('H' level), the data held in the PDC remains at the 'H' level.

<Erase verification (odd)>
Next, the erase verify operation of the odd bit line BLi (odd) will be described.

Step S24- (10) (SABL charge)
First, the signal BLCCLAMP and the signal BLPRE are selected, the MOS transistors 76 and 81 are turned on, the current (10) is supplied, and the potential of the node N12 (TDC) is set to the voltage VDD.

Step S24- (11) (BL transition wait & TDC charge)
Subsequently, the potential of the gate signal BLCCAMP is deselected (VSS), the transistor 81 is turned off, the process waits until the potential of the bit line BL transitions, the signal BLPRE is selected (Vsg), the transistor 76 is turned on, and the node N12 (TDC) and the internal power supply voltage are made conductive to charge node N12 (TDC) to internal power supply voltage VDD.

Step S24- (12) (Charge share sense (even))
Subsequently, a sensing operation for capturing the potential of the node N12 (TDC) into the PDC is performed.

  At this time, when the node N12 (TDC) is set to the 'H' level and the erase verify pass is performed, the MOS transistor 79 is turned on, and the data held in the PDC changes from the 'H' level to the 'L' level.

  On the other hand, when the node N12 (TDC) is set to the 'L' level and the erase verify fails (fail), the MOS transistor 79 is turned off. Accordingly, the data held in the PDC remains at the “H” level.

<Erase verify operation>
Next, calculation for erase verify of even and odd bit lines will be described.

Step S24- (13) (EVFY even & odd calculation)
First, the signal BLCCLAMP and the signal BLPRE are not selected (VSS), and the transistors 76 and 81 are turned off. By selecting the signal REG (VDD) and setting it to the internal power supply voltage (VSS), the current (13) in the figure is passed through the DDC, and the potential of the node N12 (TDC) is discharged.

  At this time, the calculation can be performed as follows according to the potential relationship of the node N12 (TDC).

  In the case of the 'H' level, the erase verify of the even bit line (even) is passed ('H' level), and the erase verify of the odd bit line (odd) is passed ('H'). Level).

  In the case of the 'L' level, even bit line (even) erase verify passes ('H' level) and odd bit line (odd) erase verify fails ('L'). Level).

  In the case of the “L” level, the erase verify of the even bit line (even) fails (“L” level), and the erase verify of the odd bit line (odd) passes (“H”). Level).

  In the case of the “L” level, the erase verify of the even bit line (even) fails (“L” level), and the erase verify of the odd bit line (odd) fails (“L”). Level).

Step S24- (14) (PDC Reset)
Subsequently, PRST is selected (H), the transistor 71 is turned on and a current (14) is supplied, the node N1b is set to the “H” level, the node N1a is set to the “L” level, the latch data is inverted, and the latch data of the PDC To reset.

Step S24- (15) (Sense)
Subsequently, SEN1 is selected (H), the transistor 80 is turned on, a current (15) is supplied, and the potential of the PDC is sensed.

  At this time, the calculation can be performed as follows according to the potential relationship of the PDC.

  In the case of the 'L' level, even bit line (even) erase verify is passed ('H' level) and odd bit line (odd) erase verify is passed ('H'). Level).

  In the case of “H” level, even bit line (even) erase verify passes (“H” level) and odd bit line (odd) erase verify fails (“L”). Level).

  In the case of the “H” level, the erase verify of the even bit line (even) fails (“L” level), and the erase verify of the odd bit line (odd) passes (“H”). Level).

  In the case of the “H” level, the erase verify of the even bit line (even) fails (“L” level), and the erase verify of the odd bit line (odd) fails (“L”). Level).

Step S24- (0) (Batch detection (serial mode))
Subsequently, collective detection (serial mode) for making the above determination will be described. The batch detection is an operation for batch detection that determines whether or not an erased state is set.

  First, the signal CSL is not selected ('L' level), and the MOS transistors 65 and 66 are turned off.

  Subsequently, the signal CHK1 is selected to turn on the transistor 78, and a current (0) in the drawing is supplied. Based on the voltage relationship of the terminal COM at this time, it is determined whether or not the memory cell transistor MT is in the erased state. . In this example, it is assumed that when the PDC (node N1b) is at the “H” level, the erase verify is failed (fail).

  At this time, if the terminal COM is kept at the “H” level, an erase verify pass is made. On the other hand, if the terminal COM changes from the “H” level to the “L” level, an erase verify failure (fail) occurs.

<2-5. NOT operation>
Next, the NOT operation of the sense unit SU according to the second embodiment will be described using FIG. The NOT operation is performed by inverting the data held in the PDC (node N1b). Step S25- (1) (TDC => VSS)
First, the signal BLPRE is selected ('H' level), the MOS transistor 76 is turned on, and the current (1) in the figure is generated between the node N12 (TDC) and the internal power supply voltage (VSS). By this step, the node N12 (TDC) is set to the ground power supply voltage VSS level.

Step S25- (2) (PDC => TDC)
Subsequently, the signal REG is selected (Vsg), the transistor 74 is turned on, the current (2) in the figure is generated, and the data “0” or “1” stored in the PDC is supplied to the node N12 (TDC). Let it be transferred.

Step S25- (3) (PDC reset (PRST ON))
Subsequently, in order to perform the PDC reset operation, the signal PRST is selected ('H' level), the MOS transistor 71 is turned on, the current (3) in the figure is generated, and the node N1b of the PDC is set to the power supply potential (ie, 'H' level).

Step S25- (4) (Sense (PDC confirmation))
Subsequently, the signal SEN1 is selected ('H' level) to turn on the MOS transistor 80.

  At this time, if the data transferred from the node N12 (TDC) is '0' data, the potential of the node N1b maintains the 'H' level.

  On the other hand, when the data transferred from the node N12 (TDC) is '1' data, the potential of the node N1b changes from 'H' level to 'L' level.

<Data transfer operation from PDC to SDC>
Next, the data transfer operation from the PDC to the SDC of the sense unit SU according to the second embodiment will be described with reference to FIGS. 17 and 18. This description will be made according to the timing chart shown in FIG. Here, a path (Read transfer path, ProgData transfer path) for transferring the data at the “H” level latched at the node N1b of the PDC to the node N2b of the SDC will be described.

<Read transfer path>
Step S26- (1)
First, at time t1, the signals LAT2n and SEN2 are selected (L level), and 'H' level data is set in the node N2b of the SDC.

Step S26- (2)
Subsequently, at time t2, the signal PRST is selected and a current (1) is generated.

Step S26- (3)
Subsequently, at time t3, the signal P2S is selected to turn on the transistor N22, and a data read (Read) path for transferring the data at the “H” level latched at the node N1b of the PDC to the node N2b of the SDC. Form.

<ProgData transfer path>
Step S26- (4)
First, the signal SEN1 is selected to turn on the transistor 80.

Step S26- (5)
Subsequently, at time t5, the signal PRST2 is not selected (L level), and the transistor 71-2 is turned off.

Step S26- (6)
Subsequently, the “H” level is transferred by the turned off transistor 71-2, and the NMOS transistor in SDC and SDCn is turned on, so that a current (6) is generated and the “L” level is fixed.

Step S26- (7)
Subsequently, at time t7, the signal SEN2 is not selected ('H' level), the transistor P22 is turned off, a ProgData transfer path is formed, and the transfer data is latched by the SDC.

Step S26- (8)
Subsequently, at time t8, the signal LAT2n is not selected ('H' level), the transistor P21 is turned off, and the latched data is set.

Step S26- (9)
Subsequently, at time t9, the signal P2S is not selected ('L' level), the transistor N22 is turned off, and the formed ProgData transfer path is closed.

<Effect>
As described above, according to the semiconductor memory device of the second embodiment, at least the same effect as the above (1) can be obtained.

  In addition to the sense unit 11A, the sense unit SU according to the second embodiment further includes a cache unit 11B having inverters 68-2 and 69-2 to which PMOS transistors P21 and P22 are AND-connected.

  The source of the PMOS transistor P21 is connected to the internal power supply voltage VDD, the drain is connected to the control terminal of the inverter 68-2 (the source of the PMOS transistor constituting the inverter 68-2), and the current potential signal LAT2n is applied to the gate. . The source of the PMOS transistor P22 is connected to the internal power supply voltage VDD, the drain is connected to the control terminal of the inverter 69-2 (the source of the PMOS transistor constituting the inverter 69-2), and the current potential signal SEN2n is applied to the gate. .

  Therefore, by separately controlling the current potential signals SEN2N and LAT2n, the switching current i (PMOS) of the transistor (PMOS) constituting the SDC can be limited, and the charging of the SDC can be blunted.

  More specifically, as shown in the upper part of FIG. 19 and FIG. 20, for example, at the time of step S21- (4) in the data read operation, the current signal SEN2N in the SDC is controlled to control the current in the SDC. i (PMOS) is controlled.

  For this reason, as shown in the lower part of FIGS. 19 and 20, the switching current i (PMOS: I2) of the transistor (PMOS) constituting the SDC is further reduced and limited (I2 <I1), thereby slowing the charging of the SDC. Can be made.

  As a result, it is advantageous in that the peak current can be further reduced and the power supply voltage drop can be reduced.

  Thus, this example can be applied as necessary.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 11 ... Sense amplifier, SU ... Sense unit, 6 ... MOS transistor group, PDC, PDCn ... Primary data cache, P11, P12 ... PMOS transistor, DDC ... Dynamic data cache, SDC ... Data cache

Claims (5)

A memory cell array in which a plurality of memory cells are arranged in rows and columns;
A plurality of even bit lines arranged in the even number of columns;
A plurality of odd bit lines arranged in the odd number of columns adjacent to the even number of columns;
A plurality of sense amplifiers, each of which is selectively connected to the odd bit lines and the even bit lines,
First and second inverter circuits latch-connected to hold data in the first and second nodes;
A current control signal is applied to the gate, one end of the current path is connected to the first power supply voltage, and the other end of the current path is connected to the control terminals of the first and second inverter circuits, respectively. A semiconductor memory device. The semiconductor memory device according to claim 1, wherein the sense amplifier further includes a cache unit that is electrically connected to the sense unit and latches data held by the first and second inverter circuits. The cache unit includes third and fourth inverter circuits that are latch-connected to hold data in the first and second nodes;
A current control signal is applied to the gate, one end of the current path is connected to the first power supply voltage, and the other end of the current path is connected to the control terminals of the third and fourth inverter circuits, respectively. The semiconductor memory device according to claim 2. The first and second nodes are electrically connected to complementary first and second data lines,
The sense unit further includes fifth and sixth transistors having current paths connected in series between the second data line and a second power supply voltage, and the gate of the fifth transistor is connected to the first data line. 4. The verification result is detected by a terminal connected to one end of a current path of the fifth transistor by selecting a gate signal of the sixth transistor connected thereto. 5. Semiconductor memory device. 5. The semiconductor memory device according to claim 1, wherein current control is performed to loosen a current control signal applied to the gates of the first and second transistors during a data read operation of the memory cell array.

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