JP2012134423A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which the operating speed of a bipolar transistor can be accelerated.SOLUTION: A semiconductor device comprises an n-type collector layer 20 provided above a single crystal Si substrate 1, an SiOfilm 21 provided on a periphery of a surface of the collector layer 20, and a p-type base layer 30 that covers the SiOfilm 21 and is bonded to the center portion of the surface of the collector layer 20. The base layer 30 includes a single crystal SiGe film 31a provided on the center portion of the surface of the collector layer 20 and a single crystal Si film 35a stacked on the single crystal SiGe film 21 so as to cover the SiOfilm 21. Since a junction region 60 between the base layer 30 and the collector layer 20 is limited on the center portion of the surface of the collector layer 20, the junction area can be minimized, thereby reducing capacitance Cbetween the base layer and the collector layer.

Description

  The present invention relates to a method for manufacturing a semiconductor device including a bipolar transistor.

  As this type of prior art, for example, there is one disclosed in Patent Document 1. Such a reference discloses a bipolar transistor having a structure in which the collector layer side surface (that is, the bottom surface) of the base layer sandwiched between the collector layer and the emitter layer in a cross-sectional view is in contact with the collector layer. Yes. That is, Patent Document 1 discloses a bipolar transistor having a structure in which the junction region between the base layer and the collector layer is the entire bottom surface of the base layer.

JP-A-6-349841

Conventionally, bipolar transistors have been applied to various electronic devices (for example, wireless communication devices). In recent years, bipolar transistors capable of operating at higher speeds have been desired along with the great progress of wireless communication technology.
Accordingly, the present invention has been made in view of such circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can increase the operating speed of a bipolar transistor.

In order to solve the above problems, a method for manufacturing a semiconductor device according to one embodiment of the present invention is a method for manufacturing a semiconductor device including a bipolar transistor, the step of forming a first conductivity type collector layer on a substrate; A step of sequentially forming a SiGe film and a Si film on the collector layer to form a base layer having a structure in which the SiGe film and the Si film are stacked; and the SiGe film is more than the Si film. Removing the SiGe film from the peripheral portion of the collector layer while leaving the SiGe film on the central portion of the collector layer by performing an etching process on the base layer under conditions that are easily etched. Forming an insulating film on the substrate so as to be embedded between the peripheral portion of the collector layer and the Si film. Here, the “first conductivity type” is one of n-type and p-type, and the “second conductivity type” is the other of n-type and p-type. Moreover, as the “insulating film”, for example, a SiO ₂ film 21 described later corresponds.

With such a method, the junction (contact) region between the base layer and the collector layer can be limited to the center of the surface of the collector layer, and the area where the base layer and the collector layer are in contact (that is, between the BCs) Junction area) and the capacitance _CBC can be reduced.
The relationship of the following formulas (1) and (2) is established between the capacitance C _BC and the cutoff frequency fT and the maximum oscillation frequency fmax, which are indicators of the operation speed of the bipolar transistor. (1) As apparent from the equation, fT increases as C _BC is small. Further, (2) As apparent from the equation, the more C _BC is small (and the larger fT) fmax is increased.

Therefore, by reducing the capacitance C _BC, it is possible to increase the cut-off frequency fT and the maximum oscillation frequency fmax of the bipolar transistor, respectively. Therefore, a bipolar transistor that can operate at higher speed can be provided.
Further, in the method of manufacturing the semiconductor device, in the step of forming the base layer, the SiGe film is formed by an epitaxial growth method to form a SiGe film having a single crystal structure on the collector layer, In the step of forming the Si film by an epitaxial growth method to form a single crystal Si film on the single crystal SiGe film and etching the base layer, a dry process using ClF ₃ (chlorine trifluoride) is performed. The single crystal SiGe film may be removed from the periphery of the collector layer by etching. With such a method, it is possible to etch the SiGe film with high selectivity while suppressing the scraping of the Si film.

The method for manufacturing a semiconductor device may further include a step of forming an element isolation layer in a region of the substrate adjacent to the collector layer, and in the step of forming the base layer, the SiGe film may be epitaxially grown. The single crystal SiGe film is formed simultaneously with the formation of the polycrystalline SiGe film on the element isolation layer, and then the Si film is formed by an epitaxial growth method. At the same time as forming the film, a polycrystalline Si film is formed on the polycrystalline SiGe film, and the base layer is etched. In the step of etching, the polycrystalline Si film is formed by wet etching using TMAH (tetramethylammonium hydroxide). membranes are removed and subsequently, removing the polycrystalline SiGe film by dry etching using the ClF ₃ Rukoto may be characterized.

With such a method, at the time of wet etching using TMAH, it is possible to etch and remove the polycrystalline Si film with high selectivity while suppressing the shaving of the single crystal Si film. Thereby, the polycrystalline SiGe film can be exposed from under the polycrystalline Si film. Further, at the time of dry etching using ClF ₃ , the polycrystalline SiGe film can be etched and removed with high selectivity while suppressing the scraping of the single crystal Si film. Thereby, the side surface of the single crystal SiGe film is exposed, so that the single crystal SiGe film can be side-etched with high selectivity.

According to the present invention, the capacitance _CBC between the base layer and the collector layer of the bipolar transistor can be reduced, and the cutoff frequency fT and the maximum oscillation frequency fmax can be increased. Thereby, the operation speed of the bipolar transistor can be increased.

1 is a diagram illustrating a configuration example of a semiconductor device 100 according to an embodiment of the present invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof may be omitted.
FIG. 1A is a cross-sectional view showing a configuration example of a semiconductor device 100 according to an embodiment of the present invention. FIG. 1B is an enlarged view of a main part of the bipolar transistor 50 shown in FIG.

As shown in FIGS. 1A and 1B, the semiconductor device 100 includes, for example, a p-type single crystal silicon (Si) substrate 1 and a high concentration n-type buried layer formed on the single crystal Si substrate 1. The buried layer (n + layer) 3, the Si layer (that is, the epitaxial Si layer) 5 formed on the single crystal Si substrate 1 by the epitaxial growth method, and the n-type deep well layer (n -Layer) 7, deep trench isolation (DTI layer) for isolating the n-layer 7, and a bipolar transistor 50 formed in a region isolated by the DTI layer 10.
Among these, the DTI layer 10 includes, for example, a trench, a SiO ₂ film (silicon oxide film) 11 formed so as to cover the inner wall and bottom surface of the trench, and polycrystalline Si embedded in the SiO ₂ film 11. And a film 13.

Bipolar transistor 50 is formed on epitaxial Si layer 5, n-type collector layer 20 located on n − layer 7, and SiO ₂ film 21 formed on the periphery of the surface of collector layer 20. A base layer 30 covering the SiO ₂ film 21 and joining to the central portion of the surface of the collector layer 20, an SiO ₂ film 36 and a polycrystalline Si film 34 covering the base layer, and the SiO ₂ film 36 and the polycrystalline film And an emitter layer 40 connected to the base layer 30 through an opening formed in the Si film 37. Here, the base layer 30 is a p-type single crystal SiGe film 31 a provided on the center of the surface of the collector layer 20 and a p layer laminated on the single crystal SiGe film 31 a so as to cover the SiO ₂ film 21. In this bipolar transistor 50, a shallow trench isolation (STI layer) 15 is partially formed near the surface of the epitaxial Si layer 5 in this bipolar transistor 50. Yes. On this STI layer 15, a polycrystalline Si film 34 b for leading the base layer 30 onto the interlayer insulating film 51 (that is, an external base) is formed. An n-type impurity diffusion layer (n layer) 25 for connection to the collector layer 20 is formed in a region opposite to the collector layer 20 with the STI layer 15 interposed therebetween.
The surfaces of the polycrystalline Si film 34b, the n layer 25, and the emitter layer 40 are silicided, and a base electrode 46, a collector electrode 47, and an emitter electrode 48 are formed through the silicide layer 45, respectively. ing.

By the way, in this bipolar transistor 50, the junction (contact) region 60 between the base layer 30 and the collector layer 20 is limited to the central portion of the surface of the collector layer 20. An SiO ₂ film 21 is formed on the peripheral portion of the surface of the collector layer 20 so that the peripheral portion of the collector layer 20 is not in direct contact with the base layer 30. For this reason, compared with the case where the junction area | region of a collector layer and a base layer is the whole surface (namely, both center part and peripheral part) of a collector layer, the area (namely, junction area) of a junction area | region is reduced. The capacitance _CBC between the base layer and the collector layer can be reduced. Next, a method for manufacturing the semiconductor device 100 shown in FIGS. 1A and 1B will be described.

2 to 24 are process diagrams showing the method for manufacturing the semiconductor device 100 according to the embodiment of the present invention. In FIG. 2, first, an n + layer 3 is formed by ion-implanting an n-type impurity into a p-type single crystal Si substrate 1. The ion implantation conditions for forming this n + layer 3 are, for example, that the impurity species is arsenic (As), the implantation energy is 100 keV, and the dose is 5.0E + 15 / cm ² . Next, an epitaxial Si layer 5 is formed on the single crystal Si substrate 1. The thickness of the epitaxial Si layer 5 is 9500 mm, for example.

Then, the DTI layer 10 is formed on the epitaxial Si layer 5 and the single crystal Si substrate 1, and the STI layer 15 is formed on the epitaxial Si layer 5. Specifically, the DTI layer 10 forms a deep trench having a depth of, for example, 80000 mm from the surface of the epitaxial Si layer 5 to the inside of the single crystal Si substrate 1, and the SiO ₂ film 11 and the polycrystal are formed in the deep trench. It is formed by embedding the Si film 13. The STI layer 15 is formed by forming a shallow trench in the epitaxial Si layer 5 and embedding a SiO ₂ film in the shallow trench.

Next, an n − layer 7 is formed in a region of the epitaxial Si layer 5 that is element-isolated by the DTI layer 10. The ion implantation conditions for forming the n − layer 7 are, for example, that the impurity species is phosphorus (P), the implantation energy is 320 keV, and the dose is 6.0E + 12 / cm ² .
Next, as shown in FIG. 3, a SiO ₂ film 61 is formed on the single crystal Si substrate. The method for forming the SiO ₂ film 61 is, for example, CVD (Chemical Vapor Deposition), and the thickness thereof is, for example, 1000 mm. Next, as shown in FIG. 4, an n-type collector layer 20 is formed by partially ion-implanting n-type impurities into the epitaxial Si layer 5 by a photolithography technique and an ion implantation technique. The ion implantation conditions for forming the collector layer 20 are, for example, that the impurity species is phosphorus (P), the implantation energy is 330 keV, and the dose is 1.0E + 13 / cm ² .

Next, as shown in FIG. 5, a polycrystalline Si film 63 is formed on the SiO ₂ film 61. The method for forming the polycrystalline Si film 63 is, for example, CVD, and the thickness thereof is, for example, 1000 mm. Next, the polycrystalline Si film 63 is partially etched by a photolithography technique and an etching technique. Thereby, as shown in FIG. 6, the polycrystalline Si film 63 is removed from the collector layer 20 and the STI layers 15 on both sides thereof. Further, the polycrystalline Si film 63 is left on the other region.

Next, the SiO ₂ film 61 is etched using the polycrystalline Si film 63 as a mask. The etching of the SiO ₂ film 61 is performed by wet etching using a hydrofluoric acid (HF) solution, for example. As an example, a dilute HF aqueous solution (49% HF: H 2 O = 1: 99) is used. Thereby, as shown in FIG. 7, the surface of the collector layer 20 and the surfaces of the STI layers 15 on both sides thereof are exposed.

Next, as shown in FIG. 8, the SiGe film 31 and the Si film 33 doped with boron in-situ (that is, a film forming process) are sequentially formed on the entire upper surface of the single crystal Si substrate by, for example, an epitaxial growth method. To do.
Here, the film formed by the epitaxial growth method inherits the underlying crystal structure. Therefore, the SiGe film 31 is epitaxially grown on the epitaxial Si layer 5 to be formed into a single crystal SiGe film 31a, and is formed into a polycrystalline SiGe film 31b on the STI layer 15 or on the polycrystalline Si film. Similarly, the Si film 33 is formed as a single crystal Si film 33a on the single crystal SiGe film 31a, and is formed as a polycrystal Si film 33b on the polycrystalline SiGe film 31b. The thickness of the single crystal SiGe film 31a is, for example, 300 mm, and the thickness of the polycrystalline SiGe film 31b is, for example, 300 mm. Moreover, the thickness of the single crystal Si film 33a is, for example, 500 mm, and the thickness of the polycrystalline Si film 33b is, for example, 500 mm. Note that boron doped in the Si film 33 is diffused into the single crystal SiGe film 31a in a process accompanied by a later heat treatment.

  Next, the polycrystalline Si film 33b is etched and removed by wet etching using a TMAH (tetramethylammonium hydroxide) aqueous solution. Here, in the wet etching using the TMAH aqueous solution, the etching rate for the polycrystalline Si film is larger than the etching rate for the single crystal Si film. According to experiments conducted by the present inventors, for example, with respect to the etch rate of a TMAH aqueous solution having a temperature of 70 ° C. and a concentration of 20%, the etch rate for the polycrystalline Si film is 83.7 Å / sec. The etch rate for the Si film was 58.1 K / sec.

  Therefore, in this step, for example, wet etching for 6.9 sec is performed using the above-described TMAH aqueous solution (70 ° C., 20%). As a result, as shown in FIG. 9, the polycrystalline Si film can be removed from the polycrystalline SiGe film 31b while leaving about 100% of the single-crystal Si film 33a. That is, from the difference in the etching rate, the polycrystalline SiGe film can be completely removed while the single crystal Si film 33a can be left about 100%.

Next, the polycrystalline SiGe film 31b is etched and removed by dry etching using ClF ₃ , and the single crystal SiGe film 31a is also side-etched. Here, in dry etching using ClF ₃ , Ge serves as a catalyst to accelerate etching, and therefore the etching rate for the SiGe film is much higher than the etching rate for the Si film. Moreover, the etch rate of SiGe does not depend much on its crystal structure. That is, the single crystal SiGe film 31a and the polycrystal SiGe film 31b are etched with higher selectivity than the single crystal Si film 33a and the polycrystal Si film 63.
For example, for the etch rate when the pressure of ClF ₃ in the vacuum chamber is 0.02 mbar, the etch rate for the Si film is 0.16 Å / sec, whereas the etch rate for the SiGe film is 333 Å / sec. is there.

Therefore, in this step, for example, 9 seconds of dry etching is performed under the above conditions (ClF ₃ , 0.02 mbar). As a result, as shown in FIG. 10, the polycrystalline SiGe film 31b can be almost completely removed without substantially removing the single-crystal Si film 33a, and further exposed by removing the polycrystalline SiGe film 31b. Both side surfaces of the single-crystal SiGe film 31a to be cut can be cut by about 2600 mm in the horizontal direction (that is, the side direction). By this side etching, a gap 65 having a height (for example, 300 mm) corresponding to the thickness of the single crystal SiGe film 31a is formed between the peripheral portion of the collector layer 20 and the single crystal Si film 33a.

Next, as shown in FIG. 11, a SiO ₂ film 21 is formed on the entire upper surface of the single crystal Si substrate. The formation method of the SiO ₂ film 21 is, for example, CVD, and the thickness thereof is, for example, 1000 mm. As a result, the gap is filled with the SiO ₂ film 21.
Next, an anisotropic dry etching process such as RIE (Reactive Ion Etching) is performed on the entire upper surface of the SiO ₂ film 21. That is, the SiO ₂ film 21 is etched back. Thus, as shown in FIG. 12, the SiO ₂ film 21 is removed from other regions while leaving the SiO ₂ film 21 under the single crystal Si film 33a (that is, on the periphery of the collector layer 20).

Next, as shown in FIG. 13, a Si film 34 doped with boron in-situ is formed on the entire upper surface of the single crystal Si substrate by, for example, an epitaxial growth method. Here, the Si film 34 is epitaxially grown on the single crystal Si film 33a to be formed into a single crystal Si film 34a, and is formed on the STI layer 15 and the polycrystalline Si film 63 into a polycrystalline Si film 34b. The thickness of the single crystal Si film 34a is, for example, 300 mm, and the thickness of the polycrystalline Si film 34b is also, for example, 300 mm.
Note that the base single-crystal Si film 33a and the single-crystal Si film 34a formed in this step have the same crystal structure, and the single-crystal Si film 34a is an integral film with the base single-crystal Si film 33a. For this reason, in the following description, these are collectively referred to as a single crystal Si film 35a. The thickness of the single crystal Si film 35a is, for example, 400 mm (= 100 mm + 300 mm).

Next, as shown in FIG. 14, a SiO ₂ film 36 is formed on the entire upper surface of the single crystal Si substrate, and subsequently, a polycrystalline Si film 37 is formed on the SiO ₂ film 36. The formation method of the SiO ₂ film 36 is, for example, CVD, and the thickness thereof is, for example, 300 mm. The polycrystalline Si film 37 is formed by CVD, for example, and its thickness is, for example, 500 mm.

Next, as shown in FIG. 15, the polycrystalline Si film 37 is partially etched by a photolithography technique and an etching technique. Thereby, for example, an opening 67 exposing the SiO ₂ film 36 is formed in the polycrystalline Si film 37 immediately above the single crystal SiGe layer. Next, the SiO ₂ film 36 is etched using the polycrystalline Si film 37 in which the opening 67 is formed as a mask. The etching of the SiO ₂ film 36 is performed by wet etching using a dilute HF aqueous solution (49% HF: H 2 O = 1: 99), for example. Thereby, the single crystal Si film 35 a is exposed on the bottom surface of the opening 67.

Next, as shown in FIG. 16, a polycrystalline Si film 40 ′ is formed on the entire upper surface of the single crystal Si substrate so as to fill the opening 67. The method for forming the polycrystalline Si film 40 'is, for example, CVD, and the thickness thereof is, for example, 2500 mm. Next, n-type impurities are ion-implanted into the polycrystalline Si film 40 '. The ion implantation conditions are, for example, that the impurity species is phosphorus (P), the implantation energy is 20 keV, and the dose is 7.0E + 15 / cm ² .

Next, the polycrystalline Si film 40 'is partially etched by photolithography technique and etching technique. Thereby, as shown in FIG. 17, an emitter layer 40 made of a polycrystalline Si film is formed. Next, as shown in FIG. 18, the base layer 30 having a structure in which the single crystal SiGe film 31a and the single crystal Si film 35a are stacked and the emitter layer 40 formed thereon are covered, and other regions are covered. An exposed resist pattern 69 is formed above the single crystal Si substrate. Then, using the resist pattern 69 as a mask, the SiO ₂ film 36, the polycrystalline Si film 34b, and the polycrystalline Si film 63 are sequentially etched and removed.

Further, in FIG. 19, the SiO ₂ film 61 is etched and removed using the resist pattern 69 as a mask. As a result, as shown in FIG. 20, in the region not covered with the resist pattern, the surface of the DTI layer 10, the surface of the STI layer 15, and the surface of the epitaxial Si layer 5 are exposed. Next, the resist pattern 69 is removed.

Next, as shown in FIG. 21, a SiO ₂ film 38 is formed on the entire upper surface of the single crystal Si substrate by, eg, CVD. Then, n-type impurities are ion-implanted into the epitaxial Si layer 5 covered with the SiO ₂ film 38. The ion implantation conditions are, for example, that the impurity species is phosphorus (P), the implantation energy is 320 keV, and the dose is 6.0E + 12 / cm ² . Thus, an n layer 25 for collector connection is formed in the region surrounded by the STI layer 15 and the DTI layer 10 in the epitaxial Si layer 5.
Next, an SiO ₂ film (not shown) is formed on the entire upper surface of the single crystal Si substrate by, eg, CVD. Then, the SiO ₂ film is etched back. As a result, as shown in FIG. 22, sidewalls 39 made of SiO ₂ films are formed on the side surfaces of the base layer 30, the emitter layer 40, and the side surfaces of the polycrystalline Si film 34b serving as the external base.

  Next, as shown in FIG. 23, the surface of Si exposed from the sidewall 39 (that is, the surface of the emitter layer 40, the surface of the n layer 25, the surface of the polycrystalline Si film 34b) is silicided, respectively. A silicide layer 45 is formed. Then, as shown in FIG. 24, an interlayer insulating film 51 is formed on the entire upper surface of the single crystal Si substrate, and a contact hole 73 is formed in the interlayer insulating film 51. Then, for example, a metal film is buried in the contact hole 73 to form a base electrode, a collector electrode, and an emitter electrode, respectively. In this manner, the semiconductor device 100 shown in FIGS. 1A and 1B is completed.

As described above, according to the embodiment of the present invention, the junction (contact) region 60 between the base layer 30 and the collector layer 20 is limited to the central portion of the surface of the collector layer 20. Therefore, the junction area between the base layer and the collector layer can be reduced, and the capacitance _CBC between the base layer and the collector layer can be reduced. For example, compared to the case where the junction region is the entire surface of the collector layer, the junction area can be reduced by about 70%, and in that case, the capacitance _CBC can be reduced by about 70%.

As described above, the relationship between the equation (1) and the equation (2) is between the capacitor C _BC and the cutoff frequency fT and the maximum oscillation frequency fmax, which are indicators of the operation speed of the bipolar transistor 50, respectively. It holds, but as is apparent from equation (1), fT increases as C _BC is small. Further, (2) As apparent from the equation, the more C _BC is small (and the larger fT) fmax is increased. For this reason, the operation speed of the bipolar transistor 50 can be increased.

In the above-described embodiment, the case of the npn-type bipolar transistor 50 has been described. However, the present invention is not limited to the npn-type, and may be a pnp-type. The pnp bipolar transistor also has a similar structure in which the n-type and p-type are interchanged, so that the junction area between the base layer and the collector layer can be reduced and the capacitance C _BC can be reduced. It is possible to increase the speed.

1 Single-crystal Si substrate 3 High-concentration n-type buried layer (n + layer)
5 Epitaxial Si Layer 6 Japanese Patent Laid-Open Publication No. 7 n-type deep well layer (n-layer)
10 DTI layers 11, 21, 36, 38, 61 SiO ₂ film 13, 37 Polycrystalline Si film 15 STI layer 20 Collector layer 25 n-type impurity diffusion layer (n layer)
30 Base layer 31 SiGe film 31a Single crystal SiGe film 31b Polycrystalline SiGe film 33, 34 Si films 33a, 34a, 35a Single crystal Si films 33b, 34b, 40 ', 63 Polycrystalline Si film 39 Side wall 40 Emitter layer 45 Silicide Layer 46 Base electrode 47 Collector electrode 48 Emitter electrode 50 Bipolar transistor 51 Interlayer insulating film 60 Junction region 65 Void 67 Opening 69 Resist pattern 73 Contact hole 100 Semiconductor device

Claims (3)

A method of manufacturing a semiconductor device including a bipolar transistor,
Forming a first conductivity type collector layer on a substrate;
Forming a SiGe film and a Si film sequentially on the collector layer to form a base layer having a structure in which the SiGe film and the Si film are stacked;
By performing an etching process on the base layer under the condition that the SiGe film is more easily etched than the Si film, the SiGe film is left on the central portion of the collector layer, and the peripheral portion of the collector layer is left. Removing the SiGe film from:
And a step of forming an insulating film on the substrate so as to fill a gap between a peripheral portion of the collector layer and the Si film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of etching the base layer, the single crystal SiGe film is removed from the periphery of the collector layer by dry etching using ClF _3. . In the step of etching the base layer,
Removing the polycrystalline Si film by wet etching using TMAH;
The method of manufacturing a semiconductor device according to claim 2, wherein the polycrystalline SiGe film is removed by dry etching using the ClF ₃ .

Images