JP2012124479A - Semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package excellent in drop impact resistance.SOLUTION: A semiconductor package 1 includes a package substrate 7 having a core layer 9 containing an insulating resin 15. The insulating resin 15 comprises: an epoxy resin containing a biphenyl novolac type epoxy resin represented by a structure specified by the general formula where each of the positions specified by Rto Rindependently has a hydrogen atom, an alkyl group with the carbon number 1-6, an alkoxy group with the carbon number 1-6, or a halogen group; and a cured material of a resin composition containing a curing agent.

Description

  The present invention relates to a semiconductor package.

In recent years, as mobile devices become lighter, thinner, and smaller, semiconductor packages to be mounted are becoming smaller, thinner, and narrower in pitch. For this reason, solder bumps, which are electrodes for connecting the semiconductor package and the mother board, are miniaturized, and it is difficult to ensure the drop impact resistance.
Therefore, various methods for improving the drop impact resistance have been studied. The related prior art is shown below.

  Patent Document 1 discloses a technique for preventing a solder crack by avoiding stress concentration on a wiring / solder portion where bonding is weakened by drawing a wiring extending from an electrode pad on the outer periphery of the BGA (Ball Grid Array) to the inside. Is described. Further, Patent Document 2 describes a technique that makes it difficult for a drop impact to reach an electrical connection portion by concentrating strain deformation of the wiring board at the time of a drop impact on a concave portion or a slit portion provided on the wiring board. Yes. Further, Patent Document 3 describes a technique for preventing the wiring board from being destroyed during a drop impact by using a resin material that is difficult to break even during high-speed deformation for the wiring board.

Japanese Patent No. 3211746 JP 2001-326428 A Japanese Patent No. 3765210

As described above, as a technology aiming at improving the drop impact resistance so far, since the circuit board is also related to the mother board, a semiconductor package having excellent drop impact resistance has long been desired. Also did not happen.
The present invention has been made in view of such circumstances, and as a result of intensive studies, the present inventors have found a semiconductor package that improves drop impact resistance by devising a package substrate.
An object of the present invention is to provide a semiconductor package effective for improving the drop impact resistance.

Ｔ１：封止温度（℃）
Ｔ２：はんだバンプの融点（℃）
Ｅ_T2：はんだバンプの融点における絶縁樹脂の弾性率（ＭＰａ）
α（Ｔ）：Ｔ℃のときの絶縁樹脂の熱膨張係数（℃^-1） The present invention has the following aspects.
1. A package substrate having a core layer containing an insulating resin, at least one semiconductor element mounted on the package substrate and sealed with a sealing material, and a connection electrode for connecting the package substrate to a motherboard In the semiconductor package having the solder bump, the characteristic value A represented by the following formula (1) of the insulating resin is 1.4 MPa or less.

T1: Sealing temperature (° C)
T2: Melting point of solder bump (° C)
E _T2 : Elastic modulus of insulating resin at melting point of solder bump (MPa)
α (T): Thermal expansion coefficient of insulating resin at T ° C (° C ^-1 )

2. 2. In the formula (1), the characteristic value A is 1.4 MPa or less when 170 ≦ T1 ≦ 180 (° C.) and 200 ≦ T2 ≦ 230 (° C.). Semiconductor package.

  If this semiconductor package is used in mobile devices such as mobile phones and PDAs ((Personal Digital Assistants)), the drop impact resistance can be improved without applying special circuit design, processes and materials to the motherboard. , Its industrial value is great.

The perspective view for demonstrating the twist height of a semiconductor package, and the connection height of the solder bump of four corners of a semiconductor package Partial sectional view of a semiconductor device in an embodiment Arrangement diagram of solder bump and solder resist opening A plan view showing the relationship between the hole drilling position of the motherboard, the size of the motherboard, and the positions of the solder bump electrode pads arranged in a grid Sectional view for explaining conditions of drop impact test

  It is known that failures are concentrated on the solder bumps at the four corners of the semiconductor package during a drop impact. As a result of intensive studies, the present inventors have found that when the connection height of the solder bumps at the four corners of the semiconductor package is increased, the drop impact resistance is improved. That is, when the connection height of the solder bumps at the four corners of the semiconductor package is lowered, the drop impact resistance is lowered. This is because if the connection height of the solder bumps is low, the solder bumps become thick and difficult to be distorted, so that the entire solder bumps are distorted, thereby relieving stress concentration on the faulty part (solder bump root). This is thought to be due to lower ability.

  Here, paying attention to the twist of the semiconductor package (difference in warpage between both diagonals), the connection height of the solder bumps at the four corners of the semiconductor package was examined. As a result, the semiconductor package 1 was twisted as shown in FIG. In this case, among the four corners of the semiconductor package, there is a corner 3 where the distance from the mother board 2 is shorter than the distance in the state without twisting, and the connection height of the solder bumps existing in the corner 3 is locally It turned out to be lower. Furthermore, it was found that the connection height of the solder bumps at the four corners of the semiconductor package 1 can be increased by reducing the twist of the semiconductor package 1 as shown in FIG.

  Since the deformation of the semiconductor package is mainly caused by the difference in thermal expansion between the sealing material and the package substrate to which the semiconductor element is bonded, the deformation tends to be minimized at the temperature at the time of sealing. Further, since the semiconductor package is fixed to the motherboard by solidification of the solder bumps, deformation of the semiconductor package is restricted by the solder bump solidification temperature (melting point). From these facts, the present inventors have found that the twist of the semiconductor package is reduced by suppressing the deformation of the semiconductor package in the temperature range from the sealing temperature to the melting point of the solder bump.

  Here, by setting the insulating resin physical property of the package substrate in the temperature range from the sealing temperature to the melting point of the solder bump as shown in the formula (1), the stress generated by the package substrate in the semiconductor package can be reduced. Can be suppressed. Therefore, the deformation of the semiconductor package in the same temperature range can be suppressed, the twist of the semiconductor package can be reduced, the connection height of the solder bumps at the four corners of the semiconductor package can be kept high, and the drop impact resistance can be maintained. It can be improved.

The characteristic value A in the formula (1) according to claim 1 can easily evaluate the magnitude of the stress generated by the insulating resin in the semiconductor package in the temperature range from the sealing temperature to the melting point of the solder bump. This is the value. As the characteristic value A decreases, the stress generated by the package substrate in the semiconductor package tends to decrease.
Here, if the characteristic value A exceeds 1.4 MPa, the deformation of the semiconductor package due to the temperature change becomes large, and the twist of the semiconductor package 1 in the temperature range from the sealing temperature to the melting point of the solder bump cannot be suppressed. It is not preferable for the drop impact resistance. More preferably, it is 1.35 MPa or less, and it is very preferable that it is 1.3 MPa or less.

The sealing temperature T1 is not particularly specified, but 170 ≦ T1 ≦ 180 (° C.), which is the sealing temperature of a general-purpose epoxy resin-based sealing material for semiconductor packages, is preferable. If it is too low or too high, a general-purpose sealing material cannot be used, which is not preferable in terms of cost and reliability.
Similarly, although the melting point T2 of the solder bump is not particularly specified, 200 ≦ T2 ≦ 230 (° C.) is preferable because it has been used as a semiconductor package connection application among lead-free solders and can be applied with a relatively inexpensive solder. . A solder having a lower melting point than this often has a problem in connection reliability, and is not preferable because it is more expensive. Conversely, a solder having a higher melting point than this is not preferable because it causes an increase in reflow temperature and requires heat resistance and high temperature reliability of the entire semiconductor device. Further, like lead-tin eutectic solder, lead-containing solder is not preferable because it is avoided in terms of the environment.

  As for the form of the semiconductor package of the present invention, at least one semiconductor element is mounted on a package substrate having a core layer containing an insulating resin, and the periphery of the semiconductor element is sealed with a sealing material, If the connection electrode between the package substrate and the motherboard is a solder bump, the form and size are not specified.

  The package substrate is not particularly limited as long as the core layer includes an insulating resin. Here, the core layer refers to an insulating layer located in the innermost layer of the package substrate. The core layer may be a layer having a wiring layer made of a conductor on one side or both sides, for example, a single-sided or double-sided printed wiring board. A layer having a plurality of wiring layers, for example, a multilayer wiring board may be used. One or more wiring layers may be further formed on one or both surfaces of the core layer via an insulating layer by a build-up method.

  The mounting form of the semiconductor element on the package substrate is not particularly limited as long as the semiconductor element is fixed to the package substrate and electrically connected. For example, the orientation of the semiconductor element may be a face-down method in which the circuit surface of the semiconductor element faces the package substrate or a face-up method in which the circuit surface of the semiconductor element does not face the package substrate. The electrical connection between the semiconductor element and the conductor layer of the package substrate is not particularly limited. For example, (1) a semiconductor element and a package substrate are bonded with a film-like or paste-like insulating adhesive, and the electrode pad of the semiconductor element and the electrode pad of the conductor layer of the package substrate are connected by a wire such as a gold wire. Wire bonding method, (2) Metal bumps of semiconductor elements that are bonded to the package substrate with an insulating adhesive using a TAB tape on which a conductive circuit such as copper is formed on an insulating resin film such as a polyimide resin film A TAB (Tape Automated Bonding) method in which the electrode pads on which the conductors are formed and the electrode pads of the conductor layer of the package substrate are connected by a TAB tape circuit. (3) Metal bumps are formed on the electrode pads of the semiconductor chip and face down For example, a flip-chip method for directly connecting to the electrode pad of the conductor layer of the package substrate may be used.

  A plurality of solder bumps as connection electrodes for connecting the package substrate to the mother board are usually formed on the back surface side of the semiconductor element mounting surface of the package substrate.

  FIG. 2 is a partial cross-sectional view of a semiconductor package in one embodiment of the present invention. In the present embodiment, a package form generally called FBGA (Fine-pitch Ball Grid Array) is adopted.

In FIG. 2, the semiconductor package 1 is connected to a mother board 2 by solder bumps 4. The semiconductor package 1 includes a semiconductor element 5, a sealing material 6 that covers the semiconductor element 5, a package substrate 7, and a die bond material 8 that adheres the semiconductor element 5 to the package substrate 7. In the present embodiment, the die bond material 8 is insulative or conductive, and wires, metal bumps, TAB tape, and the like that electrically connect the package substrate 7 and the semiconductor element 5 are not shown. When the die bond material 8 is anisotropically conductive, the package substrate 7 and the electrode pads of the semiconductor element 5 are directly connected face-down by the die bond material 8. The package substrate 7 includes a core layer 9 having a wiring layer 11 formed on both sides, and a solder resist layer 10 formed at a necessary position on the wiring layer 11, and the wiring layer 11 facing the mother board 2 has a plurality of electrodes. Pads 12 are provided and are arranged to face the same number of electrode pads 13 of the mother board, and the opposite electrode pads 12 and 13 are connected by solder bumps 4 so as to be electrically connected to the mother board 2. Yes. The core layer 9 is composed of a glass woven fabric or a glass unwoven cloth 14 and an insulating resin 15. The insulating resin 15 is a cured product of a resin composition containing a base resin, a curing agent, an additive (curing accelerator) and a filler. is there. Here, the solder bump refers to a connection electrode for connecting the semiconductor package 1 and the mother board 2 manufactured using a solder ball, a solder paste, or the like.
Although omitted in FIG. 2, a plurality of insulating layers having a wiring layer such as a build-up layer may be laminated between the core layer 9 and the solder resist layer 10, and each wiring layer is connected in the thickness direction. Therefore, a via hole or a through hole may be provided.

  Although the base resin used for the resin composition before curing used as the material for the insulating resin is not specified, an epoxy resin that is superior in terms of insulation and hygroscopicity is suitable for wiring board applications. For example, epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, cresol novolac type epoxy resin, phenol novolac type epoxy resin, cycloaliphatic epoxy resin, glycidyl ester type epoxy resin, glycidyl amine type epoxy resin, etc. Various thermosetting resins such as an epoxy resin to which halogen such as bromine is added and a resol type phenol resin can be used. In particular, crystalline epoxy resins such as naphthalene type epoxy resins, anthracene type epoxy resins, dihydroanthracene type epoxy resins, biphenyl novolac type epoxy resins and biphenyl type epoxy resins, and epoxy resins obtained by adding halogen to these are preferable. In particular, it is preferable to use crystalline epoxy resins such as naphthalene type epoxy resin, anthracene type epoxy resin, dihydroanthracene type epoxy resin, biphenyl novolac type epoxy resin and biphenyl type epoxy resin. The epoxy resin may have any molecular weight, and two or more types may be used in combination.

As a naphthalene type epoxy resin, the epoxy resin represented by following formula (1) is mentioned, for example.

（一般式（２）中、R¹〜R⁸は、各々独立に水素原子、炭素数１〜６のアルキル基、炭素数１〜６のアルコキシ基又はハロゲン基を表し、ｎは０以上の数、例えば０〜６の整数を表す。） As an anthracene type epoxy resin, the epoxy resin represented by following General formula (2) is mentioned, for example.

(In General Formula (2), R ^{1 to} R ⁸ each independently represents a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, an alkoxy group having 1 to 6 carbon atoms, or a halogen group, and n is a number of 0 or more. Represents an integer of 0 to 6, for example.)

（一般式（３）中、R¹〜R⁸は、各々独立に水素原子、炭素数１〜６のアルキル基、炭素数１〜６のアルコキシ基又はハロゲン基を表し、ｎは０以上の数、例えば０〜６の整数を表す。。） Examples of the dihydroanthracene type epoxy resin include an epoxy resin represented by the following general formula (3).

(In General Formula (3), R ^{1 to} R ⁸ each independently represents a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, an alkoxy group having 1 to 6 carbon atoms, or a halogen group, and n is a number of 0 or more. For example, an integer of 0 to 6 is represented.)

（一般式（４）中、R¹〜R⁸は、各々独立に水素原子、炭素数１〜６のアルキル基、炭素数１〜６のアルコキシ基又はハロゲン基を表し、R⁹は、各々独立に炭素数１〜６のアルキル基、炭素数１〜６のアルコキシ基又はハロゲン基を表し、aは０〜４の整数、ｂは０〜３の整数、ｎは０以上の整数、例えば０〜６の整数を表す。） Examples of the biphenyl novolac type epoxy resin include an epoxy resin represented by the following general formula (4).

(In General Formula (4), R ^{1 to} R ⁸ each independently represents a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, an alkoxy group having 1 to 6 carbon atoms, or a halogen group, and R ⁹ is each independently Represents an alkyl group having 1 to 6 carbon atoms, an alkoxy group having 1 to 6 carbon atoms, or a halogen group, a is an integer of 0 to 4, b is an integer of 0 to 3, and n is an integer of 0 or more, for example, 0 to Represents an integer of 6.)

（一般式（５）中、R¹〜R⁸は、各々独立に水素原子、炭素数１〜１０のハロゲン基等で置換又は非置換の１価の炭化水素基（たとえばアルキル基、アリール基）或いはハロゲン基を表し、ｎは０以上、例えば０〜６の整数を表す。） As a biphenyl type epoxy resin, the epoxy resin represented by following General formula (5) is mentioned, for example.

(In the general formula (5), R ^{1 to} R ⁸ are each independently a hydrogen atom, a monovalent hydrocarbon group substituted or unsubstituted with a halogen group having 1 to 10 carbon atoms (for example, an alkyl group, an aryl group) Alternatively, it represents a halogen group, and n represents 0 or more, for example, an integer of 0 to 6.)

  Moreover, it is preferable that the resin composition used as the material of insulating resin contains a hardening | curing agent. The curing agent is not particularly limited as long as it has a curing effect on the base resin, and examples thereof include various amines, acid anhydrides, various novolak resins, and the like. For example, various amines such as diaminodiphenylmethane and dicyandiamide, various polyamide curing agents such as polyamide resin made by polycondensation of polyamine and polymerized fatty acid, acid anhydrides such as phthalic anhydride and trimellitic anhydride, phenol Bisphenol A, bisphenol F, bisphenol S, etc., which are compounds having two or more functional hydroxyl groups in one molecule, and phenol resins. As the phenolic resin, a novolak resin is preferable, for example, a phenol novolak resin, a cresol novolak resin, a bisphenol novolak resin, or a reaction product of a phenol and a compound having a triazine ring and an aldehyde such as a melamine-modified phenol novolak resin. Can be mentioned. These compounds may be used alone or in combination of two or more.

  The ratio of the curing agent to the epoxy resin is preferably in the range of 2 to 100 parts by weight, more preferably in the range of 5 to 80 parts by weight, and particularly preferably in the range of 7 to 75 parts by weight with respect to 100 parts by weight of the epoxy resin. A hardening | curing agent can be used individually by 1 type or in combination of 2 or more types.

  As other additives, various silane coupling agents, curing accelerators, antifoaming agents and the like can be used. Furthermore, in order to mix these with resin, it is preferable to add a solvent. The solvent may be any solvent as long as it dissolves and mixes the resin, the curing agent, and the additive. Moreover, you may use a solvent in combination of several types.

  The curing accelerator is not particularly limited as long as it accelerates the curing reaction of a normal epoxy resin. For example, imidazoles, organophosphorus compounds, tertiary amines, quaternary ammonium salts and the like are exemplified. Examples of imidazoles include imidazole, 1-methylimidazole, 2-methylimidazole, 4-methylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole, 1-benzyl-2-methylimidazole. 4-phenylimidazole, benzimidazole, 1-cyanoethyl-2-methylimidazole, etc., organophosphorus compounds such as triphenylphosphine, tertiary amines such as triethylamine, tributylamine, pyridine, Examples of the quaternary ammonium salt include tetrabutylammonium acetate and tetrabutylammonium hydrogen sulfate. The ratio of the curing accelerator to the epoxy resin is preferably in the range of 0.01 to 10 parts by weight and more preferably in the range of 0.03 to 5 parts by weight with respect to 100 parts by weight of the epoxy resin.

  A filler may be used for the insulating resin. The filler is not particularly limited, and silica, alumina, aluminum hydroxide, calcium carbonate, clay, talc, silicon nitride, boron nitride, titanium oxide, barium titanate, lead titanate, strontium titanate, etc. Organic fillers such as inorganic fillers and rubbers can be used. The ratio of the filler to the epoxy resin is preferably 300 parts by weight or less, more preferably 270 parts by weight or less, and particularly preferably 250 parts by weight or less with respect to 100 parts by weight of the total amount of the epoxy resin and the curing agent.

  The core layer may be composed only of a cured product of the resin composition. Usually, the resin composition is impregnated into a fiber reinforcement such as glass fiber such as glass woven fabric or glass nonwoven fabric, and heated. It is preferable that it is a hardened | cured material by pressing.

  As the sealing material 6, the hardened | cured material of an insulating and thermosetting resin composition is mentioned. The resin composition is not particularly limited as long as it is insulative and thermosetting. Examples of these base resins include thermosetting resin systems such as epoxy, silicone, phenol, and polyimide. For these reasons, a general-purpose epoxy resin-based sealing material for semiconductor packages having a sealing temperature (curing temperature) of 170 ° C. or higher and 180 ° C. or lower is preferable.

  Although it does not specifically limit as a solder used for the solder bump 4, For the reason as stated above, Preferably, melting | fusing point is 200 degreeC or more and 230 degrees C or less, ie, as an alloy kind, Sn-Cu, Sn-Ag Lead-free solders such as —Cu, Sn—Ag—Cu—Bi, Sn—Ag—Cu—Sb, Sn—Ag—Bi—In, and Sn—Zn are preferred.

  In the embodiment shown in FIG. 2, the die bond material 8 is not particularly limited, and the solder resist layer 10 is not particularly limited as long as it is insulative. Examples of these base resins include epoxy, silicone, phenol, and polyimide. There are various polymer resins such as thermosetting resin and photocurable resin. Both paste and film can be applied. Those that are difficult to form voids when bonded to each other and those that have a low moisture absorption rate after curing do not cause separation or cracking during reflow mounting and can prevent unintentional deformation of the semiconductor package 1.

The method for assembling the semiconductor package is not particularly limited, but a method for assembling the semiconductor package 1 and a method for connecting to the mother board 2 in the general embodiment shown in FIG. 2 will be described.
The semiconductor element 5 is bonded to the package substrate 7 by thermocompression bonding using a die bonding material 8, the semiconductor element 5 and the package substrate 7 are electrically connected by wire bonding, and then heated / pressurized by a transfer press. The semiconductor element 5 and the die bond material 8 are covered and sealed with a sealing material 6, and the sealing material 6 is heated and cured in an oven to assemble the semiconductor package 1. Thereafter, solder is supplied between the electrode pads 13 of the motherboard facing the electrode pads 12 of the semiconductor package 1 by solder balls or solder paste, and the solder is melted and solidified in a reflow furnace in a nitrogen atmosphere. The electrode pads 12 of the mother board 2 and the electrode pads 13 of the mother board 2 are connected by solder bumps 4.
There are various methods for supplying the solder. Generally, there are a method of reflow mounting a solder ball on the electrode pad 12 of the semiconductor package 1 and a method of printing a solder paste on the electrode pad 13 of the motherboard 2. Any method may be used.

Note that, as long as the package substrate 7 includes a core layer including the insulating resin 15, a specific manufacturing method is not particularly limited, but a general method for manufacturing a package substrate will be described.
First, a base resin, a curing agent, an additive, an inorganic filler and / or an organic filler, a solvent, and the like are mixed to produce a resin composition that is a material for the insulating resin 15. A glass woven fabric or nonwoven fabric 14 is impregnated with the resin composition and heated to obtain a semi-cured prepreg. Several prepregs are stacked, copper foils are stacked on both sides thereof, and press-molded under heating and pressure conditions to obtain a copper-clad laminate that becomes the core layer 9. Through holes and wiring patterns are formed in the core layer 9 as necessary. Here, when it is necessary to further increase the number of layers in order to obtain the necessary wiring, an insulating layer having new wiring layers on the front and back surfaces of the core layer 9 can be formed by a laminator method, a press method, a coating method, a printing method, or the like. The process of producing and making a via hole, a through hole, and a wiring pattern is repeated as needed. When the necessary wiring is obtained, the solder resist layer 10 is provided on the outermost layer for circuit protection, and the solder resist layer 10 on the electrode pad 12 is opened. Finally, plating corresponding to the solder type to be used is applied to the electrode pad 12 to obtain the package substrate 7.

  Next, the present invention will be described with reference to examples using the semiconductor device in the above embodiment, but the scope of the present invention is not limited to these examples.

A procedure for manufacturing a package substrate will be described.
(1) Table 1 shows the types and blending amounts (parts by weight) of epoxy resins, curing agents, additives, inorganic fillers, organic fillers and solvents used in Example 1 and Comparative Examples 1-3. Show. These were mixed to obtain a resin composition.
(2) A glass woven fabric having a thickness of 0.1 mm was impregnated with the resin composition obtained in (1) and heated at 160 ° C. for 3 minutes to obtain a semi-cured prepreg. Further, two prepregs were stacked, and a copper foil having a thickness of 18 μm was stacked on both sides thereof, and press-molded under the conditions of 175 ° C., 90 minutes, 2.5 MPa to obtain a copper clad laminate as a core layer. The thickness of the obtained copper clad laminate was 220 to 240 μm.
(3) Etching the copper foils on the front and back surfaces of the copper clad laminate, wiring layer consisting of solder bump electrode pads and wiring patterns on one side, and wire bonding electrode pads and wiring patterns on the other side A wiring layer comprising: As shown in FIG. 3, the electrode pads 12 for solder bumps have a diameter of 0.32 mm, a pitch of 0.5 mm, and an array obtained by excluding the center 12 rows × 12 rows from the 20 rows × 20 rows grid arrangement. 256 were arranged. The wiring pattern was fabricated so that it was possible to check the continuity of the solder bumps at least at the four corners when connected to the motherboard with solder bumps. The electrode pads and the wiring pattern for wire bonding were prepared so that the remaining copper ratio was the same as the surface on which the electrode pads and the wiring pattern for solder bumps were prepared.
(4) Solder resist AUS-308 (product name, manufactured by Taiyo Ink Manufacturing Co., Ltd.) was applied to the front and back surfaces of the core layer having the wiring layer under predetermined conditions. Thereafter, exposure and development were sequentially performed, and a solder resist layer having a thickness of 30 μm was formed on the front and back surfaces of the core layer having the wiring layer. At that time, as shown in FIG. 3, the diameter of the solder resist opening 16 on the solder bump electrode pad was set to 0.23 mm.
(5) About 10 μm of Ni plating and about 3 μm of gold plating were applied to the electrode pads for solder bumps by electrolysis.
In addition, since these are very general production steps, the processes such as drying and washing between steps are omitted.

A procedure for manufacturing a motherboard will be described.
(1) Etching a 0.6 mm thick double-sided copper-clad laminate MCL-E-67 (product name, manufactured by Hitachi Chemical Co., Ltd.) with 18 μm thick copper foil on the front and back surfaces, and soldering on the front and back surfaces Bump electrode pads and wiring patterns were prepared. As shown in FIG. 3, the electrode pads for solder bumps have a diameter of 0.32 mm, a pitch of 0.5 mm, and an array obtained by removing the central 12 rows × 12 rows from the 20 rows × 20 rows grid arrangement, for a total of 256. Arranged. The wiring pattern was prepared so that the continuity check of the solder bumps at least at the four corners was possible when the package substrates were connected by solder bumps.
(2) A solder resist layer was produced in the same manner as in the package substrate production procedure (4). As shown in FIG. 3, the solder resist opening 17 on the solder bump electrode pad 13 had a diameter of 0.23 mm.
(3) The solder bump electrode pad and the continuity check pad were subjected to Ni plating by an electrolytic method of about 10 μm and gold plating of about 3 μm by an electrolytic method.
(4) As shown in FIG. 4, a hole 19 for fixing the substrate to the dropping jig in the drop impact test so that the center position of the electrode pads 18 for solder bumps arranged in a lattice is in the center is 70 mm. The holes were opened at a diameter of 3.2 mm at four locations at intervals of × 30 mm. Then, it cut | disconnected to 110 mm x 50 mm so that the center position of the electrode pad for solder bumps arranged in the grid might become the center.
In addition, since these are very general production steps, the processes such as drying and washing between steps are omitted.

A procedure for assembling the semiconductor package will be described.
(1) A die bond material having a film thickness of 25 μm, HIATTACH FH-900 (product name, Hitachi, Ltd.) so that a semiconductor element of 8 mm × 8 mm × 0.1 mm is positioned on the center back surface of the electrode pad for solder bumps arrayed on the package substrate Using a Kasei Kogyo Co., Ltd.), bonding was performed under conditions of 130 ° C., 0.08 MPa (5 N), 1 second.
(2) A sealing material, CEL-9240HF10 (product name, manufactured by Hitachi Chemical Co., Ltd.) was transferred using a transfer press under conditions of 175 ° C., 6.9 MPa, 90 seconds, and a thickness of 0.3 mm on the package substrate. The semiconductor element and the die bond material were sealed. Thereafter, the encapsulant was completely cured at 175 ° C. for 5 hours.
(3) A semiconductor package was obtained by dividing into pieces of 10 mm × 10 mm using a dicer so that the semiconductor element was in the center.

A connection procedure between the semiconductor package and the motherboard will be described.
(1) An appropriate amount of flux, sparkle flux WF-6300LF (product name, manufactured by Senju Metal Co., Ltd.) was transferred onto an electrode pad for solder bumps of a semiconductor package.
(2) A 0.3 mm diameter, melting point 217 ° C., Sn—Ag—Cu solder ball, Eco Solder Ball S 705M (product name, Senju Metal Industry Co., Ltd.) was placed thereon.
(3) The solder was melted and solidified in a reflow furnace under a nitrogen atmosphere, and solder balls were attached on the electrode pads for solder bumps. At that time, the reflow profile for lead-free solder defined by IPC / JEDEC J-STD-020C was used.
(4) An appropriate amount of flux, sparkle flux WF-6300LF (product name, manufactured by Senju Metal Co., Ltd.) was transferred onto the solder bump electrode pads of the motherboard.
(5) The semiconductor package with solder balls was aligned so that the corresponding electrode pads of the mother board and the semiconductor package face each other.
(6) The solder was melted and solidified in a reflow furnace under a nitrogen atmosphere, and the electrode pads were connected. At that time, the reflow profile for lead-free solder defined by IPC / JEDEC J-STD-020C was used.

The procedure for performing the drop impact test will be described.
(1) As shown in FIG. 5, the mother board 2 is used with four screwing columns 21 (made of iron, spacing 70 mm × 30 mm, height 10 mm) provided on a bathtub-shaped dropping jig 20 (made of hard polystyrene). Screwed. At that time, the semiconductor package 1 connected to the mother board 2 with the solder bumps 4 was fixed so as to face down.
(2) From the height of 750 mm, the dropping jig 20 was dropped so that the lower surface of the dropping jig 20 hit the concrete block 22 almost in parallel. At the same time, the continuity of the solder bumps 4 connecting the semiconductor package 1 and the mother board 2 was checked, and the drop was repeated until the continuity failure at the time of the drop impact was confirmed.

A method for measuring the elastic modulus and thermal expansion coefficient of the insulating resin will be described.
(1) A glass woven fabric is separated from a prepreg obtained by impregnating the resin composition used in Example 1 and Comparative Examples 1 to 3 and semi-cured, obtained in (2) of the package substrate production procedure, and a semi-cured resin is obtained. The powdered product was heated for 15 minutes under conditions of 180 ° C. and 6.9 MPa using a transfer press and a predetermined mold, molded into 60 mm × 6 mm × 1.5 mm, and then at 180 ° C. under normal pressure. It was cured by heating for 2 hours under conditions.
(2) In the case of elastic modulus measurement, the cured insulating resin is 60 mm × 6 mm × 1.5 mm insulative resin and viscoelasticity measuring device DMS6100 (product name, manufactured by Seiko Instruments Inc.) is used. It was measured by a double-end bending method with min, measurement distance 20 mm, frequency 1 Hz, and amplitude 5 μm. Data collection was performed at least once each time the temperature was raised by 1 ° C.
(3) In the case of measuring the thermal expansion coefficient, the cured insulating resin is cut into 20 mm × 1.5 mm × 1.5 mm, and the temperature is increased using a thermomechanical analyzer TMA / SS6100 (product name, manufactured by Seiko Instruments Inc.). The measurement was performed by a compression method with a speed of 5 ° C./min, a measurement distance of 20 mm, and a sample cross-sectional area of 2.3 mm ² . Data collection was performed at least once each time the temperature was raised by 1 ° C.

  The twist of the semiconductor package and the solder bump connection height at the four corners were measured using a non-contact laser displacement meter, YP-10 (trade name, manufactured by Sony Precision Technology Co., Ltd.). The twist of the semiconductor package was defined as a difference in the amount of warpage measured on both diagonal lines of the semiconductor package sealing material surface.

Table 2 shows the characteristic value A, the twist of the semiconductor package, the minimum value of the solder bump connection height, and the drop impact test result in Example 1 and Comparative Examples 1 to 3.
As is clear from Table 2, the characteristic value A of Example 1 is kept low compared with Comparative Examples 1 to 3, and therefore, from 175 ° C. to 217 ° C., which is near the solder bump solidification temperature from the sealing temperature. It can be seen that the stress generated by the package substrate is kept low, the twist of the semiconductor package is small, the minimum connection height of the solder bumps is high, and the drop impact resistance is improved.

DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 Mother board 3 Corner where distance is locally shortened 4 Solder bump 5 Semiconductor element 6 Sealing material 7 Package substrate 8 Die bond material 9 Core layer 10 Solder resist layer 11 Wiring layer 12 Electrode pad 13 Motherboard electrode pad 14 Glass Woven or non-woven fabric 15 Insulating resin 16 Solder resist opening of package substrate 17 Solder resist opening of mother board 18 Solder bump electrode pads 19 Holes for fixing substrate to dropping jig 20 Dropping jig 21 Screwing column 22 Concrete block

Claims (3)

In a semiconductor package having a package substrate having a core layer containing an insulating resin, the insulating resin has the following general formula (4):

(In General Formula (4), R ^{1 to} R ⁸ each independently represents a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, an alkoxy group having 1 to 6 carbon atoms, or a halogen group, and R ⁹ is each independently Represents an alkyl group having 1 to 6 carbon atoms, an alkoxy group having 1 to 6 carbon atoms, or a halogen group, a represents an integer of 0 to 4, b represents an integer of 0 to 3, and n represents an integer of 0 or more.)
A semiconductor package, which is a cured product of an epoxy resin containing a biphenyl novolac type epoxy resin represented by formula (I) and a resin composition containing a curing agent.   The semiconductor package according to claim 1, wherein the resin composition further contains a curing accelerator.   The semiconductor package according to claim 1 or 2, wherein the resin composition further contains a filler.

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