JP2012115090A - Insulated switching power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an insulated switching power supply that can prevent malfunctions while sufficiently reducing power consumption in a standby mode.SOLUTION: An insulated switching power supply 1 includes: a capacitor C5 for supplying control power required for switching control of a switch element Q1; a first control section 10 for switching-controlling the switch element Q1 with the use of the control power supplied from the capacitor C5 according to a voltage Vat a terminal P2 varying in response to an output voltage V; and an output voltage mask section 19 for causing the first control section 10 to recognize that the voltage Vat the terminal P2 is a predetermined voltage in the period of a predetermined time from a restart of control power supply to the first control section 10.

Description

  The present invention relates to an isolated switching power supply, and more particularly to an isolated switching power supply that reduces power consumption in a standby mode.

  Conventionally, an insulating switching power supply converts an input voltage into a desired voltage and outputs it by switching a switching element. In this insulated switching power supply, a technique of performing burst control of the switch elements in the standby mode is used in order to reduce power consumption in the standby mode (see, for example, Patent Document 1). According to this method, in the standby mode, an oscillation period in which switching of the switch element is performed at a predetermined cycle and a switching pause period in which switching of the switch element is temporarily stopped are repeated. For this reason, since the frequency | count of switching per unit time can be reduced, the switching loss per unit time can be reduced, As a result, the power consumption in standby mode can be reduced.

  In such an isolated switching power supply, as a method for further reducing the power consumption in the standby mode, for example, at least a part of the control circuit that controls the switching of the switch element during at least a part of the switching pause period in the standby mode. It is conceivable to stop the supply of control power to. According to this method, since the power consumption of the control circuit in the standby mode can be reduced, the power consumption in the standby mode can be further reduced in the isolated switching power supply including this control circuit.

JP 2002-58238 A

  In an isolated switching power supply employing the above-described method, it is conceivable to perform switching control by the above-described control circuit based on a voltage at a specific point that changes according to the output voltage.

  Here, in order to reduce the influence of noise caused by switching and others, the specific point and the reference potential source may be connected via a capacitor. In this case, the output voltage can be reflected on the voltage at a specific point in a more stable state than when no capacitor is provided, and a more appropriate voltage can be output. Even when no capacitor is provided as described above, a parasitic capacitance is connected as a capacitor at a specific point.

  However, the change in the voltage at the specific point described above becomes gentler than the change in the output voltage due to the capacitance components of the capacitor and the parasitic capacitance. Further, when the supply of control power is resumed in the standby mode, the voltage across the capacitor and the parasitic capacitance starts to increase from 0 V, and thus a predetermined time elapses after the supply of control power is resumed. There is a period during which the voltage at the specific point is not a voltage corresponding to the output voltage. According to these, malfunction may occur.

  In view of the above-described problems, an object of the present invention is to provide an isolated switching power supply that can prevent malfunction while sufficiently reducing power consumption in a standby mode.

The present invention proposes the following items in order to solve the above-described problems.
(1) In the present invention, the switch element (for example, equivalent to the switch element Q1 in FIG. 1) is in a continuous oscillation state (for example, equivalent to a normal mode described later) or an intermittent oscillation state (for example, equivalent to a standby mode described later). Control power that supplies switching power necessary for the switching control, which is an isolated switching power supply (for example, equivalent to the isolated switching power supply 1 in FIG. 1) that performs switching control and controls conversion from the input voltage to a required output voltage. Using a supply source (for example, equivalent to the capacitor C5 in FIG. 1) and the control power supplied from the control power supply source, a specific point that changes corresponding to the output voltage (for example, the terminal P2 in FIG. 1). A first control unit (for example, corresponding to the first control unit 10 of FIG. 3) that controls the switching element based on the voltage of the first control unit, and the first control unit And a control power supply switch that short-circuits or opens the control power supply source (for example, equivalent to the switch element Q11 in FIG. 4), and a switching pause period in the intermittent oscillation state (for example, from time t2 to time t4 in FIG. 13). In at least a part of the period (equivalent to the period from time t3 to t4 in FIG. 13), the control power supply switch is opened, and the control power to the first control unit is A second control unit (for example, corresponding to the second control unit 12 in FIG. 3) that stops supply and a predetermined time after the supply of control power to the first control unit is resumed. In the period until the time (for example, corresponding to the period from time t4 to time t7 in FIG. 13), the voltage at the specific point is assumed to be a predetermined voltage (for example, equivalent to the H level voltage in FIG. 13). The first Voltage mask means to recognize the control unit (e.g., output voltage mask unit 19 of FIG. 3) proposes a insulated switching power supply, characterized in that it comprises a, a.

  According to this invention, the control power supply source and the first control unit are provided in the insulating switching power supply. The control power supply source supplies control power necessary for switching control. Further, the first control unit uses the control power supplied from the control power supply source to control the switching of the switch element based on the voltage at a specific point that changes in accordance with the output voltage. For this reason, when the supply of the control power to the first control unit is stopped, the switching of the switch element is stopped.

  A voltage mask means is further provided in the above-described isolated switching power supply, and a period until a predetermined time elapses after the supply of control power to the first control unit is resumed by the voltage mask means. In this case, the first control unit recognizes the voltage at the specific point as being a predetermined voltage. For this reason, when the supply of the control power to the first control unit is resumed by setting the above-described predetermined time, the specific point is kept until the voltage at the specific point becomes a level corresponding to the output voltage. Can be recognized by the first control unit as a predetermined voltage. Therefore, by setting the above-described predetermined voltage, it is possible to prevent a malfunction from occurring when restarting the supply of control power to the first control unit.

  In addition, according to the present invention, the insulated switching power supply is further provided with a second control unit, and the second control unit causes the first control unit to perform the first switching in the switching pause period in the intermittent oscillation state. The supply of control power to the control unit was stopped. For this reason, the power supply to the first control unit is stopped during at least a part of the switching pause period in the intermittent oscillation state, so that the power consumption of the isolated switching power supply in the intermittent oscillation state can be reduced.

  Here, as a technique for reducing the power consumption of the insulating switching power supply, it is conceivable to set the control voltage supplied to the first control unit to 0V. However, in the intermittent oscillation state, when shifting from the switching pause period to the oscillation period, it is necessary to operate the activation circuit in order to raise the control voltage from 0 V to a specified level in a short time. For this reason, in the intermittent oscillation state, power is consumed in the start-up circuit every time the switching suspension period is shifted to the oscillation period.

  Therefore, according to the present invention, as described above, the insulated switching power supply is provided with the control power supply source, the first control unit, and the second control unit. For this reason, the supply of control power to the first control unit can be stopped in at least a part of the switching pause period in the intermittent oscillation state, and as a result, the insulation type can be achieved without setting the control voltage to 0V. The power consumption of the switching power supply can be reduced. Therefore, in the intermittent oscillation state, it is not necessary to operate the activation circuit when shifting from the switching pause period to the oscillation period, so that the power consumption of the isolated switching power supply can be sufficiently reduced.

  (2) In the insulated switching power supply of (1), the second control unit includes a capacitor (for example, equivalent to the capacitor C4 in FIG. 5) and a first switch element (for example, in FIG. 5). Switch element Q22) and a second switch element (for example, switch element Q24 in FIG. 5), and one end of the capacitor is connected to a control terminal of the first switch element, The other end of the capacitor is connected to the output terminal of the first switch element and the output terminal of the second switch element, and the input terminal of the first switch element is connected to the second switch. The control terminal of the element is connected, and the control power supply source is connected via a drive unit (for example, equivalent to the drive unit 123 in FIG. 5) that drives the second switch element, and the second The input terminals of the switch elements, proposes the insulated switching power supply, characterized in that said control power supply switch is connected.

  According to this invention, the capacitor, the first switch element, and the second switch element are provided in the second control unit. A capacitor is provided between the control terminal and the output terminal of the first switch element, and a first switch element is provided between the control terminal and the output terminal of the second switch element. Therefore, the first switch element is short-circuited or opened according to the voltage across the capacitor, and the second switch element is opened or short-circuited according to the state of the first switch element. Depending on the state, the control voltage level input to the control power supply switch changes, and the first control unit and the control power supply source are short-circuited or opened. For this reason, the control power supply switch can be opened corresponding to the voltage across the capacitor during the switching pause period in the intermittent oscillation state.

  (3) In the insulated switching power supply of (1) or (2), the voltage of the specific point varies depending on whether or not the output voltage is equal to or higher than a predetermined upper limit voltage. An isolated switching power supply is proposed.

  According to the present invention, the voltage at the specific point is changed depending on whether or not the output voltage is equal to or higher than a predetermined upper limit voltage. Therefore, the switch element can be controlled depending on whether the output voltage is equal to or higher than the upper limit voltage.

  (4) In the insulated switching power supply according to (3), the voltage of the specific point is equal to or lower than a specific voltage when the output voltage is equal to or higher than a predetermined upper limit voltage (for example, the voltage V2 in FIG. 13). When the output voltage is less than the upper limit voltage, the voltage mask means becomes higher than the specific voltage, and the voltage masking means is a predetermined time after the supply of control power to the first control unit is resumed. In the period until the time elapses, an insulating switching power supply is proposed in which at least a part of the first control unit recognizes the voltage at the specific point higher than the specific voltage. .

  According to the present invention, when the output voltage is equal to or higher than the upper limit voltage, the voltage at the specific point is equal to or lower than the specific voltage, and when the output voltage is lower than the upper limit voltage, the voltage at the specific point is higher than the specific voltage. In the period from when the supply of control power to the first control unit is resumed until a predetermined time elapses, the voltage mask means sets the voltage at the specific point to be higher than the specific voltage, At least a part of the control unit 1 is made to recognize. For this reason, even if the supply of control power to the first control unit is resumed, the output voltage is not reflected on at least a part of the first control unit until a predetermined time elapses. It is possible to avoid performing an incorrect operation based on the voltage at a specific point. Accordingly, when the voltage at a specific point has dropped below a specific voltage during the period when the output voltage has dropped below the upper limit voltage because the supply of control power to the first control unit has been stopped. Even so, it is possible to prevent a malfunction from occurring when the supply of control power to the first control unit is resumed.

  ADVANTAGE OF THE INVENTION According to this invention, malfunctioning can be prevented about an insulation type switching power supply, fully reducing the power consumption in an intermittent oscillation state.

It is a circuit diagram of the insulation type switching power supply concerning one embodiment of the present invention. It is a timing chart of the said insulation type switching power supply. It is a circuit diagram of the control circuit with which the said insulation type switching power supply is provided. It is a circuit diagram of the control power supply switch part with which the control circuit is provided. It is a circuit diagram of the 2nd control part with which the said control circuit is provided. It is a circuit diagram of the starting circuit part with which the said control circuit is provided. It is a circuit diagram of the constant current supply part with which the said control circuit is provided. It is a circuit diagram of the low voltage malfunction prevention circuit part with which the said control circuit is provided. It is a circuit diagram of the oscillation control part with which the said control circuit is provided. FIG. 3 is a circuit diagram of an oscillation stop control unit provided in the control circuit. It is a circuit diagram of the terminal voltage detection part with which the said control circuit is provided. It is a circuit diagram of the output voltage mask part with which the said control circuit is provided. 3 is a timing chart of the control circuit in a standby mode.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the constituent elements in the following embodiments can be appropriately replaced with existing constituent elements, and various variations including combinations with other existing constituent elements are possible. Accordingly, the description of the following embodiments does not limit the contents of the invention described in the claims.

[Configuration of Isolated Switching Power Supply 1]
FIG. 1 is a circuit diagram of an isolated switching power supply 1 according to an embodiment of the present invention. The insulating switching power supply 1 includes a transformer T, a control circuit 2, an output voltage upper limit detection unit 50, an output voltage lower limit detection unit 60, a mode switching signal generation unit 70, and a switch element Q1 composed of an N-channel MOSFET. And capacitors C1 to C6, diodes D1 and D2, phototransistors PT1 and PT2, and a resistor R1.

  First, the configuration of the primary side of the transformer T will be described. The control circuit 2 is provided with six terminals P1 to P6. A terminal GND1 connected to the reference potential source is connected to the terminal P3, and an input terminal IN is connected via the capacitor C1.

The terminal P3 is connected to the terminal P1 through the capacitor C4. A resistor R1 and a phototransistor PT1 are connected in parallel to the capacitor C4. The phototransistor PT1 is turned on / off in response to signals output from the output voltage lower limit detection unit 60 and the mode switching signal generation unit 70. The output voltage lower limit detection unit 60 is connected to the output terminal OUT, and turns on the phototransistor PT1 when the output voltage _VOUT output from the output terminal OUT is equal to or lower than the lower limit voltage. In addition, when the isolated switching power supply 1 is operated in the normal mode, the mode switching signal generation unit 70 outputs a mode switching signal to the phototransistor PT1, turns on the phototransistor PT1, and operates in the standby mode. In this case, the output of the mode switching signal is stopped and the phototransistor PT1 is turned off.

The terminal P3 is connected to the terminal P2 through the capacitor C6. A phototransistor PT2 is connected in parallel to the capacitor C6. Phototransistor PT2, in response to the signal output from the output voltage limit detection unit 50, so that the voltage V _P2 of the terminal P2 becomes a voltage corresponding to the output voltage V _OUT, actively turned on and off. The output voltage upper limit detection unit 50 is connected to the output terminal OUT. When the output voltage _VOUT is equal to or higher than the upper limit voltage, the output voltage upper limit detection unit 50 activates the phototransistor PT2, and in the activation on state as the output voltage _VOUT increases. The impedance of the phototransistor PT2 is reduced. According to this, when the output voltage V _OUT is equal to or higher than the upper limit voltage, the voltage V _{P2 at the} terminal P2 is a voltage that changes according to the output voltage V _OUT , more specifically, the output voltage _VOUT is higher. As a result, the voltage becomes lower. On the other hand, when the output voltage _VOUT is less than the upper limit voltage, the phototransistor PT2 is turned off.

  A terminal P3 is connected to the terminal P4 via a capacitor C5, and a cathode of the diode D1 is connected to the terminal P4. The other end of the control winding T2 of the transformer T is connected to the anode of the diode D1, and the terminal P3 is connected to one end of the control winding T2.

  The input terminal IN is connected to the terminal P5. One end of the primary winding T1 of the transformer T is also connected to the input terminal IN. A terminal P3 is connected to the other end of the primary winding T1 through a capacitor C2. The drain of the switching element Q1 is also connected to the other end of the primary winding T1. The terminal P3 is connected to the source of the switch element Q1, and the terminal P6 is connected to the gate of the switch element Q1.

  Next, the configuration of the secondary side of the transformer T will be described. One end of the secondary winding T3 of the transformer T is connected to a terminal GND2 connected to a reference potential source. The anode of the diode D2 is connected to the other end of the secondary winding T3, and the output terminal OUT is connected to the cathode of the diode D2, and the terminal GND2 is connected via the capacitor C3.

  The output voltage upper limit detector 50 and the output voltage lower limit detector 60 connected to the output terminal OUT are also connected to the terminal GND2.

[Operation of Isolated Switching Power Supply 1]
Insulated switching power supply 1 having the above configuration, the voltage _{V P1} terminal P1 which varies in accordance with the output voltage _{V OUT} and the mode switching signal, the voltage _{V P2} terminal P2 which changes in accordance with the output voltage _{V OUT,} In response to this, the control circuit 2 performs switching control of the switch element Q1 in the normal mode or the standby mode, converts the input voltage input from the input terminal IN to the necessary output voltage _VOUT, and converts the output voltage _VOUT to Output from the output terminal OUT. In the present embodiment, in the standby mode, the insulating switching power supply 1 performs burst control of the switch element Q1.

FIG. 2 is a timing chart of the isolated switching power supply 1. V _C5 indicates a voltage across the capacitor C5.

As shown in FIG. 2, in the normal mode, the switch element Q1 is oscillated to make the output voltage _VOUT substantially constant. On the other hand, in the standby mode, the switch element Q1 is intermittently oscillated by alternately repeating an oscillation period in which the switch element Q1 oscillates and an oscillation stop period in which the switch element Q1 stops oscillating.

[Configuration of Control Circuit 2]
FIG. 3 is a circuit diagram of the control circuit 2. The control circuit 2 includes a first control unit 10, a control power supply switch unit 11, a second control unit 12, and an activation circuit unit 13. The first control unit 10 includes a constant current supply unit 14, a low voltage malfunction prevention circuit unit 15, an oscillation control unit 16, an oscillation stop control unit 17, a terminal voltage detection unit 18, an output voltage mask unit 19, and a soft start circuit unit 20. A latch protection circuit unit 21 and a control voltage generation unit 22.

[Configuration of Control Power Supply Switch Unit 11]
FIG. 4 is a circuit diagram of the control power supply switch unit 11. The control power supply switch unit 11 includes a diode D11 and a switch element Q11 composed of a P-channel MOSFET. The contact A1 and the contact A4 are connected via the switch element Q11. Specifically, the contact A1 is connected to the source of the switch element Q11, and the contact A4 is connected to the drain of the switch element Q11. The contact A2 and the cathode of the diode D11 are also connected to the source of the switch element Q11, and the anode of the diode D11 is also connected to the drain of the switch element Q11. A contact A3 is connected to the gate of the switch element Q11.

[Configuration of Second Control Unit 12]
FIG. 5 is a circuit diagram of the second control unit 12. The second control unit 12 includes a drive unit 123, a capacitor C21, a comparator CMP21, a diode D21, a flip-flop FF21 composed of a NAND gate, an inverter INV21, and a switch element composed of an N-channel MOSFET. Q21 to Q25 and resistors R21 to R23 are provided. In FIG. 5, it is emphasized that the control voltage source VDD and the reference potential source GND are connected to the comparator CMP21, the flip-flop FF21, and the inverter INV21 for the sake of convenience. In addition, the control voltage source VDD and the reference potential source GND are connected to the comparator, the flip-flop, and the inverter. Control power output from the control voltage generator 22 is supplied from the control voltage source VDD, as will be described later.

<Configuration of Capacitance Element Unit 121>
The switch elements Q22 and Q24 and the capacitor C4 constitute a capacitive element unit 121. One end of the capacitor C4 is connected to the gate of the switch element Q22 via the contact B0. A reference potential source GND is connected to the other end of the capacitor C4, and a source of the switch element Q22 and a source of the switch element Q24 are also connected to the reference potential source GND.

  The gate of the switch element Q24 is connected to the drain of the switch element Q22 via the switch element Q21 and the drive unit 123. Specifically, the source of the switch element Q21 is connected to the drain of the switch element Q22, and the gate of the switch element Q24 is connected to the drain of the switch element Q21 via the drive unit 123.

  Further, one end of the capacitor C5 in FIG. 1 is connected to the drain of the switch element Q22 via the switch element Q21, the drive unit 123, the contact B1, and the terminal P4 in FIG. Specifically, the source of the switch element Q21 is connected to the drain of the switch element Q22, and the contact B1 is connected to the drain of the switch element Q21 via the drive unit 123. A terminal P4 is connected to the contact B1 as shown in FIG. 3, and one end of a capacitor C5 is connected to the terminal P4 as shown in FIG.

  Returning to FIG. 5, the contact B2 is also connected to the contact B1. The contact A1 of FIG. 3 is connected to the contact B2.

  The gate of the switch element Q11 shown in FIG. 4 is connected to the drain of the switch element Q24 through the contact B4 and the contact A3 in FIG. 3, and the contact B3 is connected through the drive unit 123.

<Configuration of a portion of the second control unit 12 excluding the capacitive element unit 121>
A contact B1 is connected to the gate of the switch element Q21 via a resistor R21, and a reference potential source GND is connected to the gate of the switch element Q21 via a switch element Q23. Specifically, the gate of the switch element Q21 is connected to the drain of the switch element Q23, and the source of the switch element Q23 is connected to the reference potential source GND.

  The contact B4 is also connected to a diode D21 and a time constant circuit 122 including a resistor R22 and a capacitor C21. Specifically, the anode of the diode D21 and one end of the resistor R22 are connected to the contact B4. The gate of the switch element Q25 is connected to the cathode of the diode D21 and the other end of the resistor R22, and the reference potential source GND is connected via the capacitor C21.

  The reference potential source GND is connected to the source of the switch element Q25, the control voltage source VDD is connected to the drain of the switch element Q25 via the resistor R23, and the input terminal of the inverter INV21 is connected. A contact B7 is also connected to the input terminal of the inverter INV21. Contacts B5 and B6 are connected to the output terminal of the inverter INV21.

  The output terminal of the flip-flop FF21 is connected to the gate of the switch element Q23, and the contact B9 is connected to the set terminal of the flip-flop FF21. The output terminal of the comparator CMP21 is connected to the reset terminal of the flip-flop FF21. The contact B8 is connected to the inverting input terminal of the comparator CMP21, the positive electrode of the DC power supply Vref is connected to the non-inverting input terminal of the comparator CMP21, and the reference potential source GND is connected to the negative electrode of the DC power supply Vref. Is done.

[Configuration of Startup Circuit Section 13]
FIG. 6 is a circuit diagram of the activation circuit unit 13. The startup circuit unit 13 includes switch elements Q31 to Q35 configured by N-channel MOSFETs, and resistors R31 and R32.

  A contact E6 is connected to the source of the switch element Q31, and a contact E2 is connected to the drain of the switch element Q31 via a resistor R31. A contact E2 is connected to the gate of the switch element Q31 via a resistor R32, and each drain of the switch elements Q32 to Q35 is connected. The contact E1 is connected to the gate of the switch element Q32, the contact E5 is connected to the gate of the switch element Q33, the contact E4 is connected to the gate of the switch element Q34, and the gate of the switch element Q35 is Contact E3 is connected. A reference potential source GND is connected to each source of the switch elements Q32 to Q35.

[Configuration of Constant Current Supply Unit 14]
FIG. 7 is a circuit diagram of the constant current supply unit 14. The constant current supply unit 14 includes a flip-flop FF41 composed of a NAND gate, an inverter INV41, a negative logical product NAND41, switch elements Q41 and Q42 composed of P-channel MOSFETs, and current sources S41 and S42. Prepare.

  The contact F1 is connected to the reset terminal of the flip-flop FF41, the contact F2 is connected to the set terminal of the flip-flop FF41, and the input terminal of the inverter INV41 is connected to the output terminal of the flip-flop FF41. Are connected to one of the two input terminals. The contact F3 is connected to the other of the two input terminals of the negative logical product NAND41, and the gate of the switch element Q41 is connected to the output terminal of the negative logical product NAND41. The contact F4 is connected to the drain of the switch element Q41, and the current source S41 connected to the control voltage source VDD is connected to the source of the switch element Q41. The gate of the switch element Q42 is connected to the output terminal of the inverter INV41, the contact F5 is connected to the drain of the switch element Q42, and the current source S42 connected to the control voltage source VDD is connected to the source of the switch element Q42. Is connected.

[Configuration of Low Voltage Malfunction Prevention Circuit Unit 15]
FIG. 8 is a circuit diagram of the low-voltage malfunction prevention circuit unit 15. The low-voltage malfunction prevention circuit unit 15 includes a comparator CMP51, switch elements Q51 and Q52 formed of N-channel MOSFETs, and resistors R51 to R53.

  The resistor R51 and the resistor R52 are connected in series, and the control voltage source VDD and the reference potential source GND are connected through the resistors R51 and R52 connected in series. Specifically, one end of the resistor R51 is connected to the control voltage source VDD, one end of the resistor R52 is connected to the other end of the resistor R51, and the reference potential source GND is connected to the other end of the resistor R52. The resistor R52 is connected in parallel with the resistor R53 and the switch element Q51 connected in series and the resistor R53 and the switch element Q52 connected in series. Specifically, one end of the resistor R53 is connected to the connection point between the resistor R51 and the resistor R52, and the drains of the switch elements Q51 and Q52 are connected to the other end of the resistor R53. A reference potential source GND is connected to each source of the switch elements Q51 and Q52. The contact G1 is connected to the gate of the switch element Q51, and the contact G4 is connected to the gate of the switch element Q52. Further, the inverting input terminal of the comparator CMP51 is also connected to the connection point between the resistor R51 and the resistor R52. The contact G2 is connected to the non-inverting input terminal of the comparator CMP51, and the contact G3 is connected to the output terminal of the comparator CMP51.

[Configuration of Oscillation Control Unit 16]
FIG. 9 is a circuit diagram of the oscillation control unit 16. The oscillation control unit 16 includes an output voltage upper limit control unit 161, an on trigger generation unit 162, an on width control unit 163, a flip-flop FF61 composed of a NAND gate, an inverter INV61, and a negative logical product NAND61. .

  The output voltage upper limit control unit 161 is connected to contacts H5 and H6 and an ON width control unit 163. The on-width controller 163 is also connected to the contact H6 and the second reset terminal of the flip-flop FF61. The on-trigger generator 162 is connected to the set terminal of the flip-flop FF61, and the contact H4 is connected to the first reset terminal of the flip-flop FF61. The four input terminals of the NAND circuit NAND61 are connected to the contacts H1 to H3 and the output terminal of the flip-flop FF61, respectively. The input terminal of the inverter INV61 is connected to the output terminal of the negative logical product NAND61, and the contact H7 is connected to the output terminal of the inverter INV61.

[Configuration of Oscillation Stop Control Unit 17]
FIG. 10 is a circuit diagram of the oscillation stop control unit 17. The oscillation stop control unit 17 includes a flip-flop FF71 formed of a NAND gate, an inverter INV71, and a negative logical product NAND71.

  A contact J5 is connected to the reset terminal of the flip-flop FF71, a contact J2 is connected to the output terminal of the flip-flop FF71, and contacts J1 and J7 are connected to the inverted output terminal of the flip-flop FF71. The set terminal of the flip-flop FF71 is connected to the output terminal of the NAND NAND 71. One of the two input terminals of the NAND NAND 71 is connected to the contact J4, and the two input terminals of the NAND NAND 71. The other is connected to the output terminal of the inverter INV71. Contacts J3 and J6 are connected to the input terminal of the inverter INV71.

[Configuration of Terminal Voltage Detection Unit 18]
FIG. 11 is a circuit diagram of the terminal voltage detector 18. The terminal voltage detection unit 18 includes an inverter INV81, a switch element Q81 formed of an N-channel MOSFET, and a resistor R81.

  The contact point K2 is connected to the gate of the switch element Q81, the reference potential source GND is connected to the source of the switch element Q81, and the control voltage source VDD is connected to the drain of the switch element Q81 via the resistor R81. The The control voltage source VDD is also connected to an input terminal of an inverter INV81 via a resistor R81. Contacts K1 and K3 are connected to the output terminal of the inverter INV81.

[Configuration of Output Voltage Masking Section 19]
FIG. 12 is a circuit diagram of the output voltage mask unit 19. The output voltage mask unit 19 includes a counter unit 191, a negative logical product NAND 91, and an inverter INV 91.

  The counter unit 191 is connected to the contact L2 and one of the two input terminals of the NAND NAND 91. The output terminal of the inverter INV91 is connected to the other of the two input terminals of the negative logical product NAND91, and the contact L1 is connected to the input terminal of the inverter INV91. A contact L3 is connected to the output terminal of the NAND NAND 91.

[Operation of control circuit 2 in normal mode]
Regarding the control circuit 2 having the above configuration, first, the operation in the normal mode will be described below with reference to FIGS.

In the normal mode, the mode switching signal generator 70 in FIG. 1 turns on the phototransistor PT1. Then, the capacitor C4 is discharged by the resistor R1 and the phototransistor PT1, and the voltage V _P1 at the terminal P1 drops to substantially zero. According to this, as shown in FIG. 3, the voltage of the contact B0 of the second control unit 12 connected to the terminal P1 is also lowered, and the switch element Q22 of FIG. 5 is turned off.

  Further, the capacitor C5 of FIG. 1 is connected to the gate of the switch element Q21 via the resistor R21, the contact B1, and the terminal P4 of FIG. 3, and this capacitor C5 is connected to the control winding T2 via the diode D1. Connected in parallel. Here, in the normal mode, since the switching element Q1 oscillates as described above, a voltage is generated across the control winding T2. Therefore, the voltage across the capacitor C5 is substantially equal to the voltage generated across the control winding T2. Therefore, the gate voltage is applied to the switch element Q21 in FIG. However, the switch element Q21 is turned off by the comparator CMP21, the flip-flop FF21, and the switch element Q23.

Specifically, the terminal P1 of FIG. 3 is connected to the inverting input terminal of the comparator CMP21 via the contact B8. The comparator CMP21 compares the voltage V _{P1 at the} terminal P1 with the positive voltage of the DC power supply Vref, and outputs an H level voltage if the voltage V _{P1 at the} terminal _P1 is less than Vth1.

Here, in the normal mode, as described above, the voltage V _P1 of the terminal P1 drops to substantially zero, so the voltage V _{P1 of the} terminal P1 becomes less than Vth1, and as a result, the comparator CMP21 outputs an H level voltage. . This H level voltage is applied to the reset terminal of the flip-flop FF21. On the other hand, since the voltage V _{P1 of the} terminal P1 is also less than Vth2, the switch element Q81 in FIG. 11 whose gate is connected to the terminal P1 through the contact K2 of the terminal voltage detector 18 is turned off, and the inverter INV81 is at the L level. Output voltage. This L level voltage is applied to the set terminal of the flip-flop FF21 of FIG. 5 via the contact K3 and the contact B9 of the second controller 12 of FIG. Here, Vth2 indicates the threshold voltage of the switch element constituted by the N-channel MOSFET in the present embodiment. This switch element is turned on when the gate-source voltage is equal to or higher than Vth2, and the gate-source voltage. Is less than Vth2, it is assumed to be in an off state.

  As described above, in the flip-flop FF21, the H level voltage is applied to the reset terminal and the L level voltage is applied to the set terminal. Therefore, an H level voltage is output from the output terminal of the flip-flop FF21, and the switch element Q23 is turned on. According to this, the gate voltage of the switch element Q21 is extracted, and the switch element Q21 is turned off.

  The drive unit 123 in FIG. 5 turns on the switch element Q24 when at least one of the switch elements Q21 and Q22 is in the off state. For this reason, since both the switch elements Q21 and Q22 are in the off state as described above, the switch element Q24 is in the on state, and as a result, the contact B4 and the reference potential source GND are electrically connected.

  The contact B4 is connected to the contact A3 of the control power supply switch unit 11 in FIG. 3, and the contact A3 is connected to the gate of the switch element Q11 in FIG. For this reason, when the contact B4 and the reference potential source GND are conducted as described above, the switch element Q11 is turned on, and the contact A1 and the contact A4 are conducted.

  The contact A1 is connected to the capacitor C5 via the contact B2 of the second controller 12 in FIG. 3, the contact B1 in FIG. 5, and the terminal P4 in FIG. Therefore, when the switch element Q11 is turned on, the capacitor C5 and the first control unit 10 are brought into conduction, and the control voltage generation unit 22 supplies control power to various circuits of the control circuit 2 as the control voltage source VDD. Will be supplied. According to this, various circuits of the control circuit 2 operate, and a control signal is supplied to the gate of the switch element Q1 in FIG. 1 according to the periodic signal output from the on trigger generation unit 162 in FIG. The switch element Q1 oscillates.

[Operation of Control Circuit 2 in Standby Mode]
Next, the operation of the control circuit 2 in the standby mode will be described below with reference to FIGS. 1 to 12 described above and FIG. 13 described later.

FIG. 13 is a timing chart of the control circuit 2 in the standby mode. ST _Q1 indicates the state of the switch element Q1 in FIG. 1, and ST ₁₃ indicates the state of the activation circuit unit 13 in FIG. ST _Q11 shows the state of the switch element Q11 in FIG. 4, and ST _CMP51 shows the state of the comparator CMP51 in FIG. V _INV91 indicates a voltage output from the inverter INV91 of FIG. V ₁₉₁ indicates a voltage output from the counter unit 191, and V _{NAND 91} indicates a voltage output from the negative logical product NAND 91.

First, at time t1, the voltage V _{P1 at the} terminal _P1 is zero. For this reason, the switch element Q22 in FIG. 5 is turned off.

Further, the gate of the switch element Q81 in FIG. 11 is connected to the terminal P1 through the contact K2 of the terminal voltage detector 18. Therefore, when the voltage V _{P1 at the} terminal P1 is zero, the switch element Q81 is turned off, and an L level voltage is output from the output terminal of the inverter INV81. This L level voltage is applied to the set terminal of the flip-flop FF21 of FIG. 5 via the contact K3 and the contact B9 of the second controller 12 of FIG. Therefore, an H level voltage is output from the output terminal of the flip-flop FF21, and the switch element Q23 is turned on. Therefore, as described above, the gate voltage of the switch element Q21 is extracted, and the switch element Q21 is turned off.

  As described above, since both the switch elements Q21 and Q22 are in the off state, the drive unit 123 turns on the switch element Q24 and the switch element Q11 in FIG. 4 is turned on as described above.

  According to this, the capacitor C5 of FIG. 1 and the first control unit 10 are brought into conduction, and the control power is supplied from the control voltage source VDD to various circuits of the control circuit 2.

  The control power supplied to the first control unit 10 is applied to the non-inverting input terminal of the comparator CMP51 in FIG. 8 via the contact G2 of the low voltage malfunction prevention circuit unit 15 in FIG. The comparator CMP51 has a hysteresis characteristic, outputs an H level voltage when the voltage at the non-inverting input terminal is equal to or higher than the first threshold voltage, and the voltage at the non-inverting input terminal is lower than the first threshold voltage. When the voltage is equal to or lower than the threshold voltage of 2, an L level voltage is output. Here, the control voltage supplied to the first controller 10 is higher than the first threshold voltage. Therefore, when the control power supplied to the first control unit 10 is applied to the non-inverting input terminal, the H level voltage is output from the output terminal of the comparator CMP51, and the voltage at the contact point G3 becomes the H level voltage. . The H level voltage is applied to the reset terminal of the flip-flop FF41 in FIG. 7 via the contact F1 of the constant current supply unit 14 in FIG.

On the other hand, at time t1, the voltage VP2 at the terminal _P2 is Vth3. The output voltage limit control unit 161 of FIG. 9 is connected to the terminal P2 via the contact H6, voltage _{V P2} of the terminal P2 is equal to or Vth3 less, and outputs the L level voltage. For this reason, at time t1, the output voltage upper limit control unit 161 outputs an L level voltage, and this L level voltage is applied to the contact H5, the contact J6 of the oscillation stop control unit 17 in FIG. 3, the contact J3 in FIG. 3 is applied to the input terminal of the inverter INV91 shown in FIG. Therefore, the voltage _{V INV91} output from the inverter INV91 becomes a H-level voltage, and thus applied to the other of the two input terminals of the NAND NAND91. The counter unit 191 in FIG. 12 outputs an H level voltage at time t1, although details will be described later. Therefore, the voltage V ₁₉₁ output from the counter unit 191 becomes an H level voltage, and is applied to one of the two input terminals of the NAND NAND 91. Therefore, the voltage V _NAND91 output from the negative logical product NAND91 is an L level voltage. The L level voltage is applied to the set terminal of the flip-flop FF41 of FIG. 7 via the contact L3 and the contact F2 of the constant current supply unit 14 of FIG.

  As described above, in the flip-flop FF41, the H level voltage is applied to the reset terminal and the L level voltage is applied to the set terminal. For this reason, the H level voltage is output from the output terminal of the flip-flop FF41, converted into the L level voltage by the inverter INV41, and the switch element Q42 is turned on. According to this, the constant current output from the current source S42 is supplied to the capacitor C4 via the switch element Q42, the contact F5, and the terminal P1 in FIG. 3, and the capacitor C4 is charged.

  In addition, the H level voltage output from the output terminal of the flip-flop FF41 is also applied to one of the two input terminals of the NAND circuit NAND41. On the other hand, the L level voltage output from the above-described inverter INV81 is applied to the other of the two input terminals of the NAND NAND 41 via the contact F3 and the contact K1 of the terminal voltage detection unit 18 of FIG. . For this reason, an H level voltage is output from the NAND circuit NAND41 of FIG. 7 and the switch element Q41 is turned off, so that no constant current is supplied from the current source S41 to the capacitor C4.

According to the above, charging of the capacitor C4 with the constant current supplied from the current source S42 is started at time t1, and the voltage V _P1 at the terminal P1 rises as time passes, and becomes Vth2 at time t2.

Next, at time t2, when the voltage V _{P1 at the} terminal P1 becomes Vth2, the switch element Q81 in FIG. 11 is turned on. Then, an H level voltage is output from the output terminal of the inverter INV81, and this H level voltage is supplied to the two NAND circuits NAND41 of FIG. 7 via the contact K1 and the contact F3 of the constant current supply unit 14 of FIG. Applied to the other input terminal. Therefore, since the L level voltage is output from the NAND circuit NAND41 in FIG. 7 and the switch element Q41 is turned on, the constant current output from the current source S41 is changed to the switch element Q41, the contact F4, and The voltage is supplied to the capacitor C4 via the terminal P1, and the capacitor C4 is charged.

According to the above, at time t2, charging of the capacitor C4 by the constant current supplied from the current source S41 and the constant current supplied from the current source S42 is started, and the voltage V _P1 at the terminal P1 It rises as time passes and becomes Vth1 at time t3.

Further, at time t2, the voltage _{V P1} of the terminal P1 is becomes to Vth2, voltage becomes Vth2 contact E3 of the starting circuit portion 13 of FIG. 3, the switch element Q35 of FIG. 6 is turned on. For this reason, the gate voltage of the switch element Q31 is extracted, and the switch element Q31 is turned off.

  According to the above, at time t2, the switch element Q31 is fixed in the off state, and the operation of the activation circuit unit 13 is prohibited.

Further, at time t2, the voltage _{V P2} of the terminal P2 is Vth3 less, the output voltage limit control unit 161 of FIG. 9, and outputs the L level voltage. This L level voltage is applied to the input terminal of the inverter INV71 of FIG. 10 via the contact H5 and the contact J6 of the oscillation stop control unit 17 of FIG. 3, and the H level voltage is applied to the two input terminals of the negative logical product NAND71. The other is applied. On the other hand, one of the two input terminals of the NAND NAND 71 has an H level voltage output from the inverter INV81 of FIG. 11 described above via the contact J4 and the contact K3 of the terminal voltage detection unit 18 of FIG. Applied.

  As described above, the L level voltage is output from the output terminal of the NAND circuit NAND71 in FIG. 10, and this L level voltage is the flip-flop FF71, the contact J7, the contact H4 of the oscillation control unit 16 in FIG. This is applied to one of the four input terminals of the NAND NAND 61 via the flip-flop FF61. According to this, regardless of what voltage is applied to the other three of the four input terminals of the NAND NAND 61, an H level voltage is output from the output terminal of the NAND NAND 61. This H level voltage is converted to an L level voltage by the inverter INV61, and then applied to the gate of the switch element Q1 in FIG. 1 via the contact H7 and the terminal P6 in FIG.

  According to the above, at time t2, the switch element Q1 is fixed in the off state, and the switch element Q1 is prohibited from oscillation.

At time t2, when the voltage V _{P1 at the} terminal P1 becomes Vth2, the switch element Q22 in FIG. 5 is turned on. On the other hand, the switch element Q21 is maintained in the OFF state by the comparator CMP21, the flip-flop FF21, and the switch element Q23 of FIG.

Specifically, the voltage V _{P1 at the} terminal P1 is Vth2 lower than Vth1 at time t2. Therefore, if the voltage V _{P1 at the} terminal P1 is less than Vth1, the comparator CMP21 that outputs the H level voltage outputs the H level voltage. Therefore, the H level voltage is applied to the reset terminal of the flip-flop FF21. On the other hand, an H level voltage is applied to the set terminal of the flip-flop FF21 from the output terminal of the inverter INV81 of FIG. 11 via the contact B9 and the contact K3 of the terminal voltage detector 18 of FIG.

  As described above, in the flip-flop FF21, the H level voltage is applied to the reset terminal and the H level voltage is applied to the set terminal. Therefore, the H level voltage is output from the output terminal of the flip-flop FF21 without change from the previous state held, and the switch element Q23 is maintained in the on state. According to this, as described above, the gate voltage of the switch element Q21 is pulled out and the switch element Q21 is maintained in the off state.

  As described above, at time t2, the switch element Q22 is turned on, but the switch element Q21 is maintained in the off state. As described above, the drive unit 123 turns on the switch element Q24 if at least one of the switch elements Q21, Q22 is off. Therefore, the switch element Q24 is maintained in the ON state, and the contact B4 and the reference potential source GND are brought into conduction through the switch element Q24.

  According to the above, at time t2, the switch element Q11 of FIG. 4 is maintained in the on state.

Next, when the voltage V _{P1 at the} terminal P1 becomes Vth1 at time t3, the comparator CMP21 in FIG. 5 outputs an L level voltage, so that the switch element Q23 is turned off, and the gate of the switch element Q21 has a resistance The voltage V _C5 across the capacitor _C5 is applied via R21, the contact B1, and the terminal P4 in FIG. Therefore, the switch element Q21 is turned on. As described above, the drive unit 123 turns on the switch element Q24 if at least one of the switch elements Q21, Q22 is in the off state, but if both the switch elements Q21, Q22 are in the on state, Element Q24 is turned off. According to this, the gate of the switch element Q11 in FIG. 4 is connected to the capacitor via the contact A3, the contact B4 of the second control unit 12 in FIG. 3, the drive unit 123, the contact B1, and the terminal P4 in FIG. A voltage V _C5 across _C5 is applied.

  According to the above, at time t3, the gate of the switch element Q11 is not driven, and the switch element Q11 is turned off. For this reason, the capacitor C5 and the first control unit 10 are insulated, and supply of control power from the control voltage source VDD to various circuits of the control circuit 2 is stopped. According to this, the operation of the first control unit 10 is stopped, and the operations of the comparator CMP21, the flip-flop FF21, and the inverter INV21 in the second control unit 12 are also stopped. Therefore, the operation of the comparator CMP51 in FIG. 8 is stopped, and the inverter INV91, the counter unit 191 and the negative logical product NAND91 in FIG. 12 are stopped.

Here, the switch element Q11 that has been turned off at time t3 remains off until time t4 described later. For this reason, in the period from time t3 to t4, the supply of control power to various circuits of the control circuit 2 is stopped, so that the operation of the first control unit 10 is completely stopped and the second control unit Only a part of 12 operates. When the operation of the first control unit 10 is completely stopped, the high impedance state is established between the terminal P1 and the terminal P3 (at least in the direction of the positive polarity of the terminal P1). It is assumed that the control circuit 2 is configured, and even if the supply of control power is stopped, the capacitor C4 is not discharged due to current flowing into the control circuit 2. However, since the capacitor C4 is discharged by the resistor R1 connected in parallel, the voltage V _{P1 at the} terminal P1 gradually decreases as time passes.

Further, the voltage V _C5 across the capacitor C5 applied to the gate of the switching element Q11 at time t3 continues to be applied until time t4 described later. The voltage V _C5 across the capacitor C5 is also applied to the capacitor C21 during the period from time t3 to time t4, so that the capacitor C21 is charged.

Next, at time t4, the output voltage lower limit detection unit 60 in FIG. 1 detects that the output voltage _VOUT has decreased to the lower limit voltage, and turns on the phototransistor PT1. Then, the capacitor C4 is rapidly discharged, and the voltage V _P1 at the terminal P1 becomes zero. When the voltage V _P1 terminal P1 becomes zero, the switching element Q22 in FIG. 5 because the off state, the switching element Q11 in FIG. 4 is turned on as described above. Then, since the supply of control power to the various circuits of the control circuit 2 is resumed, the switch element Q1 in FIG. 1 can oscillate.

Further, at time t4, when the voltage V _{P1 of the} terminal P1 becomes zero as described above, the switch element Q35 of FIG. 6 whose gate is connected to the terminal P1 via the contact E3 of the activation circuit unit 13 is turned off. . For this reason, the fixed off state of the switch element Q31 is released. According to this, the prohibition of operation of the activation circuit unit 13 is released.

  However, at time t4, the switch element Q25 is turned on by the voltage across the capacitor C21 of FIG. 5 charged as described above. For this reason, the H level voltage is applied to the gate of the switch element Q32 in FIG. 6 via the inverter INV21, the contact B5, and the contact E1 of the activation circuit unit 13 in FIG. 3, and the switch element Q32 is turned on. According to this, the gate voltage of the switch element Q31 is extracted, and the switch element Q31 is turned off.

  According to the above, at time t4, the switch element Q31 is turned off, and the operation of the activation circuit unit 13 is stopped.

  At time t4, the switch element Q25 is in the on state as described above. Therefore, the H level voltage is applied to the gate of the switch element Q51 of FIG. 8 via the inverter INV21, the contact B6, and the contact G1 of the low voltage malfunction prevention circuit unit 15 of FIG. Therefore, the switch element Q51 is turned on, and the resistor R53 is connected in parallel to the resistor R52. According to this, the threshold voltage used by the comparator CMP51 is fixed to the second threshold voltage described above.

  As described above, at time t4, the threshold voltage used by the comparator CMP51 is fixed to the second threshold voltage.

At time t4, the output voltage upper limit detection unit 50 in FIG. 1 detects that the output voltage _VOUT is less than the upper limit voltage, and turns off the phototransistor PT2. Here, since the contact H6 of FIG. 9 is pulled up by the output voltage upper limit control unit 161, when the phototransistor PT2 is turned off, the contact H6 of FIG. 1 connected to the contact H6 via the terminal P2 of FIG. Capacitor C6 is charged, and voltage V _{P2 at} terminal P2 rises as time passes. However, at time t4, the voltage _{V P2} of the terminal P2 is Vth3 less, is L-level voltage is output from the output voltage limit control section 161, the L level voltage, the contact H5, the oscillation stop control unit of FIG. 3 17 Is applied to the input terminal of the inverter INV91 of FIG. 12 via the contact J6 of FIG. 10, the contact J3 of FIG. 10, and the contact L1 of the output voltage mask unit 19 of FIG. Therefore, the voltage _{V INV91} output from the inverter INV91 becomes the H level voltage.

  At time t4, as described above, the H level voltage is output from the inverter INV21 of FIG. This H level voltage is applied to the counter unit 191 via the contact point B6 and the contact point L2 of the output voltage mask unit 19 of FIG. When the H level voltage is applied, the counter unit 191 determines that the supply of control power to the various circuits of the control circuit 2 has been resumed in the standby mode, not when the isolated switching power supply 1 is started. . Then, the counter unit 191 starts measuring the time after the supply of control power to the various circuits of the control circuit 2 is resumed, and outputs an L level voltage. Note that the counter unit 191 always outputs the H level voltage in a state where the CMP 51 in FIG. 8 outputs the H level voltage except during the above-described time measurement period.

  Here, during the period in which the counter unit 191 outputs the L level voltage, the negative AND NAND 91 outputs the H level voltage regardless of the output of the inverter INV91. This H level voltage is applied to the set terminal of the flip-flop FF41 of FIG. 7 via the contact L3 and the contact F2 of the constant current supply unit 14 of FIG. For this reason, during the period in which the counter unit 191 outputs the L level voltage, it is prohibited to apply the L level voltage to the set terminal of the flip-flop FF41, and the switching elements Q41 and Q42 are prohibited from being turned on. As a result, charging of the capacitor C4 in FIG. 1 is prohibited.

Then, at time t5, next voltage _{V P2} is Vth3 terminal P2 of FIG. 1, in a period from time t9 will be described later, the voltage _{V P2} of the terminal P2 is higher than Vth3. Therefore, in a period from time t5 to t9, the output voltage limit control unit 161 of FIG. 9 voltage _{V P2} of the terminal P2 is for outputting the L level voltage if Vth3 below, outputs an H level voltage. Therefore, the voltage _{V INV91} output from the inverter INV91 shown in FIG. 12, the L level voltage, and thus applied to the other of the two input terminals of the NAND NAND91. Therefore, the voltage V _NAND91 output from the negative logical product NAND91 is maintained at the H level voltage.

  Next, at time t6, the voltage across capacitor C21 of FIG. 5 charged as described above decreases until both switch element Q32 of FIG. 6 and switch element Q51 of FIG. 8 are turned off. Note that the time from t4 to t6 is determined by the time constant of the time constant circuit 122 in FIG.

  According to the above, at time t6, the operation stop of the activation circuit unit 13 is released, the activation circuit unit 13 becomes operable, and the threshold voltage used by the comparator CMP51 is fixed to the second threshold voltage. Is released.

Next, at time t7, it is assumed that a predetermined time has elapsed since the time measurement by the counter unit 191 was started at time t4. Then, the counter unit 191 outputs an H level voltage. Therefore, the voltage V ₁₉₁ output from the counter unit 191 becomes an H level voltage, and the prohibition of charging of the capacitor C4 in FIG. 1 is released. However, the voltage _{V INV91} output from the inverter INV91 remains at L-level voltage. As described above, the voltage V _NAND91 output from the _{NAND NAND 91} is maintained at the H level voltage.

Next, at time t8, the output voltage upper limit detection unit 50 in FIG. 1 detects that the output voltage _VOUT has reached the upper limit voltage, and turns on the phototransistor PT2. Then, the capacitor C6 is discharged, and decrease the voltage _{V P2} of the terminal P2, the at time t9 Vht3.

Then, at time t9, the voltage _{V P2} of the terminal P2 becomes Vth3. Then, the output voltage limit control unit 161 of FIG. 9 outputs the L level voltage, the voltage _{V INV91} output from the inverter INV91 in FIG. 12, the H level voltage. Here, at time t9, since the voltage V ₁₉₁ output from the counter unit 191 is the H level voltage, the voltage V _{NAND 91} output from the negative logical product NAND ₉₁ becomes the L level voltage. According to this, the L level voltage is applied to the set terminal of the flip-flop FF41 of FIG. 7, the switch element Q42 is turned on, and as a result, charging of the capacitor C4 by the current source S42 is started.

  Thereafter, at times t9 to t11, the control circuit 2 operates in the same manner as at times t1 to t3.

  According to the above insulation type switching power supply 1, the following effects can be produced.

In the isolated switching power supply 1, in the standby mode, if the output voltage _VOUT is equal to or lower than the lower limit voltage, the phototransistor PT1 is turned on, and the voltage VP1 at the terminal _P1 is lowered. As a result, the switch shown in FIG. The element Q11 is turned on, and the supply of control power to the various circuits of the control circuit 2 is resumed. If the output voltage _VOUT is equal to or lower than the lower limit voltage, the phototransistor PT2 is turned off because the output voltage _VOUT is less than the upper limit voltage. As described above, in the standby mode, if the output voltage _VOUT is equal to or lower than the lower limit voltage, the control circuit 2 starts to operate and starts charging the capacitor C6. As a result, as the voltage across the capacitor C6 increases. Thus, the voltage V _{P2 at the} terminal P2 starts to rise.

Here, the period due to the capacitance component of the capacitor C6, i.e. the period until the voltage _{V P2} of the terminal P2 becomes the voltage corresponding to the output voltage _{V OUT,} the voltage _{V P2} of the terminal P2 corresponds to the output voltage _{V OUT} Even though not a voltage, the voltage V _P2 of the terminal P2 is L level voltage is output from the output voltage limit control section 161 to be Vth3 less. However, when the above-described supply of control power is resumed in the standby mode, the output voltage upper limit is exceeded in a period (a period from time t4 to t7 in FIG. 13) until a predetermined time elapses after resumption. Even if the control unit 161 outputs the L level voltage, the H level voltage is forcibly applied to the set terminal of the flip-flop FF41 to prohibit the L level voltage from being applied. According to this, by setting the predetermined time described above, in a period in which not the voltage to which the voltage V _P2 of the terminal P2 corresponds to the output voltage V _OUT, the capacitor by the current source S41 and a current source S42 C4 Can be prevented from being erroneously charged, and malfunction can be prevented from occurring when the supply of control power to various circuits of the control circuit 2 is resumed.

  In addition, the insulating switching power supply 1 is configured to operate in a part of the switching suspension period in the standby mode, such as the period from time t3 to t4 in the period from time t2 to t4 in FIG. The switch element Q11 is turned off, and power supply from the capacitor C5 in FIG. 1 to the first control unit 10 is stopped. For this reason, the power consumption of the insulating switching power supply 1 in the standby mode can be reduced.

  In addition, the insulating switching power supply 1 supplies the current from the constant current supply unit 14 to the capacitor C4 in the first control, for example, during a period from time t1 to t3 in FIG. 13 or from time t9 to t11. This is performed within a period in which the unit 10 receives power from the capacitor C5 in FIG. For this reason, the constant current supply unit 14 can be incorporated in the first control unit 10, and the power consumption of the insulating switching power supply 1 in the standby mode can be further reduced.

  Further, as described above, the insulating switching power supply 1 turns off the switch element Q11 in FIG. 4 during the part of the switching pause period in the standby mode, and performs the first control from the capacitor C5 in FIG. The power supply to the unit 10 is stopped. For this reason, the power consumption of the insulated switching power supply 1 can be reduced without setting the voltage across the capacitor C5 of FIG. 1 to 0 V during the switching pause period in the standby mode. Accordingly, in the standby mode, it is not necessary to operate the activation circuit unit 13 when shifting from the switching pause period to the oscillation period, and therefore, the power consumption of the insulating switching power supply 1 can be sufficiently reduced.

In addition, when the isolated switching power supply 1 detects that the output voltage _VOUT is equal to or lower than the lower limit voltage by the output voltage lower limit detection unit 60 in FIG. 1, the phototransistor PT1 is turned on, for example, at time t4 in FIG. The capacitor C4 is rapidly discharged. According to this, the second control unit 12 turns on the switch element Q11 in FIG. 4, and the switching of the switch element Q1 in FIG. 1 is resumed. For this reason, it is possible to prevent the output voltage _VOUT from becoming less than the lower limit voltage.

Further, the isolated switching power supply 1 has a phototransistor PT1 when the output voltage _VOUT is detected to be lower than the lower limit voltage by the output voltage lower limit detection unit 60 of FIG. 1 or when operating in the normal mode. Turn on the. For this reason, since the phototransistor PT1 can be shared for the above two cases, the power consumption of the insulating switching power supply 1 in the standby mode can be reduced at a low cost.

  Further, in the insulated switching power supply 1, the capacitor C21 in FIG. 5 is charged during a period in which the switch element Q11 in FIG. 4 is in an OFF state, for example, during a period from time t3 to t4 in FIG. Therefore, the case where the power supply to the insulating switching power source 1 is started and the case where the power supply from the capacitor C5 in FIG. 1 to the first control unit 10 is resumed in the standby mode are the capacitor C21 in FIG. Can be identified by the voltage across For this reason, when power supply from the capacitor C5 in FIG. 1 to the first control unit 10 is resumed in the standby mode, the first operation is different from the case where the power supply to the insulating switching power supply 1 is started. When the power supply to the control unit 10 is resumed, an appropriate operation can be performed.

  In the insulated switching power supply 1, a resistor R1 is connected in parallel to the capacitor C4 in FIG. Therefore, the capacitor C4 cannot be discharged by turning on the phototransistor PT1 when an abnormality such as taking a peak load exceeding the capability of the isolated switching power supply 1 in the standby mode occurs. In addition, the capacitor C4 can be discharged by the resistor R1. Therefore, the operation of the startup circuit unit 13 and the power supply to the first control unit 10 can be resumed within a time determined by the capacitance of the resistor R1 and the capacitor C4 and the residual voltage, and the isolated switching power supply 1 is in an abnormal state. Can be restored to normal.

The insulated switching power supply 1 charges the capacitor C4 only with the current output from the current source S42 in FIG. 7 according to whether or not the voltage V _{P1 at the} terminal P1 is equal to or higher than Vth2, It is controlled whether the current is output from each of the sources S41 and S42. For this reason, it is possible to reduce the loss when there is no need to increase the voltage V _P1 of the terminal P1, and it is possible to rapidly charge the capacitor C4 when it is necessary to increase the voltage V _{P1 of the} terminal P1. . Therefore, the ratio of the period during which power is supplied to the first control unit 10 to the intermittent oscillation period can be reduced, and the power consumption of the insulating switching power supply 1 in the standby mode can be further reduced.

In addition, when the voltage V _P1 at the terminal P1 becomes equal to or higher than Vth1, for example, at time t3 in FIG. 13, the insulated switching power supply 1 turns off the switch element Q11 in FIG. Therefore, time switching element Q11 is turned on, i.e. during the period when the power supply is being performed to the first control unit 10, the voltage V _P1 terminal P1 can be increased up to Vth1. Therefore, the state in which the charge remains in the capacitor C4 can be prolonged, and the intermittent oscillation period can be prolonged. As a result, the power consumption of the insulating switching power supply 1 in the standby mode can be further reduced.

The insulation type switching power supply 1, for example, as the time t2 in FIG. 13, in the voltage _{V P1} of the terminal P1 is Vth2 or more, and, when the output voltage _{V OUT} becomes equal to or higher than the upper limit voltage, stops the switching of the switching element Q1 To do. For this reason, since the oscillation can be stopped immediately when the output voltage _VOUT reaches the upper limit voltage, the ratio of the oscillation period to the intermittent oscillation period, that is, the oscillation duty of the intermittent oscillation can be reduced, and the unit time per unit time can be reduced. The number of oscillations of the switch element Q1 can be reduced. Therefore, the power consumption of the insulating switching power supply 1 in the standby mode can be further reduced.

Further, when the voltage V _{P1 at the} terminal P1 is equal to or higher than Vth2 and the output voltage _VOUT is equal to or higher than the upper limit voltage, the insulated switching power supply 1 stops switching of the switch element Q1. Therefore, the output voltage switching control of the switching element Q1 can be carried out in accordance with the V _OUT, the output voltage V _OUT can be prevented from being higher than the upper limit voltage. Here, the insulating switching power supply 1 can prevent the output voltage _{VOUT from} becoming lower than the lower limit voltage as described above. Therefore, the insulating switching power supply 1 can control the upper limit and the lower limit of the output voltage _VOUT .

Further, when the output voltage _VOUT becomes equal to or higher than the upper limit voltage during the period when power is supplied to the first control unit 10, for example, at time t <b> 1 in FIG. 13, the insulated switching power supply 1 is constant current supply unit 14. To start supplying current to the capacitor C4. For this reason, even during the period when power is supplied to the first control unit 10, the capacitor C4 is not charged unless the output voltage _VOUT rises to the upper limit voltage. Therefore, the capacitor C4 can be charged after securing the output voltage _VOUT to some extent, and malfunction can be prevented.

In addition, the insulated switching power supply 1 prohibits the operation of the startup circuit unit 13 when the voltage V _{P1 of the} terminal P1 becomes equal to or higher than Vth2, for example, at time t2 in FIG. For this reason, even if the power supply to the first control unit 10 is stopped, the startup circuit unit 13 does not operate, so the voltage across the capacitor C5 in FIG. 1 is monitored to stop the operation of the startup circuit unit 13. Thus, the power consumption of the insulating switching power supply 1 can be further reduced without providing a special circuit.

The insulation type switching power supply 1, for example, as a time t4 in FIG. 13, the voltage _{V P1} of the terminal P1 is less than Vth2, the second control unit 12 is turned on and the switching element Q11 in FIG. 4, Switching of the switch element Q1 in FIG. 1 is started. For this reason, the switching of the switching element Q1 can be started before the output voltage V _OUT becomes too low, and the output voltage V _OUT can be prevented from decreasing too much.

The insulation type switching power supply 1, for example, as in the time t4 in FIG. 13, the voltage _{V P1} of the terminal P1 is less than Vth2, releases the operation inhibition of the activation circuit 13. For this reason, during the switching suspension period in the standby mode, when the voltage across the capacitor C5 in FIG. 1 drops to a voltage at which the starting circuit unit 13 must be operated, the starting circuit unit 13 may be operated. It is possible to prevent the output voltage _{VOUT from} being excessively lowered.

  Further, the insulating switching power supply 1 is switched to the time constant circuit of FIG. 5 after the switch element Q11 of FIG. 4 in the off state is turned on in the standby mode, for example, during a period from time t4 to t6 in FIG. In the period until the time determined by the time constant of 122 elapses, the operation of the activation circuit unit 13 is stopped. For this reason, since it is possible to prevent the activation circuit unit 13 from operating even though it is not necessary to operate, the power consumption of the insulating switching power supply 1 in the standby mode can be further reduced.

  Further, the insulating switching power supply 1 is switched to the time constant circuit of FIG. 5 after the switch element Q11 of FIG. 4 in the off state is turned on in the standby mode, for example, during a period from time t4 to t6 in FIG. The threshold voltage used by the comparator CMP51 of FIG. 8 is fixed at the second threshold voltage until the time determined by the time constant 122 elapses. For this reason, even if the intermittent oscillation period is lengthened, the switching control of the switch element Q1 in FIG. 1 can be started immediately without operating the starter circuit section 13, so that the power consumption of the isolated switching power supply 1 is further reduced. it can.

  The present invention is not limited to the above-described embodiment, and various modifications and applications can be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1: Isolated switching power supply 2; Control circuit 10; 1st control part 11; Control power supply switch part 12; 2nd control part 13; Start-up circuit part 14; Constant current supply part 15; 16; Oscillation control unit 17; Oscillation stop control unit 18; Terminal voltage detection unit 19; Output voltage detection delay unit 50: Output voltage upper limit detection unit 60: Output voltage lower limit detection unit 70: Mode switching signal generation unit 121; Capacitance element unit 122; time constant circuit 123; drive unit 191; counter unit C1 to C5, C21: capacitors PT1, PT2: phototransistors Q1, Q11, Q21 to Q25, Q31 to Q35, Q41, Q42, Q51, Q52, Q81: switch element S41, S42; current source T; transformer

Claims (4)

An isolated switching power supply that controls switching in a continuous oscillation state or intermittent oscillation state and controls conversion from an input voltage to a required output voltage,
A control power supply source for supplying control power necessary for the switching control;
Using a control power supplied from the control power supply source, a first control unit that performs switching control of the switch element based on a voltage at a specific point that changes corresponding to the output voltage;
A control power supply switch for short-circuiting or opening the first control unit and the control power supply source;
A second control unit that opens the control power supply switch and stops the supply of control power to the first control unit in at least a part of the switching pause period in the intermittent oscillation state;
In the period from when the supply of control power to the first control unit is restarted until a predetermined time elapses, the voltage at the specific point is assumed to be a predetermined voltage. Voltage mask means to be recognized by the control unit;
An insulated switching power supply comprising: The second control unit includes a capacitor, a first switch element, and a second switch element,
A control terminal of the first switch element is connected to one end of the capacitor,
The other end of the capacitor is connected to the output terminal of the first switch element and the output terminal of the second switch element,
The control terminal of the second switch element is connected to the input terminal of the first switch element, and the control power supply source is connected via a drive unit that drives the second switch element,
The insulated switching power supply according to claim 1, wherein the control power supply switch is connected to an input terminal of the second switch element.   The insulated switching power supply according to claim 1 or 2, wherein the voltage at the specific point changes depending on whether or not the output voltage is equal to or higher than a predetermined upper limit voltage. The voltage at the specific point is equal to or lower than the specific voltage when the output voltage is equal to or higher than a predetermined upper limit voltage, and is higher than the specific voltage when the output voltage is lower than the upper limit voltage.
The voltage mask means sets the voltage at the specific point higher than the specific voltage in a period from when the supply of control power to the first control unit is restarted until a predetermined time elapses. The insulated switching power supply according to claim 3, wherein at least a part of the first control unit is recognized.

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