JP2012103386A - Electro-optic device, projection type display device, and method of manufacturing electro-optic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optic device capable of preventing a hillock from being formed on a surface of a pixel electrode and a cavity from being formed at a part where a recess is filled with a flattening insulating film, a projection type display device, and a method of manufacturing the electro-optic device.SOLUTION: On an element substrate 10 of an electro-optic device 100, a flattening insulating film 17 provided on an upper layer side of a reflective pixel electrode 9a includes a doped silicon oxide film 170 as a layer laminated on the pixel electrode 9a. The doped silicon oxide film 170 has a small difference in coefficient of thermal expansion from an aluminum film constituting the pixel electrode 9a. Consequently, even when the flattening insulating film 17 is formed in a heated state, large thermal stress is generated in neither the pixel electrode 9a nor the flattening insulating film 17, so a defect such as a hillock is hardly generated on the surface of the pixel electrode 9a. Further, the doped silicon oxide film 170 has a superior step covering property.

Description

  The present invention relates to an electro-optical device including an element substrate on which a reflective pixel electrode is formed, a projection display device including the electro-optical device, and a method for manufacturing the electro-optical device.

  In an electro-optical device such as a liquid crystal device, an organic electroluminescence display device, or a plasma display device, an element substrate in which a pixel transistor, an interlayer insulating film, and a pixel electrode are provided in this order on one surface side of a substrate body is used. For example, among electro-optical devices, an element substrate used in a reflective liquid crystal device has a configuration in which a pixel transistor, an interlayer insulating film, a reflective pixel electrode, and an alignment film are provided in this order on one side of the substrate body. (See Patent Document 1).

  In addition, when an oblique deposition film such as a silicon oxide film is used as an alignment film in a liquid crystal device, an insulating film made of a silicon oxide film, a silicon nitride film, or the like is formed as a planarized insulating film on the surface of the reflective pixel electrode. Often done.

JP 2010-139862 A

However, when forming a planarization insulating film on the upper layer side of the reflective pixel electrode, due to heat at the time of forming the planarization insulating film, when a large thermal stress occurs in the pixel electrode and the planarization insulating film, There is a problem that defects such as hillocks occur on the surface of the pixel electrode and the smoothness of the surface of the pixel electrode is lowered. For example, when the reflective pixel electrode is formed of an aluminum film and the planarization insulating film is formed of a non-doped silicon oxide film, the thermal expansion coefficient (23.1 × 10 ⁻⁶ / ° C.) of the aluminum film and the non-doped silicon oxide film ^Therefore , a large thermal stress is generated in the pixel electrode and the planarization insulating film. As a result, defects such as hillocks are generated on the surface of the pixel electrode and the smoothness of the surface of the pixel electrode is lowered, so that the reflectance of the pixel electrode is lowered.

  Further, when a planarization insulating film made of a non-doped silicon oxide film is formed on the upper layer side of the reflective pixel electrode, the step coverage of the non-doped silicon oxide film is low. For this reason, when a recess due to a contact hole is formed on the surface of the pixel electrode, a cavity is likely to be generated in a portion filling the recess in the non-doped silicon oxide film. There is a problem that the orientation of the image is disturbed and the contrast of the display image is lowered.

  In view of the above problems, an object of the present invention is to provide an electro-optical device that can prevent generation of hillocks on the surface of a pixel electrode and generation of cavities in a portion of a planarization insulating film that fills a recess. An object of the present invention is to provide a projection display device using an optical device and a method for manufacturing the electro-optical device.

  In order to solve the above problems, an electro-optical device according to the present invention corresponds to a plurality of pixel transistors provided on one side of a substrate body for an element substrate, and the pixel transistors on one side of the element substrate. A plurality of reflective pixel electrodes provided on the opposite side of the pixel electrode from the side on which the substrate body is located, and a surface of a portion overlapping the pixel electrode and the adjacent pixel electrode A planarization insulating film that forms a continuous flat surface with the surface of the portion formed between the layers, and at least a layer in contact with the pixel electrode in the planarization insulating film is made of phosphorus and boron. At least one of them is made of a doped silicon oxide film.

  The electro-optical device manufacturing method according to the present invention includes a pixel electrode forming step of forming a reflective pixel electrode corresponding to a pixel transistor on one side of a substrate body for an element substrate, and a surface of the pixel electrode. An insulating film forming step for forming an insulating film made of a doped silicon oxide film in which at least one of phosphorous and boron is doped at least in contact with the pixel electrode, and planarizing the surface of the insulating film And a planarization step.

In the present invention, in the planarization insulating film provided on the upper layer side of the reflective pixel electrode (the side opposite to the side on which the substrate body is located), at least the layer stacked on the pixel electrode is made of phosphorus and boron. At least one of these comprises a doped silicon oxide film. The thermal expansion coefficient (2-4 × 10 ⁻⁶ / ° C.) of the doped silicon oxide film is smaller than the thermal expansion coefficient (0.5 × 10 ⁻⁶ / ° C.) of the non-doped silicon oxide film. The difference between the thermal expansion coefficient (23.1 × 10 ⁻⁶ / ° C.) of the aluminum film constituting the metal and the thermal expansion coefficient of other metal materials is small. For this reason, even if the planarization insulating film is formed in a heated state, a large thermal stress is not generated in the pixel electrode and the planarization insulating film, so that defects such as hillocks are hardly generated on the surface of the pixel electrode. Therefore, it is possible to avoid a decrease in the reflectance of the pixel electrode due to a decrease in the smoothness of the surface of the pixel electrode due to defects such as hillocks. In addition, since the doped silicon oxide film is excellent in step coverage, even when a recess due to a contact hole is formed on the surface of the pixel electrode, a cavity is formed in the portion of the doped silicon oxide film that fills the recess. Hard to occur. Therefore, it is possible to prevent the occurrence of the liquid crystal orientation being disturbed and the contrast of the display image being lowered due to the cavity being exposed on the planarization insulating film surface.

  In the present invention, the planarization insulating film may be configured such that the entire thickness direction is made of a doped silicon oxide film.

  In the present invention, it is preferable that a non-doped silicon oxide film in which neither phosphorus nor boron is doped is laminated on the surface of the planarization insulating film (doped silicon oxide film). The doped silicon oxide film is excellent in preventing generation of hillocks and cavities in the pixel electrode, but easily adsorbs moisture. For this reason, the water | moisture content adsorbed by the doped silicon oxide film may mix in a liquid crystal layer through an alignment film, and may cause a display defect. However, if a non-doped silicon oxide film is laminated on the surface of the planarization insulating film (doped silicon oxide film), there is an advantage that such moisture can be prevented from entering the liquid crystal layer.

  In the present invention, the planarization insulating film includes a first insulating film in contact with the pixel electrode, and a second insulating film stacked on the opposite side of the first insulating film from the side on which the substrate body is located. The first insulating film is a doped silicon oxide film doped with at least one of phosphorus and boron, and the surface of the first insulating film is on the side where the substrate body is located. Concavities and convexities resulting from the concavities and convexities are formed, and the second insulating film is a non-doped silicon oxide film in which neither phosphorus nor boron is doped, and the second insulating film is a surface of a portion overlapping the pixel electrode It is preferable that a flat surface that is continuous with a surface of a portion formed between adjacent pixel electrodes is formed. The doped silicon oxide film is excellent in preventing generation of hillocks and cavities in the pixel electrode, but easily adsorbs moisture. For this reason, the water | moisture content adsorbed by the doped silicon oxide film may mix in a liquid crystal layer through an alignment film, and may cause a display defect. However, if a non-doped silicon oxide film is laminated on the surface of the planarization insulating film (doped silicon oxide film), there is an advantage that mixing of such moisture into the liquid crystal layer can be prevented. In addition, if the surface of the doped silicon oxide film is polished and flattened, the polishing apparatus is contaminated with phosphorus and boron, which hinders the subsequent polishing process, but the surface of the non-doped silicon oxide film is polished. If flattening is performed, the polishing apparatus can be prevented from being contaminated with phosphorus or boron.

  In the present invention, when the electro-optical device is configured as a liquid crystal device, a counter substrate disposed to face one side of the element substrate, and a liquid crystal layer held between the element substrate and the counter substrate are provided. In addition, an alignment film is provided on the outermost surface of the element substrate.

  In the present invention, the alignment film is preferably an inorganic alignment film. According to such a configuration, unlike the organic alignment film, it is not necessary to perform a rubbing process, so that an increase in cost and a variation in alignment characteristics due to the rubbing process do not occur.

  The electro-optical device according to the present invention is a liquid crystal device, and in a projection display device using the liquid crystal device as a light valve, a light source unit that emits light supplied to the electro-optical device, and modulation by the electro-optical device A projection optical system for projecting the emitted light.

1 is a block diagram illustrating an electrical configuration of an electro-optical device to which the present invention is applied. It is explanatory drawing of the liquid crystal panel used for the electro-optical apparatus to which this invention is applied. FIG. 3 is an explanatory diagram of a pixel of the electro-optical device according to the first embodiment of the invention. FIG. 6 is a process cross-sectional view illustrating the main part of the method for manufacturing the electro-optical device according to the first embodiment of the invention. FIG. 6 is a cross-sectional view of a pixel of an electro-optical device according to a second embodiment of the invention. FIG. 10 is a process cross-sectional view illustrating a main part of a method for manufacturing an electro-optical device according to Embodiment 2 of the invention. 6 is a cross-sectional view of a pixel of an electro-optical device according to a third embodiment of the present invention. FIG. FIG. 10 is a process cross-sectional view illustrating a main part of a method for manufacturing an electro-optical device according to Embodiment 3 of the invention. 1 is a schematic configuration diagram of a projection display device using an electro-optical device (reflection liquid crystal device) to which the present invention is applied.

  Embodiments of the present invention will be described with reference to the drawings. In the drawings to be referred to in the following description, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawing. In addition, the field effect transistor used as the pixel transistor switches the source and the drain as the direction of the flowing current is reversed, but in the following description, for convenience, the side to which the pixel electrode is connected is the drain, The side to which the data line is connected will be described as a source. In the description of the configuration of the element substrate, the side on which the substrate body of the element substrate is located is the lower layer side, and the side opposite to the side on which the substrate body is located is the upper layer side.

[Embodiment 1]
(overall structure)
FIG. 1 is a block diagram showing an electrical configuration of an electro-optical device to which the present invention is applied. In FIG. 1, an electro-optical device 100 according to this embodiment is a reflective liquid crystal device, and includes a reflective liquid crystal panel 100p in a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode. The liquid crystal panel 100p includes a pixel region 10a (image display region) in which a plurality of pixels 100a are arranged in a matrix in the central region. In the liquid crystal panel 100p, in the element substrate 10 (see FIG. 2 and the like) described later, a plurality of data lines 6a and a plurality of scanning lines 3a extend vertically and horizontally inside the pixel region 10a, and correspond to the intersections thereof. The pixel 100a is configured at the position where the image is to be processed. In each of the plurality of pixels 100a, a pixel transistor 30 made of a field effect transistor and a pixel electrode 9a described later are formed. The data line 6 a is electrically connected to the source of the pixel transistor 30, the scanning line 3 a is electrically connected to the gate of the pixel transistor 30, and the pixel electrode 9 a is electrically connected to the drain of the pixel transistor 30. Has been.

  In the element substrate 10, a scanning line driving circuit 104 and a data line driving circuit 101 are provided on the outer peripheral side from the pixel region 10 a. The data line driving circuit 101 is electrically connected to each data line 6a, and sequentially supplies the image signal supplied from the image processing circuit to each data line 6a. The scanning line driving circuit 104 is electrically connected to each scanning line 3a, and sequentially supplies a scanning signal to each scanning line 3a.

  In each pixel 100a, the pixel electrode 9a is opposed to a common electrode formed on a counter substrate 20 (see FIG. 2 and the like), which will be described later, via a liquid crystal layer, and constitutes a liquid crystal capacitor 50a. Each pixel 100a is provided with a holding capacitor 55 in parallel with the liquid crystal capacitor 50a in order to prevent fluctuations in the image signal held in the liquid crystal capacitor 50a. In this embodiment, in order to form the storage capacitor 55, the capacitor line 5b extending in parallel with the scanning line 3a is formed across the plurality of pixels 100a. In this embodiment, the capacitor line 5b is electrically connected to the common potential line 5c to which the common potential Vcom is applied.

(Configuration of liquid crystal panel 100p and element substrate 10)
FIG. 2 is an explanatory view of a liquid crystal panel 100p used in the electro-optical device 100 to which the present invention is applied. FIGS. 2A and 2B are respectively a liquid crystal panel 100p of the electro-optical device 100 to which the present invention is applied. FIG. 5 is a plan view of each of the components together with each component viewed from the counter substrate side, and its HH ′ cross-sectional view. As shown in FIGS. 2A and 2B, in the liquid crystal panel 100p, the element substrate 10 and the counter substrate 20 are bonded to each other with a seal material 107 through a predetermined gap. It is provided in the shape of a frame along the outer edge. The sealing material 107 is an adhesive made of a photo-curing resin, a thermosetting resin, or the like, and is mixed with a gap material such as glass fiber or glass beads for setting the distance between both substrates to a predetermined value.

  In the liquid crystal panel 100p having such a configuration, the element substrate 10 and the counter substrate 20 are both rectangular, and the pixel region 10a described with reference to FIG. 1 is provided as a rectangular region at the approximate center of the liquid crystal panel 100p. Yes. Corresponding to this shape, the sealing material 107 is also provided in a substantially rectangular shape, and a substantially rectangular peripheral region 10b is provided in a frame shape between the inner peripheral edge of the sealing material 107 and the outer peripheral edge of the pixel region 10a. . In the element substrate 10, a data line driving circuit 101 and a plurality of terminals 102 are formed along one side of the element substrate 10 outside the pixel region 10 a, and scanning line driving is performed along another side adjacent to the one side. A circuit 104 is formed. Note that a flexible wiring board (not shown) is connected to the terminal 102, and various potentials and various signals are input to the element substrate 10 through the flexible wiring board.

  As will be described in detail later, the pixel transistor 10 described with reference to FIG. 1 and the pixel electrode 9a provided corresponding to the pixel transistor 30 are formed in a matrix on the one surface side of the element substrate 10 in the pixel region 10a. An alignment film 16 is formed on the upper layer side of the pixel electrode 9a. Note that a dummy pixel electrode 9b formed simultaneously with the pixel electrode 9a is formed in the peripheral region 10b on one surface side of the element substrate 10. For the dummy pixel electrode 9b, a configuration in which the dummy pixel transistor is electrically connected, a configuration in which the dummy pixel transistor is not provided, and a configuration in which the dummy pixel electrode is directly electrically connected to the wiring, or a floating state in which no potential is applied The structure which exists in is adopted. The dummy pixel electrode 9b is a surface on which the alignment film 16 is formed by aligning the height positions of the pixel region 10a and the peripheral region 10b when the surface on which the alignment film 16 is formed in the element substrate 10 is flattened by polishing. Contributes to a flat surface. Further, if the dummy pixel electrode 9b is set to a predetermined potential, it is possible to prevent the disorder of the alignment of the liquid crystal molecules at the outer peripheral side end of the pixel region 10a.

  A common electrode 21 is formed on one side of the counter substrate 20 facing the element substrate 10, and an alignment film 26 is formed on the common electrode 21. The common electrode 21 is formed across the plurality of pixels 100a as substantially the entire surface of the counter substrate 20 or a plurality of strip electrodes. Further, a light shielding layer 108 is formed on the lower layer side of the common electrode 21 on one surface side of the counter substrate 20 facing the element substrate 10. In this embodiment, the light shielding layer 108 is formed in a frame shape extending along the outer peripheral edge of the pixel region 10a. Here, the outer peripheral edge of the light shielding layer 108 is located with a gap between the inner peripheral edge of the sealing material 107 and the light shielding layer 108 and the sealing material 107 do not overlap. In the counter substrate 20, the light shielding layer 108 may be formed in a region that overlaps with a region sandwiched between adjacent pixel electrodes 9a.

  In the liquid crystal panel 100p configured as described above, the element substrate 10 is electrically connected between the element substrate 10 and the counter substrate 20 in a region overlapping the corner portion of the counter substrate 20 outside the sealant 107. The inter-substrate conducting portion 109 is formed. The inter-substrate conducting portion 109 is provided with an inter-substrate conducting material 109a containing conductive particles, and the common electrode 21 of the counter substrate 20 is interposed between the inter-substrate conducting material 109a and an inter-substrate conducting electrode described later. Are electrically connected to the element substrate 10 side. Therefore, the common potential Vcom is applied to the common electrode 21 from the element substrate 10 side. The sealing material 107 is provided along the outer peripheral edge of the counter substrate 20 with substantially the same width dimension. For this reason, the sealing material 107 is substantially rectangular. However, the sealing material 107 is provided so as to pass inside avoiding the inter-substrate conducting portion 109 in a region overlapping with the corner portion of the counter substrate 20, and the corner portion of the sealing material 107 has a substantially arc shape.

  In the electro-optical device 100 having such a configuration, in this embodiment, the common electrode 21 is formed of a light-transmitting conductive film, and the pixel electrode 9a is formed of a reflective conductive film. For this reason, in the electro-optical device 100 according to the present embodiment, the light incident from the counter substrate 20 side is modulated while being reflected from the element substrate 10 side and emitted from the counter substrate 20 side to display an image.

  The electro-optical device 100 can be used as a color display device of an electronic device such as a mobile computer or a mobile phone. In this case, a color filter (not shown) and a protective film are formed on the counter substrate 20. Further, in the electro-optical device 100, a polarizing film, a retardation film, a polarizing plate, and the like are predetermined with respect to the liquid crystal panel 100p according to the type of the liquid crystal layer 50 to be used and the normally white mode / normally black mode. Arranged in the direction. Furthermore, the electro-optical device 100 can be used as a light valve for RGB in a projection display device (liquid crystal projector) described later. In this case, each of the RGB electro-optical devices 100 receives light of each color separated through RGB color separation dichroic mirrors as projection light, so that no color filter is formed. .

  Hereinafter, in the electro-optical device 100 of this embodiment, a case where a nematic liquid crystal compound having negative dielectric anisotropy is used as the liquid crystal layer 50 and the liquid crystal panel 100p is configured for the VA mode will be mainly described.

(Specific pixel configuration)
FIG. 3 is an explanatory diagram of a pixel of the electro-optical device 100 according to the first embodiment of the present invention. FIGS. 3A and 3B are elements used in the electro-optical device 100 to which the present invention is applied. FIG. 4 is a plan view of adjacent pixels on the substrate 10 and a cross-sectional view when the electro-optical device 100 is cut at a position corresponding to the line FF ′ in FIG. In FIG. 3A, the semiconductor layer 1a is indicated by a thin and short dotted line, the scanning line 3a is indicated by a thick solid line, the data line 6a and a thin film formed simultaneously with it are indicated by a one-dot chain line, and the capacitance line 5b is indicated by two lines. The pixel electrode 9a is indicated by a thick and long broken line, and the lower electrode layer 4a is indicated by a thin solid line.

  As shown in FIG. 3A, a rectangular pixel electrode 9a is formed on each of the plurality of pixels 100a on the element substrate 10, and a data line is formed along the vertical and horizontal boundaries of each pixel electrode 9a. 6a and scanning line 3a are formed. Each of the data line 6a and the scanning line 3a extends linearly, and a pixel transistor 30 is formed in a region where the data line 6a and the scanning line 3a intersect. On the element substrate 10, a capacitor line 5b is formed so as to overlap the scanning line 3a. In this embodiment, the capacitor line 5b includes a main line portion extending linearly so as to overlap the scanning line 3a, and a sub-line portion extending so as to overlap the data line 6a at the intersection of the data line 6a and the scanning line 3a. It has.

  As shown in FIGS. 3A and 3B, the element substrate 10 is a pixel electrode formed on the surface (one surface side) of the substrate body 10w such as a quartz substrate, a glass substrate, or a silicon substrate on the liquid crystal layer 50 side. 9a, the pixel transistor 30 for pixel switching, and the alignment film 16, and the counter substrate 20 includes a translucent substrate body 20w such as a quartz substrate or a glass substrate, and a surface on the liquid crystal layer 50 side ( The common electrode 21 and the alignment film 26 formed on one side) are mainly composed.

  In the element substrate 10, a pixel transistor 30 including the semiconductor layer 1a is formed in each of the plurality of pixels 100a. The semiconductor layer 1a includes a channel region 1g, a source region 1b, and a drain region 1c that are opposed to the gate electrode 3c formed of a part of the scanning line 3a via the gate insulating layer 2, and the source region 1b The drain region 1c has a low concentration region and a high concentration region, respectively. The semiconductor layer 1a is composed of, for example, a polycrystalline silicon film or the like formed on the base insulating film 12 made of a silicon oxide film or the like on the substrate body 10w, and the gate insulating layer 2 is formed by a CVD method or the like. It consists of a silicon oxide film or a silicon nitride film. The gate insulating layer 2 may have a two-layer structure of a silicon oxide film obtained by thermally oxidizing the semiconductor layer 1a and a silicon oxide film or silicon nitride film formed by a CVD method or the like. For the scanning line 3a, a conductive polysilicon film, a metal silicide film, or a metal film is used.

  A first interlayer insulating film 41 made of a silicon oxide film or the like is formed on the upper layer side of the scanning line 3a, and a lower electrode layer 4a is formed on the upper layer of the first interlayer insulating film 41. The lower electrode layer 4a is formed in a substantially L-shape extending along the scanning line 3a and the data line 6a with a position where the scanning line 3a and the data line 6a intersect as a base point. The lower electrode layer 4a is made of a conductive polysilicon film, a metal silicide film, a metal film, or the like, and is electrically connected to the drain region 1c through the contact hole 7c.

  A dielectric layer 42 made of a silicon nitride film or the like is formed on the upper layer side of the lower electrode layer 4a. A capacitor line 5b (upper electrode layer) is formed on the upper side of the dielectric layer 42 so as to face the lower electrode layer 4a with the dielectric layer 42 interposed therebetween. The capacitor line 5b, the dielectric layer 42, and the lower electrode are formed. A storage capacitor 55 is formed by the layer 4a. The capacitor line 5b is made of a conductive polysilicon film, a metal silicide film, a metal film, or the like. Here, the lower electrode layer 4a, the dielectric layer 42, and the capacitor line 5b (upper electrode layer) are formed on the upper layer side of the pixel transistor 30 and overlap the pixel transistor 30 in plan view. Therefore, the storage capacitor 55 is formed on the upper layer side of the pixel transistor 30 and overlaps at least the pixel transistor 30 in plan view.

  A second interlayer insulating film 43 made of a silicon oxide film or the like is formed on the upper side of the capacitor line 5b, and a data line 6a and a drain electrode 6b are formed on the upper layer of the second interlayer insulating film 43. Data line 6a is electrically connected to source region 1b through contact hole 7a. The drain electrode 6b is electrically connected to the lower electrode layer 4a through the contact hole 7b, and is electrically connected to the drain region 1c through the lower electrode layer 4a. The data line 6a and the drain electrode 6b are made of a conductive polysilicon film, a metal silicide film, a metal film, or the like.

(Configuration of pixel electrode 9a, planarization insulating film, etc.)
A third interlayer insulating film 44 made of a silicon oxide film or the like is formed on the upper side of the data line 6a and the drain electrode 6b. In the third interlayer insulating film 44, a contact hole 7d leading to the drain electrode 6b is formed. A pixel electrode 9a made of a reflective conductive film such as an aluminum film is formed on the third interlayer insulating film 44. The pixel electrode 9a is electrically connected to the drain electrode 6b through the contact hole 7d. ing. In this embodiment, the surface of the third interlayer insulating film 44 is a flat surface. A dummy pixel electrode 9b (not shown in FIG. 3) described with reference to FIG. 2B is formed on the surface of the third interlayer insulating film 44, and the dummy pixel electrode 9b includes It consists of a reflective conductive film formed simultaneously with the pixel electrode 9a.

  In this embodiment, the pixel electrode 9a includes a single layer film of an aluminum film, a laminated film in which a titanium nitride film (lower layer side) and an aluminum film (upper layer side) are laminated, a titanium film (lower layer side), and an aluminum film (upper layer side). ) Are used. Among the pixel electrodes 9a, if a titanium nitride film or a titanium film is formed on the lower layer side of the aluminum film, the reflection on the lower surface side of the pixel electrode 9a can be prevented, and the generation of stray light can be prevented. Has the advantage of smoothing and improving the reflectivity of the aluminum film.

An alignment film 16 is formed on the surface of the pixel electrode 9a. The alignment film 16 is made of a resin film such as polyimide or an oblique deposition film such as a silicon oxide film. In this embodiment, the alignment film 16 is an obliquely deposited film of SiO _x (x <2), SiO ₂ , TiO ₂ , MgO, Al ₂ O ₃ , In ₂ O ₃ , Sb ₂ O ₃ , Ta ₂ O ₅ or the like. A flattening insulating film 17 is formed between the alignment film 16 and the pixel electrode 9a. The planarization insulating film 17 fills the recess 9e formed between adjacent pixel electrodes 9a and the recess 9f formed in the pixel electrode 9a due to the contact hole 7d. The surface of the planarization insulating film 17 is a flat surface, and the surface of the portion formed between the adjacent pixel electrodes 9a and the surface of the portion overlapping the pixel electrode 9a form a continuous flat surface. is doing. For this reason, since the alignment film 16 can be formed by performing oblique vapor deposition on a flat surface, the oblique vapor deposition film constituting the alignment film 16 can be suitably formed.

  In this embodiment, as the planarization insulating film 17, a phosphorus-doped silicon oxide film (PSG film) doped with phosphorus, a boron-doped silicon oxide film (BSG film) doped with boron, boron doped with boron and phosphorus -It consists of a doped silicon oxide film 170 doped with at least one of phosphorus and boron, such as a phosphorus-doped silicon oxide film (BPSG film). The doped silicon oxide film 170 has a smaller difference in thermal expansion coefficient from the material constituting the pixel electrode 9a than the non-doped silicon oxide film (NSG film) in which neither phosphorus nor boron is doped.

That is, the thermal expansion coefficient of the material constituting the pixel electrode 9a is the following level. The thermal expansion coefficient of the aluminum film = 23.1 × 10 ⁻⁶ / ° C.
Thermal expansion coefficient of titanium nitride film = 9.3 × 10 ⁻⁶ / ° C.
Thermal expansion coefficient of titanium film = 11.0 × 10 ⁻⁶ / ° C.
It is. On the other hand, the thermal expansion coefficients of the doped silicon oxide film 170 and the non-doped silicon oxide film are as follows: doped silicon oxide film 170 = 2 to 4 × 10 ⁻⁶ / ° C.
Thermal expansion coefficient of non-doped silicon oxide film = 0.5 × 10 ⁻⁶ / ° C.
It is.

(Configuration of counter substrate 20 etc.)
The counter substrate 20 is made of a light-transmitting conductive film such as an ITO film on the surface of the light-transmitting substrate body 20 w such as a quartz substrate or a glass substrate on the liquid crystal layer 50 side (surface facing the element substrate 10). A common electrode 21 is formed, and an alignment film 26 is formed so as to cover the common electrode 21. Similar to the alignment film 16, the alignment film 26 is made of a resin film such as polyimide or an oblique deposition film such as a silicon oxide film. In this embodiment, the alignment film 26 is an obliquely deposited film such as SiO _x (x <2), SiO ₂ , TiO ₂ , MgO, Al ₂ O ₃ , In ₂ O ₃ , Sb ₂ O ₃ , Ta ₂ O _5. A protective film 27 such as a silicon oxide film or a silicon nitride film is formed between the alignment film 26 and the common electrode 21. The protective film 27 has a flat surface, and the alignment film 26 is formed on the flat surface. The alignment films 16 and 26 vertically align the nematic liquid crystal compound having negative dielectric anisotropy used for the liquid crystal layer 50, and the liquid crystal panel 100p operates as a normally black VA mode.

  Note that the data line driving circuit 101 and the scanning line driving circuit 104 described with reference to FIGS. 1 and 2 are complementary transistor circuits each including an N-channel driving transistor and a P-channel driving transistor. Etc. are configured. Here, the driving transistor is formed by utilizing a part of the manufacturing process of the pixel transistor 30. Therefore, the region where the data line driving circuit 101 and the scanning line driving circuit 104 are formed in the element substrate 10 also has a cross-sectional configuration substantially similar to the cross-sectional configuration shown in FIG.

(Method of manufacturing electro-optical device 100)
FIG. 4 is a process cross-sectional view illustrating the main part of the method for manufacturing the electro-optical device 100 according to Embodiment 1 of the present invention. In manufacturing the electro-optical device 100 of this embodiment, in the method for manufacturing the element substrate 10, as shown in FIG. 4A, the pixel transistor 30, the storage capacitor 55, the data line 6a, the third interlayer insulating film 44, and the like are provided. After the formation, a contact hole 7 d is formed in the third interlayer insulating film 44.

  Next, after forming a conductive film for forming the pixel electrode 9a on the third interlayer insulating film 44, the conductive film is patterned to form the pixel electrode 9a as shown in FIG. Pixel electrode forming step).

Next, as shown in FIG. 4C, a thick insulating film (planarized insulating film 17) made of the doped silicon oxide film 170 is formed on the surface side of the pixel electrode 9a by an atmospheric pressure CVD method or the like (insulating film). Forming step). As a result, the recess 9e formed between adjacent pixel electrodes 9a and the recess 9f formed in the pixel electrode 9a due to the contact hole 7d are filled with the planarization insulating film 17. The film formation temperature when forming such doped silicon oxide film 170 is, for example, 350 to 450 ° C. When a phosphorus doped silicon oxide film (PSG film) is formed as the planarization insulating film 17 (doped silicon oxide film 170), the source gas used is SiH ₄ , PH ₃ , O _3, etc. When forming a doped silicon oxide film (BSG film), the source gas used is SiH ₄ , B ₂ H ₆ , O _3, etc., and when forming a boron / phosphorus doped silicon oxide film (BPSG film), The source gas used is SiH ₄ , B ₂ H ₆ , PH ₃ , O ₃ or the like.

  Next, as shown in FIG. 4D, the surface of the insulating film (flattened insulating film 17) is polished to flatten the surface. At that time, the insulating film (planarized insulating film 17) is left to the extent that the surface of the pixel electrode 9a is not exposed. As a result, in the planarization insulating film 17, the surface of the portion formed between the adjacent pixel electrodes 9a and the surface of the portion overlapping the pixel electrode 9a form a continuous flat surface. In this planarization step, chemical mechanical polishing can be used, and in chemical mechanical polishing, a smooth polishing surface can be obtained at high speed by the action of chemical components contained in the polishing liquid and the relative movement of the abrasive and the element substrate 10. Can do. More specifically, in a polishing apparatus, polishing is performed while relatively rotating a surface plate on which a polishing cloth (pad) made of nonwoven fabric, polyurethane foam, porous fluororesin, or the like is attached and a holder for holding the element substrate 10. To do. At that time, for example, an abrasive containing cerium oxide particles having an average particle diameter of 0.01 to 20 μm, an acrylate derivative as a dispersant, and water is supplied between the polishing cloth and the element substrate 10.

  After the planarization insulating film 17 is formed in this manner, external connection terminals (not shown) and the like are formed, and then oblique deposition is performed on the surface of the planarization insulating film 17 to align as shown in FIG. A film 16 is formed.

(Main effects of this form)
As described above, in the electro-optical device 100 according to this embodiment, the planarization insulating film 17 provided on the upper layer side of the reflective pixel electrode 9a has at least a layer laminated on the pixel electrode 9a doped silicon. It consists of an oxide film 170. More specifically, in this embodiment, a planarization insulating film 17 made of a doped silicon oxide film 170 as a whole in the thickness direction is provided on the upper layer side of the reflective pixel electrode 9a. The thermal expansion coefficient (2-4 × 10 ⁻⁶ / ° C.) of the silicon oxide film 170 is larger than that of the non-doped silicon oxide film (0.5 × 10 ⁻⁶ / ° C.). The difference from the thermal expansion coefficient (23.1 × 10 ⁻⁶ / ° C.) of the aluminum film is small. For this reason, even if the planarization insulating film 17 is formed in a heated state, a large thermal stress is not generated in the pixel electrode 9a and the planarization insulating film 17, so that defects such as hillocks occur on the surface of the pixel electrode 9a. Hateful. Therefore, it is possible to avoid a decrease in the smoothness of the surface of the pixel electrode 9a due to defects such as hillocks and a decrease in the reflectance of the pixel electrode 9a. In addition, since the doped silicon oxide film 170 is excellent in step coverage, even when the concave portion 9f due to the contact hole 7d is formed on the surface of the pixel electrode 9a, the concave portion 9f in the doped silicon oxide film 170 is formed. It is hard to generate a cavity in the part that fills up. Therefore, it is possible to prevent the liquid crystal orientation on the pixel electrode 9a from being disturbed and the contrast of the display image from being lowered due to the exposure of the cavity on the surface of the planarization insulating film 17.

  In this embodiment, since the alignment films 16 and 26 are inorganic alignment films, it is not necessary to perform a rubbing process unlike the organic alignment films. Therefore, there is no increase in cost or variation in alignment characteristics due to the rubbing process.

[Embodiment 2]
FIG. 5 is a cross-sectional view of a pixel of the electro-optical device 100 according to Embodiment 2 of the present invention. FIG. 6 is a process cross-sectional view illustrating the main part of the method for manufacturing the electro-optical device 100 according to Embodiment 2 of the present invention. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 5, even in the element substrate 10 used in the electro-optical device 100 of the present embodiment, as in the first embodiment, the pixel electrode 9a includes a single-layer film of aluminum film, a titanium nitride film (lower layer side), and A laminated film in which an aluminum film (upper layer side) is laminated, a laminated film in which a titanium film (lower layer side) and an aluminum film (upper layer side) are laminated, or the like is used.

  Similarly to the first embodiment, the surface of the pixel electrode 9a is a phosphorus-doped silicon oxide film (PSG film), a boron-doped silicon oxide film (BSG film), or a boron-phosphorus-doped silicon oxide film (BPSG film). A planarization insulating film 17 made of a doped silicon oxide film 170 is formed.

  In this embodiment, a protective film 18 made of a non-doped silicon oxide film is stacked on the planarizing insulating film 17, and an alignment film 16 (inorganic alignment film / obliquely deposited film) is stacked on the protective film 18. ing. According to such a configuration, in the planarization insulating film 17, the surface of the portion formed between the adjacent pixel electrodes 9a and the surface of the portion overlapping the pixel electrode 9a form a continuous flat surface. The surface of the protective film 18 is a flat surface without performing a polishing process. For this reason, since the alignment film 16 can be formed by performing oblique vapor deposition on a flat surface, the oblique vapor deposition film constituting the alignment film 16 can be suitably formed.

In order to manufacture the electro-optical device 100 having such a configuration, after the planarization insulating film 17 made of the doped silicon oxide film 170 is formed by the method described in the first embodiment, as shown in FIG. As shown in FIG. 6B, a protective film 18 made of a non-doped silicon oxide film is formed on the surface of the planarization insulating film 17 by a low pressure CVD method, a plasma CVD method or the like. When the low pressure CVD method is employed when forming the protective film 18 (non-doped silicon oxide film), the film forming temperature is, for example, 650 to 750 ° C., and the source gas used is Si (OC ₂ H ₅ ). It is ₄ mag. When the plasma CVD method is employed when forming the protective film 18 (non-doped silicon oxide film), the film forming temperature is, for example, 250 to 450 ° C., and the source gas used is SiH ₄ , N ₂ O. Etc. Thereafter, oblique deposition is performed on the surface of the protective film 18 to form the alignment film 16 as shown in FIG.

  As described above, in the electro-optical device 100 according to this embodiment, the planarization insulating film 17 provided on the upper layer side of the reflective pixel electrode 9a has at least a layer laminated on the pixel electrode 9a doped silicon. It consists of an oxide film 170. More specifically, in this embodiment, a planarization insulating film 17 made of a doped silicon oxide film 170 as a whole in the thickness direction is provided on the upper layer side of the reflective pixel electrode 9a. The difference between the thermal expansion coefficient of the silicon oxide film 170 and the thermal expansion coefficient of the aluminum film constituting the pixel electrode 9a is smaller than that of the non-doped silicon oxide film. For this reason, even if the planarization insulating film 17 is formed in a heated state, a large thermal stress is not generated in the pixel electrode 9a and the planarization insulating film 17, so that defects such as hillocks occur on the surface of the pixel electrode 9a. There are the same effects as in the first embodiment, such as being difficult.

  In this embodiment, since the protective film 18 made of a non-doped silicon oxide film is formed on the planarization insulating film 17 made of the doped silicon oxide film 170, the electro-optical device 100 has high reliability. In other words, the doped silicon oxide film 170 is excellent in preventing the generation of hillocks and the generation of cavities in the pixel electrode 9a, but easily adsorbs moisture. For this reason, when moisture is released from the doped silicon oxide film 170, the moisture may enter the liquid crystal layer 50, but non-doped silicon is formed on the surface of the planarization insulating film 147 (doped silicon oxide film 170). By laminating the oxide film (protective film 18), there is an advantage that the penetration of moisture into the liquid crystal layer 50 can be prevented by the non-doped silicon oxide film (protective film 18).

[Embodiment 3]
FIG. 7 is a cross-sectional view of a pixel of the electro-optical device 100 according to Embodiment 3 of the present invention. FIG. 8 is a process cross-sectional view illustrating the main part of the method for manufacturing the electro-optical device 100 according to Embodiment 3 of the present invention. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 7, even in the element substrate 10 used in the electro-optical device 100 of the present embodiment, as in the first embodiment, as the pixel electrode 9a, a single-layer film of an aluminum film, a titanium nitride film (lower layer side), and A laminated film in which an aluminum film (upper layer side) is laminated, a laminated film in which a titanium film (lower layer side) and an aluminum film (upper layer side) are laminated, or the like is used.

  Further, a planarization insulating film 17 is formed on the surface of the pixel electrode 9a as in the first embodiment, and an alignment film 16 (inorganic alignment film / rhombic vapor deposition film) is formed on the planarization insulating film 17. Are stacked. For this reason, since the alignment film 16 can be formed by performing oblique vapor deposition on a flat surface, the oblique vapor deposition film constituting the alignment film 16 can be suitably formed.

  Here, the planarization insulating film 17 includes a first insulating film 17a stacked on the pixel electrode 9a and a second insulating film 17b stacked on the first insulating film 17a. In this embodiment, the first insulating film 17a is a doped silicon oxide film 170 doped with at least one of phosphorus and boron, and includes a recess 9e formed between adjacent pixel electrodes 9a, a pixel electrode 9a substantially fills the recess 9f formed due to the contact hole 7d. In addition, unevenness due to the unevenness on the lower layer side is formed on the surface of the first insulating film 17a (doped silicon oxide film 170). On the other hand, the second insulating film 17b is a non-doped silicon oxide film 171 in which neither phosphorus nor boron is doped, and the second insulating film 17b is adjacent to the surface of the portion overlapping the pixel electrode 9a. The surface of the part formed between the matching pixel electrodes 9a forms a continuous flat surface.

  To manufacture the electro-optical device 100 having such a configuration, a conductive film for forming the pixel electrode 9a is formed on the third interlayer insulating film 44, and then the conductive film is patterned, as shown in FIG. Thus, the pixel electrode 9a is formed (pixel electrode forming step).

  Next, the insulating film forming step shown in FIGS. 8B and 8C is performed, and the first insulating film 17a (doped silicon oxide film 170) and the second insulating film 17b (non-doped silicon oxide film 171) are stacked. The formed insulating film (planarized insulating film 17) is formed. More specifically, as shown in FIG. 8B, a thick doped silicon oxide film 170 (first insulating film 17a) is formed on the surface side of the pixel electrode 9a by atmospheric pressure CVD or the like (first insulating film 17a). Film formation step). As a result, the recess 9e formed between the adjacent pixel electrodes 9a and the recess 9f formed in the pixel electrode 9a due to the contact hole 7d are filled with the doped silicon oxide film 170. However, the surface of the doped silicon oxide film 170 has unevenness due to the unevenness on the lower layer side (recesses 9e and 9f). Next, as shown in FIG. 8C, a non-doped silicon oxide film 171 (second insulating film 17b) is thickly stacked on the doped silicon oxide film 170 by a low pressure CVD method or a plasma CVD method (first insulating film 17b). 2 insulating film forming step). As a result, the recess formed on the surface of doped silicon oxide film 170 is filled with non-doped silicon oxide film 171.

  Next, as shown in FIG. 8D, the surface of the insulating film (planarized insulating film 17) in which the doped silicon oxide film 170 and the non-doped silicon oxide film 171 are stacked is polished by chemical mechanical polishing. The surface of the non-doped silicon oxide film 171 is planarized. At that time, the insulating film (planarized insulating film 17) is left to the extent that the surface of the pixel electrode 9a is not exposed. As a result, in the planarization insulating film 17, the surface of the portion formed between the adjacent pixel electrodes 9a and the surface of the portion overlapping the pixel electrode 9a form a continuous flat surface.

  As described above, in the electro-optical device 100 according to this embodiment, the planarization insulating film 17 provided on the upper layer side of the reflective pixel electrode 9a has at least a layer laminated on the pixel electrode 9a doped silicon. It consists of an oxide film 170. More specifically, in this embodiment, the planarization insulating film 17 has a structure in which a doped silicon oxide film 170 and a non-doped silicon oxide film 171 are stacked, but the upper side of the reflective pixel electrode 9a. The doped silicon oxide film 170 is laminated, and the thermal expansion coefficient of the doped silicon oxide film 170 constitutes the pixel electrode 9a as compared with the thermal expansion coefficient of the non-doped silicon oxide film 171. The difference with the thermal expansion coefficient of the aluminum film to be performed is small. For this reason, even if the planarization insulating film 17 is formed in a heated state, a large thermal stress is not generated in the pixel electrode 9a and the planarization insulating film 17, so that defects such as hillocks occur on the surface of the pixel electrode 9a. There are the same effects as in the first embodiment, such as being difficult.

  Further, in this embodiment, since the protective film 18 made of the non-doped silicon oxide film is formed on the planarization insulating film 17 made of the doped silicon oxide film 170, the moisture is transferred from the doped silicon oxide film 170 to the liquid crystal layer 50. Can be prevented by the non-doped silicon oxide film 171.

  In this embodiment, the surface of the non-doped silicon oxide film 171 is polished, but the surface of the doped silicon oxide film 170 is not polished. For this reason, it is possible to prevent the polishing apparatus from being contaminated with phosphorus or boron.

[Modification of Embodiment 3]
In the third embodiment, the surface of the doped silicon oxide film 170 is not polished and only the surface of the non-doped silicon oxide film 171 is polished. However, the surface of the doped silicon oxide film 170 and the non-doped silicon oxide film 171 are polished. Both surfaces may be polished. Even in such a configuration, the planarization insulating film 17 has a structure in which the doped silicon oxide film 170 and the non-doped silicon oxide film 171 are stacked. A doped silicon oxide film 170.

[Application example to other electro-optical devices]
In the above embodiment, the present invention is applied to the element substrate 10 of the reflective liquid crystal device as the element substrate 10 of the electro-optical device 100. However, other electro-optical devices such as an organic electroluminescence display device and a plasma display device are used. The present invention may be applied to an element substrate.

[Example of mounting on electronic devices]
An electronic apparatus to which the electro-optical device 100 according to the above-described embodiment is applied will be described. FIG. 9 is a schematic configuration diagram of a projection display device using the electro-optical device 100 (reflection type liquid crystal device) to which the present invention is applied.

  In the projection display apparatus 1000 shown in FIG. 9, the light source unit 890 includes a polarization illumination device 800 in which a light source 810, an integrator lens 820, and a polarization conversion element 830 are arranged along the system optical axis L. The light source unit 890 also reflects the S-polarized light beam emitted from the polarization illumination device 800 along the system optical axis L by the S-polarized light beam reflecting surface 841 and the S-polarized light beam of the polarized beam splitter 840. Of the light reflected from the reflecting surface 841, the dichroic mirror 842 that separates the blue light (B) component and the red light (R) component of the luminous flux after the blue light is separated are separated. And a dichroic mirror 843.

  The projection display apparatus 1000 includes three reflective electro-optical devices 100 (reflective liquid crystal devices 100R, 100G, and 100B) on which light of each color enters, and the light source unit 890 includes three electro-optical devices. A predetermined color light is supplied to 100 (liquid crystal devices 100R, 100G, and 100B).

  In the projection display apparatus 1000, the light modulated by the three liquid crystal devices 100R, 100G, and 100B is synthesized by the dichroic mirrors 842 and 843 and the polarization beam splitter 840, and then the synthesized light is projected by the projection optical system 850. Is projected onto a projection target member such as a screen 860.

(Other projection display devices)
In addition, about a projection type display apparatus, you may comprise the LED light source etc. which radiate | emit the light of each color as a light source part, and supply each color light radiate | emitted from this LED light source to another liquid crystal device. .

(Other electronic devices)
As for the electro-optical device 100 to which the present invention is applied, in addition to the electronic devices described above, mobile phones, personal digital assistants (PDAs), digital cameras, liquid crystal televisions, car navigation devices, video phones, POS terminals In addition, it may be used as a direct-view display device in an electronic device such as a device provided with a touch panel.

9a..Pixel electrode, 9e, 9f..Recess, 10..Element substrate, 16..Orientation film, 17..Flattening insulating film, 17a..First insulating film, 17b..Second insulating film, 18 ..Protective film 20 ..Counter substrate 21 ..Common electrode 50 ..Liquid crystal layer 100 ..Electro-optical device 170 ..Doped silicon oxide film 171 ..Non-doped silicon oxide film 1000. Projection display

Claims (8)

A plurality of pixel transistors provided on one side of the substrate body for the element substrate;
A plurality of reflective pixel electrodes provided on one side of the element substrate corresponding to the pixel transistors;
Provided on the opposite side of the pixel electrode from the side where the substrate body is located, the surface of the portion overlapping the pixel electrode and the surface of the portion formed between the adjacent pixel electrodes are continuous A planarization insulating film forming a flat surface;
Have
2. The electro-optical device according to claim 1, wherein at least the layer in contact with the pixel electrode in the planarization insulating film is made of a doped silicon oxide film doped with at least one of phosphorus and boron.   The electro-optical device according to claim 1, wherein the planarization insulating film is entirely made of a doped silicon oxide film in a thickness direction.   3. The electro-optical device according to claim 2, wherein a non-doped silicon oxide film in which neither phosphorus nor boron is doped is laminated on the surface of the planarization insulating film. The planarization insulating film includes a first insulating film in contact with the pixel electrode, and a second insulating film stacked on a side opposite to the side on which the substrate body is positioned with respect to the first insulating film,
The first insulating film is a doped silicon oxide film doped with at least one of phosphorus and boron, and the surface of the first insulating film is caused by unevenness on the side where the substrate body is located. Irregularities are formed,
The second insulating film is a non-doped silicon oxide film in which neither phosphorus nor boron is doped, and the second insulating film is formed between the surface of the portion overlapping the pixel electrode and the adjacent pixel electrode. The electro-optical device according to claim 1, wherein the surface of the portion formed on the surface forms a continuous flat surface. A counter substrate disposed opposite to one side of the substrate body;
A liquid crystal layer held between the element substrate and the counter substrate;
Have
The electro-optical device according to claim 1, wherein an alignment film is provided on an outermost surface of the element substrate.   The electro-optical device according to claim 5, wherein the alignment film is an inorganic alignment film. A projection display device comprising the electro-optical device according to any one of claims 1 to 6,
A light source unit that emits light supplied to the electro-optical device;
A projection optical system that projects light modulated by the electro-optical device;
A projection display device characterized by comprising: A pixel electrode forming step of forming a reflective pixel electrode corresponding to the pixel transistor on one side of the substrate body for the element substrate;
An insulating film forming step of forming an insulating film made of a doped silicon oxide film in which at least one of phosphorous and boron is doped at least on the surface side of the pixel electrode;
A planarization step of planarizing the surface of the insulating film;
A method for manufacturing an electro-optical device.

Images