JP2012099832A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- JP2012099832A JP2012099832A JP2011274530A JP2011274530A JP2012099832A JP 2012099832 A JP2012099832 A JP 2012099832A JP 2011274530 A JP2011274530 A JP 2011274530A JP 2011274530 A JP2011274530 A JP 2011274530A JP 2012099832 A JP2012099832 A JP 2012099832A
- Authority
- JP
- Japan
- Prior art keywords
- region
- drift region
- electrode
- front surface
- drift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000000903 blocking effect Effects 0.000 claims abstract description 18
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 46
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 43
- 230000002441 reversible effect Effects 0.000 claims description 8
- 235000012431 wafers Nutrition 0.000 abstract description 63
- 239000013078 crystal Substances 0.000 abstract description 58
- 238000000034 method Methods 0.000 abstract description 30
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 36
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 239000007789 gas Substances 0.000 description 18
- 230000008901 benefit Effects 0.000 description 10
- 229910052757 nitrogen Inorganic materials 0.000 description 10
- 238000000137 annealing Methods 0.000 description 9
- 239000001257 hydrogen Substances 0.000 description 9
- 229910052739 hydrogen Inorganic materials 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 8
- 229910052799 carbon Inorganic materials 0.000 description 8
- 230000007547 defect Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 238000005259 measurement Methods 0.000 description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 6
- 239000000969 carrier Substances 0.000 description 6
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 230000006798 recombination Effects 0.000 description 5
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 4
- 239000005977 Ethylene Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 238000005215 recombination Methods 0.000 description 4
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229930195733 hydrocarbon Natural products 0.000 description 3
- 150000002430 hydrocarbons Chemical class 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910052723 transition metal Inorganic materials 0.000 description 3
- 150000003624 transition metals Chemical class 0.000 description 3
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
- 239000000370 acceptor Substances 0.000 description 2
- 239000007833 carbon precursor Substances 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005424 photoluminescence Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000007847 structural defect Effects 0.000 description 2
- 238000000859 sublimation Methods 0.000 description 2
- 230000008022 sublimation Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical class Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical class [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000001443 photoexcitation Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000001294 propane Substances 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000012686 silicon precursor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/36—Carbides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/931—Silicon carbide semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
本発明は、ウェーハに注入された自由キャリアをバイポーラパワーデバイスのために利益のある寿命で再結合させるために、不純物、内因性欠陥又は構造欠陥のいずれかに起因する深い準位の十分な濃度を有する低不純物(低ドーピング)n型又はp型炭化ケイ素ウェーハを、15kV又はそれ以上の電圧阻止能力を有するIGBTのようなハイパワーデバイス構造のベース領域として用いることに関する。 The present invention provides a sufficient concentration of deep levels due to either impurities, intrinsic defects or structural defects to recombine free carriers injected into the wafer with a lifetime that is beneficial for bipolar power devices. The use of a low-impurity (low-doping) n-type or p-type silicon carbide wafer having a high-power device structure such as an IGBT having a voltage blocking capability of 15 kV or higher.
現在、シリコンパワーデバイスにより実現する最も高い破壊電圧はIGBTとGTOに対して4.5〜6.5kVの範囲であり、サイリスタに対して9〜12kVの範囲である。今日、高めの電圧を扱うためのこれらスイッチング装置の能力は、直列操作(直列演算)の要件のような技術因子、及びシリコン半導体の物理特性により制限される。高めの電圧(>10kV)の電気送信システムは広めのバンドギャップの炭化ケイ素半導体の高めの臨界電場から利益を得ると考えられている。加えて、同等の電圧定格のために、炭化ケイ素装置はそれらのシリコンの片方より低いオン抵抗と低いスイッチングのロスの利点を提供する。 Currently, the highest breakdown voltage achieved with silicon power devices is in the range of 4.5-6.5 kV for IGBTs and GTOs and in the range of 9-12 kV for thyristors. Today, the ability of these switching devices to handle higher voltages is limited by technical factors such as the requirements for series operation (series operation) and the physical properties of silicon semiconductors. High voltage (> 10 kV) electrical transmission systems are believed to benefit from the higher critical electric field of wider bandgap silicon carbide semiconductors. In addition, for equivalent voltage ratings, silicon carbide devices offer the advantages of lower on-resistance and lower switching loss than one of those silicons.
SiC基板1に析出した低不純物電圧阻止層3を有する、従来技術に従う例の構造が図1に示されている。現在のところ、このような全ての電圧支持SiC層は、高不純物(高ドーピング)のオフ(オフオリエント)したSiC基板1においてエピタキシャル成長する。このような層3を成長させるための確立した方法は、1600℃付近の温度で実行されるCVD技術である。CVD技術の利点は、SiCバイポーラ装置に必要な、低n型又はp型ドーピング(典型的には1015cm−3の範囲及びより低い)と長いキャリア寿命(数百ナノ秒)の要件を満たすその能力にある。CVDプロセスの主な不利益はその遅い成長速度と、従って100μmより厚い層に対してコスト高になる点にある。例えば、ND〜3×1014cm−3で5〜10μm/hの範囲の成長速度で、20kVの阻止層のための250μm厚のドリフト領域のために、既存のCVDプロセスは25〜50時間の成長時間を必要とする。
An example structure according to the prior art having a low impurity
シリコンの技術では、エピタキシャルパワーデバイス構造の高いコストは、伝導基板で成長した厚い低不純物エピレイヤーの代わりに、低不純物シリコンウェーハをドリフト領域として用いることにより取り組まれてきた。最新式のハイパワーシリコンデバイスのための出発ウェーハは、フロート領域で成長したSi結晶から作られた4〜6インチの中性子変換ウェーハである。例えば、5kVスイッチング装置のドリフト領域は、2×1013cm−3のドーピングを有する約500μm厚のシリコンウェーハを用いる。 In silicon technology, the high cost of epitaxial power device structures has been addressed by using low impurity silicon wafers as drift regions instead of thick low impurity epilayers grown on conductive substrates. The starting wafer for state-of-the-art high power silicon devices is a 4-6 inch neutron conversion wafer made from Si crystals grown in the float region. For example, the drift region of a 5 kV switching device uses a silicon wafer about 500 μm thick with a doping of 2 × 10 13 cm −3 .
現在、この技術はシリコンパワーデバイスを10kVレンジまでの電圧操作能力に限定する。25kVのシリコンデバイスは、1012cm−3又はそれ以下のドリフト領域として2mm厚のウェーハを使用すること、及び400μsの担体寿命を必要とする。炭化ケイ素スイッチング装置は、同じ阻止電圧を実現するために、1桁薄いドリフト領域、1〜2桁高いドーピング及び低めの担体寿命を使用する一方、低めのオン抵抗と低めのスイッチングロスの利点をもたらす。 Currently, this technology limits silicon power devices to voltage manipulation capabilities up to the 10 kV range. A 25 kV silicon device requires the use of a 2 mm thick wafer as a drift region of 10 12 cm −3 or less and a carrier lifetime of 400 μs. Silicon carbide switching devices use the advantages of lower on-resistance and lower switching loss while using an order of magnitude thinner drift region, 1-2 orders of magnitude higher doping and lower carrier lifetime to achieve the same blocking voltage .
しかしながら、低不純物のマイクロ秒レンジの寿命を有するSiCウェーハの不足のために、このアプローチは現在の最新式の炭化ケイ素ウェーハによって使用できる。現在、SiCウェーハは、低めのレンジの抵抗率(n型、約0.015Ωcm及びp型約2.5Ωcm)と、半絶縁性フォーム(ρ>106Ωcm)において基板として用いるために利用できる。低い抵抗率の基板のために、浅いドーパントの濃度(例えば、窒素又はアルミニウム)は典型的には1018cm−3又はそれより高いレンジにある一方、半絶縁性基板は浅い準位(例えば窒素)より高い密度の深い準位(内因性又は外因性)を含む。従って、逆電圧支持能力を有しない低い抵抗率の基板も、自由キャリアの寿命が数ナノ秒よりも短い半絶縁性基板も、パワーデバイスのドリフト領域として用いることができない。 However, this approach can be used with current state-of-the-art silicon carbide wafers due to the lack of SiC wafers with low impurity microsecond range lifetimes. Currently, SiC wafers are available for use as substrates in lower range resistivity (n-type, about 0.015 Ωcm and p-type about 2.5 Ωcm) and semi-insulating foam (ρ> 10 6 Ωcm). For low resistivity substrates, shallow dopant concentrations (eg, nitrogen or aluminum) are typically in the range of 10 18 cm −3 or higher, while semi-insulating substrates are at shallow levels (eg, nitrogen). ) Includes deeper levels (intrinsic or extrinsic) of higher density. Therefore, neither a low-resistivity substrate that does not have reverse voltage support capability nor a semi-insulating substrate with a free carrier lifetime shorter than a few nanoseconds can be used as the drift region of a power device.
十分な伝導率を有する適切なベース材料が利用できないので(n型材料の0.02Ωcmに対して約8Ωcm)、「低い抵抗率」のp型基板に作製された縦型SiC半導体パワーデバイスは、これまでのところ理論にのみ存在する。この不足の理由は、最も一般的な結晶成長プロセスの現在の技術にあると考えられる。アルミニウムの組み込みは、特に高不純物濃度の場合に昇華成長炉で制御することが困難である。さらに、炭化ケイ素における全ての知られたアクセプタのイオン化エネルギーは比較的高い。従って、エピタキシーにより成長したn型ドリフト領域を有するp型基板を用いる基板のような魅力的なIGBTを作製することは可能でない。さらに、適切なベース材料の利用性をも考えると、推定されるIGBT構造の逆方向エミッタの近くで寿命変調によってデバイスパラメータを調節することは限られた可能性しかない(図1)。 Since a suitable base material with sufficient conductivity is not available (approximately 8 Ωcm compared to 0.02 Ωcm for n-type material), vertical SiC semiconductor power devices fabricated on “low resistivity” p-type substrates are: So far it exists only in theory. The reason for this shortage is believed to be the current technology of the most common crystal growth process. The incorporation of aluminum is difficult to control with a sublimation growth furnace, especially at high impurity concentrations. Furthermore, the ionization energy of all known acceptors in silicon carbide is relatively high. Therefore, it is not possible to fabricate an attractive IGBT such as a substrate using a p-type substrate having an n-type drift region grown by epitaxy. Furthermore, considering the availability of a suitable base material, there is only a limited possibility to adjust the device parameters by lifetime modulation near the estimated reverse emitter of the IGBT structure (FIG. 1).
分かっている限りでは、エピタキシャルのSiC基板において実現したIGBT構造は、満足できない技術的なパラメータにより損なわれる。全ての場合で、ベース材料は非常に低い伝導率を有するp型だった。この場合、酸化物の応力が非常に高く、信頼度が非常に低下することになるので(十分な遮断の対策の使用を除く)、MOSゲートを用いた典型的なIGBT構造の成功の実現は可能ではないようである。 As far as is known, the IGBT structure realized in an epitaxial SiC substrate is impaired by unsatisfactory technical parameters. In all cases, the base material was p-type with very low conductivity. In this case, the stress of the oxide is very high and the reliability is greatly reduced (except for the use of sufficient blocking measures), so the success of a typical IGBT structure using a MOS gate is achieved. It seems not possible.
(材料の目的と要約)
本発明の目的は、ウェーハ全体(図2)が高電圧パワーデバイスのドリフト領域として使用することができるような質を有する低不純物n型又はp型結晶からSiCウェーハを作製するための方法を提供することである。この方法は、エピタキシーのために基板として用いられる低い抵抗率のSiCウェーハにおける厚い(>100μm)低不純物層の従来のCVD成長より低いコスト解決法を提供する。本発明は、IGBTのようなSiCスイッチング装置の新しい効率的な設計をも可能にする。
(Material purpose and summary)
It is an object of the present invention to provide a method for fabricating SiC wafers from low impurity n-type or p-type crystals having a quality such that the entire wafer (FIG. 2) can be used as a drift region for high voltage power devices. It is to be. This method provides a lower cost solution than conventional CVD growth of thick (> 100 μm) low impurity layers in low resistivity SiC wafers used as substrates for epitaxy. The present invention also enables new and efficient designs for SiC switching devices such as IGBTs.
(デバイスの目的と要約)
本発明の最も重要な利点は、低い抵抗基板なしに半導体構造を作製することができることである。この基板は、縦型パワーデバイスの場合、不要な付加的な抵抗だけを表す。ウェーハ全体は、非常に高い電圧(15kVよりも大きい)を阻止することができる低不純物nドリフト領域(図2)から成る。
(Device purpose and summary)
The most important advantage of the present invention is that semiconductor structures can be made without a low resistance substrate. This substrate represents only unnecessary additional resistance in the case of a vertical power device. The entire wafer consists of a low impurity n drift region (FIG. 2) that can block very high voltages (greater than 15 kV).
(材料の記述)
バイポーラ装置での適切な操作を可能にするために、ドリフト領域は幾つかの要件を満たさなければならない。第一の要件は高電圧を維持するための低ドーピングであり、典型的には1013〜1014cm−3の正味のキャリア濃度と、100〜300μm程度の十分な厚みである。
(Material description)
In order to allow proper operation in bipolar devices, the drift region must meet several requirements. The first requirement is low doping to maintain a high voltage, typically a net carrier concentration of 10 13 to 10 14 cm −3 and a sufficient thickness of about 100 to 300 μm.
第二の要件は、順方向バイアス下でドリフト領域に注入されるキャリアの十分な寿命であり、それでその結果生じる伝導変調が高い電流密度を可能にする。再結合中心として作用するバンドギャップ内の欠陥準位の存在が、キャリアの寿命に不利な影響を及ぼすことになる。ゆえに、伝導帯と価電子帯の両方とキャリアを交換することができる深い準位のような効率的な再結合中心の濃度は、所望の装置性能によって、同じ位低く保たれなければならない。幾つかの欠陥は、遷移金属及び内因性欠陥のようなSiCにおける深い準位を生じさせることが知られている。積層欠陥のような構造欠陥及び低角度境界は寿命キラーと認定されているので避けなければならない。 The second requirement is a sufficient lifetime of carriers injected into the drift region under forward bias, so that the resulting conduction modulation allows a high current density. The presence of a defect level in the band gap that acts as a recombination center adversely affects the lifetime of the carrier. Therefore, the concentration of efficient recombination centers, such as deep levels that can exchange carriers with both the conduction and valence bands, must be kept as low as desired depending on the desired device performance. Some defects are known to give rise to deep levels in SiC such as transition metals and intrinsic defects. Structural defects such as stacking faults and low-angle boundaries are recognized as lifetime killer and must be avoided.
従来の昇華により、又は物理気相輸送(PVT)から成長した炭化ケイ素結晶から製造されたウェーハは、現在、パワーデバイスのドリフト領域として役立つには十分純粋ではない。PVT成長結晶からスライスされた最も高い純度のウェーハにおいてさえ、窒素濃度は5×1016cm−3程のままである。さらには、発明者の知る限り、層のエピタキシャル成長のための基板としてのみ用いられるこのようなウェーハにおける自由キャリアの寿命を検出することは決して可能ではなかった。 Wafers made from silicon carbide crystals grown by conventional sublimation or from physical vapor transport (PVT) are currently not pure enough to serve as drift regions for power devices. Even in the highest purity wafers sliced from PVT grown crystals, the nitrogen concentration remains on the order of 5 × 10 16 cm −3 . Furthermore, to the best of the inventors' knowledge, it has never been possible to detect the lifetime of free carriers in such wafers used only as substrates for the epitaxial growth of layers.
本発明の一つの目的は、高めの純度かつ長い自由キャリアの寿命のウェーハが製造され得る低不純物炭化ケイ素結晶を成長させるための方法を提供することである。 One object of the present invention is to provide a method for growing low-impurity silicon carbide crystals from which high purity and long free carrier lifetime wafers can be produced.
引例により開示する特許文献1、2及び3に記述されているように、高めの純度のSiC結晶を成長させるための好ましい方法は、いわゆる高温化学気相成長(HTCVD)法である。この気相技術では、従来のCVD法のようにケイ素及び炭素を含有する原材料が浄化ガスによって供給される。例えば、シラン(SiH4)がケイ素前駆体として使用される一方、メタン(CH4)又はエチレン(C2H4)のような炭化水素は炭素前駆体として使用される。SiC結晶又はブールの成長は、所望の時間の長さの間、1900℃を超える温度まで熱せられたSiC種結晶をソースガスの連続流れに晒すことにより実現する。その後、そこから所望の直径及び厚みのウェーハがスライスされ、研磨される。ヘリウム、アルゴン又は水素のようなキャリアガスが前駆体の輸送を援助するのに用いられる。
As described in the
本発明のためのHTCVD技術の幾つかの利点は、超高純度ガスの原材料としての使用、ケイ素に対する炭素のガス混合の比を最適化する能力、及び所望の量のドーピングソースガスを連続して供給する能力である。例えば、SiC結晶は、少量の窒素ガスをソースガス混合気体に導入することにより僅かにn型に作られる。窒素前駆体の流れ速度が、例えば希釈構成を用いてマスフローコントローラによって制御される。その技術は、いわゆるオンアクシスとオフアクシスの種の両方において単一のポリタイプ結晶を成長させることが可能な1900℃より高い成長温度を用いる。ここで、オンアクシスの種結晶は種として定められ、ここではソースガス混合気体に晒された表面が結晶面、例えば(0001)面と10分の数度以内で平行である。オフアクシスの種結晶は、わざと基準結晶面から2分の1度以上に晒された表面を有する。 Some advantages of the HTCVD technique for the present invention include the use of ultra-high purity gas as a raw material, the ability to optimize the gas mixing ratio of carbon to silicon, and the desired amount of doping source gas in succession. The ability to supply. For example, SiC crystals are made slightly n-type by introducing a small amount of nitrogen gas into the source gas mixture. The flow rate of the nitrogen precursor is controlled by the mass flow controller using, for example, a dilution configuration. The technique uses growth temperatures higher than 1900 ° C. that allow single polytype crystals to grow in both so-called on-axis and off-axis seeds. Here, the seed crystal of on-axis is determined as a seed, and here, the surface exposed to the source gas mixed gas is parallel to the crystal plane, for example, the (0001) plane within a few tenths of a degree. An off-axis seed crystal has a surface intentionally exposed to more than one-half degrees from the reference crystal plane.
原子のステップの十分な密度をもたらすために8°までオフされた高不純物基板を用いる従来のCVD法と比べて、HTCVD法は、オンアクシスの又は僅かに間違って方向付けられた(1°以下)種結晶を用いて、種に実質的に低めのステップ密度を有するSiC結晶を成長させることが可能である。軸上のウェーハと少し間違って方向付けされたウェーハの両方ともこのような結晶からスライスされ、研磨される。このようなウェーハをハイパワーデバイスの電圧阻止層として用いることは、電場の異方性効果を減少させる利点がある。 Compared to conventional CVD methods that use high impurity substrates that are turned off by 8 ° to provide sufficient density of atomic steps, HTCVD methods are on-axis or slightly misoriented (below 1 °) ) It is possible to grow a SiC crystal having a substantially lower step density on the seed using the seed crystal. Both on-axis wafers and slightly misoriented wafers are sliced from such crystals and polished. Using such a wafer as a voltage blocking layer in a high power device has the advantage of reducing the electric field anisotropy effect.
本発明は4Hポリタイプの成長、又は炭化ケイ素結晶の結晶格子変異体のために示されるが、その方法は、例えば6H、15R又は3Cのような他のポリタイプの低不純物結晶を成長させるのにも用いられることが明らかである。当該方法は、結晶格子のc軸に沿って、又は近くで成長した結晶のために示される。それは、例えば「数1」や「数2」のようなa軸方向又はSiC結晶格子のc軸とa軸の中間の方向のような他の方向に沿って成長した結晶にも当てはまる。
Although the present invention is shown for 4H polytype growth, or crystal lattice variants of silicon carbide crystals, the method grows low impurity crystals of other polytypes such as 6H, 15R or 3C, for example. It is clear that it can also be used. The method is shown for crystals grown along or near the c-axis of the crystal lattice. This also applies to crystals grown along other directions, such as the a-axis direction such as “
好ましい方法が本発明の実現性を示すために記述されるが、いわゆる当業者は同じタイプの結果を実現する一方で、本発明を改良することもできる。特に、本発明を改良することにより改善されるキャリア寿命の実験値は、以下に与えられる例に限られないと解されるべきである。 Although preferred methods are described to demonstrate the feasibility of the present invention, so-called persons skilled in the art can improve the present invention while achieving the same type of results. In particular, it should be understood that the experimental values of carrier lifetime that are improved by improving the present invention are not limited to the examples given below.
第一の実施形態(参考例)では、本発明は低不純物SiCウェーハを準備するための新規な方法に関する。ウェーハでは、これらのウェーハに作られた装置を操作することにより又は光励起により注入された自由キャリアがある速度で再結合する。第一の実施形態は、結晶自体又はこの結晶からスライスされたウェーハの後成長熱処理に先行する、決められた低n型又はp型ドーピングを用いたSiC結晶の成長に関する。 In a first embodiment (reference example), the present invention relates to a novel method for preparing a low impurity SiC wafer. For wafers, free carriers injected by manipulating the devices made on these wafers or by photoexcitation recombine at a certain rate. The first embodiment relates to the growth of a SiC crystal using a defined low n-type or p-type doping prior to a post-growth heat treatment of the crystal itself or a wafer sliced from this crystal.
本発明によれば、n型又はp型ドーピングは窒素のようなドーパントガスの導入と一体化したバックグラウンドドーピングの正確な制御により得られる。それで結晶のドーパント原子濃度は5×1015cm−3より低く、好ましくは1013〜1014cm−3の範囲になる。図3に示されるように、本発明によって成長した4H結晶における窒素濃度は、SIMSのような分析測定の検出限界より低い。このような結晶からスライスされ、研磨されたウェーハは1014cm−3の範囲の正味のキャリア濃度を有するn型の伝導率を示す(図4)。 According to the present invention, n-type or p-type doping is obtained by precise control of background doping integrated with the introduction of a dopant gas such as nitrogen. Therefore, the dopant atom concentration of the crystal is lower than 5 × 10 15 cm −3 , preferably in the range of 10 13 to 10 14 cm −3 . As shown in FIG. 3, the nitrogen concentration in 4H crystals grown according to the present invention is lower than the detection limit of analytical measurements such as SIMS. A wafer sliced and polished from such a crystal exhibits n-type conductivity with a net carrier concentration in the range of 10 14 cm −3 (FIG. 4).
本発明によれば、低不純物結晶は、HTCVD技術のような純粋な気相法によって100μm/hより高い成長率で成長する。しかしながら、例えば開示する特許文献4に記述されているように、本発明は、純粋なガス前駆体の使用とSi及びCを含有する固体又は液体状態の原材料を結びつける方法により結晶を成長させることによっても実現する。特に、キャリア寿命が光学的に測定されるn型SiCウェーハを得るために、アクセプタ(例えばBとAl)を補償する遷移金属(例えばV、Tiなど)などの不純物の濃度を減少させる必要があることが知られている。これは、成長プロセスの間に意図的な不純物を結晶に放つことを防ぐ材料の選択と、成長プロセスの間に用いられるキャリアと前駆体ガスの両方のための浄化技術の使用を必要とする。特に炭素前駆体がメタンとして選択されるのが好ましい。それは、他の炭化水素より高い純度で製造され、さらにゲッタリングデバイスにより元の位置(インサイチュ)で浄化される。本発明の別な結果は、成長パラメータ及び結晶冷却速度が調節され、それで再結合中心として作用する内因性欠陥の密度が低く保たれ、残りの内因性欠陥がアニール化されることである。例えば、特許文献5の教示を用いて、as-grown結晶がケイ素空格子点を含むように成長条件が調節される。特に、ケイ素空格子点の濃度はこのような結晶のアニール処理によって減少することが分かった。もう一つの選択肢として、成長条件は、例えば炭素空格子点がas-grown結晶に存在するように選択される。
According to the present invention, the low impurity crystal is grown at a growth rate higher than 100 μm / h by a pure gas phase method such as HTCVD technology. However, as described in, for example, US Pat. No. 6,099,077, the present invention is based on the growth of crystals by a method that combines the use of pure gas precursors with raw materials in the solid or liquid state containing Si and C. Also realized. In particular, in order to obtain an n-type SiC wafer whose carrier lifetime is optically measured, it is necessary to reduce the concentration of impurities such as transition metals (such as V and Ti) that compensate the acceptors (such as B and Al). It is known. This requires the selection of materials that prevent intentional impurities from being released into the crystal during the growth process and the use of purification techniques for both the carrier and precursor gases used during the growth process. In particular, the carbon precursor is preferably selected as methane. It is produced with higher purity than other hydrocarbons and is further purified in situ by a gettering device. Another result of the present invention is that growth parameters and crystal cooling rates are adjusted so that the density of intrinsic defects acting as recombination centers is kept low and the remaining intrinsic defects are annealed. For example, using the teaching of
先に述べた、引用によりこの明細書に開示した従来技術のHTCVD技術に従う炭化ケイ素単結晶を製造する早期に知られた方法の例として、以下のプロセスステップについて言及する:
−ケイ素及び炭素原子を含むガスの流れをエンクロージャーに導入し、
−種結晶の温度が、種結晶が、熱せられたエンクロージャーに導入されたSi及びCを含む種の分圧下で分解する温度より低いままになるように、種炭化ケイ素結晶を含むエンクロージャーを1900℃を超える温度に熱し、
−バルク結晶が成長するように、十分な時間の間、1900℃を超える温度とケイ素ガス及び炭素ガスの流れとを維持し、
−その成長の時間の間、n型又はp型の結晶を作るためにドーパントの流れを結晶に導入し、
−内因性準位の濃度をドーパントとして作用する浅い不純物の濃度以下に減少させるために、十分ゆっくりした速度で成長温度から室温まで結晶を冷却し、
−メタン、エチレン及びプロパンの群の炭化水素から炭素を含有するガスを選択し、及び
−シラン、クロロシラン化合物及びメチルシラン化合物の群からケイ素を含有するガスを選択する、各ステップ。
As an example of an earlier known method of manufacturing a silicon carbide single crystal according to the prior art HTCVD technology disclosed herein by reference, reference is made to the following process steps:
Introducing a gas stream containing silicon and carbon atoms into the enclosure;
The enclosure containing the seed silicon carbide crystal at 1900 ° C. so that the temperature of the seed crystal remains below the temperature at which the seed crystal decomposes under the partial pressure of the seed containing Si and C introduced into the heated enclosure Heated to a temperature exceeding
Maintaining a temperature above 1900 ° C. and a flow of silicon and carbon gas for a sufficient time so that the bulk crystal grows;
Introducing a stream of dopant into the crystal to make an n-type or p-type crystal during the growth time;
Cooling the crystal from the growth temperature to room temperature at a sufficiently slow rate in order to reduce the concentration of intrinsic levels below the concentration of shallow impurities acting as dopants,
Each step of selecting a gas containing carbon from the hydrocarbons of the group of methane, ethylene and propane, and-selecting a gas containing silicon from the group of silanes, chlorosilane compounds and methylsilane compounds.
以下の例は、本発明の低不純物及び寿命の要件を満たすと特定された条件を示す。 The following examples illustrate conditions identified as meeting the low impurity and lifetime requirements of the present invention.
(実施例1)
4HポリタイプのSiC単結晶が、400μm/hの平均成長速度を有するHTCVD炉で成長した。少量の窒素流れが、低n型ドーピングをもたらすために炉に供給されたシラン、エチレン及びキャリアガス流れに加えられた。ウェーハはこの結晶からスライスされ、研磨され、容量−電圧(C−V)、深部準位時間分解分光(DLTS)、二次イオン質量分析(SIMS)及び時間分解フォトルミネッセンス(TRPL)の技術を用いて解析される。CV及びDLTS測定は、少なくとも一つの深い準位による窒素ドナーの補償のためにこれらのウェーハで実施することは可能でないと確認された。SIMS測定は、3×1015cm−3の濃度のTi混入を明らかにした。一方、B、Al及びVのような他の不純物は、少なくとも1桁低い濃度を有していた。研磨された後又は1時間1600℃でアニールされた後、このようなウェーハに実行されたTRPL測定は、実験のセットアップの検出限界(<5ns)より小さい減衰時間を示した。このようなウェーハを本発明の目的にとって適切でない。
Example 1
A 4H polytype SiC single crystal was grown in an HTCVD furnace having an average growth rate of 400 μm / h. A small amount of nitrogen stream was added to the silane, ethylene and carrier gas streams fed to the furnace to provide low n-type doping. Wafers are sliced from this crystal, polished, and using capacitance-voltage (CV), deep level time-resolved spectroscopy (DLTS), secondary ion mass spectrometry (SIMS), and time-resolved photoluminescence (TRPL) techniques. Is analyzed. CV and DLTS measurements have been confirmed to be impossible to perform on these wafers due to nitrogen donor compensation by at least one deep level. The SIMS measurement revealed Ti contamination at a concentration of 3 × 10 15 cm −3 . On the other hand, other impurities such as B, Al and V had concentrations that were at least an order of magnitude lower. After being polished or annealed at 1600 ° C. for 1 hour, TRPL measurements performed on such wafers showed decay times that were less than the detection limit of the experimental setup (<5 ns). Such a wafer is not suitable for the purposes of the present invention.
(実施例2)
成長システムを変形し、遷移金属のような望ましくない不純物が成長雰囲気に放たれるのを防ぐ構成要素を選択することにより、成長結晶へのTi混入が抑えられた。低不純物n型4HSiC結晶が先の例の条件と比較した条件で成長した。この結晶におけるTi濃度は5×1013cm−3に減少した。しかしながら、この結晶のas-polishedウェーハにおけるDLTS測定は、それぞれ4.5×1015cm−3と3×1015cm−3の濃度を有する伝導帯から約0.66eVと1.5eVに位置する深い準位の存在を示した。同じ基板においてTRPLで測定されたキャリア寿命は5nsより小さかった。その後、ウェーハは水素環境において1600℃で1時間アニールされた。アニール後、as-polishedウェーハにおいてDLTSで確認された深い準位の濃度は極めて減少した(図5)。TRPL測定は、約20nsの光寿命を有する自由キャリアの再結合は水素でアニールされたウェーハで観測されることも示した。この結果は、ウェーハに存在し、効率的な再結合チャネルとして作用する内因性欠陥の水素の種によるアニール又はパッシベーションとして解釈できる。ケイ素空格子点及び炭素空格子点のような内因性欠陥、及び寿命キラーとして作用するケイ素アンチサイトは、例えば半絶縁性SiC結晶において確認されている(特許文献5)。
(Example 2)
By modifying the growth system and selecting components that prevent unwanted impurities such as transition metals from being released into the growth atmosphere, Ti contamination into the growth crystal was suppressed. A low-impurity n-type 4HSiC crystal was grown under conditions compared to those in the previous example. The Ti concentration in this crystal decreased to 5 × 10 13 cm −3 . However, DLTS measurements on as-polished wafers of this crystal are located at about 0.66 eV and 1.5 eV from the conduction bands having concentrations of 4.5 × 10 15 cm −3 and 3 × 10 15 cm −3 , respectively. It showed the existence of a deep level. The carrier lifetime measured by TRPL on the same substrate was less than 5 ns. The wafer was then annealed at 1600 ° C. for 1 hour in a hydrogen environment. After annealing, the deep level concentration confirmed by DLTS in the as-polished wafer was greatly reduced (FIG. 5). TRPL measurements also showed that free carrier recombination with an optical lifetime of about 20 ns was observed in hydrogen annealed wafers. This result can be interpreted as an annealing or passivation by endogenous species of hydrogen present in the wafer and acting as an efficient recombination channel. Intrinsic defects such as silicon vacancies and carbon vacancies and silicon antisites acting as lifetime killer have been confirmed in, for example, semi-insulating SiC crystals (Patent Document 5).
(実施例3)
結晶で成長した内因性欠陥の濃度を減少させるために成長条件を変化させることにより、先の実施例の結果は考慮された。この例では、エチレン/シランガスの混合気体のインプットC/Si比は増加した。図6は、このような結晶からスライスされ、研磨されたウェーハが1.5eVでDLTSにより確認された実質的に低めの深い準位の濃度(しかしZ1/2準位と同等な濃度)を有することを示す。水素又はアルゴン環境で1600℃でアニールすると、深い準位の両方の濃度は先の例(図6)のように減少する。しかしながら、水素を含む環境でアニールされた基板のキャリア寿命は3倍になり、約60nsまで増加した(図7)。しかしながら、同じ結晶から切られ、純粋なアルゴン環境でアニールされた別なウェーハのキャリア寿命は、TRPLシステムの検出限界より低いままである。
(Example 3)
By changing the growth conditions to reduce the concentration of intrinsic defects grown in the crystal, the results of the previous examples were considered. In this example, the input C / Si ratio of the ethylene / silane gas mixture increased. FIG. 6 shows that a wafer sliced and polished from such a crystal has a substantially lower deep level concentration (but equivalent to the Z1 / 2 level) as confirmed by DLTS at 1.5 eV. It shows that. When annealing at 1600 ° C. in a hydrogen or argon environment, both deep level concentrations decrease as in the previous example (FIG. 6). However, the carrier lifetime of the substrate annealed in an environment containing hydrogen tripled and increased to about 60 ns (FIG. 7). However, the carrier lifetime of another wafer cut from the same crystal and annealed in a pure argon environment remains below the detection limit of the TRPL system.
15kV以上の阻止電圧を有するデバイスの電流密度の要求を満たすために、TRPLで光崩壊により測定される寿命の値を数マイクロ秒の値まで増加させるために、本発明の第一実施形態の教示が使用され、改良されることが理解される。光学的に測定される寿命値がバイポーラ装置から抽出された値と異なることも理解される。しかしながら、本発明は、以下に主張する低不純物SiC結晶における寿命値を増加させる第一の方法を教示する。 The teaching of the first embodiment of the present invention to increase the value of lifetime measured by photodisintegration in TRPL to a value of a few microseconds to meet the current density requirement of devices with blocking voltages of 15 kV or higher Is used and improved. It is also understood that the lifetime value measured optically is different from the value extracted from the bipolar device. However, the present invention teaches a first method of increasing the lifetime value in the low impurity SiC crystal claimed below.
(デバイスの記述)
第二実施形態では、本発明は、本発明の実施形態のいずれかに従って製造される低不純物ウェーハを用いたハイパワーバイポーラ装置構造を提案する。
(Device description)
In a second embodiment, the present invention proposes a high power bipolar device structure using a low impurity wafer manufactured according to any of the embodiments of the present invention.
本発明は、低不純物ウェーハをドリフト領域として用いて高抵抗基板の問題を解決する。ドリフト領域は同時に装置構造のためのメカニカルサポートとして働く。このようなウェーハは、第一実施形態で記述されるオンアクシスプロセスによって成長する。約150μmを超える厚みのために、材料は別な処理ステップに対して十分な機械的安定度を有する。エミッタは、裏面から、マスクした又はマスクしていない裏面へのイオン注入により実現する(図8及び9)。この注入は、特に適用の要求のために調節されるエミッタ効率及び少数キャリアの寿命を得るために最適化される。さらに、逆阻止装置を得るために、単純なプロセスステップを用いて、ウェーハの裏面で平面接合エッジ終端の実現が可能になる(図2)。ここで公開した開示は、非常に高い阻止電圧を阻止することができる単一のスイッチング装置を作製する機会を提供する。これは、シリコンにおいて、複雑な制御回路を必要とするスイッチング装置の直列接続を使用することによってのみ実現する(例SiC:250〜280μm厚のドリフト領域、ND−NA=3×1014cm−3、20kV阻止電圧)。 The present invention solves the problem of high resistance substrates using a low impurity wafer as the drift region. The drift region simultaneously serves as a mechanical support for the device structure. Such a wafer is grown by the on-axis process described in the first embodiment. Due to the thickness above about 150 μm, the material has sufficient mechanical stability for another processing step. The emitter is realized by ion implantation from the back side into the masked or unmasked back side (FIGS. 8 and 9). This injection is optimized to obtain emitter efficiency and minority carrier lifetimes that are tailored specifically for application requirements. Furthermore, it is possible to realize planar junction edge termination on the backside of the wafer using simple process steps to obtain a reverse blocking device (FIG. 2). The disclosure disclosed here provides an opportunity to create a single switching device that can block very high blocking voltages. This is only realized in silicon by using a series connection of switching devices that require complex control circuits (eg SiC: 250-280 μm thick drift region, N D −N A = 3 × 10 14 cm). -3 , 20 kV blocking voltage).
ここで公開した解決法の最も重要な利点は、縦型パワーデバイスの場合に不要な付加的な抵抗を表す基板なしに半導体構造を作製する可能性である。ウェーハ全体は、非常に高い電圧(15kVより大きい)を阻止することができる低不純物n−ドリフト領域から成る。さらに、逆方向エミッタがウェーハ裏面へのイオン注入を介して慎重に設計される。これは、選択的に付加的なフィールドストップ領域を用いて又は用いずに実現する。裏面エミッタにおいて接合終端エクステンション(JTE)を実現することにより、逆阻止装置が可能になる。別な利点は、少数キャリアの寿命を調節するために逆方向pn接合を局所的に照射する可能性である。SiCウェーハ自体は可視光を通すので、前面の制御セルに対するウェーハ裏面における構造の調節は、リソグラフィー用のラージギャップの対物レンズを用いて容易に実行される。従って、調節は前面の位置合わせマークに対して実行される。さらに、HTCVDプロセスはオンアクシス成長を実行する可能性をもたらす。ゆえに、例えば電気破壊フィールドの異方性による否定的な影響は最小化され又は排除される。 The most important advantage of the solution disclosed here is the possibility of producing a semiconductor structure without a substrate that represents additional resistance that is not necessary in the case of vertical power devices. The entire wafer consists of a low impurity n-drift region that can block very high voltages (greater than 15 kV). In addition, the reverse emitter is carefully designed through ion implantation into the backside of the wafer. This is achieved optionally with or without an additional field stop region. By implementing a junction termination extension (JTE) at the backside emitter, a reverse blocking device is possible. Another advantage is the possibility of locally irradiating the reverse pn junction to adjust the minority carrier lifetime. Since the SiC wafer itself transmits visible light, adjustment of the structure on the backside of the wafer relative to the front control cell is easily performed using a large gap objective lens for lithography. Therefore, the adjustment is performed on the front alignment mark. Furthermore, the HTCVD process offers the possibility of performing on-axis growth. Thus, negative effects due to, for example, the anisotropy of the electrical breakdown field are minimized or eliminated.
(例)
限定的な例ではない。図9がアクティブなデバイス層として低不純物n−基板を用いた仮定の新しいIGBT構造の断面を示す。
(Example)
This is not a limiting example. FIG. 9 shows a cross section of a hypothetical new IGBT structure using a low impurity n - substrate as the active device layer.
N−ウェーハは装置の所望な阻止電圧に従ってドープ処理されなければならない。層の最小の厚みは薄いウェーハを扱う技術の能力によって与えられる。技術プロセスの状態を考慮すると、この限界は150μmぐらいに見出される。しかしながら、別な発展型はこの厚みをより低い値にシフトさせることができる。pウエルベース領域_5がドリフト領域に注入され、選択的なエピタキシャル成長により拡散又は創出される。この層の深さは用いられる技術に依存して数ナノメートル〜数マイクロメートルになる。ドーピングは1×1016cm−3から1020cm−3より高い値にまでなる。典型的には、それは数1018cm−3〜1019cm−3の範囲にある。pウエルの間の隙間は数μm〜100μmの範囲にある。N−ウェーハの表面及びpウエルの内部にn型ソース領域が位置している。ソース領域と表面のpウエルの端との距離が装置のチャネルの長さを定める。これは1μm〜100μmの間であり、パワーデバイスでは典型的には2〜4μm程の値である。ソース領域は、p領域に対して用いられるより高いドーピングによって(典型的には1019cm−3より大きい)、n型伝導率の領域で形成される。デバイスの周囲では、JTE(特許文献6)が実行される。ソース領域に多少重なり、pウエルの間の間隔に完全に重なったチャネル領域の上に、ゲート酸化膜が位置する。ゲート酸化膜として、全て一般的な二酸化ケイ素、窒化ケイ素又は他の新しい誘電体のような薄いフィルム絶縁体が用いられる。熱で成長した又は析出した約80nm厚の二酸化ケイ素層が、パワーデバイスにとって典型的である。ゲート材料として、金属、金属ケイ化物又はポリシリコンのような高伝導材料が用いられる。このゲートは、広範囲の前面のエミッタコンタクトから電気的に絶縁している。このコンタクト層は普通、厚いアルミニウム又は別な金属によって形成される。pウエル(酸化物、ゲート電極)の上の層は制御領域として作用する。その構造の裏面には、コレクタコンタクト領域がある。このコレクタコンタクトはアクティブ領域(pウエル)と反対側の全領域にわたって位置するか、低不純物ウェーハとのオーミックコンタクトを有する小さい領域によって間隔をあけられる。コレクタ領域(裏面エミッタ)は低不純物ウェーハと反対の伝導率を有し、そのドーピングはウェーハのドーピングを超える。典型的な値は、1017cm−3〜1019cm−3である。この層の深さと形成に対して、pウエルのルールが当てはまる。順方向の注入を維持する一方で阻止の場合に十分な遮断効果を保障するために、幅と間隔は数μm程度の範囲で選択される。逆阻止のために、前面のJTEに対応するJTEが実行される。裏面の層は透明なSiCウェーハのために前面の構造に位置合わせがなされる。これは、シリコンの解決法に比べて重要な利点である。さらに、ウェーハ全体が装置のアクティブ領域として働くという事実のため、裏面構造は表面での直接の選択されたドーピングにより形成される。 The N - wafer must be doped according to the desired blocking voltage of the device. The minimum layer thickness is given by the ability of the technology to handle thin wafers. Considering the state of the technical process, this limit is found around 150 μm. However, other developments can shift this thickness to lower values. A p-well base region_5 is implanted into the drift region and is diffused or created by selective epitaxial growth. The depth of this layer can be from a few nanometers to a few micrometers depending on the technology used. The doping goes from 1 × 10 16 cm −3 to a value higher than 10 20 cm −3 . Typically, it is in the range of a few 10 18 cm −3 to 10 19 cm −3 . The gap between the p-wells is in the range of several μm to 100 μm. An n-type source region is located on the surface of the N-wafer and inside the p-well. The distance between the source region and the surface p-well edge determines the channel length of the device. This is between 1 μm and 100 μm, and is typically about 2 to 4 μm for power devices. The source region is formed in a region of n-type conductivity by the higher doping used for the p region (typically greater than 10 19 cm −3 ). JTE (Patent Document 6) is executed around the device. A gate oxide is located on the channel region that overlaps the source region somewhat and completely overlaps the spacing between the p-wells. A thin film insulator such as common silicon dioxide, silicon nitride or other new dielectric is used as the gate oxide. A thermally grown or deposited silicon dioxide layer of about 80 nm thickness is typical for power devices. As the gate material, a highly conductive material such as metal, metal silicide or polysilicon is used. This gate is electrically isolated from a wide range of front emitter contacts. This contact layer is usually formed of thick aluminum or another metal. The layer above the p-well (oxide, gate electrode) acts as a control region. On the back side of the structure is a collector contact region. This collector contact is located over the entire region opposite the active region (p-well) or is spaced by a small region having ohmic contact with a low impurity wafer. The collector region (backside emitter) has the opposite conductivity to the low impurity wafer and its doping exceeds that of the wafer. Typical values are 10 < 17 > cm < -3 > to 10 < 19 > cm < -3 >. The p-well rule applies to the depth and formation of this layer. In order to maintain a forward injection while ensuring a sufficient blocking effect in the case of blocking, the width and spacing are selected in the range of a few μm. For reverse blocking, a JTE corresponding to the front JTE is executed. The back layer is aligned to the front structure for a transparent SiC wafer. This is an important advantage over silicon solutions. Furthermore, due to the fact that the entire wafer serves as the active area of the device, the backside structure is formed by direct selected doping at the surface.
Claims (17)
ドリフト領域の前面に配された第一コンタクト電極、
前面に配され、かつ少なくとも第一伝導率タイプのキャリアのドリフト領域への入射を制御する制御領域、及び
ドリフト領域の裏面に第二コンタクト電極を有する、ドリフト領域が第一コンタクト電極と第二コンタクト電極の間でキャリア流れを運ぶように配された半導体装置において、
ドリフト領域が、1015cm−3より低い正味のキャリア濃度と少なくとも50nsのキャリア寿命を有する炭化ケイ素ウェーハから成ることを特徴とする半導体装置。 A drift region of the first conductivity type that acts as a substrate layer having a front surface and a back surface;
A first contact electrode disposed in front of the drift region;
A control region disposed on the front surface and controlling the incidence of at least a first conductivity type carrier on the drift region, and a second contact electrode on the back surface of the drift region, wherein the drift region includes the first contact electrode and the second contact In a semiconductor device arranged to carry a carrier flow between electrodes,
A semiconductor device, wherein the drift region comprises a silicon carbide wafer having a net carrier concentration lower than 10 15 cm −3 and a carrier lifetime of at least 50 ns.
ドリフト領域内の前面の表面に配され、スペースで分離されている、所定の深さを有する第二伝導率タイプの少なくとも二つのベース領域;
前面の表面に位置し、第二伝導率タイプのベース領域内にある第一伝導率タイプのソース領域;
ソース領域を有するベース領域内の前面の表面に配され、ソース領域とベース領域の端の間に配されたチャネル領域;
チャネル領域を制御するためのゲート電極;及び
ゲート電極をチャネル領域から電気的に分離するためのゲート絶縁領域
を有することを特徴とする請求項1に記載の装置。 The control area is
At least two base regions of the second conductivity type having a predetermined depth, arranged on the front surface in the drift region and separated by a space;
A first conductivity type source region located on the front surface and within a second conductivity type base region;
A channel region disposed on a front surface in a base region having a source region and disposed between an end of the source region and the base region;
The apparatus of claim 1, comprising: a gate electrode for controlling the channel region; and a gate insulating region for electrically isolating the gate electrode from the channel region.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE0202585A SE525574C2 (en) | 2002-08-30 | 2002-08-30 | Low-doped silicon carbide substrate and its use in high-voltage components |
SE0202585-6 | 2002-08-30 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004532493A Division JP5081373B2 (en) | 2002-08-30 | 2003-08-22 | Method for producing low impurity silicon carbide wafer |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015006669A Division JP2015099932A (en) | 2002-08-30 | 2015-01-16 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2012099832A true JP2012099832A (en) | 2012-05-24 |
Family
ID=20288862
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004532493A Expired - Fee Related JP5081373B2 (en) | 2002-08-30 | 2003-08-22 | Method for producing low impurity silicon carbide wafer |
JP2011274530A Pending JP2012099832A (en) | 2002-08-30 | 2011-12-15 | Semiconductor device |
JP2015006669A Pending JP2015099932A (en) | 2002-08-30 | 2015-01-16 | Semiconductor device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004532493A Expired - Fee Related JP5081373B2 (en) | 2002-08-30 | 2003-08-22 | Method for producing low impurity silicon carbide wafer |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015006669A Pending JP2015099932A (en) | 2002-08-30 | 2015-01-16 | Semiconductor device |
Country Status (5)
Country | Link |
---|---|
US (3) | US7482068B2 (en) |
EP (1) | EP1540050A1 (en) |
JP (3) | JP5081373B2 (en) |
SE (1) | SE525574C2 (en) |
WO (1) | WO2004020706A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015099932A (en) * | 2002-08-30 | 2015-05-28 | ノーステル エービー | Semiconductor device |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10330571B8 (en) * | 2003-07-07 | 2007-03-08 | Infineon Technologies Ag | Vertical power semiconductor devices with injection damping agent in the edge area and manufacturing method therefor |
US7157785B2 (en) * | 2003-08-29 | 2007-01-02 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices |
US6974720B2 (en) * | 2003-10-16 | 2005-12-13 | Cree, Inc. | Methods of forming power semiconductor devices using boule-grown silicon carbide drift layers and power semiconductor devices formed thereby |
DE102004047313B3 (en) * | 2004-09-29 | 2006-03-30 | Siced Electronics Development Gmbh & Co. Kg | Semiconductor arrangement with a tunnel contact and method for its production |
US7811943B2 (en) * | 2004-12-22 | 2010-10-12 | Cree, Inc. | Process for producing silicon carbide crystals having increased minority carrier lifetimes |
US7615801B2 (en) * | 2005-05-18 | 2009-11-10 | Cree, Inc. | High voltage silicon carbide devices having bi-directional blocking capabilities |
US7414268B2 (en) * | 2005-05-18 | 2008-08-19 | Cree, Inc. | High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities |
DE102005053487B4 (en) * | 2005-11-09 | 2011-06-09 | Infineon Technologies Ag | Power IGBT with increased robustness |
US20090087967A1 (en) * | 2005-11-14 | 2009-04-02 | Todd Michael A | Precursors and processes for low temperature selective epitaxial growth |
US8432012B2 (en) | 2006-08-01 | 2013-04-30 | Cree, Inc. | Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same |
US7728402B2 (en) | 2006-08-01 | 2010-06-01 | Cree, Inc. | Semiconductor devices including schottky diodes with controlled breakdown |
WO2008020911A2 (en) | 2006-08-17 | 2008-02-21 | Cree, Inc. | High power insulated gate bipolar transistors |
JP4946264B2 (en) * | 2006-08-23 | 2012-06-06 | 日立金属株式会社 | Method for manufacturing silicon carbide semiconductor epitaxial substrate |
JP5261907B2 (en) * | 2006-09-19 | 2013-08-14 | 富士電機株式会社 | Trench gate type silicon carbide semiconductor device |
US8835987B2 (en) | 2007-02-27 | 2014-09-16 | Cree, Inc. | Insulated gate bipolar transistors including current suppressing layers |
US8866150B2 (en) * | 2007-05-31 | 2014-10-21 | Cree, Inc. | Silicon carbide power devices including P-type epitaxial layers and direct ohmic contacts |
US8409351B2 (en) * | 2007-08-08 | 2013-04-02 | Sic Systems, Inc. | Production of bulk silicon carbide with hot-filament chemical vapor deposition |
DE102007052202B3 (en) * | 2007-10-30 | 2008-11-13 | Infineon Technologies Austria Ag | Semiconductor component i.e. Schottky diode, has metallization structure electrically connected with compensation zones by Schottky contact and with drift zones by ohmic contact, where structure is arranged opposite to another structure |
US7759213B2 (en) * | 2008-08-11 | 2010-07-20 | International Business Machines Corporation | Pattern independent Si:C selective epitaxy |
US8294507B2 (en) | 2009-05-08 | 2012-10-23 | Cree, Inc. | Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits |
US8629509B2 (en) | 2009-06-02 | 2014-01-14 | Cree, Inc. | High voltage insulated gate bipolar transistors with minority carrier diverter |
US8193848B2 (en) | 2009-06-02 | 2012-06-05 | Cree, Inc. | Power switching devices having controllable surge current capabilities |
US8541787B2 (en) | 2009-07-15 | 2013-09-24 | Cree, Inc. | High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability |
US8354690B2 (en) | 2009-08-31 | 2013-01-15 | Cree, Inc. | Solid-state pinch off thyristor circuits |
US8574528B2 (en) * | 2009-09-04 | 2013-11-05 | University Of South Carolina | Methods of growing a silicon carbide epitaxial layer on a substrate to increase and control carrier lifetime |
US9117739B2 (en) | 2010-03-08 | 2015-08-25 | Cree, Inc. | Semiconductor devices with heterojunction barrier regions and methods of fabricating same |
US8415671B2 (en) | 2010-04-16 | 2013-04-09 | Cree, Inc. | Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices |
CN102560671B (en) * | 2010-12-31 | 2015-05-27 | 中国科学院物理研究所 | Semi-insulating silicon carbide mono-crystal |
US9029945B2 (en) | 2011-05-06 | 2015-05-12 | Cree, Inc. | Field effect transistor devices with low source resistance |
US9673283B2 (en) | 2011-05-06 | 2017-06-06 | Cree, Inc. | Power module for supporting high current densities |
US9142662B2 (en) | 2011-05-06 | 2015-09-22 | Cree, Inc. | Field effect transistor devices with low source resistance |
JP2013004572A (en) * | 2011-06-13 | 2013-01-07 | Mitsubishi Electric Corp | Semiconductor device manufacturing method |
US9640617B2 (en) | 2011-09-11 | 2017-05-02 | Cree, Inc. | High performance power module |
US9373617B2 (en) | 2011-09-11 | 2016-06-21 | Cree, Inc. | High current, low switching loss SiC power module |
JP6017127B2 (en) * | 2011-09-30 | 2016-10-26 | 株式会社東芝 | Silicon carbide semiconductor device |
CH707901B1 (en) | 2012-02-06 | 2017-09-15 | Cree Inc | SIC device with high blocking voltage, completed by a flattening edge termination. |
DE112012006967B4 (en) | 2012-10-02 | 2022-09-01 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing a semiconductor device |
US11721547B2 (en) * | 2013-03-14 | 2023-08-08 | Infineon Technologies Ag | Method for manufacturing a silicon carbide substrate for an electrical silicon carbide device, a silicon carbide substrate and an electrical silicon carbide device |
JP6183080B2 (en) * | 2013-09-09 | 2017-08-23 | 住友電気工業株式会社 | Silicon carbide semiconductor device and manufacturing method thereof |
JP6271309B2 (en) * | 2014-03-19 | 2018-01-31 | 株式会社東芝 | Semiconductor substrate manufacturing method, semiconductor substrate, and semiconductor device |
CN108463885A (en) | 2015-12-11 | 2018-08-28 | 罗姆股份有限公司 | Semiconductor device |
KR102185158B1 (en) | 2016-08-19 | 2020-12-01 | 로무 가부시키가이샤 | Semiconductor device |
JP6811118B2 (en) * | 2017-02-27 | 2021-01-13 | 株式会社豊田中央研究所 | MOSFET |
JP2017228790A (en) * | 2017-08-30 | 2017-12-28 | 良孝 菅原 | Semiconductor device and operation method of the same |
US11094806B2 (en) * | 2017-12-29 | 2021-08-17 | Texas Instruments Incorporated | Fabricating transistors with implanting dopants at first and second dosages in the collector region to form the base region |
JP2020129675A (en) * | 2020-04-21 | 2020-08-27 | ローム株式会社 | Semiconductor device |
TW202200498A (en) * | 2020-06-18 | 2022-01-01 | 盛新材料科技股份有限公司 | Semi-insulating single crystal silicon carbide bulk and powder |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07307469A (en) * | 1994-03-14 | 1995-11-21 | Toshiba Corp | Semiconductor device |
JPH09500861A (en) * | 1993-07-31 | 1997-01-28 | ダイムラー−ベンツ アクチエンゲゼルシャフト | Manufacturing method of high and low anti-silicon carbide |
JP2001511315A (en) * | 1997-02-07 | 2001-08-07 | クーパー,ジェームズ・アルバート,ジュニアー | Structure for increasing the maximum voltage of silicon carbide power transistor |
JP2005507360A (en) * | 2001-10-29 | 2005-03-17 | オクメティック オーワイジェー | High resistivity silicon carbide single crystal |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5043773A (en) * | 1990-06-04 | 1991-08-27 | Advanced Technology Materials, Inc. | Wafer base for silicon carbide semiconductor devices, incorporating alloy substrates |
CA2113336C (en) * | 1993-01-25 | 2001-10-23 | David J. Larkin | Compound semi-conductors and controlled doping thereof |
US5709745A (en) * | 1993-01-25 | 1998-01-20 | Ohio Aerospace Institute | Compound semi-conductors and controlled doping thereof |
JP3182262B2 (en) * | 1993-07-12 | 2001-07-03 | 株式会社東芝 | Semiconductor device |
TW286435B (en) | 1994-07-27 | 1996-09-21 | Siemens Ag | |
US5736430A (en) * | 1995-06-07 | 1998-04-07 | Ssi Technologies, Inc. | Transducer having a silicon diaphragm and method for forming same |
SE9502288D0 (en) | 1995-06-26 | 1995-06-26 | Abb Research Ltd | A device and a method for epitaxially growing objects by CVD |
US6030661A (en) | 1995-08-04 | 2000-02-29 | Abb Research Ltd. | Device and a method for epitaxially growing objects by CVD |
US6573534B1 (en) * | 1995-09-06 | 2003-06-03 | Denso Corporation | Silicon carbide semiconductor device |
SE9503428D0 (en) | 1995-10-04 | 1995-10-04 | Abb Research Ltd | A method for growing epitaxially and a device for such growth |
US6039812A (en) | 1996-10-21 | 2000-03-21 | Abb Research Ltd. | Device for epitaxially growing objects and method for such a growth |
US6180958B1 (en) * | 1997-02-07 | 2001-01-30 | James Albert Cooper, Jr. | Structure for increasing the maximum voltage of silicon carbide power transistors |
JPH10256529A (en) * | 1997-03-14 | 1998-09-25 | Fuji Electric Co Ltd | Insulated gate type silicon carbide thyristor |
JPH11162850A (en) * | 1997-08-27 | 1999-06-18 | Matsushita Electric Ind Co Ltd | Silicon carbide substrate and its production, and semiconductor element using the same |
JP3968860B2 (en) * | 1998-03-20 | 2007-08-29 | 株式会社デンソー | Method for manufacturing silicon carbide semiconductor device |
US6100169A (en) * | 1998-06-08 | 2000-08-08 | Cree, Inc. | Methods of fabricating silicon carbide power devices by controlled annealing |
JP2000101066A (en) * | 1998-09-25 | 2000-04-07 | Toshiba Corp | Power semiconductor device |
JP2000216090A (en) * | 1999-01-27 | 2000-08-04 | Toshiba Corp | Manufacture of polycrystalline semiconductor device |
US6218680B1 (en) * | 1999-05-18 | 2001-04-17 | Cree, Inc. | Semi-insulating silicon carbide without vanadium domination |
US6329088B1 (en) * | 1999-06-24 | 2001-12-11 | Advanced Technology Materials, Inc. | Silicon carbide epitaxial layers grown on substrates offcut towards <1{overscore (1)}00> |
TW565630B (en) * | 1999-09-07 | 2003-12-11 | Sixon Inc | SiC wafer, SiC semiconductor device and method for manufacturing SiC wafer |
JP4581179B2 (en) * | 2000-04-26 | 2010-11-17 | 富士電機システムズ株式会社 | Insulated gate semiconductor device |
JP3650727B2 (en) * | 2000-08-10 | 2005-05-25 | Hoya株式会社 | Silicon carbide manufacturing method |
JP4887559B2 (en) * | 2000-11-07 | 2012-02-29 | 富士電機株式会社 | Manufacturing method of semiconductor device |
JP3864696B2 (en) * | 2000-11-10 | 2007-01-10 | 株式会社デンソー | Method and apparatus for producing silicon carbide single crystal |
JP2002231944A (en) * | 2001-01-31 | 2002-08-16 | Sanken Electric Co Ltd | Power semiconductor device |
JP3451247B2 (en) * | 2001-02-07 | 2003-09-29 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
AU2002237483A1 (en) | 2001-03-23 | 2002-10-08 | International Business Machines Corporation | Apparatus and method for storing and reading high data capacities |
EP1306890A2 (en) * | 2001-10-25 | 2003-05-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor substrate and device comprising SiC and method for fabricating the same |
FR2834123B1 (en) * | 2001-12-21 | 2005-02-04 | Soitec Silicon On Insulator | SEMICONDUCTOR THIN FILM DELIVERY METHOD AND METHOD FOR OBTAINING A DONOR WAFER FOR SUCH A DELAYING METHOD |
US6814801B2 (en) * | 2002-06-24 | 2004-11-09 | Cree, Inc. | Method for producing semi-insulating resistivity in high purity silicon carbide crystals |
SE525574C2 (en) * | 2002-08-30 | 2005-03-15 | Okmetic Oyj | Low-doped silicon carbide substrate and its use in high-voltage components |
US6964917B2 (en) * | 2003-04-08 | 2005-11-15 | Cree, Inc. | Semi-insulating silicon carbide produced by Neutron transmutation doping |
-
2002
- 2002-08-30 SE SE0202585A patent/SE525574C2/en not_active IP Right Cessation
-
2003
- 2003-08-22 JP JP2004532493A patent/JP5081373B2/en not_active Expired - Fee Related
- 2003-08-22 US US10/526,059 patent/US7482068B2/en not_active Expired - Lifetime
- 2003-08-22 EP EP03791515A patent/EP1540050A1/en not_active Ceased
- 2003-08-22 WO PCT/SE2003/001309 patent/WO2004020706A1/en active Application Filing
-
2009
- 2009-01-13 US US12/352,793 patent/US8097524B2/en not_active Expired - Lifetime
-
2011
- 2011-12-15 JP JP2011274530A patent/JP2012099832A/en active Pending
- 2011-12-29 US US13/340,192 patent/US8803160B2/en not_active Expired - Fee Related
-
2015
- 2015-01-16 JP JP2015006669A patent/JP2015099932A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09500861A (en) * | 1993-07-31 | 1997-01-28 | ダイムラー−ベンツ アクチエンゲゼルシャフト | Manufacturing method of high and low anti-silicon carbide |
JPH07307469A (en) * | 1994-03-14 | 1995-11-21 | Toshiba Corp | Semiconductor device |
JP2001511315A (en) * | 1997-02-07 | 2001-08-07 | クーパー,ジェームズ・アルバート,ジュニアー | Structure for increasing the maximum voltage of silicon carbide power transistor |
JP2005507360A (en) * | 2001-10-29 | 2005-03-17 | オクメティック オーワイジェー | High resistivity silicon carbide single crystal |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015099932A (en) * | 2002-08-30 | 2015-05-28 | ノーステル エービー | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US8803160B2 (en) | 2014-08-12 |
JP2005537657A (en) | 2005-12-08 |
JP2015099932A (en) | 2015-05-28 |
US20060137600A1 (en) | 2006-06-29 |
US20120091471A1 (en) | 2012-04-19 |
US8097524B2 (en) | 2012-01-17 |
EP1540050A1 (en) | 2005-06-15 |
US7482068B2 (en) | 2009-01-27 |
SE0202585D0 (en) | 2002-08-30 |
SE525574C2 (en) | 2005-03-15 |
WO2004020706A1 (en) | 2004-03-11 |
JP5081373B2 (en) | 2012-11-28 |
US20090114924A1 (en) | 2009-05-07 |
SE0202585L (en) | 2004-03-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5081373B2 (en) | Method for producing low impurity silicon carbide wafer | |
JP3854508B2 (en) | SiC wafer, SiC semiconductor device, and method of manufacturing SiC wafer | |
JP4185215B2 (en) | SiC wafer, SiC semiconductor device, and method of manufacturing SiC wafer | |
US5709745A (en) | Compound semi-conductors and controlled doping thereof | |
US5463978A (en) | Compound semiconductor and controlled doping thereof | |
JP5458509B2 (en) | Silicon carbide semiconductor substrate | |
JP3650727B2 (en) | Silicon carbide manufacturing method | |
Liu et al. | Low temperature chemical vapor deposition growth of β-SiC on (100) Si using methylsilane and device characteristics | |
US20110006310A1 (en) | Semiconductor device and semiconductor device manufacturing method | |
JP2009088223A (en) | Silicon carbide semiconductor substrate and silicon carbide semiconductor device using the same | |
JP2007131504A (en) | SiC EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE USING THE SAME | |
KR20070029694A (en) | Bipolar semiconductor device and process for producing the same | |
KR20160070743A (en) | N-type aluminum nitride single-crystal substrate and vertical nitride semiconductor device | |
US9590047B2 (en) | SiC bipolar junction transistor with reduced carrier lifetime in collector and a defect termination layer | |
Davis | Epitaxial growth and doping of and device development in monocyrstalline β-SiC semiconductor thin films | |
US20050184296A1 (en) | System and method for fabricating diodes | |
JP2019067982A (en) | Silicon carbide semiconductor device | |
RU2297690C1 (en) | Method for manufacturing superconductor heterostructure around a3b5 compounds by way of liquid-phase epitaxy | |
Kong et al. | Growth, doping, device development and characterization of CVD beta-SiC epilayers on Si (100) and alpha-SiC (0001) | |
JP2000223719A (en) | Semiconductor device | |
WO2008015765A1 (en) | Bipolar semiconductor device and process for producing the same | |
Chen | Epitaxial growth of 4H-silicon carbide by CVD for bipolar power device applications |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130729 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130820 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20131119 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20131122 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20131219 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20131225 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20140117 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20140122 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140219 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140916 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150116 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20150324 |
|
A912 | Removal of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20150529 |