JP2012094697A - Circuit board and electronic device - Google Patents

Circuit board and electronic device Download PDF

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JP2012094697A
JP2012094697A JP2010240987A JP2010240987A JP2012094697A JP 2012094697 A JP2012094697 A JP 2012094697A JP 2010240987 A JP2010240987 A JP 2010240987A JP 2010240987 A JP2010240987 A JP 2010240987A JP 2012094697 A JP2012094697 A JP 2012094697A
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circuit board
plating layer
thickness
joint
electronic device
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Tomoki Inoue
友喜 井上
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board and an electronic device capable of reducing the effects of mechanical shock or stress due to differences in thermal expansion coefficient.SOLUTION: A circuit board 1 includes a substrate 11 and lead members 12a and 12b joined to the substrate 11. The lead members 12a and 12b include: a first joining part 121 joined to the substrate 11; a second joining part 122; and a bent part 123 provided between the first joining part 121 and the second joining part 122. The lead members 12a and 12b are made up of a plating layer 125 formed on the surface of a metallic component 124 and the metallic component 124, and the thickness of the plating layer 125 in the first joining part 121 and the second joining part 122 is smaller than that in the bent part 123.

Description

本発明は、例えばパワーモジュール等に用いられる回路基板および電子装置に関するものである。   The present invention relates to a circuit board and an electronic device used for, for example, a power module.

近年、例えばＩＧＢＴ（Insulated Gate Bipolar Transistor）等の電子部品を有して
おり比較的大きな電流が印加されるパワーモジュール等に用いられる回路基板として、例えばセラミック基板の両面に銅またはアルミニウム等の金属板が接合されたセラミック回路基板が用いられている。このような回路基板において、複数の構成部材の熱膨張係数の違いによる応力または機械的衝撃を緩和することを目的に、屈曲部を有するリード部材を含むものが提案されている（例えば、特許文献１を参照）。 In recent years, as a circuit board used for a power module or the like having electronic parts such as IGBT (Insulated Gate Bipolar Transistor) and applying a relatively large current, for example, a metal plate such as copper or aluminum on both sides of a ceramic substrate A ceramic circuit board to which is bonded is used. In such a circuit board, there has been proposed a circuit board including a lead member having a bent portion for the purpose of alleviating stress or mechanical impact due to differences in thermal expansion coefficients of a plurality of constituent members (for example, Patent Documents). 1).

特開平8-70071号公報JP-A-8-70071

しかしながら、リード部材の防食または取扱い性の向上のために、リード部材を構成する金属部材に例えばニッケル（Ｎｉ）等から成るめっき層を形成した場合、屈曲部における硬度が平坦部における硬度よりも大きくなることがあり、熱膨張係数の違いによる応力または機械的衝撃を十分に緩和させることができない場合がある。   However, when a plating layer made of, for example, nickel (Ni) is formed on the metal member constituting the lead member in order to prevent corrosion or handleability of the lead member, the hardness at the bent portion is larger than the hardness at the flat portion. In some cases, the stress or mechanical impact due to the difference in thermal expansion coefficient cannot be sufficiently relaxed.

本発明は上記課題に鑑みて完成されたものであり、熱膨張係数の違いによる応力または機械的衝撃による影響を低減させることができる回路基板および電子装置を提供することを目的とするものである。   The present invention has been completed in view of the above problems, and an object of the present invention is to provide a circuit board and an electronic device that can reduce the influence of stress or mechanical impact due to the difference in thermal expansion coefficient. .

本発明の一つの態様によれば、回路基板は、基体と、基体に接合されたリード部材とを含んでいる。リード部材は、基体に接合された第１の接合部と、第２の接合部と、第１および第２の接合部の間に設けられた屈曲部とを有している。リード部材は、金属部材および金属部材の表面に形成されためっき層から成り、めっき層の厚みが第１および第２の接合部よりも屈曲部の方が小さい。   According to one aspect of the present invention, the circuit board includes a base and a lead member joined to the base. The lead member has a first joint part joined to the base, a second joint part, and a bent part provided between the first and second joint parts. The lead member is composed of a metal member and a plating layer formed on the surface of the metal member, and the thickness of the plating layer is smaller at the bent portion than at the first and second joint portions.

本発明の他の態様によれば、電子装置は、上述の回路基板と、回路基板に実装されておりリード部材の第１の接合部に電気的に接続された電子部品とを含んでいる。   According to another aspect of the present invention, an electronic device includes the above-described circuit board and an electronic component mounted on the circuit board and electrically connected to the first joint portion of the lead member.

本発明の一つの態様による回路基板は、基体に接合されており金属部材およびめっき層から成るリード部材を含んでおり、リード部材は、基体に接合された第１の接合部と、第２の接合部と、第１および第２の接合部の間に設けられた屈曲部とを有している。めっき層の厚みは、第１および第２の接合部よりも屈曲部の方が小さい。本発明の一つの態様による回路基板は、屈曲部と第１および第２の接合部とのめっき層の厚みの違いによって、応力または衝撃がより屈曲部に集中しやすくなり、この屈曲部において応力または衝撃を緩和させることができ、熱膨張係数の違いによる応力または機械的衝撃による影響を低減させることができる。   A circuit board according to an aspect of the present invention includes a lead member that is bonded to a base and includes a metal member and a plating layer. The lead member includes a first bonding portion that is bonded to the base; It has a joined part and a bent part provided between the first and second joined parts. The thickness of the plating layer is smaller at the bent portion than at the first and second joint portions. In the circuit board according to one aspect of the present invention, stress or impact is more easily concentrated on the bent portion due to the difference in the thickness of the plating layer between the bent portion and the first and second joint portions. Alternatively, the impact can be mitigated, and the influence of stress or mechanical impact due to the difference in thermal expansion coefficient can be reduced.

本発明の他の態様による電子装置は、上述の回路基板と、回路基板に実装されておりリード部材の第１の接合部に電気的に接続された電子部品とを含んでいることによって、熱膨張係数の違いによる応力または機械的衝撃による影響が低減されている。   An electronic device according to another aspect of the present invention includes the above-described circuit board and an electronic component mounted on the circuit board and electrically connected to the first joint of the lead member. The effect of stress or mechanical shock due to the difference in expansion coefficient is reduced.

（ａ）は本発明の一つの実施形態における電子装置の部分的な平面図を示しており、（ｂ）は（ａ）に示された電子装置のＡ−Ａにおける縦断面図を示している。(A) has shown the partial top view of the electronic device in one embodiment of this invention, (b) has shown the longitudinal cross-sectional view in AA of the electronic device shown by (a). . 図１（ｂ）に示された電子装置において符号Ｂによって示された部分の拡大図を示している。The enlarged view of the part shown with the code | symbol B in the electronic device shown by FIG.1 (b) is shown.

以下、本発明の例示的な実施形態について図面を参照して説明する。   Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings.

図１および図２に示されているように、本発明の一つの実施形態における電子装置は、第１の回路基板１と、第１の回路基板１に実装された電子部品２とを含んでいる。以下、第１の回路基板１を単に回路基板１という。電子装置は、回路基板１に電気的に接続された第２の回路基板３をさらに含んでいる。以下、第２の回路基板３を単に回路基板３という。電子装置は、回路基板１および回路基板３が接合されている放熱部材４をさらに含んでいる。放熱部材４は、金属材料を含んでおり、例えば電子部品収納用パッケージの基体である。   As shown in FIGS. 1 and 2, an electronic device according to an embodiment of the present invention includes a first circuit board 1 and an electronic component 2 mounted on the first circuit board 1. Yes. Hereinafter, the first circuit board 1 is simply referred to as a circuit board 1. The electronic device further includes a second circuit board 3 that is electrically connected to the circuit board 1. Hereinafter, the second circuit board 3 is simply referred to as a circuit board 3. The electronic device further includes a heat dissipation member 4 to which the circuit board 1 and the circuit board 3 are joined. The heat radiating member 4 includes a metal material, and is, for example, a base of an electronic component storage package.

回路基板１は、基体11と、基体11の上面に接合された複数のリード部材12ａおよび12ｂと、基体11の下面に接合された放熱板13とを含んでいる。   The circuit board 1 includes a base body 11, a plurality of lead members 12 a and 12 b joined to the upper surface of the base body 11, and a heat sink 13 joined to the lower surface of the base body 11.

基体11は、例えば実質的にセラミック材料からなる。セラミック材料は、例えば、酸化アルミニウム質セラミックス，ムライト質セラミックス，炭化ケイ素質セラミックス，窒化アルミニウム質セラミックス，または窒化ケイ素質セラミックス等である。これらセラミック材料において、放熱性に影響する熱伝導性に関して、炭化ケイ素質セラミックス，窒化アルミニウム質セラミックス，または窒化ケイ素質セラミックスが好ましく、強度に関して、窒化ケイ素質セラミックスまたは炭化ケイ素質セラミックスが好ましい。基体11が窒化ケイ素質セラミックスのように比較的強度の高いセラミック材料からなる場合、より厚みの大きいリード部材12ａ、12ｂおよび放熱板13を用いたとしても基体11にクラックが入る可能性が低減されるので、小型化を図りつつより大きな電流を流すことができる回路基板１を実現することができる。   The base 11 is substantially made of a ceramic material, for example. The ceramic material is, for example, aluminum oxide ceramics, mullite ceramics, silicon carbide ceramics, aluminum nitride ceramics, or silicon nitride ceramics. Among these ceramic materials, silicon carbide ceramics, aluminum nitride ceramics, or silicon nitride ceramics are preferable in terms of thermal conductivity that affects heat dissipation, and silicon nitride ceramics or silicon carbide ceramics are preferable in terms of strength. When the substrate 11 is made of a relatively strong ceramic material such as silicon nitride ceramics, the possibility of cracks in the substrate 11 is reduced even if the lead members 12a and 12b and the heat sink 13 having a larger thickness are used. Therefore, it is possible to realize the circuit board 1 capable of flowing a larger current while reducing the size.

基体11の厚みが小さい方が、熱伝導性が向上される。基体11の厚みは、回路基板１の大きさ、用いられる材料の熱伝導率または強度に応じて選択される。例示的な厚みは、0.1
ｍｍ〜１ｍｍ程度である。 The smaller the thickness of the substrate 11, the better the thermal conductivity. The thickness of the substrate 11 is selected according to the size of the circuit board 1 and the thermal conductivity or strength of the material used. An exemplary thickness is 0.1
It is about mm to 1 mm.

基体11は、例えば窒化ケイ素質セラミックスから成る場合であれば、窒化ケイ素，酸化アルミニウム，酸化マグネシウム，および酸化イットリウム等の原料粉末に適当な有機バインダー，可塑剤，および溶剤を添加混合して泥漿物に従来周知のドクターブレード法やカレンダーロール法を採用することによってセラミックグリーンシート（セラミック生シート）を形成し、次にこのセラミックグリーンシートに適当な打ち抜き加工を施して所定形状となすとともに、必要に応じて複数枚を積層して成形体となし、しかる後、これを窒化雰囲気等の非酸化性雰囲気にて1,600〜2,000℃の温度で焼成することによって製作される。   If the substrate 11 is made of, for example, silicon nitride ceramics, a suitable organic binder, plasticizer, and solvent are added to and mixed with raw material powders such as silicon nitride, aluminum oxide, magnesium oxide, and yttrium oxide, and the slurry 11 is mixed. A ceramic green sheet (ceramic green sheet) is formed by adopting a conventionally known doctor blade method or calendar roll method, and then the ceramic green sheet is appropriately punched to obtain a predetermined shape. Accordingly, a plurality of sheets are laminated to form a molded body, and then manufactured by firing at a temperature of 1,600 to 2,000 ° C. in a non-oxidizing atmosphere such as a nitriding atmosphere.

複数のリード部材12ａおよび12ｂは、基体11に接合された第１の接合部121と、第２の
回路基板３に接合された第２の接合部122と、第１および第２の接合部の間に設けられた
屈曲部123とを有している。第１の接合部121は、接合材14によって基体11の上面に接合されており、第２の接合部122は、接合材14によって回路基板３の上面に接合されている。 The plurality of lead members 12a and 12b include a first joint 121 joined to the base 11, a second joint 122 joined to the second circuit board 3, and the first and second joints. And a bent portion 123 provided therebetween. The first bonding portion 121 is bonded to the upper surface of the base body 11 by the bonding material 14, and the second bonding portion 122 is bonded to the upper surface of the circuit board 3 by the bonding material 14.

接合材14は、銀および銅粉末，銀−銅合金粉末，またはこれらの混合粉末から成る銀ろう材（例えば、銀：72質量％−銅：28質量％）粉末に、チタン，ハフニウム，ジルコニウムまたはその水素化物等の活性金属を銀ろう材に対して２〜５質量％添加混合し、適当なバインダーと有機溶剤および溶媒とを添加混合し、混練することによって製作される。接合温度またはろう材の硬度を低下させる目的でインジウム（Ｉｎ）またはスズ（Ｓｎ）を１〜10質量％程度添加しても良い。   The bonding material 14 is made of silver, copper powder, silver-copper alloy powder, or a silver brazing material (for example, silver: 72% by mass—copper: 28% by mass) powder, and titanium, hafnium, zirconium or An active metal such as a hydride is added and mixed in an amount of 2 to 5% by mass with respect to the silver brazing material, an appropriate binder, an organic solvent and a solvent are added and mixed, and then kneaded. About 1 to 10% by mass of indium (In) or tin (Sn) may be added for the purpose of reducing the bonding temperature or the hardness of the brazing material.

複数のリード部材12ａおよび12ｂは、金属部材124と金属部材124の表面に形成されためっき層125とを含んでいる。   The plurality of lead members 12 a and 12 b include a metal member 124 and a plating layer 125 formed on the surface of the metal member 124.

金属部材124は、例えば銅（Ｃｕ）を含んでおり、例えば0.1〜１ｍｍの範囲に含まれる厚みを有する。   The metal member 124 includes, for example, copper (Cu), and has a thickness included in a range of 0.1 to 1 mm, for example.

めっき層125は、例えばニッケル（Ｎｉ）を含んでおり、めっき層125の厚みは、第１の接合部121および第２の接合部122よりも屈曲部123の方が小さい。   The plating layer 125 includes, for example, nickel (Ni), and the thickness of the plating layer 125 is smaller in the bent portion 123 than in the first joint portion 121 and the second joint portion 122.

めっき層125が例えば実質的にニッケルから成る場合、めっき層125が1.5μｍ以上の厚
みを有すると、金属部材124の表面を被覆しやすく、金属部材124の酸化腐蝕を抑制しやすくなる。めっき層125が10μｍ以下の厚みを有すると、特に絶縁基板の厚さが例えば300μｍ以下の薄いものである場合、めっき層125に内在する応力を低減させることができ、基
体11に生じる反りまたは割れ等を抑制しやすくなる。 In the case where the plating layer 125 is substantially made of nickel, for example, if the plating layer 125 has a thickness of 1.5 μm or more, the surface of the metal member 124 is easily covered, and the oxidative corrosion of the metal member 124 is easily suppressed. When the plating layer 125 has a thickness of 10 μm or less, particularly when the thickness of the insulating substrate is as thin as, for example, 300 μm or less, the stress inherent in the plating layer 125 can be reduced, and warping or cracking generated in the substrate 11 It becomes easy to suppress etc.

第１の接合部121および第２の接合部122におけるめっき層125の厚みと屈曲部123におけるめっき層125の厚みとを異ならせるために、第１の接合部121および第２の接合部122に
おけるめっき層125が例えば３〜10μｍの範囲に含まれる厚みを有するように設計し、屈
曲部123におけるめっき層125が例えば1.5〜３μｍの範囲に含まれる厚みを有するように
設計するとよい。 In order to make the thickness of the plating layer 125 in the first joint part 121 and the second joint part 122 different from the thickness of the plating layer 125 in the bent part 123, the first joint part 121 and the second joint part 122 have different thicknesses. The plating layer 125 may be designed to have a thickness included in a range of 3 to 10 μm, for example, and the plating layer 125 in the bent portion 123 may be designed to have a thickness included in a range of 1.5 to 3 μm, for example.

以下、めっき層125がリンの含有率が８％の無電解ニッケルめっきである場合を例に、
リード部材12ａおよび12ｂの曲げ強度について説明する。金属部材124は、例えば0.3ｍｍの厚みを有しており、実質的に銅から成るものであるとする。第１の接合部121および第
２の接合部122におけるめっき層125の厚みを６μｍとして、屈曲部123におけるめっき層125の厚みを３μｍとする。実質的に銅から成る金属部材124の硬さに対して、めっき層125の硬さは５〜10倍程度である。リード部材12ａおよび12ｂの曲げ強度としてＪＩＳ Ｒ １６０１の曲げ強さ試験方法に準じた３点曲げ強度測定を行ったときの降伏応力を用いた場合に、屈曲部123の曲げ強度は、第１の接合部121および第２の接合部122の曲げ強度の1/2程度となる。したがって、リード部材12ａおよび12ｂに熱膨張係数の差による応力または機械的衝撃が加わった場合、応力または衝撃は屈曲部123集中しやすくなり、第１の接
合部121および第２の接合部122の接合信頼性が向上される。 Hereinafter, in the case where the plating layer 125 is electroless nickel plating with a phosphorus content of 8%,
The bending strength of the lead members 12a and 12b will be described. The metal member 124 has a thickness of 0.3 mm, for example, and is substantially made of copper. The thickness of the plating layer 125 at the first bonding portion 121 and the second bonding portion 122 is 6 μm, and the thickness of the plating layer 125 at the bent portion 123 is 3 μm. The hardness of the plating layer 125 is about 5 to 10 times the hardness of the metal member 124 substantially made of copper. When the yield stress obtained when the three-point bending strength measurement according to the bending strength test method of JIS R 1601 is used as the bending strength of the lead members 12a and 12b, the bending strength of the bent portion 123 is as follows. The bending strength of the joint 121 and the second joint 122 is about ½. Therefore, when stress or mechanical impact due to the difference in thermal expansion coefficient is applied to the lead members 12a and 12b, the stress or impact tends to concentrate on the bent portion 123, and the first joint portion 121 and the second joint portion 122 Bonding reliability is improved.

以下、第１の接合部121および第２の接合部122におけるめっき層125の厚みを６μｍと
して、かつ屈曲部123におけるめっき層125の厚みを３μｍとして、めっき層125の形成方
法について説明する。まず、リード部材12ａおよび12ｂの屈曲部123となる部位にめっき
レジストを形成して、３μｍの無電解ニッケルめっき層を形成する。次に、めっきレジストを剥離して、さらに３μｍの無電解ニッケルめっき層を形成する。 Hereinafter, a method for forming the plating layer 125 will be described in which the thickness of the plating layer 125 in the first bonding portion 121 and the second bonding portion 122 is 6 μm and the thickness of the plating layer 125 in the bent portion 123 is 3 μm. First, a plating resist is formed on the portions of the lead members 12a and 12b that are to be bent portions 123 to form a 3 μm electroless nickel plating layer. Next, the plating resist is peeled off to further form an electroless nickel plating layer having a thickness of 3 μm.

めっき層125の他の形成方法を説明する。まず、３μｍの電解ニッケルめっき層を形成
する。その後、屈曲部123となる部分にめっきレジストを形成して、３μｍの無電解ニッ
ケルめっき層を形成する。電解ニッケルめっきの硬さは、無電解ニッケルめっきの硬さの1/2以下であるため、屈曲部123の曲げ強度がより小さくなる。 Another method for forming the plating layer 125 will be described. First, a 3 μm electrolytic nickel plating layer is formed. Thereafter, a plating resist is formed on a portion to become the bent portion 123, and a 3 μm electroless nickel plating layer is formed. Since the hardness of the electrolytic nickel plating is 1/2 or less than the hardness of the electroless nickel plating, the bending strength of the bent portion 123 becomes smaller.

リード部材12ａおよび12ｂは、基体11に接合された後に、その表面に導電性が比較的高くかつ耐蝕性およびろう材との濡れ性が良好な金属が第１の接合部121および第２の接合
部122に屈曲部123よりも厚く被着されると、第１の接合部121および第２の接合部122の硬さが大きくなり、第１の接合部121および第２の接合部122のピール強度を高めることができる。 After the lead members 12a and 12b are joined to the base 11, the first joining portion 121 and the second joining are made of metal having relatively high conductivity and good corrosion resistance and wettability with the brazing material. When the portion 122 is attached to be thicker than the bent portion 123, the hardness of the first joint portion 121 and the second joint portion 122 is increased, and the peel of the first joint portion 121 and the second joint portion 122 is increased. Strength can be increased.

放熱板13は、接合材14によって基体11の下面に接合されており、例えば銅（Ｃｕ）から成る。   The heat radiating plate 13 is bonded to the lower surface of the base 11 by a bonding material 14, and is made of, for example, copper (Cu).

電子部品２は、リード部材12ａに搭載および接合されており、ボンディングワイヤによってリード部材12ｂに電気的に接続されている。電子部品２は、例えばＩＧＢＴ（Insulated Gate Bipolar Transistor）等の半導体素子である。   The electronic component 2 is mounted and bonded to the lead member 12a, and is electrically connected to the lead member 12b by a bonding wire. The electronic component 2 is a semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor).

回路基板３は、基体31と、基体31の上面に形成された複数の導体層32ａおよび32ｂとを含んでいる。基体31は、例えばセラミックス等の絶縁材料から成る。導体層32ａおよび32ｂは、例えば、基体31がセラミックスから成る場合、焼成によって基体31と一体的に形成されたメタライズ配線層である。導体層32ａおよび32ｂは、メタライズ層の表面に、ニッケル（Ｎｉ）めっき層および金（Ａｕ）めっき層を有する場合もある。導体層32ａは、リード部材12ａに電気的に接続されており、導体層32ｂは、リード部材12ｂの第２の接合部122に接合されている。   The circuit board 3 includes a base 31 and a plurality of conductor layers 32a and 32b formed on the upper surface of the base 31. The base 31 is made of an insulating material such as ceramics. The conductor layers 32a and 32b are metallized wiring layers formed integrally with the base 31 by firing, for example, when the base 31 is made of ceramics. The conductor layers 32a and 32b may have a nickel (Ni) plating layer and a gold (Au) plating layer on the surface of the metallization layer. The conductor layer 32a is electrically connected to the lead member 12a, and the conductor layer 32b is joined to the second joint 122 of the lead member 12b.

本実施形態の回路基板１において、めっき層125の厚みは、第１の接合部121および第２の接合部122よりも屈曲部123の方が小さい。このように、屈曲部123と第１の接合部121および第２の接合部122とのめっき層の厚みの違いによって、応力または衝撃がより屈曲部123に集中しやすくなり、この屈曲部123において応力または衝撃を緩和させることができ
、熱膨張係数の違いによる応力または機械的衝撃による影響を低減させることができる。 In the circuit board 1 of the present embodiment, the thickness of the plating layer 125 is smaller in the bent portion 123 than in the first joint portion 121 and the second joint portion 122. As described above, the difference in plating layer thickness between the bent portion 123 and the first bonded portion 121 and the second bonded portion 122 makes it easier for stress or impact to concentrate on the bent portion 123. Stress or impact can be relaxed, and the influence of stress or mechanical impact due to the difference in thermal expansion coefficient can be reduced.

本実施形態における電子装置は、上述の回路基板１と、回路基板１に実装されておりリード部材12ａおよび12ｂの第１の接合部121に電気的に接続された電子部品２とを含んで
いることによって、熱膨張係数の違いによる応力または機械的衝撃による影響が低減されている。 The electronic device in the present embodiment includes the above-described circuit board 1 and the electronic component 2 mounted on the circuit board 1 and electrically connected to the first joint portion 121 of the lead members 12a and 12b. As a result, the influence of stress or mechanical shock due to the difference in thermal expansion coefficient is reduced.

１ 第１の回路基板
11 基体
12ａ、12ｂ リード部材
121 第１の接合部
122 第２の接合部
123 屈曲部
124 金属部材
125 めっき層
13 放熱板
14 接合材
２ 電子部品
３ 第２の回路基板
31 基体
32
４ 放熱部材 1 First circuit board
11 Substrate
12a, 12b Lead member
121 First joint
122 Second joint
123 Bend
124 Metal parts
125 plating layer
13 Heat sink
14 Bonding material 2 Electronic component 3 Second circuit board
31 substrate
32
4 Heat dissipation member

Claims (2)

基体と、
該基体に接合された第１の接合部と第２の接合部と前記第１および第２の接合部の間に設けられた屈曲部とを有しており、金属部材および該金属部材の表面に形成されためっき層から成り、該めっき層の厚みが前記第１および第２の接合部よりも前記屈曲部の方が小さいリード部材とを備えていることを特徴とする回路基板。 A substrate;
A metal member and a surface of the metal member, the first and second joints being joined to the base body, and a bent portion provided between the first and second joints. And a lead member having a thickness of the plating layer smaller than that of the first and second joints. 請求項１に記載された回路基板と、
該回路基板に実装されており、前記リード部材の前記第１の接合部に電気的に接続された電子部品とを備えていることを特徴とする電子装置。 A circuit board according to claim 1;
An electronic device comprising: an electronic component mounted on the circuit board and electrically connected to the first joint portion of the lead member.
JP2010240987A 2010-10-27 2010-10-27 Circuit board and electronic device Pending JP2012094697A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015222759A (en) * 2014-05-22 2015-12-10 三菱電機株式会社 Power semiconductor device
CN107615565A (en) * 2015-10-02 2018-01-19 株式会社Lg化学 Battery module with improved cooling pipe sealing characteristics

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267526A (en) * 1992-03-18 1993-10-15 Chichibu Fuji:Kk Method for plating integrated circuit and lead frame
JPH0621301A (en) * 1992-06-30 1994-01-28 Sharp Corp Surface mounted semiconductor device and manufacture thereof
JPH0870071A (en) * 1994-08-29 1996-03-12 Toshiba Corp Radiator
JP2001053222A (en) * 1999-08-09 2001-02-23 Fuji Electric Co Ltd Semiconductor device
JP2006303215A (en) * 2005-04-21 2006-11-02 Denso Corp Resin-sealed semiconductor device
JP2007155474A (en) * 2005-12-05 2007-06-21 Japan Electronic Materials Corp Probe and its manufacturing method
JP2008235651A (en) * 2007-03-22 2008-10-02 Fuji Electric Device Technology Co Ltd Semiconductor device and manufacturing method therefor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267526A (en) * 1992-03-18 1993-10-15 Chichibu Fuji:Kk Method for plating integrated circuit and lead frame
JPH0621301A (en) * 1992-06-30 1994-01-28 Sharp Corp Surface mounted semiconductor device and manufacture thereof
JPH0870071A (en) * 1994-08-29 1996-03-12 Toshiba Corp Radiator
JP2001053222A (en) * 1999-08-09 2001-02-23 Fuji Electric Co Ltd Semiconductor device
JP2006303215A (en) * 2005-04-21 2006-11-02 Denso Corp Resin-sealed semiconductor device
JP2007155474A (en) * 2005-12-05 2007-06-21 Japan Electronic Materials Corp Probe and its manufacturing method
JP2008235651A (en) * 2007-03-22 2008-10-02 Fuji Electric Device Technology Co Ltd Semiconductor device and manufacturing method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015222759A (en) * 2014-05-22 2015-12-10 三菱電機株式会社 Power semiconductor device
CN107615565A (en) * 2015-10-02 2018-01-19 株式会社Lg化学 Battery module with improved cooling pipe sealing characteristics
CN107615565B (en) * 2015-10-02 2020-06-12 株式会社Lg化学 Battery module with improved cooling duct sealing characteristics

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