JP2012089656A - Tape carrier for semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tape carrier for a semiconductor device capable of reducing costs such as a material cost by reducing an amount of Au in the tape carrier for the semiconductor device and the method for manufacturing the same.SOLUTION: The tape carrier for the semiconductor device is provided with a conductor pattern containing a flying lead section formed by carrying out a pattern processing of a copper (Cu) foil. The tape carrier for the semiconductor device also comprises an Au plated film only on the flying lead section in the conductor pattern.

Description

  The present invention relates to a tape carrier for a semiconductor device that involves bending of a thin and fine flying lead portion (inner lead portion) such as a TAB tape for μBGA, and a method for manufacturing the same.

  A BGA type package that is mounted on a printed wiring board using a solder ball as an external connection terminal is known as one of the mounting forms that can realize an ultra-small and thin mounting package. In the BGA type package, solder balls can be arranged on the entire surface of the flat surface of one mounting package, so that electrical connection with the printed wiring board is possible on the entire surface of the flat surface. As a result, the BGA type package structure has the outstanding feature that it can cope with the increase in the number of pins without narrowing the pitch between terminals (between leads), which can accommodate the ultra-small and thin mounting package. Have. In such a BGA type mounting package, as an insulating substrate that is a base material that substantially (mechanically mechanically) supports the mechanical structure, it is thin while having appropriate mechanical strength and thermal strength. TAB tape that can be used is preferably used.

  A TAB (Tape Automated Bonding) tape for μBGA (micro Ball Grid Array), which is one type of tape carrier for semiconductor devices, is formed by bonding a copper foil to a polyimide film via an adhesive, and then using a photoetching method or the like. By performing pattern processing on the foil, various conductor patterns such as wiring patterns and flying lead portions are formed, and gold plating is applied as a final surface treatment for mounting on the surface of the conductor pattern. This gold plating is to ensure reliable bonding by generating an alloy with the aluminum pad on the IC chip and the solder ball that will be the external connection terminal in the mounting process. Therefore, it is an indispensable component for ensuring good bonding characteristics such as the flying lead portion and the inner lead portion.

  In recent years, the price of gold has increased remarkably due to its mining scarcity value and economic price fluctuations, and the ratio of the material cost to the product price has become increasingly higher. For this reason, it has been increasingly demanded to reduce the material cost by reducing the amount of gold used in the tape carrier for semiconductor devices.

  In order to respond to such a request, it is considered to reduce the thickness of the gold plating film as much as possible.

  Therefore, in order to cope with such inconveniences, a gold / palladium / copper three-layer structure is sandwiched between lower cost palladium as an intermediate layer, thereby reducing the thickness of the gold plating and reducing the material cost. There has been proposed a technique for reducing the amount. That is, in this proposal, by interposing a palladium film having the property of suppressing copper diffusion as an intermediate layer, it is possible to prevent copper atoms from diffusing into the gold plating film. It has become.

  Although this has a different purpose from the above three-layer laminated structure, in order to ensure the mechanical hardness of the inner lead portion and the connection pad portion made of copper, plating made of, for example, tin or nickel in addition to palladium. A method of interposing a film between a gold plating film and a copper plating film has also been proposed. It is considered that the thickness of the gold plating film can be reduced by using such a plating film made of nickel as an intermediate layer of the above three-layer structure (Patent Document 1).

JP 2007-67022 A

  However, as described above, since the entire wiring pattern is plated, there is a problem that the cost is increased.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a tape carrier for a semiconductor device and a method for manufacturing the same that enable cost reduction.

  The present invention is a tape carrier for a semiconductor device having a conductor pattern including a flying lead portion formed by patterning a copper foil, and for the semiconductor device having a gold plating film only on the flying lead portion of the conductor pattern. It is a tape carrier.

  The present invention also includes a step of laminating a dry film resist on both surfaces of an insulating substrate having an opening formed and a metal foil bonded to at least one surface, and exposing and developing the dry film resist to bond to a semiconductor chip. A step of forming an opening so as to be located in a portion, a step of forming a gold plating film by electrolysis or electroless plating in the opening formed in the dry film resist, and a step of removing the dry film resist And a step of patterning the metal foil to form a conductor pattern including a flying lead portion.

  In the present invention, since the gold plating film is not formed on the wiring portion because the gold plating film is formed by the plating method only at the joint portion with the semiconductor chip before patterning to the copper foil, the cost can be reduced.

  In the present invention, it is not necessary to provide a power supply line on the TAB tape, and the degree of freedom in pattern design is increased.

It is a figure which shows the principal part of the mounting package of the (micro | micron | mu) BGA structure comprised using the tape carrier for semiconductor devices which concerns on embodiment of this invention. It is sectional drawing which shows the tape carrier for semiconductor devices which concerns on embodiment of this invention. It is a top view which shows the tape carrier for semiconductor devices which concerns on embodiment of this invention. FIG. 4 is an AA enlarged view of FIG. 3. It is sectional drawing which shows the manufacturing method of the tape carrier for semiconductor devices which concerns on embodiment of this invention.

  A μBGA structure mounting package manufactured using the semiconductor device tape carrier and the semiconductor device tape carrier according to the present embodiment will be described in detail with reference to FIGS.

  The semiconductor device tape carrier and μBGA structure mounting package of the present invention are, for example, a μBGA structure mounting package bonded on the surface of an insulating film substrate 1 such as a polyimide resin film as shown in the figure. The conductive pattern 2 is formed by patterning a thin copper foil having a thickness of about 15 μm, which is preferably used in a tape carrier for a semiconductor device applied to the semiconductor device. The conductor pattern 2 includes a flying lead portion 3.

  The flying lead portion 3 of the conductor pattern 2 is provided with a gold plating film 4 only in a portion that becomes a joint portion with the semiconductor chip 5. The gold plating film 4 is formed at a position where the aluminum pad 6 formed on the semiconductor chip 5 is placed.

  As will be described later, the conductor pattern 2 may be subjected to rust prevention treatment including OSP treatment.

  The semiconductor chip 5 is supported on one surface (wiring surface) of the tape carrier for a semiconductor device via an elastic body having an insulating property such as an elastomer 7.

  A mold resin 8 is provided so as to cover almost the entire wiring surface, and the entire wiring surface is sealed.

  In this tape carrier for a semiconductor device, solder balls 9 are set so as to be arranged at predetermined positions on the BGA surface side which is the surface opposite to the wiring surface side. In addition, an opening 10 is provided at a substantially central portion of the insulating film substrate 1, and the flying lead 3 is bonded through the opening 10 using a bonding tool (not shown). Has been.

  The wiring pattern is provided as a terminal pattern or a pattern connected to the flying lead portion 3 and occupies most of the conductor pattern 2. In other words, the conductor pattern 2 is mainly composed of a wiring pattern, and includes a terminal pattern and a flying lead portion 3 and the like connected to the wiring pattern.

  This tape carrier for a semiconductor device is set as a tape carrier for a semiconductor device suitable for a mounting package having a μBGA (micro Ball Grid Array) structure as shown in FIG.

  The manufacturing process of the semiconductor device tape carrier will be described with reference to FIG.

  First, an insulating film substrate 1 is prepared (FIG. 5A), and openings 10 for mounting solder balls and connecting semiconductor chips are formed in the insulating film substrate 1 by punching or the like (FIG. 5 ( b)).

  Subsequently, a copper foil 2a, which later becomes a conductor pattern by etching, is bonded to one side of the film substrate via an adhesive (FIG. 5C).

  Next, the dry film resist 11 is laminated on both sides (upper and lower surfaces), exposed and developed. Here, an opening is formed in the dry film resist 11 on the copper foil 2a side so as to be located at a portion to be joined to the semiconductor chip 5 (FIG. 5D).

  Thereafter, a gold plating film is formed in the opening formed in the dry film resist 11 by electrolysis or electroless plating (FIG. 5E).

  Then, the dry film resist 11 is peeled off (FIG. 5 (f)) and subjected to pattern processing by a photolithography method and an etching method to form the conductor pattern 2 including the flying lead portion 3 (FIG. 5 (g)). .

  In the present embodiment, OSP treatment may be performed after the conductor pattern 2 is formed.

  The conductor pattern may be plated with tin, nickel, palladium or the like.

  According to this method, since the electroplating or electroless plating can be performed at the time of the gold plating process, the power supply wiring which has been conventionally required is not required, and the degree of freedom in wiring design is increased.

  In addition, since the gold plating film is formed only at the minimum necessary location, the amount of gold used is reduced, leading to cost reduction.

  A tape carrier for a semiconductor device as described in the above embodiment was produced as a sample according to an example of the present invention (Example 1).

  For comparison with the above, a tape carrier for a semiconductor device having a layer structure in which a gold plating film was formed on the entire surface of a conductor pattern was produced as a sample according to a conventional example (Comparative Example 1).

<Example 1>
First, Upilex S (thickness 50 μm, manufactured by Ube Industries) is used as the polyimide tape of the insulating film substrate 1, FQ-VLP foil (thickness 15 μm, manufactured by Mitsui Metals) is used as the copper foil, and the copper foil is used. As an adhesive for attaching to the surface of an insulating film substrate, a copper clad film substrate material for double tape carrier with a width of 105 mm is prepared using Yodogawa X-type (thickness 12 μm, manufactured by Yodogawa Paper Mill). The tape carrier for semiconductor devices was manufactured by the manufacturing method mentioned above. As the dry film (product name: AQ2538, thickness 25 μm, manufactured by Asahi Kasei E-materials) was used. Further, the gold plating film was formed so as to have a thickness of 0.4 μm only in a portion to be a joint portion with the semiconductor chip 5.

  As a result, the amount of gold used could be reduced to about 1/200 compared to Comparative Example 1 described later.

<Comparative Example 1>
First, Upilex S (thickness 50 μm, manufactured by Ube Industries) is used as the polyimide tape of the insulating film substrate 1, FQ-VLP foil (thickness 15 μm, manufactured by Mitsui Metals) is used as the copper foil, and the copper foil is used. As an adhesive for attaching to the surface of an insulating film substrate, a copper clad film substrate material for double tape carrier with a width of 105 mm is prepared using Yodogawa X-type (thickness 12 μm, manufactured by Yodogawa Paper Mill). After the copper foil was patterned by a subtractive method to form a wiring pattern including inner leads and power supply leads, a gold plating film was formed on the formed wiring so as to have a thickness of 0.4 μm.

DESCRIPTION OF SYMBOLS 1 Insulating film base material 2 Conductor pattern 2a Copper foil 3 Flying lead part 4 Gold plating film 5 Semiconductor chip 6 Aluminum pad 7 Elastomer 8 Mold resin 9 Solder ball 10 Opening part 11 Dry film resist

Claims (5)

A tape carrier for a semiconductor device having a conductor pattern including a flying lead portion formed by patterning a copper foil,
The tape carrier for semiconductor devices which equips only the said flying lead part among the said conductor patterns with a gold plating film.   The tape carrier for a semiconductor device according to claim 1, further comprising an underlayer made of at least one of tin, nickel, or palladium between the conductor pattern and the gold plating film. Laminating a dry film resist on both sides of an insulating substrate in which an opening is formed and a metal foil is bonded to at least one side;
A step of exposing and developing the dry film resist to form an opening so as to be located at a portion to be a joint portion with a semiconductor chip; and
In the opening formed in the dry film resist, a step of forming a gold plating film by electrolysis or electroless plating,
Removing the dry film resist;
Forming a conductor pattern including a flying lead portion by patterning the metal foil;
A method for manufacturing a tape carrier for a semiconductor device.   4. The method of manufacturing a tape carrier for a semiconductor device according to claim 3, wherein an OSP process is performed on the conductor pattern after the step of forming the conductor pattern.   The method according to claim 3, further comprising a step of forming an underlayer made of at least one of tin, nickel, or palladium by electroless or electrolytic plating in the opening after the step of forming the opening in the dry film resist. The manufacturing method of the tape carrier for semiconductor devices of description.

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