JP2012085063A - Image pick-up device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pick-up device in which adverse effect of the variation in current consumption of a transfer circuit on the analog/digital conversion operation can be minimized by eliminating a period where transfer operation by the transfer circuit is not performed during the analog/digital conversion operation.SOLUTION: The image pick-up device comprises a pixel part (111) where pixels are arranged in matrix, a column analog/digital converter group (112) where the signal of each row read from the pixel in the pixel part is converted from analog to digital for each column, a selection unit (113) which outputs the signal of a pixel in the column of the read region in the pixel part selectively out of the digital signals of each row converted by the column analog/digital converter group, and a transfer circuit (114) which transfers the signal of the pixel of each row output from the selection unit. The transfer circuit changes the transfer frequency according to the number of pixels in the row of the read region of the pixel part.

Description

  The present invention relates to an imaging apparatus.

  One of the area type imaging devices is a CMOS type image sensor (hereinafter referred to as a CMOS sensor). The CMOS sensor has an advantage that a sensor driving circuit, an analog / digital (A / D) converter, a data processing circuit, and the like can be mixedly mounted on the same semiconductor substrate as the sensor. In recent years, in order to increase the reading speed, a CMOS that converts an analog signal for each row from a pixel unit arranged in a matrix into an N-bit digital data signal by an A / D converter provided for each column. Sensors are being developed. The converted digital data signal is sequentially transferred to the output circuit using a horizontal transfer circuit. The transferred digital data signal is output from the CMOS sensor via the output circuit. In a CMOS sensor incorporating an A / D converter for each column, the frame rate can be improved by performing a pipeline operation for the A / D conversion operation and the horizontal transfer operation. In Patent Document 1, the digital data signal of the (N−1) th row which is A / D converted immediately before the pixel signal of each column of the Nth row is held in the memory unit in parallel with the period of the A / D conversion operation. Describes a method of sequentially transferring.

Japanese Patent Laid-Open No. 5-48460

  In general, the output pixel area, the number of pixels, and the frame rate vary greatly depending on the shooting mode such as a moving image or a still image. Patent Document 1 describes that the interval between signal readout from pixels, that is, the readout time for one row, is determined as the longer of the A / D conversion time and the data transfer time. When the number of pixels to be output from one line is small, the number of data signals to be horizontally transferred in a certain time is reduced, so that the horizontal transfer time is shortened with respect to the A / D conversion time. When the horizontal transfer time becomes shorter than the A / D conversion time, there are a period during which the horizontal transfer operation is performed during the A / D conversion operation and a period during which the horizontal transfer operation is not performed. During the horizontal transfer period, current consumption increases because the horizontal transfer circuit operates. For this reason, the potential due to the resistance of the power supply wiring and the ground wiring in the CMOS sensor fluctuates between the period during which the horizontal transfer operation is performed and the period when the horizontal transfer operation is not performed, and this variation occurs as an A / D conversion error. .

  An object of the present invention is to provide an imaging apparatus that eliminates a period during which no transfer operation is performed by a transfer circuit during an analog / digital conversion operation and can suppress adverse effects of fluctuations in current consumption of the transfer circuit on the analog / digital conversion operation. Is to provide.

  The imaging apparatus of the present invention includes a pixel unit in which pixels are arranged in a matrix, a column analog / digital converter group that converts a signal of each row read from the pixel of the pixel unit from analog to digital for each column, and A selection unit that selects and outputs a signal of a pixel in a column in a readout region of the pixel unit from among digital signals of each row converted by a column analog / digital converter group, and each row output by the selection unit A transfer circuit for transferring a pixel signal, wherein the transfer circuit changes a transfer frequency in accordance with the number of pixels in a row of a readout region of the pixel portion.

  By changing the transfer frequency according to the number of pixels, it is possible to prevent a change in current consumption of the transfer circuit during the analog / digital conversion operation period, and to reduce an analog / digital conversion error.

1 is a block diagram illustrating an imaging apparatus according to an embodiment of the present invention. 2 is a timing chart showing the operation of the configuration of FIG. 1. 2 is a timing chart showing the operation of the configuration of FIG. 1. 2 is a timing chart showing the operation of the configuration of FIG. 1.

  FIG. 1 is a block diagram illustrating a configuration example of an imaging apparatus according to an embodiment of the present invention. The imaging apparatus shown in FIG. 1 includes a driving circuit 100, a pixel unit 111, a column analog / digital converter group (column A / D converter group) 112, a selection unit (selection unit) 113, and a horizontal transfer circuit 114. And have. The drive circuit 100 includes an A / D drive clock circuit 102 and a transfer clock circuit 104. This image pickup apparatus is an area type image pickup apparatus in which the column A / D converter group 112 is formed on the same semiconductor substrate as the pixel portion (sensor) 111. The A / D drive clock circuit 102 outputs a clock signal ADCK for driving the column A / D converter group 112. The clock signal ADCK has a constant frequency. The transfer clock circuit 104 outputs a clock HSCK signal for driving the horizontal transfer circuit 114. This clock signal HSCK can be varied according to the number of pixels read out per row. In the pixel portion 111, pixels are arranged in a matrix. The pixel includes a photoelectric conversion element that generates a signal by photoelectric conversion. The pixel unit 111 selects a pixel signal of a row in a desired readout region 120 to 122 by row selection, and outputs a pixel signal of the selected row to the column A / D converter group 112 in units of rows. The column A / D converter group 112 includes an A / D converter for each column, reads out analog pixel signals in each row from the pixels in the pixel unit 111 in synchronization with the clock signal ADCK, and reads out the pixels in each row. The signal is converted from analog to N-bit digital for each column. Here, in the A / D converters of the column A / D converter group 112, in order to simultaneously perform the operation of reading out the output from the pixels and the operation of A / D converting the signal read out one row before, A sample and hold circuit for holding the signal may be included. The digital data signal converted by the column A / D converter group 112 is stored in a storage device for holding the data signal provided in the selection unit 113. The selection unit 113 selects a pixel signal of a column in a desired readout region 120 to 122 of the pixel unit 111 among the digital signals of each row stored in the storage device, and outputs the signal to the horizontal transfer circuit 114 having a bus. In the readout regions 120 to 122 of the pixel unit 111, the number of rows is determined by the row selection of the pixel unit 111, and the number of columns is determined by the column selection of the selection unit 113. That is, the readout areas 120 to 122 of the pixel unit 111 are determined by the setting of how many rows and every column are read out. The horizontal transfer circuit 114 sequentially transfers the pixel signals of each row output from the selection unit 113 to the output circuit in synchronization with the clock signal HSCK. The bus of the horizontal transfer circuit 114 is configured as an (N × M) bit bus (M is a natural number) by providing M transfer circuit units 115 each having an N bit bus in parallel.

  The operation of the imaging apparatus illustrated in FIG. 1 will be described with reference to the timing chart illustrated in FIG. In order to output a pixel signal of a certain row from the horizontal transfer circuit 114, first, the pixel signal from which the A / D converter of the column A / D converter group 112 reads out the pixel signal for each column from the pixel of the pixel unit 111 is first. Read operation is performed. Next, an A / D conversion operation is performed in which the A / D converters of the column A / D converter group 112 convert pixel (analog) signals read for each column from analog to digital. Finally, the horizontal transfer circuit 114 performs a horizontal transfer operation of transferring the digital data signal converted by the column A / D converter group 112 to the output circuit. By performing these pipeline operations, the horizontal transfer operation of the Nth row data signal, the A / D conversion operation of the (N + 1) th row, and the pixel signal reading operation of the (N + 2) th row are performed in parallel. FIG. 2 shows the timing when the readout area 120 of the pixel portion of FIG. 1 is set. At this time, the time required for pixel signal readout, the time required for A / D conversion operation, and the horizontal transfer operation It is assumed that the time required for each is T. Here, for simplification, it is assumed that all pixel signals in the set area are output. In the first period T, pixel signal readout of the Nth row is performed. In the second period T, the A / D conversion operation in the Nth row and the pixel signal readout operation in the N + 1th row are performed in parallel. In the third period T, the horizontal transfer operation of the Nth row, the A / D conversion operation of the (N + 1) th row, and the pixel signal reading operation of the (N + 2) th row are performed in parallel. In the fourth period T, the horizontal transfer operation of the (N + 1) th row and the A / D conversion operation of the (N + 2) th row are performed in parallel. In the fifth period T, the horizontal transfer operation of the (N + 2) th row is performed. Here, the description is given by taking three rows of pixels as an example, but actually there are four or more rows of pixels, and parallel processing is performed in each period T.

  FIG. 3 shows a timing chart when a region 122 narrower than the readout region 120 of the pixel unit 111 in FIG. 1 is set. The pixel signal reading operation and the A / D conversion operation are performed at the same time T as the timing shown in FIG. On the other hand, when the clock signal HSCK for driving the horizontal transfer circuit 114 has the same frequency as when the read area 120 is set, the number of pixels to be read is small, so that the horizontal transfer operation is completed in a time T2 shorter than T. To do. Here, the horizontal transfer operation is performed over the period T by reducing the number of units to be used among the transfer circuit units 115 of the horizontal transfer circuit 114 or decreasing the frequency of the clock signal HSCK, or by performing both. By eliminating the period during which the horizontal transfer operation is not performed during the pixel signal read operation and the A / D conversion operation, fluctuations in the power supply voltage and the ground voltage due to fluctuations in the current consumption of the horizontal transfer circuit 114 are minimized, and the pixel signal read operation is performed. And adverse effects on the A / D conversion operation.

  Next, FIG. 4 shows a timing chart when a region 121 wider than the readout region 120 of the pixel unit 111 in FIG. 1 is set. When the clock signal HSCK for driving the horizontal transfer circuit 114 has the same frequency as when the reading area 120 is set, the number of pixels to be read is large, so that the horizontal transfer operation requires a time T1 longer than the period T, and the frame rate is set. Rate limiting. Here, the number of units to be used among the transfer circuit units 115 of the horizontal transfer circuit 114 is increased, the frequency of the clock signal HSCK is increased, or both are performed, so that the horizontal transfer operation ends in the period T. This makes it possible to maintain the frame rate determined by the A / D conversion time even when the number of pixels output from one row is large.

  As described above, according to the present embodiment, the horizontal transfer circuit 114 changes the transfer frequency according to the number of pixels in the rows of the readout regions 120 to 122 of the pixel unit 111. In the first method, the transfer clock circuit 104 outputs a clock signal HSCK having a different frequency according to the number of pixels in the row of the readout region 112 of the pixel unit 111. The horizontal transfer circuit 114 transfers the above signal in synchronization with the clock signal HSCK output from the transfer clock circuit 104. The transfer clock circuit 104 lowers the frequency of the clock signal HSCK when the number of pixels in the readout regions 120 to 122 of the pixel unit 111 is small, and the clock when the number of pixels in the rows of the readout regions 120 to 122 of the pixel unit 111 is large. Increase the frequency of the signal HSCK.

  In the second method, the horizontal transfer circuit 114 includes at least two or more transfer circuit units 115 that operate in parallel, and the transfer circuit units 115 of the transfer circuit unit 115 correspond to the number of pixels in the rows of the readout regions 120 to 122 of the pixel unit 111. Change the number of movements. Specifically, the transfer circuit unit 115 reduces the number of operations when the number of pixels in the readout regions 120 to 122 of the pixel unit 111 is small, and increases the number of pixels in the rows of the readout regions 120 to 122 of the pixel unit 111. Sometimes the number of operations is increased. In the third method, both the first method and the second method are performed.

  Note that the control in FIG. 4 is not necessarily required. In this embodiment, as shown in FIG. 3, when the number of pixels in the row of the readout region 122 is small, the horizontal transfer operation period T2 is shortened, and the horizontal transfer operation is performed during the A / D conversion operation. This solves the problem when there is a period and a period during which a horizontal transfer operation is performed. During the horizontal transfer operation period T2, since the horizontal transfer circuit 114 operates, current consumption increases. For this reason, the potential due to the resistance of the power supply wiring and the ground wiring in the imaging device fluctuates between the period T2 in which the horizontal transfer operation is performed and the period in which the horizontal transfer operation is not performed, and this fluctuation occurs as an A / D conversion error. There is a problem to do. In the present embodiment, the period of the horizontal transfer operation is set to T by lowering the transfer frequency of the horizontal transfer circuit 114 as shown in FIG. Thereby, during the A / D conversion operation, the horizontal transfer operation is always performed, the current consumption of the horizontal transfer circuit 114 becomes constant, and an A / D conversion error can be prevented. In order to achieve this object, the period of the horizontal transfer operation may be the same as or longer than the period of the A / D conversion operation. Therefore, the control of FIG. 4 is not necessarily required, and the period of the horizontal transfer operation may be the period T1 longer than the period T of the A / D conversion operation. By changing the transfer frequency according to the number of pixels, a change in current consumption of the horizontal transfer circuit 114 can be prevented during the A / D conversion operation period, and an A / D conversion error can be reduced.

  The horizontal transfer circuit 114 may change the transfer frequency so that the transfer period of the horizontal transfer circuit 114 is the same or longer than the conversion period of the column analog / digital converter group 112. In the first method, the transfer clock circuit 104 outputs the clock signal HSCK having the first frequency when the number of pixels in the row of the readout region 120 of the pixel unit 111 is the first number of pixels as shown in FIG. . On the other hand, as shown in FIG. 3, the transfer clock circuit 104 has the above-described case when the number of pixels in the row of the readout region 122 of the pixel unit 111 is the second number of pixels smaller than the first number of pixels. A clock signal HSCK having a second frequency lower than the first frequency is output.

  In the second method, the transfer circuit unit 115 sets the operation number as the first operation number when the number of pixels in the row of the readout region 120 of the pixel unit 111 is the first number of pixels as shown in FIG. On the other hand, as shown in FIG. 3, the transfer circuit unit 115 sets the operation number when the number of pixels in the row of the readout region 122 of the pixel unit 111 is the second number of pixels smaller than the first number of pixels. The second operation number is smaller than the first operation number. In the third method, both the first method and the second method are performed.

  In this embodiment, the frequency of the clock signal ADCK for driving the column A / D converter group 112 is fixed, and the clock signal HSCK for driving the horizontal transfer circuit 114 is variable. This is to avoid affecting the A / D conversion accuracy by changing the frequency of the clock signal ADCK. The data signal handled by the horizontal transfer circuit 114 is a logic signal. Therefore, even if the frequency of the clock signal HSCK is varied within a range that has a sufficient margin with respect to the upper limit and lower limit frequencies at which the horizontal transfer circuit 114 can operate, the data value to be handled may change. Is low. However, the frequency of the clock signal ADCK may not be fixed if the frequency of the clock signal ADCK does not affect the conversion accuracy of the column A / D converter group 112.

  In the present embodiment, the means for changing the frequency of the clock signal may be any method such as a method of changing the multiplication number of the phase lock loop (PLL) circuit or a method of changing the frequency division ratio of the clock signal. A method may be used.

  According to the present embodiment, in the imaging device having an A / D converter for each column, the frequency of the drive clock signal HSCK of the horizontal transfer circuit 114 for transferring the data signal according to the number of pixels output from one row. And / or the number of operating circuits of the horizontal transfer circuit 114 is controlled. As a result, the A / D conversion operation and the horizontal transfer operation can be performed in the same time. As a result, it is possible to eliminate a period during which the horizontal transfer operation is not performed during the A / D conversion operation, and to suppress the adverse effect on the A / D conversion due to the consumption current fluctuation of the horizontal transfer circuit 114.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 100 Drive circuit, 111 pixel part, 112 column A / D converter group, 113 selection means, 114 horizontal transfer circuit, 115 transfer circuit unit

Claims (6)

A pixel portion in which pixels are arranged in a matrix; and
A column analog / digital converter group for converting the signal of each row read from the pixel of the pixel unit from analog to digital for each column;
A selection unit that selects and outputs a signal of a pixel in a column in a readout region of the pixel unit among digital signals of each row converted by the column analog / digital converter group;
A transfer circuit that transfers a signal of each row of pixels output by the selection unit;
The image pickup apparatus, wherein the transfer circuit changes a transfer frequency in accordance with the number of pixels in a row of a readout region of the pixel portion.   2. The imaging apparatus according to claim 1, wherein the transfer circuit changes the transfer frequency so that a transfer period of the transfer circuit is the same as or longer than a conversion period of the column analog / digital converter group. And a transfer clock circuit that outputs a clock signal having a different frequency according to the number of pixels in the row of the readout region of the pixel unit,
The imaging apparatus according to claim 1, wherein the transfer circuit transfers the signal in synchronization with a clock signal output from the transfer clock circuit.   The transfer clock circuit outputs a clock signal having a first frequency when the number of pixels in the row of the readout region of the pixel portion is the first number of pixels, and the number of pixels in the row of the readout region of the pixel portion is 4. The imaging apparatus according to claim 3, wherein when the number of pixels is smaller than the first number of pixels, a clock signal having a second frequency lower than the first frequency is output.   The transfer circuit includes at least two transfer circuit units that operate in parallel, and the number of operation of the transfer circuit units is changed in accordance with the number of pixels in a row of a readout region of the pixel portion. The imaging device according to any one of 1 to 4.   In the transfer circuit unit, when the number of pixels in the row of the readout region of the pixel unit is the first number of pixels, the number of operations is the first number of operations, and the number of pixels in the row of the readout region of the pixel unit is the first number of pixels. 6. The imaging apparatus according to claim 5, wherein when the number of pixels is smaller than the number of pixels of 1, the number of operations is a second number of operations less than the first number of operations.

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