JP4470839B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device for physical quantity distribution detection in which a plurality of unit components are arrayed, such as an imaging device (hereinafter also referred to as an imaging device). More specifically, for example, a plurality of unit components that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged, and the physical quantity distribution converted into an electric signal by the unit components is addressed. The present invention relates to a semiconductor device for physical quantity distribution detection, such as a solid-state imaging device, which can be arbitrarily selected by control and read as an electric signal. More specifically, the present invention relates to a technique for converting an analog output electrical signal suitable for use in a semiconductor device into digital data. In particular, the present invention relates to a digital data conversion technique for handling color information such as a color image.

  2. Description of the Related Art Physical quantity distribution detection semiconductor devices in which a plurality of unit components (for example, pixels) that are sensitive to electromagnetic waves input from the outside such as light and radiation are arranged in a line or matrix form are used in various fields. ing.

  For example, in the field of video equipment, CCD (Charge Coupled Device) type, MOS (Metal Oxide Semiconductor) type or CMOS (Complementary Metal-oxide Semiconductor) type solid-state imaging devices that detect light (an example of electromagnetic waves) in physical quantities are used. It is used. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device).

  Further, in some solid-state imaging devices, an amplifying solid-state imaging device (APS; Active Pixel Sensor) that has a driving transistor for amplification in a pixel signal generation unit that generates a pixel signal corresponding to the signal charge generated in the charge generation unit. There is an amplification type solid-state imaging device including a pixel having a configuration (also called a gain cell). For example, many CMOS solid-state imaging devices have such a configuration.

  In such an amplification type solid-state imaging device, in order to read out a pixel signal to the outside, address control is performed on a pixel unit in which a plurality of unit pixels are arranged, and signals from individual unit pixels are arbitrarily selected. I am trying to read it out. That is, the amplification type solid-state imaging device is an example of an address control type solid-state imaging device.

  For example, an amplification type solid-state imaging device which is a kind of XY address type solid-state imaging device in which unit pixels are arranged in a matrix form an active element (MOS transistor) such as a MOS structure in order to give the pixel itself an amplification function. ) To form a pixel. That is, signal charges (photoelectrons) accumulated in a photodiode which is a photoelectric conversion element are amplified by the active element and read out as image information.

  In this type of XY address type solid-state imaging device, for example, a plurality of pixel transistors are arranged in a two-dimensional matrix to form a pixel unit, and a signal charge corresponding to incident light for each line (row) or each pixel. Accumulation is started, and a current or voltage signal based on the accumulated signal charge is sequentially read out from each pixel by addressing. Here, in the MOS (including CMOS) type, as an example of address control, a column parallel readout method is often used in which one row is accessed simultaneously and a pixel signal is read from the pixel unit in units of rows (for example, patents). Reference 1).

JP 2000-261602 A

  In the solid-state imaging device, an analog pixel signal read from the pixel unit is converted into digital data by an analog-digital converter (AD converter; Analog Digital Converter) as necessary. For this reason, various AD conversion mechanisms have been proposed. As an example, a comparator and a counter for comparing a sawtooth voltage waveform and an electric signal (including a pulse width signal) reflecting a pixel signal are provided. (See, for example, Non-Patent Documents 1 to 5 and Patent Documents 2 and 3).

W. Yang et. Al., “An Integrated 800x600 CMOS ImageSystem,” ISSCC Digest of Technical Papers, pp. 304-305, Feb., 1999 Kazuya Yonemoto, “Basics and Applications of CCD / CMOS Image Sensors”, CQ Publisher, August 10, 2003, first edition, p201-203 Toshifumi Imamura and Miko Yamamoto, “3. Research on high-speed and functional CMOS image sensors”, [online], [March 15, 2004 search], Internet <URL: http://www.sankaken.gr.jp/ project / iwataPJ / report / h12 / h12index.html> Toshifumi Imamura, Miko Yamamoto, Naoya Hasegawa, “3. Research on high-speed and functional CMOS image sensors”, [online], [Search on March 15, 2004], Internet <URL: http://www.sankaken.gr .jp / project / iwataPJ / report / h14 / h14index.html> Oh-Bong Kwon et. Al., “A Novel Double Slope Analog-to-Digital Converter for a High-Quality 640x480 CMOS Imaging System”, VL3-03 1999 IEEE p335-338 Japanese Patent Laid-Open No. 11-331883 JP 2002-232787 A

  In the case of handling a color image, when AD conversion is performed by comparing a sawtooth voltage waveform and an electrical signal reflecting a pixel signal, a color filter of a plurality of colors is provided for capturing a color image. A mechanism for performing AD conversion in consideration of the color characteristics of each pixel is considered.

  For example, in the technique described in Patent Document 1, when analog image data is converted into digital image data, different reference voltages are generated according to analog image data characteristics of a specific color and a comparison operation is performed. When converting the analog image data output from the unit pixel into digital image data, adjustment is made according to each color to enable more precise color control.

<Configuration of conventional solid-state imaging device>
FIG. 18 is a schematic configuration diagram of a solid-state imaging device (CMOS image sensor) in which the AD conversion device shown in FIG. 4 of Patent Document 1 is mounted on the same semiconductor substrate as the pixel portion.

  The solid-state imaging device includes an analog reference voltage generating unit that generates an analog reference voltage that decreases at different reduction rates from different initial voltage levels for each color pixel, and an analog reference corresponding to each color pixel in response to a selection signal. Selection means for selectively outputting the voltage, and comparison means for comparing the analog reference voltage output from the selection means with the analog image data output from the pixel array to output digital image data, Analog image data sensed from each color pixel of the pixel array is converted into digital image data in accordance with the analog image data characteristics.

  As a specific example, as shown in FIG. 18, the solid-state imaging device includes an M (row line) × N (column line) pixel array 50 arranged in a Bayer pattern and an analog signal from the pixel array 50 as a digital signal. An analog-digital conversion unit 60 for converting into

  The analog-to-digital converter 60 includes analog reference voltage generators 601A (for B color), 601B (for G color), and 601C (for R color) prepared for each of the color components R, G, and B constituting the Bayer pattern. Comparators 603A and 603B arranged for each vertical column, and multiplexers 602A that select one of the reference signals from the analog reference voltage generators 601A, 601B, and 601C and input the comparators 603A and 603B. 602B.

  Here, the analog reference voltage generator generates a first reference voltage generator 601A that generates a reference voltage for a blue pixel, a second reference voltage generator 601B that generates a reference voltage for a green pixel, and a reference voltage for a red pixel. The reference voltage generators 601C generate reference voltages having different reduction rates from different initial voltage levels according to the color characteristics of the reference voltage generator.

  The comparators 603A and 603B are provided in total for the vertical columns (N). For example, the comparator 603A is arranged in an odd column, and the comparator 603B is arranged in an even column. Correspondingly, the multiplexer 602A is arranged on the input side of the odd-numbered column comparator 603A, and the multiplexer 602B is arranged on the input side of the even-numbered column comparator 603B.

  That is, one of the analog reference voltage generators that generate reference signals that decrease at different reduction rates from different initial voltage levels depending on the color pixel, and any of the reference signals from each analog reference voltage generator for each comparator in each column Selection means (multiplexer) for selectively outputting one is provided.

  The multiplexers 602A and 602B selectively output the output signals from the reference voltage generators 601A, 601B, and 601C in response to the selection signal SEL. The comparators 603A and 603B compare the output signals from the multiplexers 602A and 602B with the analog signals from the pixel array 50.

  In the case of the Bayer pattern, for example, red pixels or green pixels are arranged on the odd-numbered column lines such as the first column line, the third column line, and the fifth column line in the pixel array 50. The arranged multiplexer 602A outputs one of the output signals of the second or third reference voltage generators 601B and 601C. On the other hand, since the green pixels or the blue pixels are arranged on the even-numbered column lines such as the second, fourth, and sixth column lines, the multiplexer 602B arranged on the even-numbered column lines by the color pixels One of the output signals of the first or second reference voltage generators 601A and 601B is output.

  However, in the mechanism described in Patent Document 1, in the case of the Bayer array, a color image is displayed such as three units of a first reference voltage generator 601A, a second reference voltage generator 601B, and a third reference voltage generator 601C. Prepare an analog reference voltage generator for each color component of the color filter for imaging, transmit the reference signal output from each analog reference voltage generator to the input side of the comparator provided for each vertical column, Selection means (multiplexer) for selectively outputting any one of the reference signals from each analog reference voltage generator is provided immediately before the input side of the comparator.

  For this reason, the number of reference signal lines for transmitting the reference signal generated from each analog reference voltage generation device to the input side of the comparator is required only for the color components of the color filter for capturing a color image, More than the number of reference signals from each analog reference voltage generator that needs to be switched on the input side of the detector, and a selection means (multiplexer) is required for each pixel column, which requires a large area. Cost reduction is difficult.

  The present invention has been made in view of the above circumstances, and the number of reference signal lines for transmitting a reference signal corresponding to a color pixel to the input side of a comparator is the color component of a color filter for capturing a color image. It is an object to propose a mechanism that can reduce the number of selection means and the number of selection means.

  In the present invention, any color filter of a color separation filter composed of a combination of color filters for obtaining color information is provided on the surface on the side where the electromagnetic wave of each charge generation unit is incident in the effective region. The reference signal generator and the individual reference signal generator / output unit for generating and outputting the reference signal have a predetermined direction corresponding to the reading unit and a direction different from the predetermined direction corresponding to the reading unit. Less than the number of color components of the color filter existing in the repeating unit of the color filter array in each of the different directions, and within the repeating unit of the color filter array in the predetermined direction according to the reading unit of the unit signal As many as the number of color filters existing in

  Further, as the reference signal generation / output unit, a color-corresponding reference signal generation unit that generates and outputs a reference signal corresponding to the color characteristic of the corresponding color filter is different from the predetermined direction corresponding to the reading unit. The number of color filters existing in the repeating unit of the color filter array in the direction is changed, and any one of the reference signals generated by each of the color-corresponding reference signal generation units is switched to the readout unit to be processed. The selected reference signal is transmitted substantially directly to a plurality of comparison units corresponding to color filters having a common color characteristic in a predetermined direction via one common reference signal line. It shall have a selection part.

  In short, when the color filters are arranged two-dimensionally in the effective area, the number of color filters existing in the repeating unit of the color filter array is the same in the reading unit direction (for example, the row direction). A reference signal generation output unit is provided. Then, in a direction (different direction; for example, column direction) different from the direction of the reading unit (for example, row direction), the color existing in the repeating unit of the color filter array in the different direction for each reference signal generation / output unit. Color-corresponding reference signal generation units corresponding to the number of filters are provided, and a selection unit that switches the color-corresponding reference signal generation units to be used in conjunction with the switching of the processing target color associated with the switching of the reading unit is provided.

  In this case, since the reference signal generated by the color corresponding reference signal generation unit is supplied to the comparison unit, in principle, the selection unit is arranged on the reference signal line between the color corresponding reference signal generation unit and the comparison unit. It will be. In this case, the manner in which the selection unit is arranged on the reference signal line can take various forms depending on the circuit configuration. In this case, the selection unit has an adverse effect on the generation of the color-corresponding reference signal as much as possible. It is preferable to consider that the selection unit does not adversely affect the transmission of the color-corresponding reference signal generated by the color-corresponding reference signal generation unit to the comparison unit.

  For example, depending on the circuit configuration, a configuration in which a selection unit (specifically, a switch for switching) is actually included in the color-corresponding reference signal generation unit may be employed. For example, the color-corresponding reference signal generation unit includes a constant current source array including a plurality of constant current sources arranged in parallel and including an output end, and a combining element that combines currents flowing through the plurality of constant current sources. If so, the input terminal of the selection unit is connected to the output terminal of the constant current source array, the output terminal is connected to the synthesis element, and the reference signal generated by the synthesis is supplied to the common reference signal line at this output terminal. To do.

  Alternatively, a common reference signal line that is used in common with a plurality of comparison units corresponding to color filters having a common color characteristic by connecting a plurality of color-corresponding reference signal generation units and input terminals of the selection unit. And an output terminal can be connected. For example, the color-corresponding reference signal generation unit includes a constant current source array including a plurality of constant current sources arranged in parallel and including an output end, and a combining element that combines currents flowing through the plurality of constant current sources. If it is, the input terminal of the selection unit is connected to the connection point between the output terminal of the constant current source array and the combining element, and the reference signal obtained at the output terminal of the selection unit is supplied to the common reference signal line. .

  In addition, when the selection unit is arranged, it is important that the presence of the selection unit does not affect the generation of the reference signal or the reference signal transmitted to the comparison unit. It is desirable that the on-resistance is sufficiently smaller than the output resistance of the color-corresponding reference signal generation unit and the input resistance of the comparison unit.

  According to the present invention, the configuration of the reference signal generation unit that generates the reference signal is configured by the individual reference signal generation output unit that generates and outputs the reference signal, and the reference signal generation output unit is used as a reading unit. Less than the number of color components of the color filter existing in the repeating unit of the arrangement of the color filters in each of the different directions that are different from the predetermined direction according to the predetermined direction and the predetermined direction according to the readout unit, and the unit signal The same number of color filters as the number of color filters existing in the repeating unit of the color filter array in a predetermined direction according to the read unit of each reference signal, and each reference signal output independently from each reference signal generation output unit is shared The comparison unit corresponding to the color filter having the above color characteristics is substantially directly transmitted via the common reference signal line.

  In short, every predetermined direction according to the reading unit regardless of the color type of the color filter existing in the repeating unit of the color separation filter formed in a predetermined direction corresponding to the reading unit and a direction different from the predetermined direction. In addition, as many reference signal generators as the number of color filters existing in the repetition unit of the color separation filter are prepared, and the generated reference signals are shared by the respective comparison units for the corresponding color filters. Directly transmitted through the signal line.

  In addition, for each reference signal generation output unit, a selection unit that switches between the color-corresponding reference signal generation unit corresponding to each color filter and the color-corresponding reference signal generation unit according to the processing target row is provided. That is, for each reference signal generation output unit, there are provided as many color-corresponding reference signal generation units as the number of color filters existing in the repeating unit of the color filter array in different directions, and the processing target color accompanying switching of the readout unit The color-corresponding reference signal generation unit used in conjunction with the switching is switched by the selection unit, and the selected color-corresponding reference signal is supplied to the common reference signal line.

  For this reason, when the unit of the color separation filter for capturing a color image is defined in two dimensions, the number of common reference signal lines for transmitting the reference signal corresponding to the color pixel to the input side of the comparator is all The number of color components can be reduced.

  Each reference signal output independently from each reference signal generation output unit is substantially directly transmitted to a comparison unit corresponding to a color filter having a common color characteristic via a common signal line. The selection means (multiplexer) for each vertical column, which is required in Document 1, is not necessary, and the circuit scale can be greatly reduced, and the cost can be reduced.

  Supplying reference signals suitable for color imaging to the comparison unit for AD conversion while reducing the circuit scale and the number of transmission signal lines when configuring a semiconductor device for color imaging with an AD converter mounted on the same chip can do.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where a CMOS image sensor, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. The CMOS image sensor will be described on the assumption that all pixels are made of NMOS or PMOS.

  However, this is merely an example, and the target device is not limited to a MOS imaging device. All the semiconductor device for physical quantity distribution detection in which a plurality of unit components that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged in a line or matrix form, and all implementations described later. Forms are applicable as well.

<First Embodiment; Configuration of Solid-State Imaging Device; Bayer Arrangement>
FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device (CMOS image sensor) which is a first embodiment of a semiconductor device according to the present invention. FIG. 2 is a diagram illustrating an example of a relationship between an effective image region (effective portion) in the pixel portion (imaging portion) and a reference pixel region that gives optical black. This CMOS solid-state imaging device is also an aspect of electronic equipment.

  The solid-state imaging device 1 has a pixel unit in which a plurality of pixels including a light receiving element (an example of a charge generation unit) that outputs a signal corresponding to an incident light amount is arranged in rows and columns (that is, in a two-dimensional matrix form). The signal output from each pixel is a voltage signal, and a CDS (Correlated Double Sampling) processing function unit, a digital conversion unit (ADC), etc. are provided in parallel in a column. It is.

  “The CDS processing function unit and the digital conversion unit are provided in parallel with the column” means that a plurality of CDS processing function units and digital conversion units are provided substantially in parallel with the vertical signal line 19 in the vertical column. Means that Each of the plurality of functional units is arranged only on one edge side in the column direction with respect to the pixel unit (imaging unit) 10 (an output side arranged on the lower side of the drawing) when the device is viewed in plan view. Or one end side in the column direction with respect to the pixel portion 10 (the output side disposed on the lower side of the figure) and the other end side on the opposite side (see FIG. May be arranged separately on the upper side). In the latter case, it is preferable that the horizontal scanning unit that performs readout scanning (horizontal scanning) in the row direction is also arranged separately on each edge side so that each can operate independently.

  For example, as a typical example in which a CDS processing function unit and a digital conversion unit are provided in parallel in a column, a CDS processing function unit and a digital conversion unit are arranged for each vertical column in a portion called a column area provided on the output side of the imaging unit. And is a column type that sequentially reads out to the output side. In addition to the column type, a configuration in which one CDS processing function unit or digital conversion unit is assigned to a plurality of adjacent (for example, two) vertical signal lines 19 (vertical columns), or every N (N is It is also possible to adopt a form in which one CDS processing function unit or digital conversion unit is assigned to N vertical signal lines 19 (vertical columns) of a positive integer (with N−1 lines in between).

  Except for the column type, in any form, since a plurality of vertical signal lines 19 (vertical columns) commonly use one CDS processing function unit and digital conversion unit, they are supplied from the pixel unit 10 side. A switching circuit (switch) that supplies pixel signals for a plurality of columns to one CDS processing function unit or digital conversion unit is provided. Depending on the subsequent processing, it is necessary to take measures such as providing a memory for holding the output signal.

  In any case, the signal processing of each pixel signal is read out in units of pixel columns by adopting a form in which one CDS processing function unit or digital conversion unit is assigned to a plurality of vertical signal lines 19 (vertical columns). By performing the processing later, the configuration in each unit pixel can be simplified and the number of pixels of the image sensor can be reduced, the size can be reduced, and the cost can be reduced as compared with the case where the same signal processing is performed in each unit pixel.

  In addition, since a plurality of signal processing units arranged in parallel in a column can simultaneously process pixel signals for one row, one CDS processing function unit or digital conversion unit is provided on the output circuit side or outside the device. Therefore, the signal processing unit can be operated at a low speed as compared with the case where processing is performed, which is advantageous in terms of power consumption, bandwidth performance, noise, and the like. In other words, when the power consumption and bandwidth performance are the same, the entire sensor can be operated at high speed.

  In the case of a column type configuration, it can be operated at a low speed, which is advantageous in terms of power consumption, bandwidth performance, noise, and the like, and has an advantage that a switching circuit (switch) is unnecessary. In the following embodiments, this column type will be described unless otherwise specified.

  As shown in FIG. 1, the solid-state imaging device 1 according to the first embodiment includes a pixel unit (imaging unit) in which a plurality of unit pixels 3 having a substantially square pixel shape are arranged in rows and columns (that is, a square lattice). 10, a drive control unit 7 provided outside the pixel unit 10, a column processing unit 26, a reference signal generation unit 27 that supplies a reference voltage for AD conversion to the column processing unit 26, and an output circuit 28. I have.

  In addition, an AGC (Auto Gain Control) circuit having a signal amplification function or the like can be provided in the same semiconductor region as the column processing unit 26 as needed before or after the column processing unit 26. When AGC is performed before the column processing unit 26, analog amplification is performed. When AGC is performed after the column processing unit 26, digital amplification is performed. If the n-bit digital data is simply amplified, the gradation may be lost. Therefore, it is preferable to perform digital conversion after amplification by analog.

  The drive control unit 7 has a control circuit function for sequentially reading signals from the pixel unit 10. For example, the drive control unit 7 includes a horizontal scanning circuit (column scanning circuit) 12 that controls column addresses and column scanning, a vertical scanning circuit (row scanning circuit) 14 that controls row addresses and row scanning, and an internal clock. And a communication / timing control unit 20 having a function such as generation.

  In the drawing, as shown by a dotted line in the vicinity of the communication / timing control unit 20, the clock conversion unit 23 is an example of a high-speed clock generation unit that generates a pulse having a clock frequency higher than the input clock frequency. May be provided. The communication / timing control unit 20 generates an internal clock based on the input lock (master clock) CLK0 input via the terminal 5a or the high-speed clock generated by the clock conversion unit 23.

  By using a signal derived from the high-speed clock generated by the clock converter 23, AD conversion processing and the like can be operated at high speed. Also, motion extraction and compression processing requiring high-speed calculation can be performed using a high-speed clock. Also, the parallel data output from the column processing unit 26 can be converted into serial data and the video data D1 can be output outside the device. By doing so, it is possible to adopt a configuration in which high-speed operation output is performed with a smaller number of terminals than the number of bits of AD-converted digital data.

  The clock converter 23 includes a multiplier circuit that generates a pulse having a clock frequency faster than the input clock frequency. The clock conversion unit 23 receives the low-speed clock CLK2 from the communication / timing control unit 20, and generates a clock having a frequency twice or more higher based on the low-speed clock CLK2. As a multiplication circuit of the clock converter 23, a k1 multiplication circuit may be provided when k1 is a multiple of the frequency of the low-speed clock CLK2, and various known circuits can be used.

  In FIG. 1, for simplification, some of the rows and columns are omitted, but in reality, in each row and each column, dozens to thousands of unit pixels 3 are arranged, and the pixel unit 10 includes Composed. The unit pixel 3 is typically composed of a photodiode as a light receiving element (charge generation unit) and an in-pixel amplifier having an amplifying semiconductor element (for example, a transistor).

  As the intra-pixel amplifier, for example, a floating diffusion amplifier configuration is used. As an example, with respect to the charge generation unit, a read selection transistor that is an example of a charge readout unit (transfer gate unit / read gate unit), a reset transistor that is an example of a reset gate unit, a vertical selection transistor, and a floating diffusion As a CMOS sensor having a source follower-amplifying transistor, which is an example of a detection element for detecting a change in potential, a sensor composed of four general-purpose transistors can be used.

  Alternatively, as described in Japanese Patent No. 2708455, an amplifying transistor connected to a drain line (DRN) for amplifying a signal voltage corresponding to the signal charge generated by the charge generating unit, and the charge generating unit It is also possible to use a transistor composed of three transistors, each having a reset transistor for resetting and a read selection transistor (transfer gate portion) scanned from a vertical shift register via a transfer wiring (TRF). .

  In addition to the effective image region (effective portion) 10a that is an effective region for capturing an image, the pixel unit 10 includes a reference pixel region 10b that gives optical black as shown in FIG. 2 around the effective image region 10a. Configured. As an example, reference pixels that give optical black for several rows (for example, 1 to 10 rows) are arranged above and below in the vertical column direction, and several pixels to several tens in the horizontal direction including the effective image region 10a. Reference pixels that provide optical black for pixels (for example, 3 to 40 pixels) are arranged.

  The reference pixel for providing optical black is shielded on the light receiving surface side so that light does not enter a charge generation unit made of a photodiode or the like. The pixel signal from this reference pixel is used for the black reference of the video signal.

  In the solid-state imaging device 1 of the first embodiment, the pixel unit 10 is adapted for color imaging. That is, color separation composed of a combination of a plurality of color filters for capturing a color image on a light receiving surface on which electromagnetic waves (light in this example) of each charge generation unit (such as a photodiode) in the pixel unit 10 is incident. Any color filter of the filter is provided.

  The illustrated example uses a basic color filter of a so-called Bayer array, and unit pixels 3 arranged in a square lattice are three color colors of red (R), green (G), and blue (B). In order to correspond to the filter, the repeating unit of the color separation filter is arranged by 2 pixels × 2 pixels to constitute the pixel unit 10.

  For example, a first color pixel for sensing a first color (red; R) is arranged in an odd-numbered row and an odd-numbered column, and a second color (green; G; ) Is arranged, and the third color pixel for sensing the third color (blue; B) is arranged in the even-numbered row and the even-numbered column, and is different for each row. Further, two color pixels of R / G or G / B are arranged in a checkered pattern.

  In the color arrangement of the basic color filter in such a Bayer arrangement, two colors of R / G or G / B are repeated every two in both the row direction and the column direction.

  Further, as other components of the drive control unit 7, a horizontal scanning circuit 12, a vertical scanning circuit 14, and a communication / timing control unit 20 are provided. The horizontal scanning circuit 12 has a function of a reading scanning unit that reads a count value from the column processing unit 26. Each element of these drive control units 7 is formed integrally with a pixel unit 10 in a semiconductor region such as single crystal silicon using a technique similar to a semiconductor integrated circuit manufacturing technique, and is a solid-state imaging which is an example of a semiconductor system It is configured as an element (imaging device).

  The unit pixel 3 includes a column processing unit 26 in which a vertical scanning circuit 14 is provided via a row control line 15 for row selection, and a column AD circuit 25 is provided for each vertical column via a vertical signal line 19; Each is connected. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning circuit 14.

  The horizontal scanning circuit 12 and the vertical scanning circuit 14 include a decoder as will be described later, and start a shift operation (scanning) in response to control signals CN1 and CN2 given from the communication / timing control unit 20. It has become. Therefore, the row control line 15 includes various pulse signals (for example, a reset pulse RST, a transfer pulse TRF, a DRN control pulse DRN, etc.) for driving the unit pixel 3.

  Although not shown, the communication / timing control unit 20 is a master via a functional block of a timing generator TG (an example of a read address control device) that supplies a clock signal necessary for the operation of each unit and a pulse signal of a predetermined timing, and a terminal 5a. A communication interface functional block that receives the clock CLK0, receives data DATA for instructing an operation mode and the like via the terminal 5b, and outputs data including information of the solid-state imaging device 1;

  For example, the horizontal address signal is output to the horizontal decoder 12a and the vertical address signal is output to the vertical decoder 14a, and each decoder 12a, 14a receives it and selects a corresponding row or column.

  At this time, since the unit pixels 3 are arranged in a two-dimensional matrix, analog pixel signals generated by the pixel signal generation unit 5 and output in the column direction via the vertical signal lines 19 are arranged in a row unit (column parallel). (In) Scan (access) to read (vertical) scan, and then access the row direction, which is the arrangement direction of vertical columns, and read out pixel signals (in this example, digitized pixel data) to the output side (horizontal) scan By performing reading, it is preferable to speed up reading of pixel signals and pixel data. Of course, not only scanning reading but also random access for reading out only the information of the necessary unit pixel 3 is possible by directly addressing the unit pixel 3 to be read out.

  Further, in the communication / timing control unit 20 of the first embodiment, the clock CLK1 having the same frequency as the master clock (master clock) CLK0 input via the terminal 5a, or a clock obtained by dividing the clock CLK1 by two or more is divided. A low-speed clock is supplied to each part in the device, for example, the horizontal scanning circuit 12, the vertical scanning circuit 14, and the column processing unit 26. Hereinafter, the clocks divided by two and the clocks having a frequency lower than that are collectively referred to as a low-speed clock CLK2.

  The vertical scanning circuit 14 selects a row of the pixel unit 10 and supplies a necessary pulse to the row. For example, a vertical decoder 14a that defines a readout row in the vertical direction (selects a row of the pixel unit 10), and a row control line 15 for the unit pixel 3 on the readout address (in the row direction) defined by the vertical decoder 14a. And a vertical drive circuit 14b for driving by supplying a pulse. Note that the vertical decoder 14a selects a row for electronic shutter, in addition to a row from which a signal is read.

  The horizontal scanning circuit 12 sequentially selects the column AD circuit 25 of the column processing unit 26 in synchronization with the low-speed clock CLK2, and guides the signal to a horizontal signal line (horizontal output line) 18. For example, a horizontal decoder 12a that defines a horizontal readout column (selects each column AD circuit 25 in the column processor 26), and each of the column processors 26 according to a read address defined by the horizontal decoder 12a. A horizontal drive circuit 12b for guiding a signal to the horizontal signal line 18. For example, if the number of horizontal signal lines 18 is n (n is a positive integer) handled by the column AD circuit 25, for example, 10 (= n) bits, 10 horizontal signal lines 18 are arranged corresponding to the number of bits. .

  In the solid-state imaging device 1 having such a configuration, the pixel signal output from the unit pixel 3 is supplied to the column AD circuit 25 of the column processing unit 26 via the vertical signal line 19 for each vertical column.

  Each column AD circuit 25 of the column processing unit 26 receives a pixel signal for one column and processes the signal. For example, each column AD circuit 25 has an ADC (Analog Digital Converter) circuit that converts an analog signal into, for example, 10-bit digital data using, for example, a low-speed clock CLK2.

  As the AD conversion processing in the column processing unit 26, a method is adopted in which analog signals held in parallel in units of rows are subjected to AD conversion in parallel for each row using the column AD circuit 25 provided for each column. In this case, for example, Japanese Patent Publication No. 2532374 and academic literature “CMOS image sensor equipped with column AD converter without inter-column FPN” (film science technique, IPU2000-57, pp.79-84), etc. A single slope integration type (or ramp signal comparison type) AD conversion method shown in FIG. Since this method can realize an AD converter with a simple configuration, it has a feature that the circuit scale does not increase even if it is provided in parallel.

  Although the details of the configuration of the ADC circuit will be described later, the analog processing target signal is converted into digital data based on the time from the start of conversion until the reference voltage RAMP matches the processing target signal voltage. As a mechanism for this, in principle, the ramp-shaped reference voltage RAMP is supplied to the comparator (voltage comparator), and at the same time, counting with the clock signal is started and input via the vertical signal line 19. By comparing the analog pixel signal with the reference voltage RAMP and counting until a pulse signal is obtained, AD conversion is performed.

  At this time, by devising the circuit configuration, the signal level (noise level) immediately after the pixel reset and true (for the voltage mode pixel signal input via the vertical signal line 19 as well as AD conversion) are true ( It is possible to perform processing for obtaining a difference from the signal level Vsig (in accordance with the amount of received light). Thereby, it is possible to remove a noise signal component called fixed pattern noise (FPN) or reset noise.

  The pixel data digitized by the column AD circuit 25 is transmitted to the horizontal signal line 18 through a horizontal selection switch (not shown) driven by a horizontal selection signal from the horizontal scanning circuit 12, and further input to the output circuit 28. The Note that 10 bits is an example, and other bit numbers such as less than 10 bits (for example, 8 bits) and more than 10 bits (for example, 14 bits) may be used.

  With such a configuration, pixel signals are sequentially output for each vertical column for each row from the pixel unit 10 in which light receiving elements as charge generation units are arranged in a matrix. Then, one image corresponding to the pixel unit 10 in which the light receiving elements are arranged in a matrix, that is, a frame image, is shown as a set of pixel signals of the entire pixel unit 10.

<Details of column AD circuit and reference signal generator>
The reference signal generation unit 27 is a DA conversion circuit (DAC; Digital Analog) that is a functional element that generates a reference signal for AD conversion in accordance with the color type and arrangement of the color filters constituting the color separation filter in the pixel unit 10. Converter) is provided separately.

  When the pixel unit 10 (device) to be used is determined, the color type and arrangement of the color filters in the color separation filter are determined, and the number of the color filter at an arbitrary position in the two-dimensional grid position is uniquely specified. Can do. Each repetition cycle in the row direction and the column direction of the color filter is also uniquely determined by the arrangement, and one column to be processed by each column AD circuit 25 provided in parallel with the column is used in the color separation filter. There are only pixel signals of a predetermined combination of colors that are less than the total number of colors that are determined and that are determined by the repetition cycle.

  In this embodiment, paying attention to this property, when configuring an AD conversion circuit with a comparison circuit and a counter, individual reference corresponding to color, which is a functional element that generates a reference signal for AD conversion supplied to the comparison circuit A DA conversion circuit as an example of a signal generation output unit is not provided for all the colors used in the color separation filter, but first, a predetermined number that exists in the repetition cycle of the color filter with respect to the row direction as a pixel signal readout unit. Only a few minutes according to the combination of color filters is used, so that the total number of color filters existing in the two-dimensional color filter repetition cycle is reduced. For example, if there is only x (x is a positive integer greater than or equal to 2) colors in any row to be processed, a reference signal for each color corresponding to the x color is supplied to the comparison circuit. It suffices to prepare x DA conversion circuits.

  Note that it is necessary to deal with switching of the processing target row from the viewpoint of supplying individual reference signals having color-related change characteristics and initial values to the comparison circuit. For this purpose, it is preferable to provide a switching mechanism for supplying a reference signal for the current processing color in each of the x DA conversion circuits in the column direction orthogonal to the row direction.

  In other words, with respect to a different direction that is different from the row direction according to the readout unit, that is, the vertical column direction, a change characteristic (specifically, a slope) corresponding to the color characteristic of the color pixel, a black reference, and a circuit offset component A color-corresponding reference signal generator that changes with an initial value defined in terms of non-color characteristics different from color characteristics such as the color characteristics of a color filter of a predetermined color that exists in the repetition cycle of the color filter in the vertical column direction. Provided for each individual DA converter circuit (reference signal generation / output unit) by the number corresponding to the combination, and selects one of the reference signals generated by the reference signal generation / output unit corresponding to the color. Thus, a selection unit for supplying to the comparison circuit is provided.

  In this case, for example, when the same color filter exists in the two-dimensional color filter repetition cycle as in the Bayer array, an individual DA conversion circuit (reference signal generation output unit) is used for the same color filter. Each can also be configured to share (shared) one color-corresponding reference signal generation unit.

  In any configuration, each DA conversion circuit, which is an example of the reference signal generation output unit, performs DA conversion in response to switching of a predetermined color combination existing in the processing target row when the processing target row is switched. The change characteristic (specifically, the slope) of the reference signal (analog reference voltage) generated by the circuit is switched and output according to the characteristic of the color filter, that is, the analog pixel signal. The initial value is set based on a viewpoint different from the color characteristics such as black reference and circuit offset component.

  By doing so, the number of reference voltage generators (corresponding to DA conversion circuits in this example) and wiring from the reference voltage generators can be made smaller than the number of color filters constituting the color separation filter. Further, it is necessary when a reference voltage generator is prepared for each color filter (see Patent Document 1), and an analog reference voltage (corresponding to the reference signal in this example) from each reference voltage generator is selectively used. Since the selection means (multiplexer) for each vertical column to be output is not required, the circuit scale can be reduced. The number of signal lines for transmitting reference signals corresponding to the color pixels to the input side of the comparator can be made smaller than the number of color components of the color filter for capturing a color image.

  Although not employed in the present embodiment, each time the processing target row is switched for each individual DA conversion circuit (reference signal generation output unit), a repeating unit of the color filter array associated with the switching is configured. The initial value based on a different viewpoint from the color characteristics such as the black characteristics and the circuit offset component, and the change characteristics corresponding to the color characteristics of the corresponding color pixel (specifically, the slope) The communication / timing control unit 20 may be set. By doing so, it is not necessary to provide a selection unit for selecting either the color-corresponding reference signal generation unit or the color-corresponding reference signal generation unit in each of the individual DA conversion circuits (reference signal generation output units).

  In other words, the idea is to change the change characteristics (specifically, the slope) and the initial value according to the change in the combination of colors that constitute the repeating unit of the color filter array that accompanies the switching each time the processing target row is switched. If the DA conversion circuit is set, a selection unit that switches between the color-corresponding reference signal generation unit and the color-corresponding reference signal generation unit corresponding to each color filter according to the processing target row (specific examples 1 to be described later). 5), the scale of the entire configuration of the reference signal generation unit 27 can be further reduced. However, in this case, the processing of the control system of the reference signal generator 27 may be complicated.

  In this example, as the solid-state imaging device 1, a Bayer-type basic array is used, and as described above, the color filter is repeated every two rows and two columns. The pixel signal is read out in units of rows, and the pixel signal is input to each column AD circuit 25 provided in parallel for each vertical signal line 19. Therefore, one processing target row includes R / G or G / B. There are pixel signals of only two colors. Therefore, in this example, a DA conversion circuit 27a corresponding to an odd number column and a DA conversion circuit 27b corresponding to an even number column are provided.

  Further, the reference signals RAMPa and RAMPb output independently from each DA converter circuit are transmitted to the voltage comparison unit 252 through independent common reference signal lines 251a and 251b (collectively referred to as 251). A plurality of voltage comparison units 252a (in odd-numbered columns) and voltage comparison units 252b (in even-numbered columns) are connected to the common reference signal lines 251a and 251b, respectively.

  In this case, it is configured so as to be transmitted substantially directly to the plurality of voltage comparison units 252a and 252b corresponding to the color filters having common color characteristics via the independent common reference signal lines 251a and 251b. . Transmitting substantially directly through the common reference signal lines 251a and 251b means between the common reference signal lines 251a and 251b and the voltage comparison sections 252a and 252b (each of which has a plurality of columns) corresponding to the common reference signal lines 251a and 251b. Means that there is no selection means such as a multiplexer. In this respect, the reference signal output from each analog reference voltage generator is transmitted to the input side of the comparator provided for each vertical column, and the reference from each analog reference voltage generator immediately before the input side of each comparator. This is greatly different from the configuration of Patent Document 1 in which selection means (multiplexer) for selectively outputting any one of the signals is provided.

  Each DA converter circuit 27a, 27b starts counting clocks CKdaca, CKdacb (count clock CK0 and count clock CK0 from the communication / timing controller 20 from the initial value indicated by the control data CN4 (CN4a, CN4b) from the communication / timing controller 20. The stepped sawtooth wave (ramp voltage) is generated in synchronization with each other, and the generated sawtooth wave is converted into an AD conversion signal to each column AD circuit 25 corresponding to the column processing unit 26. Reference signals (ADC reference signals) RAMPa and RAMPb are supplied. Although illustration is omitted, a filter for preventing noise may be provided.

  The DA conversion circuits 27a and 27b have functions unique to the present embodiment, when performing AD conversion processing on the signal component Vsig in the pixel signal Vx at a predetermined position using the voltage comparison unit 252 and the counter unit 254, respectively. The initial voltages of the reference signals RAMPa and RAMPb to be emitted are set to values different from those at the time of AD conversion processing for the reset component ΔV, reflecting pixel characteristics and circuit variation, and the pixel is considered in consideration of the arrangement of color filters. It is characterized in that the respective inclinations βa and βb are set so as to match the characteristics.

  Specifically, first, it is assumed that the initial voltages Vas and Vbs of the reference signals RAMPa and RAMPb for the signal component Vsig are calculated based on signals obtained from pixels that generate an arbitrary plurality of black references. The pixel that generates the black reference is a pixel having a light shielding layer on a photodiode or the like as a photoelectric conversion element that forms the charge generation unit 32 arranged outside the color pixel. The arrangement form such as the arrangement location and the number of arrangements and the light shielding means are not particularly limited, and a known mechanism can be adopted.

  The initial voltage includes inherent variation components generated by the characteristics of the DA converter circuits 27a and 27b. Normally, the initial voltages Vas and Vbs are made lower by offsets OFFa and OFFb than the initial voltages Var and Vbr of the reference signals RAMPa and RAMPb for the reset component ΔV, respectively.

  Even if the initial voltages Var and Vbr of the reference signals RAMPa and RAMPb for the reset component ΔV are the same, the offsets OFFa and OFFb usually have different values, so that the initial values of the reference signals RAMPa and RAMPb for the signal component Vsig are different. The voltages Vas and Vbs are different.

  Note that the initial voltages Vas and Vbs of the reference signals RAMPa and RAMPb for the signal component Vsig may include an arbitrary offset in addition to the signal obtained from the pixel generating the black reference.

  The control for the offsets OFFa and OFFb performed by the DA conversion circuits 27a and 27b of the reference signal generation unit 27 has a function of calculating an initial voltage based on signals obtained from, for example, any reference pixel that generates a plurality of black references. The communication / timing control unit 20 may be provided, and may be performed based on an initial value indicated by the control data CN4 from the communication / timing control unit 20. Of course, the DA conversion circuits 27a and 27b may have a function of calculating the initial voltage and calculate the initial voltage by themselves.

  Alternatively, the communication / timing control unit 20 and the DA conversion circuits 27a and 27b in the chip do not have a function of calculating an initial voltage of the reference voltage, but are obtained from a reference pixel that generates a black reference by an external system outside the chip. The initial voltage is calculated based on the received signal, information indicating the initial voltage is notified to the communication / timing controller 20 as a part of the operation mode via the terminal 5b, and the control data CN4 from the communication / timing controller 20 is transmitted. May be notified to the reference signal generator 27.

  The stepped reference signal generated by the reference signal generation unit 27, specifically, the reference signal RAMPa generated by the DA conversion circuit 27a and the reference signal RAMPb generated by the DA conversion circuit 27b are a high-speed clock from the clock conversion unit 23, for example, a multiplier circuit. By generating based on the multiplied clock generated in step (5), it is possible to change the speed faster than that based on the master clock CLK0 input via the terminal 5a.

  The control data CN4a and CN4b supplied from the communication / timing control unit 20 to the DA conversion circuit 27a of the reference signal generation unit 27 also include information for instructing the ramp voltage gradient (degree of change; amount of time change) for each comparison process. It is out.

  The column AD circuit 25 includes the reference signal RAMP generated by the DA conversion circuit 27a of the reference signal generation unit 27 and the vertical signal line 19 (H1, H2) from the unit pixel 3 for each row control line 15 (V1, V2,...). ,...), And a counter unit 254 that counts the time until the voltage comparison unit 252 completes the comparison process and holds the result. And has an n-bit AD conversion function.

  The communication / timing control unit 20 functions as a control unit that switches the count processing mode in the counter unit 254 according to which of the reset component ΔV and the signal component Vsig of the pixel signal the voltage comparison unit 252 is performing comparison processing. have. A control signal CN5 for instructing whether the counter unit 254 operates in the down count mode or the up count mode is input from the communication / timing control unit 20 to the counter unit 254 of each column AD circuit 25. Yes.

  One input terminal RAMP of the voltage comparison unit 252 receives the step-like reference signal RAMP generated by the reference signal generation unit 27 in common with the input terminal RAMP of the other voltage comparison unit 252, and inputs to the other input terminal. Are connected to the vertical signal lines 19 of the corresponding vertical columns, and the pixel signal voltages from the pixel unit 10 are individually inputted. The output signal of the voltage comparison unit 252 is supplied to the counter unit 254.

  The count clock CK0 from the communication / timing control unit 20 is input to the clock terminal CK of the counter unit 254 in common with the clock terminals CK of the other counter units 254.

  The counter unit 254 is omitted from the illustration of the configuration, but can be realized by changing the wiring form of the data storage unit generally constituted by a latch to the synchronous counter form, and can receive one count clock CK0. The internal count is performed. Similarly to the stepped voltage waveform, the count clock CK0 is generated based on a high-speed clock (for example, a multiplied clock) from the clock conversion unit 23, so that the count clock CK0 is faster than the master clock CLK0 input through the terminal 5a. be able to.

  An n-bit counter unit 254 can be realized by a combination of n latches, which is halved with respect to the circuit scale of a data storage unit composed of two systems of n latches. In addition, since a counter unit for each column is not necessary, the overall size is significantly reduced.

  Here, the counter unit 254 of the first embodiment switches between a down-count operation and an up-count operation using a common up-down counter (U / D CNT) regardless of the count mode, as will be described in detail later. It is characterized in that it is configured to be able to perform a counting process (specifically alternately). Further, the counter unit 254 of the first embodiment uses a synchronous counter whose count output value is output in synchronization with the count clock CK0.

  In the case of a synchronous counter, the operations of all flip-flops (counter basic elements) are limited by the count clock CK0. Therefore, when higher frequency operation is required, the counter unit 254 uses an asynchronous counter suitable for high speed operation because its operation limit frequency is determined only by the limit frequency of the first flip-flop (counter basic element). Is more preferable.

  A control pulse is input to the counter unit 254 from the horizontal scanning circuit 12 through the control line 12c. The counter unit 254 has a latch function for holding the count result, and holds the counter output value until an instruction by a control pulse through the control line 12c is given.

  As described above, the column AD circuit 25 having such a configuration is arranged for each of the vertical signal lines 19 (H1, H2,...), And constitutes a column processing unit 26 that is an ADC block having a column parallel configuration. The

  The output side of each column AD circuit 25 is connected to the horizontal signal line 18. As described above, the horizontal signal line 18 has a signal line corresponding to the n-bit width which is the bit width of the column AD circuit 25, and passes through n sense circuits corresponding to the respective output lines (not shown). Then, the output circuit 28 is connected.

  In such a configuration, the column AD circuit 25 performs a count operation in the pixel signal readout period corresponding to the horizontal blanking period, and outputs a count result at a predetermined timing. That is, first, the voltage comparison unit 252 compares the ramp waveform voltage from the reference signal generation unit 27 with the pixel signal voltage input via the vertical signal line 19, and if both voltages are the same, the voltage comparison The comparator output of the unit 252 is inverted (in this example, transition from H level to L level).

  The counter unit 254 starts the count operation in the down-count mode or the up-count mode in synchronization with the ramp waveform voltage generated from the reference signal generation unit 27, and the counter unit 254 is notified of the inverted information of the comparator output. Then, the count operation is stopped and the AD conversion is completed by latching (holding / storing) the count value at that time as pixel data.

  Thereafter, the counter unit 254 sequentially stores the stored and held pixel data based on the shift operation by the horizontal selection signal CH (i) input from the horizontal scanning circuit 12 via the control line 12c at a predetermined timing. The data is output from the output terminal 5 c to the outside of the column processing unit 26 and the chip having the pixel unit 10.

  Although not specifically illustrated because it is not directly related to the description of the present embodiment, other various signal processing circuits may be included in the components of the solid-state imaging device 1.

<Functional description of reference signal generator>
FIG. 3 is a diagram illustrating the function of the DA conversion circuit (DAC) of the reference signal generation unit 27 used in the solid-state imaging device 1 of the first embodiment.

  The DA conversion circuits 27a and 27b are supplied with the DAC count clock CKdac from the communication / timing control unit 20, and are synchronized with the count clocks CKdaca and CKdacb, for example, in a stepwise sawtooth wave (ramp). Waveform) is generated, and the generated sawtooth wave is supplied to the voltage comparison unit 252 of the column AD circuit 25 as a reference voltage (ADC standard signal) for AD conversion.

  Here, the DA conversion circuits 27a and 27b first set the initial voltage based on the information indicating the initial value of the lamp voltage for each comparison process included in the control data CN4, and are included in the control data CN4. Based on the information indicating the slope (rate of change) of the ramp voltage for each comparison process, the voltage change ΔRAMP per clock is set, and the count value is changed by 1 for each unit time (count clock CKdac). To do. Actually, it is only necessary to set the maximum voltage width for the maximum count number (for example, 1024 in 10 bits) of the count clock CKdac. Any circuit configuration for setting the initial voltage may be used.

  Thus, the DA conversion circuits 27a and 27b decrease the voltage by ΔRAMP for each count clock CKdaca and CKdacb from the voltage (for example, 3.0V) indicating the initial value included in the control data CN4.

  When setting the coefficient for the pixel signal (specifically, the true signal component) from the unit pixel 3, the communication / timing control unit 20 is 1 / m with respect to the reference cycle of the count clock CKdac1 for setting the coefficient 1. The divided count clock CKdacm is supplied to the DA converter circuit 27a. The DA conversion circuit 27a reduces the voltage by ΔRAMP for each count clock CKdacm from the voltage (for example, 3.0V) indicating the initial value included in the control data CN4.

  As a result, the slopes of the reference signals RAMPa and RAMPb supplied to the voltage comparison unit 252 are 1 / m times that when the reference signals RAMPa and RAMPb are generated with the count clock CKdac1 (= CK0). In the unit 254, the count value becomes m times the same pixel voltage, that is, m can be set as a coefficient.

  That is, the slopes of the reference signals RAMPa and RAMPb can be changed by adjusting the periods of the count clocks CKdaca and CKdacb. For example, if a clock divided by 1 / m with respect to the reference is used, the slope becomes 1 / m. If the count clock CK0 in the counter unit 254 is the same, the counter unit 254 can set the count value to m times the same pixel voltage, that is, m can be set as a coefficient. That is, by changing the slopes of the reference signals RAMPa and RAMPb, it is possible to adjust the coefficient at the time of differential processing described later.

  As can be seen from FIG. 3, the larger the inclination of the reference signals RAMPa and RAMPb, the smaller the coefficient applied to the amount of information stored in the unit pixel 3, and the smaller the inclination, the larger the coefficient. For example, the coefficient can be set to “2” by giving the count clock CKdac2 divided by ½ with respect to the reference period of the count clock CKdac1, and the coefficient can be set by giving the count clock CKdac4 divided by ¼. Can be set to “4”. The coefficient can be set to m / n by giving the count clock CKdacnm divided by n / m.

  As described above, the coefficient is set easily and accurately by adjusting the cycle of the count clock CKdacnm supplied to the reference signal generation unit 27 while changing the voltage by ΔRAMP (decrease in this example) for each count clock CKdacm. can do. Note that the sign (+/−) of the coefficient can be designated by adjusting the count processing mode for the signal component Vsig of the pixel signal.

  The coefficient setting method using the slopes of the reference signals RAMPa and RAMPb shown here is merely an example, and the present invention is not limited to such a method. For example, if the period of the count clocks CKdaca and CKdacb supplied to the reference signal generator 27 is constant, the counter output value is x, and the ramp voltage gradient (change rate) β included in the control data CN4 is y = α ( The voltage change amount ΔRAMP for each count clock CKdac is determined by information indicating the slope (rate of change) of the lamp voltage included in the control data CN4, such as outputting a potential calculated by (initial value) −β * x. Arbitrary circuits can be used, such as adjusting. The slope of the ramp voltage, that is, the slope β of the RAMP slope can be adjusted by, for example, adjusting ΔRAMP per clock by changing the current amount of the unit current source in addition to changing the number of clocks.

  The setting method of α (initial value) that can provide an offset and β (coefficient) that can provide a slope may be set in accordance with a circuit configuration that generates a ramp waveform that gradually changes voltage for each of the count clocks CKdaca and CKdacb. . As an example, when a circuit that generates a ramp waveform is composed of a combination of constant current sources and a selection circuit that selects any one of the constant current sources (one or a plurality of arbitrary numbers), α giving an offset Both (initial value) and β (coefficient) that gives a slope can be realized by using a constant current source and adjusting the current flowing through the constant current source (details will be described later).

  Regardless of the method of generating the reference signal, the reference signal has an inclination corresponding to the color characteristic of the color pixel and has an initial value based on a viewpoint different from the color characteristic, such as a black reference or an offset component of the circuit. By doing so, it becomes possible to perform AD conversion processing using a reference signal suitable for both the viewpoint of color characteristics and the viewpoint different from the color characteristics.

<First Embodiment; Operation of Solid-State Imaging Device>
FIG. 4 is a timing chart for explaining signal acquisition difference processing which is a basic operation in the column AD circuit 25 of the solid-state imaging device 1 of the first embodiment shown in FIG.

  As a mechanism for converting an analog pixel signal sensed by each unit pixel 3 of the pixel unit 10 into a digital signal, for example, a ramp-wave reference signal RAMP descending with a predetermined inclination and a pixel signal from the unit pixel 3 are used. Find the point where the voltage of the reference component or signal component matches, and from the time of generation of the reference signal RAMP used in this comparison process, the point of time when the electrical signal corresponding to the reference component or signal component in the pixel signal matches the reference signal A method of obtaining a count value corresponding to each size of the reference component and the signal component by counting (counting) up to the count clock.

  Here, the pixel signal output from the vertical signal line 19 is such that the signal component Vsig appears after the reset component ΔV including the noise of the pixel signal as a reference component as a time series. When the first process is performed on the reference component (reset component ΔV), the second process is performed on a signal obtained by adding the signal component Vsig to the reference component (reset component ΔV). This will be specifically described below.

  For the first reading, the communication / timing control unit 20 first sets the mode control signal CN5 to the low level to set the counter unit 254 to the down-count mode and activates the reset control signal CN6 for a predetermined period (high in this example). Level) and the count value of the counter unit 254 is reset to the initial value “0” (t9). Then, after the first reading from the unit pixel 3 of the arbitrary row Vα to the vertical signal lines 19 (H1, H2,...) Is stabilized, the communication / timing control unit 20 moves toward the reference signal generation unit 27. Control data CN4a and CN4b for generating reference signals RAMPa and RAMPb are supplied.

  In response to this, the reference signal generation unit 27 first has a slope βa that matches the color pixel characteristics of one color (R or G in the odd number column) existing on the Vα row, and has a sawtooth shape (RAMP shape) as a whole. ) To generate a reference signal RAMPa having a stepped waveform (RAMP waveform) that is time-varying in the DA converter circuit 27a, and one input terminal RAMP of the voltage comparison unit 252 of the column AD circuit 25 corresponding to the odd number column. Is supplied as a comparison voltage.

  Similarly, a stepped waveform (RAMP) that has a slope βb that matches the color pixel characteristics of the other color (G or B in the even column) existing on the Vα row and is time-changed in a sawtooth shape (RAMP shape) as a whole. A reference signal RAMPb having a waveform) is generated by the DA conversion circuit 27b and supplied as a comparison voltage to one input terminal RAMP of the voltage comparison unit 252 of the column AD circuit 25 corresponding to the even column.

  The voltage comparison unit 252 compares the RAMP waveform comparison voltage with the pixel signal voltage of an arbitrary vertical signal line 19 (Hα) supplied from the pixel unit 10.

  Further, simultaneously with the input of the reference signals RAMPa and RAMPb to the input terminal RAMP of the voltage comparator 252, a reference signal generator is used to measure the comparison time in the voltage comparator 252 with the counter unit 254 arranged for each row. In synchronization with the ramp waveform voltage emitted from the counter 27 (t10), the count clock CK0 is input from the communication / timing control unit 20 to the clock terminal of the counter unit 254, and the initial count value “0” is decreased as the first count operation Start counting. That is, the count process is started in the negative direction.

  The voltage comparison unit 252 compares the ramp-shaped reference signal RAMP from the reference signal generation unit 27 with the pixel signal voltage Vx input via the vertical signal line 19, and when both voltages become the same, The comparator output is inverted from H level to L level (t12). That is, the voltage signal corresponding to the reset component Vrst is compared with the reference signal RAMP, and an active-low (L) pulse signal is generated after a time corresponding to the magnitude of the reset component Vrst and supplied to the counter unit 254. To do.

  In response to this result, the counter unit 254 stops the counting operation almost simultaneously with the inversion of the comparator output, and latches (holds / stores) the count value at that time as pixel data, thereby completing the AD conversion (t12). . In other words, down-counting is started with the generation of the ramp-shaped reference signal RAMP supplied to the voltage comparison unit 252, and counting (counting) with the clock CK0 until an active-low (L) pulse signal is obtained by the comparison process, A count value corresponding to the magnitude of the reset component Vrst is obtained.

  When a predetermined down-count period has elapsed (t14), the communication / timing control unit 20 stops supplying control data to the voltage comparison unit 252 and supply of the count clock CK0 to the counter unit 254. As a result, the voltage comparison unit 252 stops generating the ramp-shaped reference signal RAMP.

  In the first reading, the reset level Vrst in the pixel signal voltage Vx is detected by the voltage comparison unit 252 and the count operation is performed. Therefore, the reset component ΔV of the unit pixel 3 is read.

  The reset component ΔV includes noise that varies for each unit pixel 3 as an offset. However, since the variation of the reset component ΔV is generally small and the reset level Vrst is generally common to all pixels, the output value of the reset component ΔV in the pixel signal voltage Vx of an arbitrary vertical signal line 19 is approximately known.

  Therefore, at the time of reading the reset component ΔV for the first time, it is possible to shorten the down-count period (t10 to t14; comparison period) by adjusting the RAMP voltage. In this embodiment, the comparison of the reset component ΔV is performed by setting the longest period of the comparison process for the reset component ΔV to a count period (128 clocks) of 7 bits.

  In the subsequent second reading, in addition to the reset component ΔV, the electric signal component Vsig corresponding to the amount of incident light for each unit pixel 3 is read, and the same operation as the first reading is performed. That is, first, the communication / timing control unit 20 sets the mode control signal CN5 to the high level and sets the counter unit 254 to the up-count mode (t18). After the second reading from the unit pixel 3 in the arbitrary row Vα to the vertical signal lines 19 (H1, H2,...) Is stabilized, the communication / timing control unit 20 performs AD conversion processing on the signal component Vsig. Therefore, the control data CN4a for generating the reference signal RAMPa (here, including the offset OFFa and the inclination βa) is supplied to the DA conversion circuit 27a, and the control data CN4b for generating the reference signal RAMPb (here, the offset OFFb and the inclination βb is set). Are supplied to the DA converter circuit 27b.

  In response to this, the reference signal generation unit 27 first has a slope βa that matches the color pixel characteristics of one color (R or G in the odd number column) existing on the Vα row, and has a sawtooth shape (RAMP shape) as a whole. ), A reference signal RAMPa having a step-like waveform (RAMP waveform) changed with time and reduced by the offset OFFa with respect to the initial value Var for the reset component ΔV is generated by the DA converter circuit 27a, and the odd-numbered columns are generated. A comparison voltage is supplied to one input terminal RAMP of the voltage comparison unit 252 of the corresponding column AD circuit 25.

  Similarly, a stepped waveform (RAMP) that has a slope βb that matches the color pixel characteristics of the other color (G or B in the even column) existing on the Vα row and is time-changed in a sawtooth shape (RAMP shape) as a whole. And a reference signal RAMPb that is lower than the initial value Vbr for the reset component ΔV by the offset OFFb is generated by the DA conversion circuit 27b, and the reference signal RAMPb of the column AD circuit 25 corresponding to the even number column A comparison voltage is supplied to one input terminal RAMP.

  The voltage comparison unit 252 compares the RAMP waveform comparison voltage with the pixel signal voltage of an arbitrary vertical signal line 19 (Vx) supplied from the pixel unit 10.

  As described above, the initial voltage of each reference voltage at this time is calculated based on a signal obtained from a pixel that generates an arbitrary plurality of black standards, and is generated from the DA conversion circuit 27a. Different values (offset OFFa and offset OFFb) including inherent variation components respectively generated by the reference signal RAMPa and the reference signal RAMPb emitted from the DA conversion circuit 27b are obtained. In addition, the initial voltage of the reference voltage may include an arbitrary offset in addition to the signal obtained from the pixel that generates the black reference.

  Simultaneously with the input of the reference signals RAMPa and RAMPa to the input terminal RAMP of the voltage comparison unit 252, in order to measure the comparison time in the voltage comparison unit 252 with the counter unit 254 arranged for each row, from the reference signal generation unit 27 In synchronization with the generated ramp waveform voltage (t20), the count clock CK0 is input from the communication / timing control unit 20 to the clock terminal of the counter unit 254, and the unit acquired at the time of the first reading as the second counting operation From the count value corresponding to the reset component ΔV of the pixel 3, up-counting is started contrary to the first time. That is, the count process starts in the positive direction.

  The voltage comparison unit 252 compares the ramp-shaped reference signal RAMP from the reference signal generation unit 27 with the pixel signal voltage Vx input via the vertical signal line 19, and when both voltages become the same, The comparator output is inverted from H level to L level (t22). That is, the voltage signal corresponding to the signal component Vsig is compared with the reference signal RAMP, and an active low (L) pulse signal is generated after a time corresponding to the magnitude of the signal component Vsig, and supplied to the counter unit 254. To do.

  In response to this result, the counter unit 254 stops the counting operation almost simultaneously with the inversion of the comparator output, and latches (holds / stores) the count value at that time as pixel data, thereby completing the AD conversion (t22). . In other words, down-counting is started with the generation of the ramp-shaped reference signal RAMP supplied to the voltage comparison unit 252, and counting (counting) with the clock CK0 until an active-low (L) pulse signal is obtained by the comparison process, A count value corresponding to the magnitude of the signal component Vsig is obtained.

  When the predetermined down-count period has elapsed (t24), the communication / timing control unit 20 stops the supply of control data to the voltage comparison unit 252 and the supply of the count clock CK0 to the counter unit 254. As a result, the voltage comparison unit 252 stops generating the ramp-shaped reference signal RAMP.

  At the time of the second reading, the signal component Vsig in the pixel signal voltage Vx is detected by the voltage comparison unit 252 and the counting operation is performed. Therefore, the signal component Vsig of the unit pixel 3 is read out.

  Here, in the present embodiment, the counting operation in the counter unit 254 is down-counting at the first reading, and up-counting at the second reading, and therefore, automatically in the counter unit 254, using equation (1) The count value corresponding to the subtraction result is held in the counter unit 254.

  Here, equation (1) can be transformed into equation (2). As a result, the count value held in the counter unit 254 is in accordance with the signal component Vsig.

  That is, as described above, each unit pixel 3 is subtracted in the counter unit 254 by two readings and counting processes, such as down-counting at the first reading and up-counting at the second reading. The reset component ΔV including the variation and the offset component for each column AD circuit 25 can be removed, and the digital signal about the signal obtained by correcting the black reference component to the signal component Vsig corresponding to the amount of incident light for each unit pixel 3. Only data can be retrieved with a simple configuration. At this time, there is an advantage that circuit variations and reset noise can be removed.

  Therefore, the column AD circuit 25 of the present embodiment operates not only as a digital conversion unit that converts an analog pixel signal into digital pixel data but also as a CDS (Correlated Double Sampling) processing function unit. It will be.

  In addition, since the pixel data indicated by the count value obtained by Expression (2) indicates a positive signal voltage, a complement calculation or the like is unnecessary, and the compatibility with existing systems is high.

  Here, at the time of the second reading, the signal component Vsig corresponding to the amount of incident light is read out. Therefore, in order to determine the amount of light in a wide range, a wide up-count period (t20 to t24; comparison period) is taken, and the voltage It is necessary to change the lamp voltage supplied to the comparison unit 252 greatly.

  Therefore, in the present embodiment, the comparison of the signal component Vsig is performed by setting the longest comparison period for the signal component Vsig to a count period of 10 bits (1024 clocks). That is, the longest period of the comparison process for the reset component ΔV (reference component) is made shorter than the longest period of the comparison process for the signal component Vsig. The longest period of comparison processing of both the reset component ΔV (reference component) and the signal component Vsig, that is, the maximum value of the AD conversion period is not made the same, but the longest period of comparison processing for the reset component ΔV (reference component) is signaled By making it shorter than the longest period of the comparison process for the component Vsig, the total AD conversion period of two times is devised.

  In this case, although the number of comparison bits is different between the first time and the second time, control data is supplied from the communication / timing control unit 20 to the reference signal generation unit 27, and the reference signal generation unit 27 based on the control data By generating the ramp voltage, the slope of the ramp voltage, that is, the rate of change of the reference signal RAMP is made the same for the first time and the second time. Since the ramp voltage is generated by digital control, it is easy to make the slope of the ramp voltage the same at the first time and the second time. As a result, the precision of AD conversion can be made equal, and the subtraction result represented by the expression (1) by the up / down counter can be obtained correctly.

  At a predetermined timing after completion of the second count process (t28), the communication / timing control unit 20 instructs the horizontal scanning circuit 12 to read out pixel data. In response, the horizontal scanning circuit 12 sequentially shifts the horizontal selection signal CH (i) supplied to the counter unit 254 via the control line 12c.

  In this way, the count value represented by the expression (2) stored and held in the counter unit 254, that is, the pixel data represented by n-bit digital data is sequentially transferred via the n horizontal signal lines 18. Video data D1 representing a two-dimensional image is obtained by outputting from the output terminal 5c to the outside of the column processing unit 26 or the chip having the pixel unit 10 and then repeating the same operation for each row.

  As described above, according to the solid-state imaging device of the first embodiment, the count process is performed twice by switching the processing mode while using the up / down counter. Further, in the configuration in which the unit pixels 3 are arranged in a matrix, the column AD circuit 25 is configured by a column parallel column AD circuit provided for each vertical column.

  Here, when the AD conversion circuit is configured by the comparison circuit and the counter, the DA conversion circuit, which is a functional element that generates a reference signal for AD conversion supplied to the comparison circuit, is used in a color separation filter used for color image capturing. Instead of preparing all the colors of the color filter, only the amount corresponding to the combination of the predetermined colors according to the color repetition cycle determined by the type and arrangement of the colors is provided. In addition, a change characteristic (specifically, slope) of the reference signal (analog reference voltage) generated by the DA converter circuit in response to switching of a predetermined color combination existing in the processing target line by switching the processing target line. The initial value is switched according to the characteristics of the color filter, that is, the analog pixel signal.

  As a result, the DA converter circuit functioning as a reference voltage generator and the wiring from the reference voltage generator can be made smaller than the number of color filters constituting the color separation filter, and the reference voltage generator is provided for each color filter. A multiplexer that selectively outputs an analog reference voltage (reference signal) required when the circuit is prepared is not required, so that the circuit scale can be greatly reduced.

  In addition, since the change characteristic (specifically, the slope) of the reference signal generated by the DA converter circuit is switched in accordance with switching of the combination of the predetermined colors existing in the processing target row, the pixel unit 10 is configured. When converting analog pixel signals output from unit pixels into digital data by generating different reference voltages according to the characteristics of each color pixel and performing comparison processing, reference is made according to each color. By adjusting the slope of the signal, the characteristics of each color can be precisely controlled.

  In addition, since the initial value of the reference signal generated by the DA conversion circuit is switched according to the inherent variation component and black reference component generated in the DA conversion circuit, the circuit variation can be corrected and the black reference component can be corrected. AD conversion can be performed with a simple configuration only for the signal to which the signal is added.

  Further, a subtraction process between the reference component (reset component) and the signal component can be directly obtained for each vertical column as the second count result, and a memory device that holds the respective count results of the reference component and the signal component is provided. This can be realized by a latch function provided in the counter unit, and it is not necessary to prepare a dedicated memory device for holding AD converted data separately from the counter.

  In addition, a special subtracter for taking the difference between the reference component and the signal component becomes unnecessary. Therefore, the circuit scale and circuit area can be reduced as compared with the conventional configuration, and in addition, an increase in noise and an increase in current or power consumption can be eliminated.

  In addition, since the column AD circuit (AD conversion unit) is configured by the comparison unit and the counter unit, the count process can be controlled by one count clock for operating the counter unit and a control line for switching the count mode regardless of the number of bits. A signal line for guiding the count value of the counter unit required in the conventional configuration to the memory device becomes unnecessary, and an increase in noise and an increase in power consumption can be solved.

  That is, in the solid-state imaging device 1 in which the AD conversion device is mounted on the same chip, the voltage comparison unit 252 and the counter unit 254 are paired to configure the column AD circuit 25 as an AD conversion unit, and the operation of the counter unit 254 By using a combination of down-counting and up-counting as a digital data, the difference between the basic component of the signal to be processed (the reset component in this embodiment) and the signal component is converted into digital data. Alternatively, problems such as the number of interface wirings with other functional units, noise and current consumption due to the wirings can be solved.

<Second Embodiment: Configuration of Solid-State Imaging Device>
FIG. 5 is a schematic configuration diagram of a CMOS solid-state imaging device according to the second embodiment of the present invention. The solid-state imaging device 1 according to the second embodiment is different from the solid-state imaging device 1 according to the first embodiment in the configuration of the column AD circuit 25.

  That is, the column AD circuit 25 according to the second embodiment includes a data storage unit 256 as an n-bit memory device that holds a count result held by the counter unit 254, a counter unit 254, and data after the counter unit 254 A switch 258 disposed between the storage unit 256 and the storage unit 256.

  A memory transfer instruction pulse CN8 as a control pulse is supplied to the switch 258 from the communication / timing control unit 20 at a predetermined timing in common with the switches 258 in the other vertical columns. When the memory transfer instruction pulse CN8 is supplied, the switch 258 transfers the count value of the corresponding counter unit 254 to the data storage unit 256. The data storage unit 256 holds and stores the transferred count value.

  Note that the mechanism for holding the count value of the counter unit 254 in the data storage unit 256 at a predetermined timing is not limited to the configuration in which the switch 258 is disposed between them, and for example, the counter unit 254 and the data storage unit 256 are directly connected. While being connected, the output enable of the counter unit 254 can be realized by controlling the memory transfer instruction pulse CN8, or the memory transfer instruction pulse CN8 is used as a latch clock for determining the data take-in timing of the data storage unit 256. But it can be realized.

  A control pulse is input to the data storage unit 256 from the horizontal scanning circuit 12 through the control line 12c. The data storage unit 256 holds the count value fetched from the counter unit 254 until there is an instruction by a control pulse through the control line 12c.

  The horizontal scanning circuit 12 reads the count value held by each data storage unit 256 in parallel with the voltage comparison unit 252 and the counter unit 254 of the column processing unit 26 performing the processing that they are responsible for. It has the function of a readout scanning unit.

Second Embodiment; Pipeline Processing Operation
FIG. 6 is a timing chart for explaining a basic operation in the column AD circuit 25 of the solid-state imaging device 1 according to the second embodiment shown in FIG. The AD conversion process in the column AD circuit 25 is the same as that in the first embodiment. The detailed explanation is omitted here.

  In the second embodiment, a data storage unit 256 is added to the configuration of the first embodiment, and the basic operation including AD conversion processing is the same as that of the first embodiment. Before the operation 254 (t6), based on the memory transfer instruction pulse CN8 from the communication / timing control unit 20, the count result at the time of processing of the previous row Hx-1 is transferred to the data storage unit 256.

  In the first embodiment, pixel data cannot be output to the outside of the column processing unit 26 until the second reading process for the pixel signal to be processed, that is, the AD conversion process is completed. In contrast, in the configuration of the second embodiment, the count value indicating the previous subtraction process result is stored in the data storage unit 256 prior to the first reading process (AD conversion process) for the pixel signal to be processed. Since the data is transferred, there is no restriction on the reading process.

  Therefore, according to the configuration of the second embodiment, the count result held by the counter unit 254 can be transferred to the data storage unit 256. Therefore, the count operation of the counter unit 254, that is, the AD conversion process, and the count result Can be controlled independently of the reading operation to the horizontal signal line 18, and a pipeline operation can be performed independently and in parallel with the AD conversion processing and the signal reading operation to the outside (first horizontal signal line 18). realizable.

<Third Embodiment; Configuration of Solid-State Imaging Device; Add Emerald Pixel>
FIG. 7 is a schematic configuration diagram of a CMOS solid-state imaging device according to the third embodiment of the present invention. The solid-state imaging device 1 according to the third embodiment is characterized in that the arrangement of the color filters of the color separation filter is modified. Specifically, in the first and second embodiments, three color filters of red (R), green (G), and blue (B) are applied to the unit pixels 3 arranged in a square lattice pattern. Although the arrangement is based on the basic form of the Bayer arrangement, the filter colors and the arrangement order are not limited to the basic form of the Bayer arrangement. For example, a modified Bayer arrangement can be used, or a complementary color filter or other filter colors can be used.

  For example, as shown in FIG. 7, the fourth color (emerald; E) is sensed instead of the second color pixel for sensing the second color (green; G) arranged in odd rows and even columns. For this purpose, a fourth color pixel may be provided.

  Even in this case, different color pixels of R / E or G / B which are different for each row are arranged in a checkered pattern. Such a color arrangement is the same as the basic form of the Bayer arrangement in that two colors of R / E or G / B are repeated every two in the row direction and the column direction.

  That is, the fourth color pixel E is added to the color pixel in order to improve the color reproducibility, and the entire operation can be made exactly the same as in the first embodiment, and a predetermined existing in the processing target row. As with the first embodiment, the change characteristic (slope) and initial value of the reference signal generated by the DA converter circuit are switched according to the characteristics of the color filter, that is, the analog pixel signal in accordance with the switching of the color combination. The characteristics of each color can be precisely controlled by adjusting the slope of the reference signal according to each color, which eliminates the need for a DA converter circuit functioning as a reference voltage generator and does not require a multiplexer. As described in the first embodiment, only signals that have been corrected for black reference components and circuit offset components can be AD converted with a simple configuration. It is possible to receive the same effect as.

  Although detailed description of color signal processing is omitted, corresponding to the 4-color filter, a matrix operation for generating three colors of RGB close to the human eye from video signals of each color photographed with four colors is performed. An image processor to be performed is provided in the subsequent stage of the output circuit 28. If an emerald (E) filter is mounted in addition to the red (R), green (G), and blue (B) filters, the difference in color reproduction can be reduced compared to a three-color filter, for example, blue-green And red reproducibility can be improved.

<Configuration of reference signal generator; basic>
FIG. 8 is a diagram for explaining the basic configuration and operation of the reference signal generation unit 27. FIG. 9 is a diagram illustrating an example of an analog switch used for reference signal switching.

  The reference signal generation unit 27 of the present embodiment includes a plurality of DA conversion circuits (27a and 27b) that can generate reference signals having color-related change characteristics (specifically, a slope corresponding to a gain) and initial values. ) And a selection unit that switches the color-corresponding reference signal generation unit according to the processing target row (see specific examples 1 to 6 described later).

  In this case, since the reference signal generated by the color-corresponding reference signal generation unit is supplied to the voltage comparison unit, in principle, the selection unit is arranged on the reference signal line between the color-corresponding reference signal generation unit and the voltage comparison unit. However, depending on the circuit configuration, a case where a selection unit is disposed between a common reference signal line that is shared by a plurality of color-corresponding reference signal generation units and a plurality of voltage comparison units, and There is a case where a selection unit (specifically, a switch for switching) enters the color corresponding reference signal generation unit.

  In addition, as a circuit configuration in the case where the selection unit is provided, a reference signal change characteristic (specifically, slope) and an initial value can be generated as much as possible without being influenced by the selection part, and a reference signal change characteristic (specific example) If an initial value is specified, it is important to supply a reference signal to the pressure comparison unit so that the state can be maintained as faithfully as possible. Hereinafter, this point will be described with reference to FIG.

  Here, as a basic configuration of the reference signal generation unit 27, a current output type DA converter circuit is adopted. As shown in FIG. 8A, the basic circuit configuration in this case is that the reference signal generation unit 27 includes a constant current source array 270, and the reference voltage Vref and the constant current source array are provided at the output terminal 299 thereof. A voltage dividing resistor 298 that divides voltage between the voltage dividing resistor 270 and the reference signal indicated by the output voltage Sx obtained on the constant current source array 270 side of the voltage dividing resistor 298 is supplied to the voltage comparing unit 252 via the output terminal 299. It becomes the composition to do. In effect, the constant current source array 270 and the voltage dividing resistor 298 constitute a reference signal generation output unit. A plurality of constant current sources arranged in parallel are provided in the constant current source array 270, and the voltage dividing resistor 298 functions as a combining element that combines currents flowing through the plurality of constant current sources.

  The output voltage Sx in this case is expressed by the following equation (3), where I is the operating current of the constant current source array 270, and Rref is the resistance value of the voltage dividing resistor 298 (corresponding to the output resistance of the color-corresponding reference signal generator). Given in.

<First basic configuration example>
In contrast to such a basic configuration of the reference signal generation unit 27, a plurality of constant current source arrays 270 are provided for each color, and one of the plurality of reference signals generated there is selected as a voltage comparison unit 252. In the case of supplying, as a first basic configuration example, as shown in FIG. 8B, a current source array selection unit having an analog switch function having two input terminals 290a and 290b and one output terminal 290z. 290, the input terminals 290a and 290b are connected to the output terminals 271a and 271b of the two constant current source arrays 270a and 270b, the voltage dividing resistor 298 is connected to the output terminal 290z, and the output terminal 290z is divided by a composite element. It is conceivable to connect the resistor 298 and supply a reference signal generated at the output terminal 290z to the common reference signal line 251 via the output terminal 299.

  In this case, the constant current source array 270a and the voltage dividing resistor 298 constitute one color-corresponding reference signal generation unit, and the constant current source array 270b and the voltage dividing resistor 298 constitute the other color-corresponding reference signal generation unit. Current source array selection in the two color-corresponding reference signal generators, specifically between the constant current source array 270a and the voltage dividing resistor 298 and between the constant current source array 270b and the voltage dividing resistor 298. The unit 290 (specifically, a switch for switching) is configured to enter.

<2-input-1 output type analog switch>
In realizing an analog switch function having two input terminals 290a and 290b and one output terminal 290z, for example, as shown in FIG. 9, a transfer gate using complementary transistors having different polarities. By combining a circuit (one input and one output type analog switch), a multi-input (which may be two inputs in this example) and one output type analog switch can be configured.

  The transfer gate circuit is composed of a CMOS switch formed by connecting a source and a drain of a Pch (ch) channel MOS transistor p1 and an Nch MOS transistor n1. The transfer gate circuit has two control input terminals xIN and IN (corresponding to each gate) to which complementary signals Jp and Jn are input, and the complementary signal Jp (= active L level) or positive control is applied to the negative control input terminal xIN. When a complementary signal Jn (= active H level; the complementary signal Jp may be inverted by an inverter) is input to the input terminal IN, the corresponding transistor is turned on.

  As the CMOS switch, a switch using only one of the transistors p1 and n1 may be used. However, in this case, there is a problem that the threshold voltage Vth affects the switch performance. In the example, a CMOS switch that employs both p1 and n1 and can be turned on simultaneously is employed.

  By turning on these pairs of MOS transistors at the same time, there is an advantage that the resistance value at the time of turning on can be made smaller than when a switch is constituted by one MOS transistor. In addition, there is an advantage that the function as an analog switch can be maintained even when either one of them causes an open failure.

  Further, the transfer gate circuit has good switching performance, and when the multi-input-1 output type analog switch is configured by combining the transfer gate circuits, the influence of the input that is turned off is turned on. There is also an advantage of hardly affecting the output. Of course, if both are turned off, the influence of both inputs does not appear at the output end.

  For example, when configuring a 2-input-1 output-type analog switch, as shown in the figure, two sets of transfer gate circuits are prepared, and one signal port of each transfer gate circuit is used as input terminals INa and INb, respectively. The other signal port of the transfer gate circuit may be connected to serve as the output terminal OUT. When an inverter is incorporated in each transfer gate circuit, for example, complementary signals Jpa and Jpb are input to the control port. When operating as a 2-input-1 output type analog switch, normally, either one of the two transfer gate circuits is turned on and the other is turned off, so that the complementary signals Jpa and Jpb are in a logically inverted relationship. Only one of them (for example, Jpa) may be used, and the other (Jpb) may be generated by an inverter.

  Here, the first basic configuration example is a mode in which the current source array selection unit 290 enters the color-corresponding reference signal generation unit configured by the constant current source array 270 and the voltage dividing resistor 298. It is arranged on the output side of the current source array selection unit 290 and is characterized in that a plurality of constant current source arrays 270a and 270b share one voltage dividing resistor 298.

  In such a first basic configuration example, the output voltages Sa and Sb at the output terminals 271a and 271b of the two constant current source arrays 270a and 270b represent the operating resistances of the current source array selection unit 290 when they are turned on as R290a. , R290b, the constant current source arrays 270a and 270b are given by the following equations (4a) and (4b) where Ia and Ib are the operating currents and Rref is the resistance value of the voltage dividing resistor 298. Further, when there is no variation, it can be considered that Ia = Ib = I, R290a = R290b = R290, and is given by the following formula (4c).

  Therefore, as shown in FIG. 8C, the reference signal Sy transmitted to the voltage comparison unit 252 is affected by the on-state operating resistances R290a and R290b of the current source array selection unit 290 and has a deviation. End up. In this embodiment, the difference between the AD conversion processing results twice is obtained to obtain the digital data of the true signal component. Therefore, the deviation amount due to the operating resistances R290a and R290b is offset by the difference processing. The

  However, it is necessary to take a margin of the conversion range in consideration of the shift amount. This problem particularly affects the setting of the longest time of AD conversion processing of the reset component ΔV, and the maximum value of the downcount period (t10 to t14; comparison period) cannot be shortened so much. It is necessary to increase the number of count bits for the component to more than 7 bits.

<Second basic configuration example>
On the other hand, a plurality of constant current source arrays 270 are provided for each color corresponding to the basic configuration of the reference signal generation unit 27, and one of the plurality of reference signals generated there is selected and supplied to the voltage comparison unit 252. As a second basic configuration example, the voltage dividing resistors 298a and 298b are connected to the output terminals 271a and 271b of the two constant current source arrays 270a and 270b, respectively, as shown in FIG. A current source array selector 290 having two input terminals 290a and 290b and one output terminal 290z is connected to the output terminals 271a and 271b of the constant current source arrays 270a and 270b. It is considered that the terminal 290z is connected to the output terminal 299 and the reference signal obtained from the output terminal 290z is supplied to the common reference signal line via the output terminal 299. It is.

  The second basic configuration example is characterized in that voltage dividing resistors 298a and 298b used independently by each of the plurality of constant current source arrays 270a and 270b are provided on the input side of the current source array selection unit 290. Have In this case, the constant current source array 270a and the voltage dividing resistor 298a constitute one color-corresponding reference signal generation unit, and the constant current source array 270b and the voltage dividing resistor 298b constitute the other color-corresponding reference signal generation unit. The current source array selection unit 290 (specifically, a switch for switching) is provided on the reference signal line between the two color-corresponding reference signal generation units and the voltage comparison unit 252.

  In such a second basic configuration example, the output voltages Sa and Sb at the output terminals 271a and 271b of the two constant current source arrays 270a and 270b correspond to the constant current source arrays 270a and 270b of the corresponding voltage dividing resistors 298a and 298b. The output voltages Sxa and Sxb obtained on the side. The output voltages Sxa and Sxb in this case are as follows when the operating current of the constant current source array 270 is I and the resistance value of the voltage dividing resistor 298 (corresponding to the output resistance of the color-corresponding reference signal generator) is Rrefa and Rrefb. It is given by equation (5).

  Here, if the voltage comparison unit 252 is ideal and the input impedance is infinite (∞), the reference signal transmitted to the voltage comparison unit 252 is the impedance of the current source array selection unit 290. (In this case, it is not affected at all by the on-state operating resistance). As a result, the reference signal shift caused by the operating resistances R290a and R290b, which occurs in the first basic configuration example, does not occur.

  In the second basic configuration example, the output voltages Sa and Sb at the output terminals 271a and 271b of the two constant current source arrays 270a and 270b are the same as the output voltage Sa at the output terminals 271a and 271b of the two constant current source arrays 270a and 270b. , Sb. However, since the current source array selection unit 290 is sandwiched therebetween, the output voltages Sa and Sb are not transmitted to the voltage comparison unit 252 as they are. This is not a problem in itself, but the on-resistance of the current source array selector 290 is a problem.

  That is, in practice, since the input impedance of the voltage comparison unit 252 is finite, the voltage Sy transmitted to the voltage comparison unit 252 is affected by a considerable amount. For example, even when it is considered that the input impedance of the voltage comparison unit 252 does not affect the output voltages Sxa and Sxb obtained on the constant current source arrays 270a and 270b side of the voltage dividing resistors 298a and 298b, the input of the voltage comparison unit 252 The resistance is R252in, the operating resistance of each current source array selection unit 290 is R290a, R290b, the constant current source arrays 270a, 270b are the operating currents Ia, Ib, and the resistance values of the voltage dividing resistors 298a, 298b. When Rrefa and Rrefb are used, the reference signals Sya and Syb transmitted to the voltage comparator 252 are given by the following equations (6a) and (6b). Further, when there is no variation, it can be considered that Ia = Ib = I and R290a = R290b = R290, and therefore is given by the following formula (6c).

  In any expression, the output voltages Sxa and Sxb obtained on the constant current source arrays 270a and 270b side of the voltage dividing resistors 298a and 298b are not directly transmitted to the voltage comparison unit 252 and are divided according to the resistance ratio. 8 indicates that the amplitude of the reference signal is reduced because the magnitude of the voltage lost due to the voltage division increases as the signal level decreases. As shown in (E), the conversion target range and gain (tilt) are affected.

  Further, actually, as shown in FIG. 8D, the voltage dividing resistors 298a and 298b flow not only to the operating currents Ia and Ib from the constant current source arrays 270a and 270b but also to the voltage comparison unit 252 side. Since the current component Iy is also superimposed, the output voltages Sxa and Sxb obtained on the constant current source arrays 270a and 270b side of the voltage dividing resistors 298a and 298b are also affected. For example, the initial value itself is also affected by the current component Iy. The gain is also affected, and the degree of influence is further complicated.

  Therefore, in order to reduce these influences as much as possible, the resistance values Rrefa and Rrefb of the voltage dividing resistors 298a and 298b, the on-state operating resistors R290a and R290b of the current source array selector 290, and the input resistance of the voltage comparator 252 Between R252in and R252in >> Rrefa, Rrefb >> R290a, R290b.

  In the second basic configuration example, as estimated from Equation (4), the output voltages Sxa and Sxb obtained on the constant current source arrays 270a and 270b side of the voltage dividing resistors 298a and 298b are divided by the voltage dividing resistors 298a. , 298b is affected by variations in resistance values Rrefa and Rrefb, and this point needs to be taken into consideration.

  From these facts, in practice, the one that can obtain the required performance as much as possible is adopted in consideration of the characteristics of each configuration. Of course, two configuration examples and their respective features (advantages and disadvantages) are shown here, but other configurations can also be adopted, and in that case as well, it is necessary to consider the respective features (advantages and disadvantages). The one that achieves the desired performance will be adopted.

  FIG. 10 is a diagram illustrating in further detail the influence of the operating resistance (particularly on-resistance) of the current source array selector 290 in the first and second basic configuration examples. As described above, when there is no variation in the operating current, the reference signals (DAC signals) supplied to the common reference signal line 251 may be considered to be the same. At this point, since the output voltage (reference signal) does not change at first glance, it seems that no matter which one is adopted.

  However, when the ON resistance of a switch (configured by a MOS transistor) that constitutes the current source array selection unit 290 is present in the DAC signal, 1) When the operating voltage is displaced due to the current flowing through the switch, the ON resistance fluctuates and becomes DAC. 2) LSB (Least Significant Bit) for each channel fluctuates due to variations in the on-resistance of the switch, and it is necessary to perform correction when performing the desired white balance. In addition, a problem arises that the linearity of the DAC cannot be maintained because the ON resistance greatly varies depending on the temperature. This is a basic operation that is fundamental in circuit operation.

  More specifically, as shown in FIG. 10, the current source cells are connected by the cascodes of the MOS transistor M0 and the MOS transistor M1 (or M2). This is to protect the MOS transistor M0 from noise when operating Vsa (or Vsb) at 300 MHz. In this case, the MOS transistor M1 and the MOS transistor M0 are in the saturated state of cascode → MOS transistor M1 Vgs−Vth <Vds.

  Here, in the case of the first basic configuration example, as can be seen from the equation (4), the output voltage Sa (or Sb) is lowered because the on-resistance Ron of the switch is interposed in the output voltage Sa (or Sb). And a dynamic range that takes into account the on-resistance Ron of the switch that changes with temperature and potential. Therefore, for example, in the case of Ron = 100Ω, 0.5 V is lost at Itotal = 5 mA, so that it is difficult to guarantee the design with an amplitude of 1V.

  On the other hand, in the case of the second basic configuration example, as can be seen from Equation (5), the output voltage Sa (or Sb) does not include the on-resistance Ron of the switch, so that no loss due to the on-resistance Ron occurs. In this respect, the second basic configuration example is more advantageous.

<Configuration Example of Reference Signal Generation Unit; First Example>
FIG. 11 is a block diagram illustrating a first example of a specific configuration example of the reference signal generation unit 27. The reference signal generation unit 27 of the first example generates a color-corresponding reference signal generation unit that generates and outputs a reference signal having a predetermined inclination and a predetermined initial value in a direction different from the horizontal direction as a reading unit. With respect to the vertical column direction as a different direction, as many as the number of color filters existing in the repeating unit of the color filter array are provided, and any one of the reference signals output independently from the color corresponding reference signal generation unit Is selected according to the switching of the processing target row (switching of the reading unit), and a selection unit for outputting to the corresponding signal line is provided.

  Note that the color-corresponding reference signal generation unit includes reference signal generation / output units provided for the number of color filters existing in the repetition unit of the color separation filter with respect to the horizontal direction as a readout unit (in this example, a DA conversion circuit). For each of 27a and 27b), a reference signal having an inclination determined from the viewpoint of the color characteristics of the corresponding color filter and an initial value determined from a viewpoint different from the color characteristics such as black level and circuit offset is generated. And output.

  Each color-corresponding reference signal generator includes a plurality of constant current sources arranged in parallel, and a plurality of constant current sources arranged in parallel based on a predetermined control signal. The reference signal output from the color-corresponding reference signal generation unit is supported by controlling the current flowing through the constant current source selection unit that selects one or more from among the plurality of constant current sources arranged in parallel. A second characteristic is that a change characteristic control unit that controls the color filter to change with a change characteristic corresponding to the color characteristic of the color filter is provided. In particular, a constant current source selection unit is provided for each individual reference signal generation output unit, and in addition, the first basic configuration example described above is employed.

  Furthermore, the change characteristic control unit is configured with a reference constant current source having a current mirror structure for a plurality of constant current sources arranged in parallel, and the current flowing through the reference constant current source can be adjusted. Thus, the third feature is that the reference signal output from the color-corresponding reference signal generation unit is changed with a change characteristic corresponding to the color characteristic of the corresponding color filter.

  Further, each color-corresponding reference signal generation unit has an initial value setting unit for setting an initial value of a reference signal generated by a plurality of constant current sources arranged in parallel provided in each color-corresponding reference signal generation unit, Fourth, the initial value of the reference signal output from the color-corresponding reference signal generation unit can be set based on a non-color characteristic different from the color characteristic of the corresponding color filter, such as a black standard or a circuit offset component. It has the characteristics of. In particular, the initial value setting unit includes an initial value setting current source that superimposes a current that gives an initial value on a current that flows through a plurality of constant current sources arranged in parallel. It is characterized in that the flowing current can be adjusted.

  Specifically, the reference signal generation unit 27 of the first example shown in FIG. 11 corresponds to the solid-state imaging device 1 of the first and second embodiments having the pixel units 10 of the Bayer array. First, Vα A DA converter circuit 27a that generates a reference signal RAMPa for one color (R or G in an odd column) existing on a row includes a plurality of constant current sources arranged in parallel corresponding to the R color in the odd column. A constant current source array 270R including 270R-1 to -n, a constant current source array 270G including a plurality of constant current sources 270G-1 to -n corresponding to G color, and each constant current source And a constant current source selection unit 280 that selects each of the constant current sources of the arrays 270R and 270G according to a predetermined rule.

  Further, the DA conversion circuit 27a is a combination of the constant current source array selection unit 290 that switches to one of the constant current source arrays 270R and 270G according to the row to be sequentially switched, and the reference voltage Vref to the constant current source arrays 270B and 270G. And a voltage dividing resistor 298a that divides the voltage. For a specific configuration example of the constant current source array selection unit 290, a second example described later may be referred to.

  In the current source array selector 290, one input terminal 291R is connected to the output terminal 271R of the constant current source array 270R, the other input terminal 291G is connected to the output terminal 271G of the constant current source array 270G, and the output terminal 291z is Connected to voltage dividing resistor 298a. A connection point between the voltage dividing resistor 298a and the constant current source array selection unit 290 is connected to the output terminal 299a of the DA converter circuit 27a, and a reference signal RAMPa having a ramp waveform is output from the output terminal 299a.

  Similarly, the DA conversion circuit 27b for generating the reference signal RAMPb for the other color (G or B in the even column) existing on the Vα row includes a plurality of DA converters arranged in parallel corresponding to G in the even column. Constant current source array 272G including constant current sources 272G-1 to -n, constant current source array 272B including a plurality of constant current sources 272B-1 to -n arranged in parallel therein, and each constant current source array And a constant current source selection unit 282 that selects each of the constant current sources 272G and 272B according to a predetermined rule.

  Further, the DA conversion circuit 27b is a combination of the constant current source array selection unit 290 that switches to one of the constant current source arrays 272G and 272B according to the row to be sequentially switched, and the reference voltage Vref to the constant current source arrays 272G and 272B. And a voltage dividing resistor 298b that divides the voltage. For a specific configuration example of the constant current source array selection unit 292, a second example described later may be referred to.

  In the current source array selector 292, one input terminal 293G is connected to the output terminal 273G of the constant current source array 272G, the other input terminal 293B is connected to the output terminal 273G of the constant current source array 272B, and the output terminal 293z is connected. Connected to voltage dividing resistor 298b. A connection point between the voltage dividing resistor 298b and the constant current source array selection unit 292 is connected to the output terminal 299b of the DA converter circuit 27a, and a reference signal RAMPb having a ramp waveform is output from the output terminal 299b.

  A control signal J0 for controlling input switching is supplied from the communication / timing control unit 20 to the current source array selection units 290 and 292, and the current source array selection unit 290 controls the constant current source arrays 270R and 270G according to the control signal J0. One of the outputs is selected, and the current source array selection unit 292 selects one of the constant current source arrays 272G and 272B.

  Each of the constant current source arrays 270R, 270G, 272G, and 272B is an example of an individual color-corresponding reference signal generation unit that generates and outputs a reference signal corresponding to the color characteristics of the corresponding color filter.

  A count clock CKdaca is input to the constant current source selection unit 280, and a count clock CKdacb is input to the constant current source selection unit 282 from the communication / timing control unit 20, respectively. One or a plurality of constant current source selection units 280 and 282 are provided for each count clock CKdaca and CKdacb from among a predetermined number of constant current sources built in each of the constant current source arrays 270R, 270G, 272G, and 272B. By selecting, a step-like sawtooth wave (ramp voltage) is output from the output terminals 299a and 299b of the DA conversion circuits 27a and 27b as the reference signals RAMPa and RAMPb.

  As the constant current sources 270R-1 to -n provided in the constant current source array 270R, as a first example, all of the current values are equally weighted. For example, in the case of 8-bit correspondence, n = 256, 10 In the case of bit correspondence, it is preferable to prepare for the number of stages corresponding to the number of bits, such as n = 1024. The constant current source selection unit 280 sequentially increases the number of constant current sources that are turned on each time an active edge (for example, a falling edge) of the count clock CKdaca is input. With such a configuration, the number of constant current sources that are turned on sequentially increases, so that there is no step in the ramp waveform. Note that, for example, another constant current source may be sequentially turned on by counting with a counter provided separately for every n = 128 or 256.

  Alternatively, as a second example, as many constant current sources 270R-1 to -n provided in the constant current source array 270R as the number of bits are prepared. Each constant current source is assigned a current value corresponding to the bit. The constant current source selection unit 280 is provided with a counter circuit, and the constant current sources corresponding to the number of bits are turned on / off by the bit output of the counter circuit. With such a configuration, the number of constant current sources is drastically reduced as compared with the configuration of the first example. However, a ramp is generated at the carry portion of the bit due to environmental variations such as variation in weight depending on the bit and temperature. There may be a step in the waveform.

  Further, as a configuration peculiar to the first example, the constant current source array 270R includes a constant current source 270R-off that sets an offset offaR according to the control signal J1-R with respect to the initial value Var for the reset component ΔV. There is a constant current source 270R-βa that sets an inclination βaR in accordance with the control signal J2-R in accordance with the color pixel characteristics of the odd-numbered R color pixels.

  The constant current source 270R-off is an example of an initial value setting unit that sets an initial value based on a viewpoint different from the color characteristics of the color filter provided in the unit pixel 3 (unit component) to be processed. The initial value Vas for the signal component Vsig can be set by adjusting the current flowing through the constant current source 270R-off by the control signal J1-R, and has a stepped shape output from the output terminal 299a of the DA converter circuit 27a. An offset offaR with respect to the initial value Var for the reset component ΔV in the signal RAMPa can be set.

  Further, the constant current source 270R-βa controls the current flowing through the plurality of constant current sources 270R-1 to -n and the constant current source 270R-off existing in the constant current source array 270R, so that the color-corresponding reference signal An example of a change characteristic control unit that controls the reference signal RAMPaR output from the constant current source array 270R for R color as the generation unit to change with a change characteristic according to the color characteristic of the corresponding R color filter. It is.

  The constant current source 270R-βa forms a current mirror (CM) between the constant current sources 270R-1 to -n and the constant current source 270R-off, and the constant current source 270R-βa There is a ratio relationship between the flowing current and the current flowing through the constant current sources 270R-1 to -n and the constant current source 270R-off. Therefore, by adjusting the current flowing through the constant current source 270R-βa by the control signal J2-R, the current flowing through the constant current sources 270R-1 to -n and the constant current source 270R-off, that is, the constant current source array 270R The slope βaR of the reference signal RAMPaR appearing at the output terminal, and consequently, the slope βaR of the reference signal RAMPa appearing at the output terminal of the DA converter circuit 27a can be adjusted.

  Similarly, the constant current source array 270G has a constant current source 270G-off that sets an offset offaG according to the control signal J1-G with respect to the initial value Vag for the reset component ΔV, and is an odd-numbered G color pixel. A constant current source 270G-βa that sets a slope βaG according to the characteristics in accordance with the control signal J2-G is provided. The constant current source array 272G has a constant current source 272G-off that sets an offset offbG according to the control signal J3-G with respect to the initial value Vbg for the reset component ΔV, and has an even column of G color pixel characteristics. A constant current source 272G-βb that sets a slope βbG according to the control signal J4-G. The constant current source array 272B has a constant current source 272B-off that sets an offset offbB according to the control signal J3-B with respect to the initial value Vbb for the reset component ΔV, and has an even-numbered B color pixel characteristic. The constant current source 272B-βb is set according to the control signal J4-B.

  Each of the constant current source 270G-off, the constant current source 270G-βa, the constant current source 272G-off, the constant current source 272G-βb, the constant current source 272B-off, and the constant current source 272B-βb The typical operation is the same as that of the constant current source array 270R in the DA conversion circuit 27a. Here, the detailed explanation about them is omitted.

  According to the DA conversion circuits 27a and 27b of the first example as described above, the configuration of the constant current source array that generates the reference signal exhibiting the ramp voltage by turning on / off the combination of the constant current sources and the constant current sources. In addition, the constant current source 27 # @-off (# is either 0, 2 or @ is any of R, G, B) is used for the initial values Va, Vb for the reset component ΔV. In addition to setting the offset off, similarly, the constant current source 27 # @-β * (# is either 0 or 2, @ is R, G, B, * is a, b) The inclination β * @ of the reference signal exhibiting the lamp voltage is adjusted. Matches well with the configuration of the array (parallel arrangement) of constant current sources 27 # @-1 to -n that generate the basic reference signal, and it is a simple configuration that matches the color pixel characteristics of two colors in any row In addition, a reference voltage having a slope βa or βb can be generated, and the offset can be adjusted, so that there is an advantage that a black reference component and a circuit offset can be corrected.

  In the first example, a constant current source 27 # @-off for changing the offset and a constant current source 27 # @-β * for changing the slope are provided for changing the offset and the slope of the reference signal. As another means, for example, the offset can be adjusted by directly changing the reference voltage Vref. The inclination can also be adjusted by directly controlling the amount of current of the unit current sources of the constant current sources 27 # @-1 to -n.

  For example, when the pixel unit 10 has a Bayer array structure, the vertical signal line 19 has a voltage comparison unit 252a to which signals indicated by R (red) and G (green) are input, and G (green) and B It can be classified into two types of voltage comparison unit 252b to which a signal indicated by (blue) is input (see FIG. 1).

  Therefore, a configuration is adopted in which two types of reference signals RAMPa and RAMPb are supplied to the corresponding voltage comparison units 252a and 252b, respectively. Further, the reference signal generation unit 27 is provided with a function unit that generates a reference signal corresponding to each color, and corresponds to any of the reference signals RAMPaR and RAMPaR generated by the color-corresponding constant current source arrays 270R and 270G. The voltage comparison unit 252a is supplied via the current source array selection unit 290 having an analog switch function, and similarly corresponds to any one of the reference signals RAMPbG and RAMPbB generated by the color-corresponding constant current source arrays 272G and 272B. The voltage supply unit 252b to be supplied is supplied via the current source array selection unit 292 having an analog switch function.

  The switching operation of the current source array selection units 290 and 292 based on the control signal J0 is realized by performing the switching operation of the plurality of constant current source arrays 270 according to the readout position of the imaging signal. As a result, a reference signal corresponding to the color of the readout image signal is supplied to the voltage comparison units 252a and 252b.

  For example, in the case where the pixel unit 10 has a Bayer array, when an n-th row (in this case, an odd-numbered row) readout operation is performed, the vertical signal lines 19 (H1, H2,. These pixel signals are alternately output. At this time, the current source array selection units 290 and 292 in the reference signal generation unit 27 start to operate simultaneously with the head clock for row reading output from the communication / timing control unit 20.

  Here, as shown in FIG. 1, the R component pixel signal in the n-th row (or odd-numbered row) is input to the voltage comparison unit 252a, and the corresponding reference signal is input by the DA conversion circuit 27a, that is, the current source array selection unit 290. This is a reference signal RAMPa for switching operation. Therefore, when an R component pixel signal in the n-th row is output and input to the voltage comparison unit 252a, among the CMOS switches incorporated in the current source array selection unit 290, a constant current source array 270R for R (red). And the one connected to the G (green) constant current source array 270G are turned off.

  Further, as shown in FIG. 1, the G component pixel signal in the nth row (odd row) is input to the voltage comparison unit 252b, and the corresponding reference signal is switched by the DA conversion circuit 27b, that is, the current source array selection unit 292. This is a reference signal RAMPb to be operated. Therefore, when the pixel signal of the G component in the nth row is output and input to the voltage comparison unit 252b, the constant current source array 272G for G (green) among the CMOS switches incorporated in the current source array selection unit 292. And the one connected to the B (blue) constant current source array 272B are turned off.

  Further, when the reading operation of the (n + 1) -th row (here, even-numbered row) is performed, the G component and B component pixel signals are alternately output to the vertical signal lines 19 (H1, H2,...). At this time, the current source array selection units 290 and 292 in the reference signal generation unit 27 start to operate simultaneously with the head clock for row reading output from the communication / timing control unit 20.

  Here, as shown in FIG. 1, the pixel signal of the G component in the (n + 1) th row (even row) is input to the voltage comparison unit 252a, and the corresponding reference signal is switched by the DA conversion circuit 27a, that is, the current source array selection unit 290. This is a reference signal RAMPa to be operated. Therefore, when the G component pixel signal in the (n + 1) th row is output and input to the voltage comparison unit 252a, the R (red) constant current source array 270R among the CMOS switches incorporated in the current source array selection unit 290. And the one connected to the G (green) constant current source array 270G are turned on.

  As shown in FIG. 1, the B component pixel signal in the (n + 1) th row (even row) is input to the voltage comparison unit 252b, and the corresponding reference signal is switched by the DA conversion circuit 27b, that is, the current source array selection unit 292. This is a reference signal RAMPb to be operated. Therefore, when a B component pixel signal in the (n + 1) th row is output and input to the voltage comparison unit 252b, among the CMOS switches incorporated in the current source array selection unit 292, a constant current source array 272G for G (green). And the one connected to the constant current source array 272B for B (blue) are turned on.

  By repeating such an operation, an analog conversion potential appropriate for each color pixel can be input to the voltage comparison unit 252 to perform an AD conversion operation.

  In addition, when the pixel unit 10 is a monochrome-compatible one having uniform color pixels (when there is no color filter for each color or in the case of a single color), there is no need to switch the reference signal RAMP according to the color. Therefore, it is necessary to supply the common reference signal RAMP to the common reference signal lines 251a and 251b. In this case, for example, of the CMOS switches incorporated in the current source array selectors 290 and 292, regardless of switching the processing target row, the one connected to the G (green) constant current source array 272G is always used. It is preferable to set the ON state and always turn off the one connected to the constant current source array 270R for R (red) and the one connected to the constant current source array 272B for B (blue).

<Configuration Example of Reference Signal Generation Unit; Second Example>
FIG. 12 is a block diagram illustrating a second example of a specific configuration example of the reference signal generation unit 27. The reference signal generation unit 27 of the second example is characterized in that it adopts the above-described second basic configuration example. That is, the present invention is characterized in that a voltage dividing resistor that each of the plurality of constant current source arrays is uniquely used is provided on the input side of the current source array selection unit.

  Specifically, first, in the DA converter circuit 27a, a voltage dividing resistor 298aR that divides the reference voltage Vref in combination with the constant current source array 270R is connected to the output terminal 271R of the constant current source array 270R. A voltage dividing resistor 298aG that divides the reference voltage Vref in combination with the constant current source array 270G is connected to the output terminal 271G of the constant current source array 270G.

  In the current source array selector 290, one input terminal 291R is connected to the output terminal 271R of the constant current source array 270R, the other input terminal 291G is connected to the output terminal 271G of the constant current source array 270G, and the output terminal 291z is Connected to the output terminal 299a of the DA conversion circuit 27a, a reference signal RAMPa having a ramp waveform is output from the output terminal 299a.

On the other hand, in the DA converter circuit 27b, a voltage dividing resistor 298bG that divides the reference voltage Vref in combination with the constant current source array 272G is connected to the output terminal 273G of the constant current source array 272G, and similarly, the reference voltage Vref is fixed. A voltage dividing resistor 298bB that divides voltage in combination with the current source array 272B is connected to the output terminal 273B of the constant current source array 272B.
In the current source array selection unit 292, one input terminal 293G is connected to the output terminal 273G of the constant current source array 272G, the other input terminal 293B is connected to the output terminal 273B of the constant current source array 272B, and the output terminal 291z is Connected to the output terminal 299b of the DA conversion circuit 27b, a reference signal RAMPa having a ramp waveform is output from the output terminal 299b.

<Configuration example of constant current source array selection unit>
FIG. 13 is a diagram illustrating a specific configuration example of the constant current source array selection units 290 and 292. In this configuration example, any one of the four constant current source arrays 270R, 270G, 272G, and 270B is used for the two common reference signal lines 251a and 251b by making use of the color pixel arrangement and the characteristics of the pixel signal input for each column. As the current source array selectors 290 and 292 for allocating these, four analog switches are used.

  Specifically, as shown in the figure, each of the constant current source array selection units 290 and 292 includes a 2-input-1-output type analog switch that combines the 1-input-1-output type transfer gate circuit shown in FIG. And a switch control unit 296 is used in common. Here, each transfer gate circuit 270Rp1n1, 270Gp1n1, 272Gp1n1, 272Bp1n1 uses only the complementary signal Jp, and the other complementary signal Jn is generated by an inverter.

  The switch control unit 296 is supplied with a control signal J0 that controls input switching of the constant current source array selection units 290 and 292 from the communication / timing control unit 20. The switch control unit 296 generates complementary signals 290RJpa and 290GJpa for selecting one of the outputs of the constant current source arrays 270R and 270G according to the control signal J0, and supplies the complementary signal 290RJpa to the MOS transistor 290Rp1. 290 GJpa is supplied to the MOS transistor 290Gp1. The current source array selector 290 selects the output of the constant current source array 270R when the complementary signal 290RJpa is active L and the complementary signal 290GJpa is inactive H, and the complementary signal 290RJpa is inactive H and the complementary signal 290GJpa is When active L, the output of the constant current source array 270G is selected and supplied to the common reference signal line 251a via the output terminal 299a.

  Further, the switch control unit 296 generates complementary signals 292GJpb and 292BJpb for selecting one of the outputs of the constant current source arrays 272G and 272B according to the control signal J0, and supplies the complementary signal 292GJpb to the MOS transistor 292Gp1. The complementary signal 292BJpb is supplied to the MOS transistor 292Bp1. The current source array selection unit 292 selects the output of the constant current source array 272G when the complementary signal 290GJpb is active L and the complementary signal 292BJpb is inactive H, and the complementary signal 290GJpb is inactive H and the complementary signal 292BJpb is When active L, the output of the constant current source array 272B is selected and supplied to the common reference signal line 251b via the output terminal 299b.

<Configuration Example of Reference Signal Generation Unit; Third Example>
FIG. 14 is a block diagram illustrating a third example of a specific configuration example of the reference signal generation unit 27. The reference signal generation unit 27 of the third example corresponds to the solid-state imaging device 1 of the third embodiment in which the configuration of the second example is adopted and an emerald pixel is added as a fourth color pixel. Only the constant current source array 272G is changed to the constant current source array 272E, and the basic operation and effect are the same as those of the second example. Here, a detailed description of the constant current source array 272E is omitted. In the third example, the configuration of the second example is changed. However, the configuration of the first example can be similarly changed.

<Configuration Example of Reference Signal Generation Unit; Fourth Example>
FIG. 15 is a block diagram illustrating a fourth example of a specific configuration example of the reference signal generation unit 27. The reference signal generation unit 27 of the fourth example generates a constant current source selection unit that selects one or a plurality of constant current sources from a plurality of constant current sources arranged in parallel based on a predetermined control signal. It is characterized in that it is provided in common for the output section. In the fourth example, a change is made to the configuration of the second example, but a change can be similarly made to the configuration of the first example.

  Specifically, the reference signal generation unit 27 of the fourth example illustrated in FIG. 15 corresponds to the solid-state imaging device 1 of the first and second embodiments having the pixel units 10 of the Bayer array, and is a second example. This is characterized in that the constant current source selection units 280 and 282 provided for each of the DA conversion circuit 27a and the DA conversion circuit 27b in the configuration are changed to a common constant current source selection unit 284.

  A count clock CKdac is input from the communication / timing controller 20 to the constant current source selector 284. The constant current source selection unit 284 selects one or a plurality of constant current sources included in each of the constant current source arrays 270R, 270G, 272G, and 272B for each count clock CKdac from among a predetermined number of constant current sources. The stepped sawtooth wave (ramp voltage) is output from the output terminals 299a and 299b of the DA conversion circuits 27a and 27b as the reference signals RAMPa and RAMPb.

  Here, the selection operation of the constant current source selection units 280 and 282 in the configuration of the second example (the same applies to the first example) is basically the same if the constant current source arrays 270R, 270G, 272G, and 272B have the same configuration. The step-like sawtooth wave can be output as the reference signals RAMPa and RAMPb from the output terminals 299a and 299b of the DA conversion circuits 27a and 27b by an on / off operation by one circuit.

  The configuration of the fourth example is made paying attention to this point. With this configuration, it is possible to reduce the circuit for selectively switching the constant current sources in the constant current source array as compared with the configuration of the second example (or the first example).

<Configuration Example of Reference Signal Generation Unit; Fifth Example>
FIG. 16 is a block diagram illustrating a fifth example of a specific configuration example of the reference signal generation unit 27. The reference signal generation unit 27 of the fifth example corresponds to the solid-state imaging device 1 of the third embodiment in which the configuration of the fourth example is adopted and an emerald pixel is added as a fourth color pixel. Only the constant current source array 272G is changed to the constant current source array 272E, and the basic operation is the same as that of the fourth example. Here, a detailed description of the constant current source array 272E and the constant current source selection unit 284 is omitted. In the fifth example, a change is made to the configuration of the second example, but a change can be similarly made to the configuration of the first example.

<Configuration Example of Reference Signal Generation Unit; Sixth Example>
FIG. 17 is a block diagram illustrating a sixth example of a specific configuration example of the reference signal generation unit 27. The reference signal generation unit 27 of the sixth example, when there are a plurality of color filters of the same color in the two-dimensional repeating unit of the color separation filter, the first color corresponding reference signal corresponding to the same color filter A generation unit is provided, and an individual reference signal generation / output unit for a color component that exists independently includes a second color-corresponding reference signal generation unit for a color component that exists independently, and the first color correspondence It is characterized in that it is configured so that the reference signal generation unit is used in common (also used).

  In addition, the switching unit to be processed (for example, the processing target row) is switched for any one of the reference signals output independently from the first color corresponding reference signal generation unit and the second color corresponding reference signal generation unit. This is characterized in that a selection unit that selects and outputs to the corresponding signal line is provided.

  Specifically, the reference signal generation unit 27 of the sixth example illustrated in FIG. 17 corresponds to the solid-state imaging device 1 of the first and second embodiments having the pixel units 10 of the Bayer array, and is a fourth example. The configuration is characterized in that the constant current source array 270G and the constant current source array 272G provided for each of the DA conversion circuit 27a and the DA conversion circuit 27b in the configuration are changed to a common constant current source array 274G. That is, it is characterized in that a constant current source array corresponding to the second color pixels G appearing at two places in the Bayer array is shared.

  One of the constant current source array selection unit 290 and the constant current source array selection unit 292 selects the constant current source array 270G according to the processing target row. Specifically, when the processing target row is an odd row, the constant current source array selection unit 290 selects the constant current source array 270R, and the constant current source array selection unit 290 selects the constant current source array 270G. On the other hand, when the processing target row is an even-numbered row, the constant current source array selection unit 290 selects the constant current source array 270G, and the constant current source array selection unit 290 selects the constant current source array 270B.

  With this configuration, a circuit for selecting and switching the constant current sources in the constant current source array and a circuit for selecting one of the two constant current source arrays to be paired according to the Bayer array are provided. This can be reduced compared to the configurations of two examples (the same applies to the first example) and the fourth example.

  In the sixth example, the configuration of the fourth example is modified so as to share the constant current source array for G color, but the configuration of the second example (same as the first example) is added. It is also possible to make a change so as to share the constant current source array for G color.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above-described embodiment, a case in which square unit pixels 3 are arranged in a square lattice pattern and provided with a color separation filter in which 2 pixels (row direction) × 2 pixels (column direction) are repeated units. In the above description, the configuration in which the DA conversion circuits 27a and 27b for two pixels, which are repeating units in the row direction, are described. However, the repeating unit of the color separation filter is 2 pixels (row direction) × 2 pixels (column direction). ) Is not limited. For example, in the case of 3 pixels (row direction) × 2 pixels (column direction), a DA conversion circuit for 3 pixels, which is a repeating unit in the row direction, may be prepared.

  In the above-described embodiment, the description has been given for the case where the square unit pixels 3 are arranged in a square lattice shape. However, the arrangement of the unit pixels is not limited to the square lattice shape. For example, the pixels shown in FIG. The part 10 may have an oblique grid shape in which the portions 10 are inclined at 45 degrees.

  In addition, although the shape of the unit pixel in plan view is assumed to be square, the shape is not limited to square but may be hexagonal (honeycomb shape), for example. In this case, the arrangement of unit pixels is, for example, as follows. One unit pixel column and one unit pixel row each include a plurality of unit pixels.

  Each of the plurality of unit pixels constituting the even-numbered column is approximately ½ of the pitch of the unit pixels in each unit pixel column with respect to the plurality of unit pixels constituting the odd-numbered column. Shift in the direction. Similarly, each of the plurality of unit pixels constituting the even-numbered row is approximately ½ the pitch of the unit pixels in each unit pixel row in the row direction with respect to the plurality of unit pixels constituting the odd-numbered row. Shift. Each of the unit pixel columns includes only unit pixels in odd rows or even rows.

  In order to read out the pixel signal based on the signal charges accumulated in the charge generation unit of these unit pixels to the column processing unit 26 side, row control lines are provided, but the arrangement meanders around the honeycomb unit pixel 3. Arranged. In other words, each unit pixel is positioned in plan view in each hexagonal gap generated by arranging the row control lines in a honeycomb shape. By doing this, as a whole, pixel signals are read in the vertical direction while alternately shifting pixels of about ½ pitch.

  If the unit pixels and the row control lines are arranged in a honeycomb arrangement, it is possible to improve the pixel density while suppressing a reduction in the area of the light receiving surface of the charge generation unit in each unit pixel.

  Regardless of the shape and arrangement of the unit pixels, in any case, when the pixel unit 10 is adapted for color imaging, it exists in the repeating unit of the color separation filter in a predetermined direction corresponding to the readout unit to be accessed simultaneously. An individual reference signal generation / output unit may be prepared for each color filter. In short, it is only necessary to prepare as many independent reference signal generation / output units as the number of color filters existing in the repetition unit of the color separation filter.

  In the above-described embodiment, the count process is started from the final count value before the switching at the time of the count process after the mode switching. However, the synchronous output in which the count output value is output in synchronization with the count clock CK0 is used. When an up / down counter is used, this can be realized without requiring any special measures at the time of mode switching.

  However, when using an asynchronous up / down counter that has an advantage that the operation limiting frequency is determined only by the limiting frequency of the first flip-flop (counter basic element) and is suitable for high-speed operation, the count value is changed when the count mode is switched. Is destroyed, and the normal count operation cannot be performed continuously while maintaining the value before and after switching. Therefore, it is preferable to provide an adjustment processing unit that can start the count processing after the mode switching from the count value before the mode switching. Note that the details of the adjustment processing unit are omitted here. When addition processing is performed between a plurality of signals, it is only necessary to set the count modes of the preceding stage and the subsequent stage to be the same, and such a countermeasure is unnecessary.

  In the above-described embodiment, the pixel signal has a signal component Vsig after the reset component ΔV (reference component) for the same pixel as a time series, and the processing unit in the subsequent stage has a positive polarity (a larger signal level indicates a positive value). When a true signal component is obtained corresponding to what is processed with respect to a signal having a large value), as a first process, a comparison process and a down-count process are performed for the reset component ΔV (reference component), and a second process is performed. Although the comparison process and the up-count process are performed on the signal component Vsig, the combination and processing order of the target signal component and the count mode are arbitrary regardless of the time series in which the reference component and the signal component appear. Depending on the processing procedure, the digital data obtained in the second processing may become a negative value. In that case, it is sufficient to take measures such as sign inversion or correction calculation.

  Of course, as the device architecture of the pixel unit 10, the reset component ΔV (reference component) must be read after the signal component Vsig, and when the subsequent processing unit processes positive signals, the first time It is efficient to perform the comparison process and the down-count process for the signal component Vsig as the above process, and the comparison process and the up-count process for the reset component ΔV (reference component) as the second process.

  Further, in the above-described embodiment, assuming that the signal component appears as a signal component Vsig after the reset component ΔV (reference component) for the same pixel as the time series in the pixel signal, the difference processing for obtaining the true signal component for each pixel signal is performed. However, in the case where only the signal component Vsig may be targeted, for example, the reset component ΔV (reference component) can be ignored, the difference processing for obtaining the true signal component can be omitted.

  In the above embodiment, the up / down counter is used in common regardless of the operation mode, and the count process is performed by switching the processing mode. However, the count process is performed by combining the down count mode and the up count mode. However, the present invention is not limited to a configuration using an up / down counter capable of mode switching.

  For example, the counter unit can be configured by a combination of a down counter circuit that performs down-count processing and an up counter circuit that performs up-count processing. In this case, the counter circuit is preferably configured to be able to load an arbitrary initial value using a known technique.

  In this way, the output of the counter circuit at the subsequent stage can be directly subtracted between the reference component and the signal component, eliminating the need for a special adder circuit (or subtractor circuit) for taking the difference between the signals. Become. Further, the data transfer to the subtractor which is necessary in Non-Patent Document 1 becomes unnecessary, and the increase in noise and the increase in current or power consumption can be solved.

  When the counter unit is configured by a combination of the down counter circuit and the up counter circuit, the count value acquired in the first count process is not set as the initial value in the second count process, and is counted from zero. Is not to be excluded.

  In this case, an adder circuit that takes the sum of the output Qup (positive value) of the up counter circuit and the output Qdown (negative value) of the down counter circuit is required. Even in this case, the comparison unit, the counter unit, Since an adder circuit is provided for each AD conversion unit configured as described above, the wiring length can be shortened, and an increase in noise for data transfer and an increase in current or power consumption can be eliminated.

  In any configuration as a modification of the counter circuit, the operation of the down counter circuit and the up counter circuit can be instructed by the communication / timing control unit 20 as in the above embodiment. Further, both the down counter circuit and the up counter circuit may be operated by the count clock CK0.

  Further, in the above embodiment, as an example of a solid-state imaging device that can arbitrarily read out signals from individual unit pixels by address control, the solid-state imaging device is configured by NMOS or PMOS that generates signal charges by receiving sensor light. Although a CMOS sensor having a pixel unit in which unit pixels are arranged in a matrix is shown as an example, signal charge generation is not limited to light, but can be applied to electromagnetic waves such as infrared rays, ultraviolet rays, or X-rays in general The matters described in the above embodiments can be applied to a semiconductor device including unit components in which a large number of elements that receive an electromagnetic wave and output an analog signal corresponding to the amount of electromagnetic waves are arranged.

1 is a schematic configuration diagram of a CMOS solid-state imaging device which is a first embodiment of a semiconductor device according to the present invention. It is a figure which shows an example of the relationship between the effective image area | region in a pixel part, and the reference | standard pixel area | region which gives optical black. It is a figure explaining the function of the DA converter circuit (DAC) of the reference signal production | generation part used in the solid-state imaging device of 1st Embodiment. 2 is a timing chart for explaining a basic operation in a column AD circuit of the solid-state imaging device according to the first embodiment shown in FIG. 1. It is a schematic block diagram of the CMOS solid-state imaging device which concerns on 2nd Embodiment of this invention. 6 is a timing chart for explaining a basic operation in a column AD circuit of the solid-state imaging device of the second embodiment shown in FIG. 5. It is a schematic block diagram of the CMOS solid-state imaging device which concerns on 3rd Embodiment of this invention. It is a figure explaining the basic composition of a reference signal generating part, and its operation. It is a figure which shows an example of the analog switch used for switching of a reference signal. It is a figure explaining in detail the influence of the operating resistance (especially on resistance) of a current source array selection part in each of the first and second basic configuration examples. It is a block diagram which shows the 1st example of the specific structural example of a reference signal production | generation part. It is a block diagram which shows the 2nd example of the specific structural example of a reference signal production | generation part. It is a figure which shows the specific structural example of a constant current source array selection part. It is a block diagram which shows the 3rd example of the specific structural example of a reference signal production | generation part. It is a block diagram which shows the 4th example of the specific structural example of a reference signal production | generation part. It is a block diagram which shows the 5th example of the specific structural example of a reference signal production | generation part. It is a block diagram which shows the 6th example of the specific structural example of a reference signal production | generation part. FIG. 5 is a schematic configuration diagram of the solid-state imaging device shown in FIG. 4 of Patent Document 1.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 3 ... Unit pixel, 7 ... Drive control part, 10 ... Pixel part, 12 ... Horizontal scanning circuit, 14 ... Vertical scanning circuit, 15 ... Row control line, 18 ... Horizontal signal line, 19 ... Vertical signal 20 ... communication / timing control unit 24 ... counter unit 25 ... column AD circuit 26 ... column processing unit 27 ... reference signal generation unit 27a, 27b ... DA conversion circuit (reference signal generation output unit) 28 ... Output circuit, 270a, 270b, 270R, 270G, 272G, 272B, 272E, 274G ... Constant current source array, 280, 282, 284 ... Constant current source selection unit, 290, 292 ... Constant current source array selection unit, 298a, 298b: Voltage dividing resistor (synthetic element)

Claims (9)

A charge generation unit that generates a charge corresponding to an incident electromagnetic wave, and an effective region including a unit signal generation unit that generates an analog unit signal corresponding to the charge generated by the charge generation unit in a unit component, And as a functional element for converting the unit signal into digital data, a reference signal generation unit that generates a reference signal for converting the unit signal into digital data, and a reference generated by the unit signal and the reference signal generation unit A comparison unit that compares the signal, and a counter unit that performs a count process with a predetermined count clock in parallel with the comparison process in the comparison unit and holds a count value at the time when the comparison process in the comparison unit is completed A semiconductor device for physical quantity distribution detection provided,
A color filter of any one of color separation filters composed of a combination of a plurality of color filters for obtaining color information is provided on the surface on the side where the electromagnetic wave is incident of each of the charge generation units in the effective region. And
The reference signal generation unit generates an individual reference signal generation output unit that generates and outputs the reference signal in a predetermined direction corresponding to the reading unit and a different direction that is different from the predetermined direction corresponding to the reading unit. Less than the number of color components of the color filter existing in the repeating unit of the color filter array in each of the color filters, and the repetition of the array of the color filters in a predetermined direction according to the reading unit of the unit signal As many as the number of color filters present in the unit,
The reference signal generation output unit generates a color-corresponding reference signal generation unit that generates and outputs the reference signal corresponding to the color characteristic of the corresponding color filter in a direction different from a predetermined direction corresponding to the reading unit. As many as the number of color filters existing in the repeating unit of the arrangement of the color filters in the different direction, and any one of the reference signals generated by each of the color-corresponding reference signal generation units, A selection is made according to the switching of the reading unit, and the selected reference signal is connected to a plurality of the comparison units corresponding to the color filters having a common color characteristic in the predetermined direction. Having a selector that communicates substantially directly through,
The semiconductor device, wherein the selection unit is arranged in the color-corresponding reference signal generation unit. The color-corresponding reference signal generation unit includes a constant current source array including a plurality of constant current sources arranged in parallel and including an output end, and a combining element that combines currents flowing through the plurality of constant current sources. ,
The selection unit includes a plurality of input terminals and one output terminal, the input terminal is connected to the output terminal of the constant current source array, the output terminal is connected to the combining element, and the output terminal is connected to the output terminal. The semiconductor device according to claim 1, wherein the generated reference signal is supplied to the common reference signal line. A charge generation unit that generates a charge corresponding to an incident electromagnetic wave, and an effective region including a unit signal generation unit that generates an analog unit signal corresponding to the charge generated by the charge generation unit in a unit component, And as a functional element for converting the unit signal into digital data, a reference signal generation unit that generates a reference signal for converting the unit signal into digital data, and a reference generated by the unit signal and the reference signal generation unit A comparison unit that compares the signal, and a counter unit that performs a count process with a predetermined count clock in parallel with the comparison process in the comparison unit and holds a count value at the time when the comparison process in the comparison unit is completed A semiconductor device for physical quantity distribution detection provided,
A color filter of any one of color separation filters composed of a combination of a plurality of color filters for obtaining color information is provided on the surface on the side where the electromagnetic wave is incident of each of the charge generation units in the effective region. And
The reference signal generation unit generates an individual reference signal generation output unit that generates and outputs the reference signal in a predetermined direction corresponding to the reading unit and a different direction that is different from the predetermined direction corresponding to the reading unit. Less than the number of color components of the color filter existing in the repeating unit of the color filter array in each of the color filters, and the repetition of the array of the color filters in a predetermined direction according to the reading unit of the unit signal As many as the number of color filters present in the unit,
The reference signal generation output unit generates a color-corresponding reference signal generation unit that generates and outputs the reference signal corresponding to the color characteristic of the corresponding color filter in a direction different from a predetermined direction corresponding to the reading unit. As many as the number of color filters existing in the repeating unit of the arrangement of the color filters in the different direction, and any one of the reference signals generated by each of the color-corresponding reference signal generation units, A selection is made according to the switching of the reading unit, and the selected reference signal is connected to a plurality of the comparison units corresponding to the color filters having a common color characteristic in the predetermined direction. Having a selector that communicates substantially directly through,
The selection unit includes a plurality of input terminals and a single output terminal, and a plurality of the color-corresponding reference signal generation units and the respective input terminals are connected to correspond to the color filter having the common color characteristic. The semiconductor device, wherein the common reference signal line used in common with the plurality of comparison units and the output terminal are connected to each other. The color-corresponding reference signal generation unit includes a plurality of constant current sources arranged in parallel and has a constant current source array including an output end, and the plurality of constant current sources connected to the output end of the constant current source. And a synthesizing element that synthesizes the current flowing through
The selection unit is configured such that the input terminal is connected to a connection point between the output terminal of the constant current source array and the synthesis element, and the reference signal obtained at the output terminal is supplied to the common reference signal line. The semiconductor device according to claim 3. The reference signal generation unit generates an individual reference signal generation / output unit that generates and outputs the reference signal in a predetermined direction corresponding to the reading unit and a different direction that is different from the predetermined direction corresponding to the reading unit. Less than the number of color components of the color filter existing in the repeating unit of the color filter array in each of the color filters, and the repetition of the array of the color filters in a predetermined direction according to the reading unit of the unit signal Have as many color filters as there are in the unit,
Each of the individual reference signal generation / output units generates an individual color-corresponding reference signal generation unit that generates and outputs the reference signal corresponding to the color characteristic of the corresponding color filter. Each reference signal output independently from the reference signal generation output unit has the same number as the number of color filters existing in the repeating unit of the color filter array in a different direction that is different from the direction. 2. The apparatus according to claim 1, wherein the first and second comparison units corresponding to the color filters having common color characteristics in the predetermined direction are substantially directly transmitted via a common signal line. Or the semiconductor device according to 3; Each of the individual reference signal generation output units,
The individual color-corresponding reference signal generation unit that generates and outputs the reference signal according to the color characteristic of the corresponding color filter, and outputs the color in a different direction that is different from a predetermined direction according to the reading unit. As many as there are color filters present in the repeating unit of the filter array,
6. The selection unit according to claim 5, wherein the selection unit selects any one of the reference signals generated by the color-corresponding reference signal generation unit according to switching of the readout unit to be processed. The semiconductor device described. 4. The semiconductor device according to claim 1, wherein an operation resistance when the selection unit is on is smaller than an output resistance of the color-corresponding reference signal generation unit and an input resistance of the comparison unit. The semiconductor device according to claim 1, wherein the counter unit is configured to perform counting processing by selecting one of a down-count mode and an up-count mode. The unit signal is represented including a reference component and a signal component,
The semiconductor device according to claim 8, wherein the counter unit switches a mode of the counting process according to which of the reference component and the signal component the comparison unit is performing the comparison process. .

Images